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UM10198
Philips Semiconductors
Chapter 10: USB device controller
3.7.2 USB MaxPacketSize Register - (USBMaxPSize - 0x3102 024C, R/W)
At power on control endpoint is assigned the Maxpacketsize of 8 bytes. Other endpoints
are assigned 0. Modifying MaxPacketSize register content will cause the buffer address of
the internal RAM to be recalculated. This is essentially a multi-cycle process. At the end of
it, the EP_RLZED bit will be set in the Device Interrupt Status register. MaxPacket
Register Array Indexing is shown in Figure 10–28.
Table 156. USB MaxPacketSize Register - (USBMaxPSize - 0x3102 024C, R/W)
Bits
Name
Function
Reset value
31:10
-
Reserved.
NA
9:0
MaxPacketSize
The maximum packet size value.
0x8
MPS*_EP0
Endpoint index
MPS*_EP31
* MPS - Maximum Packet Size
Fig 28. Maxpacket register array indexing
3.7.3 USB Receive Data Register - (USBRxData - 0x3102 0218, R)
For an OUT transaction, CPU reads the endpoint data from this register. Data from the
endpoint RAM is fetched and filled in this register. There is no interrupt when the register
is full.
Table 157. USB Receive Data Register - (USBRxData - 0x3102 0218, R)
Bits
Name
Function
Reset value
31:0
Receive data
Receive Data.
0x0
3.7.4 USB Receive Packet Length Register - (USBRxPLen - 0x3102 0220, R)
This register gives the number of bytes remaining in the EP_RAM for the current packet
being transferred and whether the packet is valid or not. This register will get updated at
every word that gets transferred to the system. Software can use this register to get the
number of bytes to be transferred. When the number of bytes reaches zero, an end of
packet interrupt is generated.
UM10198_1
User manual
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Rev. 01 — 1 June 2006
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