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56F8367
Evaluation Module User Manual
56F8300
16-bit Digital Signal Controllers
MC56F8367EVMUM
Rev. 2
07/2005
freescale.com
Document Revision History
Version History
Description of Change
Rev 1.0
Initial Public Release
Rev 2.0
Updated look and feel
TABLE OF CONTENTS
Preface Preface-vii
Chapter 1
Introduction
1.1
1.2
1.3
56F8367EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
56F8367EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
56F8367EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Chapter 2
Technical Summary
2.1
MC56F8367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2
Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1
SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.2
SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3
RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4
Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.5
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.1
EXTBOOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.2
EMI_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5.3
CLKMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.6
Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7
Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.7.1
JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.7.2
Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.8
External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.9
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.10 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.11 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.11.1
Peripheral Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.11.2
Memory Daughter Card Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.12 Motor Control PWM Signals and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Table of Contents, Rev. 2
Freescale Semiconductor
Preliminary
i
2.13 CAN Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13.1
FlexCAN #1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13.2
FlexCAN #2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15 Peripheral Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.1
Address Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.2
Data Bus Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.3
External Memory Control Signal Expansion Connector . . . . . . . . . . . . . . . . . . . . .
2.15.4
Encoder #0 / Quad Timer Channel A Expansion Connector. . . . . . . . . . . . . . . . . .
2.15.5
Encoder #1 / SPI #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.6
Timer Channel C Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.7
Timer Channel D Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.8
A/D Port A Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.9
A/D Port B Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.10 Serial Communications Port #0 Expansion Connector . . . . . . . . . . . . . . . . . . . . . .
2.15.11 Serial Communications Port #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . .
2.15.12 Serial Peripheral Interface #0 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . .
2.15.13 FlexCAN #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.14 FlexCAN #2 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.15 PWM Port A Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15.16 PWM Port B Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-23
2-23
2-24
2-26
2-27
2-28
2-29
2-30
2-30
2-31
2-31
2-32
2-33
2-34
2-34
2-35
2-35
2-36
2-36
2-37
2-37
2-38
Appendix A
56F8367EVM Schematics
Appendix B
56F8367EVM Bill of Material
MC56F8367EVM User Manual, Rev. 2
ii
Freescale Semiconductor
Preliminary
LIST OF FIGURES
1-1
Block Diagram of the 56F8367EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2
MC56F8367 Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3
Connecting the 56F8367EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
2-1
Schematic Diagram of the External CS0 Memory Interface . . . . . . . . . . . . . . . . . . . 2-5
2-2
Schematic Diagram of the External CS1 / CS4 Memory Interface . . . . . . . . . . . . . . 2-6
2-3
Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-4
Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5
Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-6
Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-7
Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-8
Schematic Diagram of the Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-9
Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-10
PWM Group A Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2-11
CAN #1 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2-12
CAN #2 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-13
Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2-14
Typical Analog Input RC Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
List of Figures, Rev. 2
Freescale Semiconductor
Preliminary
iii
MC56F8367EVM User Manual, Rev. 2
iv
Freescale Semiconductor
Preliminary
LIST OF TABLES
1-1
56F8367EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1
SCI #0 Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-2
RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-3
EXTBOOT Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-4
EMI Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-5
EMI Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-6
LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7
JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-8
Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-12
2-9
Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-10
Parallel JTAG Interface Voltage Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-14
2-11
Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-18
2-12
Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2-13
CAN #1 Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2-14
CAN #2 Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-15
CAN #2 Pass-Through Jumper Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2-16
External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-28
2-17
External Memory Address Bus Connector Description. . . . . . . . . . . . . . . . . . . 2-29
2-18
External Memory Control Signal Connector Description . . . . . . . . . . . . . . . . . 2-30
2-19
Timer A Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
2-20
SPI #1 Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2-21
Timer Channel C Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
2-22
Timer Channel D Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
2-23
A/D Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2-24
A/D Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2-25
SCI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
List of Tables, Rev. 2
Freescale Semiconductor
Preliminary
v
2-26
SCI #1 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2-27
SPI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2-28
CAN #1 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2-29
CAN #2 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2-30
PWM Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2-31
PWM Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
MC56F8367EVM User Manual, Rev. 2
vi
Freescale Semiconductor
Preliminary
Preface
This reference manual describes in detail the hardware on the 56F8367 Evaluation Module.
Audience
This document is intended for application developers who are creating software for devices using
the Freescale 56F8367 part or a member of the 56F8300 family that is compatible with this part.
Examples would include the 56F8346 and the 56F8357 devices.
Organization
This manual is organized into two chapters and two appendices:
•
Chapter 1, Introduction provides an overview of the EVM and its features.
•
Chapter 2, Technical Summary describes in detail the 56F8367 hardware.
•
Appendix A, "56F8367EVM Schematics"contains the schematics of the
MC56F8367EVM.
•
Appendix B, "56F8367EVM Bill of Material" provides a list of the materials used on the
MC56F8367EVM board.
Suggested Reading
More documentation on the 56F8367 and the MC56F8367EVM kit may be found at URL:
www.freescale.com
Preface, Rev. 2
Freescale Semiconductor
Preliminary
vii
Notation Conventions
This manual uses the following notational conventions:
Term or Value
Symbol
Examples
Active High Signals
(Logic One)
No special symbol
attached to the signal
name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and in
most figures
WE
OE
Hexadecimal Values
Begin with a “$” symbol
$0FF0
$80
Decimal Values
No special symbol
attached to the
number
Binary Values
Begin with the letter “b”
attached to the number
Numbers
Considered positive
unless specifically
noted as a negative
value
Blue Text
Linkable on-line
Bold
Reference sources,
paths, emphasis
Exceptions
In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE
10
34
b1010
b0011
5
-10
Voltage is often shown as
positive: +3.3V
...refer to Chapter 7, License
...see: www.freescale.com/
MC56F8367EVM User Manual, Rev. 2
viii
Freescale Semiconductor
Preliminary
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.
A/D
Analog-to-Digital; a method of converting Analog signals to Digital values
ADC
Analog-to-Digital Converter; a peripheral on the 56F8367 part
CAN
Controller Area Network; serial communications peripheral and method
CiA
CAN in Automation; an international CAN user’s group that coordinates
standards for CAN communications protocols
D/A
Digital-to-Analog; a method of converting Digital values to an Analog form
56F8367
Controller with motor control peripherals
EOnCE
Enhanced On-Chip Emulation; a debug bus and port was created to enable a
designer to create a low-cost hardware interface for a professional-quality
debug environment
EVM
Evaluation Module; a hardware platform which allows a customer to evaluate
the silicon and develop his application
FlexCAN
Flexable CAN Interface Module; a peripheral on the 56F8367 part
GPIO
General Purpose Input and Output port on Freescale’s family of controllers;
does not share pin functionality with any other peripheral on the chip and can
only be set as an input, output or level-sensitive interrupt input
IC
Integrated Circuit
JTAG
Joint Test Action Group; a bus protocol/interface used for test and debug
LED
Light Emitting Diode
LQFP
MPIO
Low-profile Quad Flat Package
Multi-Purpose Input and Output port on Freescale’s family of controllers;
shares package pins with other peripherals on the chip and can function as a
GPIO
OnCETM
On-Chip Emulation, a debug bus and port created to allow a means for low-cost
hardware to provide a professional-quality debug environment
PCB
Printed Circuit Board
PLL
Phase Locked Loop
PWM
Pulse Width Modulation
QuadDec
Quadrature Decoder; a peripheral on the 56F8367 part
Preface, Rev. 2
Freescale Semiconductor
Preliminary
ix
RAM
Random Access Memory
R/C
Resistor/Capacitor Network
ROM
Read-Only Memory
SCI
Serial Communications Interface; a peripheral on Freescale’s family of
controllers
SPI
Serial Peripheral Interface; a peripheral on Freescale’s family of controllers
SRAM
Static Random Access Memory
WS
Wait State
References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, DSP56800ERM, Freescale Semiconductor
[2] 56F8300 Peripheral User Manual, MC56F8300UM, Freescale Semiconductor
[3] 56F8367 Technical Data, MC56F8367, Freescale Semiconductor
[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,
Version 1.0, CAN in Automation
[5] CAN Specification 2.0B, BOSCH or CAN in Automation
MC56F8367EVM User Manual, Rev. 2
x
Freescale Semiconductor
Preliminary
Chapter 1
Introduction
The 56F8367EVM is used to demonstrate the abilities of the 56F8367 controller and to provide a
hardware tool allowing the development of applications.
The 56F8367EVM is an evaluation module board that includes a 56F8367 part, peripheral
expansion connectors, a CAN interface, 512KB of external memory and a pair of daughter card
connectors. The daughter card connectors are for signal monitoring and user feature
expandability.
The 56F8367EVM is designed for the following purposes:
•
Allowing new users to become familiar with the features of the 56800E architecture. The
tools and examples provided with the 56F8367EVM facilitate evaluation of the feature set
and the benefits of the family.
•
Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The
breakpoint features of the EOnCE port enable the user to easily specify complex break
conditions and to execute user-developed software at full speed until the break conditions
are satisfied. The ability to examine and modify all user-accessible registers, memory and
peripherals through the EOnCE port greatly facilitates the task of the developer.
•
Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the processor's peripherals.
The EOnCE port's unobtrusive design means that all memory on the board and on the
processor is available to the user.
Introduction, Rev. 2
Freescale Semiconductor
Preliminary
1-1
1.1 56F8367EVM Architecture
The 56F8367EVM facilitates the evaluation of various features present in the 56F8367 part. The
56F8367EVM can be used to develop real-time software and hardware products. The
56F8367EVM provides the features necessary for a user to write and debug software,
demonstrate the functionality of that software and interface with the user's application-specific
device(s). The 56F8367EVM is flexible enough to allow a user to fully exploit the 56F8367's
features to optimize the performance of his product, as shown in Figure 1-1.
CAN #1 Bus
DaisyChain
56F8367
Program Memory
128K x 16-bit
SRAM
Address,
Data &
Control
FlexCAN #1
SCI #0
Data Memory
CAN #1 Interface
CAN #1 Bus
Header
DSub
9-Pin
RS-232
Interface
128K x 16-bit
SRAM
Memory
Expansion
Connector
SPI #0
SCI #1
Timer C
Memory
Daughter Card
Connector
Timer D
PWMA
Peripheral
Expansion
Connectors
Peripheral
Daughter Card
Connector
CAN #2 Interface
CAN #2 Bus
Header
ADCA
Reset Logic
Mode/IRQ
Logic
RESET
QuadDec #0
PWMB
MODE/IRQ
ADCB
QuadDec #1
JTAG
Connector
DSub
25-Pin
FlexCAN #2
JTAG/EOnCE
Parallel
JTAG
Interface
8.00MHz
Crystal
Debug LEDs
PWM LEDs
XTAL/
EXTAL
+3.3V & GND
+3.3V A &
AGND
+3.3VREF
CAN #2 Bus
DaisyChain
Power Supply
+3.3V, +3.3V A,
+5V & +3.3VREF
Figure 1-1. Block Diagram of the 56F8367EVM
MC56F8367EVM User Manual, Rev. 2
1-2
Freescale Semiconductor
Preliminary
56F8367EVM Configuration Jumpers
1.2 56F8367EVM Configuration Jumpers
Ninteen jumper groups, (JG1-JG19), shown in Figure 1-2, are used to configure various features
on the 56F8367EVM board. Table 1-1 describes the default jumper group settings.
JG4
JG6
4 3
JG7
JG5
JG14
JG12
2 1
JG13
1
3
2 4
J20
J13
J11
J17
J18
J4
J19
J14
J5
J21
JG8
JG13
3
J22
J8
J7
PC0
PC1
PC2
PC3
PD6
PD7
J6
J14
J12
J24
JG7
JG8
JG17
1 3
J23
J2
U1
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
JG16
JG5
JG4
JG6
J1
S/N
JG15
1
J16
J15
U2
JG2
JG15
JG9
JG17
JG1
JTAG
Y1
JG12
U3
JG18
JG16
J3
JG10
3 1
J9
J10
U8
MC56F8357EVM
U4
JG11 P2
LED3
JG9
S3
RESET
S2
S1
IRQA
IRQB
U9
JG3
JG19
P1
P3
4 2
JG2
JG10
JG11
JG1
1
3
3
JG18
JG19
JG3
1
Figure 1-2. MC56F8367 Default Jumper Options
Introduction, Rev. 2
Freescale Semiconductor
Preliminary
1-3
Table 1-1. 56F8367EVM Default Jumper Options
Jumper
Group
Comment
Jumpers
Connections
JG1
Use on-board EXTAL crystal input for oscillator
1–2
JG2
Use on-board XTAL crystal input for oscillator
1–2
JG3
Enable on-board Parallel JTAG Host/Target Interface
NC
JG4
Enable Internal Boot Mode
1–2
JG5
Enable A0 - A23 for external memory accesses
NC
JG6
Enable Crystal Mode
1–2
JG7
Enable SRAM Memory Bank 0 (use CS0)
1–2
JG8
Enable SRAM Memory Bank 1 (use CS1 & CS4)
1–2 & 3–4
JG9
Pass RXD0 & TXD0 to RS-232 level converter
1–2 & 3–4
JG10
Enable RS-232 output
NC
JG11
Pass RS-232 RST to CTS
1–2
JG12
Pass Temperature Diode to ANA7
1–2
JG13
CAN #1 termination selected
1–2
JG14
Pass CAN2_TX & CAN2_RX to CAN tranceiver
JG15
High selected on User Jumper #0
1–2
JG16
High selected on User Jumper #1
1–2
JG17
CAN2 termination selected
1–2
JG18
Analog Ground to Digital Ground not reconnected
NC
JG19
Use +3.3V for Printer Interface to on-board Parallel JTAG Host/Target
1-2
1–2 & 3–4
MC56F8367EVM User Manual, Rev. 2
1-4
Freescale Semiconductor
Preliminary
56F8367EVM Connections
1.3 56F8367EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply to the 56F8367EVM board.
Parallel extension
cable
MC56F8367EVM
PC-compatible
computer
P1
Connect cable
to parallel / printer port
P3
External with 2.1mm,
+12V receptacle
power connector
Figure 1-3. Connecting the 56F8367EVM Cables
Perform the following steps to connect the 56F8367EVM cables:
1. Connect the parallel extension cable to the parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the
56F8367EVM board. This provides the connection which allows the host computer to
control the board.
3. Make sure that the external +12V DC, 1.2A power supply is not plugged into a +120V AC
power source.
4. Connect the 2.1mm output power plug from the external power supply into P3, shown in
Figure 1-3, on the 56F8367EVM board.
5. Apply power to the external power supply. The green Power-On LED, LED13, will
illuminate when power is correctly applied.
Introduction, Rev. 2
Freescale Semiconductor
Preliminary
1-5
MC56F8367EVM User Manual, Rev. 2
1-6
Freescale Semiconductor
Preliminary
Chapter 2
Technical Summary
The 56F8367EVM is designed as a versatile development card using the 56F8367 processor,
allowing the creation of real-time software and hardware products to support a new generation of
applications in servo and motor control, digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit 56F8367
processor, combined with the on-board 128K x 16-bit external Program/Data Static RAM
(SRAM), 128K x 16-bit external Data/Program SRAM, RS-232 interface, CAN interface,
daughter card interface, peripheral expansion connectors and parallel JTAG interface, makes the
56F8367EVM ideal for developing and implementing many motor controlling algorithms, as
well as for learning the architecture and instruction set of the 56F8367 processor.
The main features of the 56F8367EVM, with board and schematic reference designators, include:
•
MC56F8367VPY60, a 16-bit +3.3V/+2.5V controller operating at 60MHz [U1]
•
External Fast Static RAM (FSRAM) memory, configured as:
— 128K x 16-bit of memory [U2] with 0 wait state at 60MHz via CS0
— 128K x 16-bit of memory [U3] with 0 wait state at 60MHz via CS1/CS4
•
8.00MHz crystal oscillator, for base processor frequency generation [Y1]
•
Optional external oscillator frequency input connectors [JG1 and JG2]
•
Joint Test Action Group (JTAG) port interface connector, for an external debug Host
Target Interface [J3]
•
On-board parallel JTAG host target interface, with a connector for a PC printer port cable
[P1], including a disable jumper [JG3] and a printer port voltage selection jumper [JG19]
•
RS-232 interface, for easy connection to a host processor [U4 and P2], including a disable
jumper [JG10]
•
RTS and CTS RS-232 control signal access [JG11]
•
CAN interface, for high speed, 1.0Mbps, FlexCAN communications [U10 and J20]
•
CAN bypass and bus termination [J21 and JG13]
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-1
•
CAN #2 interface, for high speed, 1.0Mbps, FlexCAN communications [U11 and J22]
•
CAN #2 bypass and bus termination [J23 and JG17]
•
CAN #2 interface signal isolation [JG14]
•
Peripheral Daughter Card connector, to allow the user to connect his own SCI, SPI or
GPIO-compatible peripheral to the controller [J1]
•
Memory Daughter Card connector, to allow the user to connect his own memory or
memory device to the device [J2]
•
SCI #0 expansion connector, to allow the user to connect his own SCI #0 /
MPIO-compatible peripheral [J13]
•
SCI #1 expansion connector, to allow the user to connect his own SCI #1 /
MPIO-compatible peripheral [J14]
•
SPI #0 expansion connector, to allow the user to connect his own SPI #0 /
MPIO-compatible peripheral [J11]
•
SPI #1 expansion connector, to allow the user to connect his own SPI #1 /
MPIO-compatible peripheral [J12]
•
PWMA expansion connector, to allow the user to connect his own PWMA-compatible
peripheral [J7]
•
PWMB expansion connector, to allow the user to connect his own PWMB-compatible
peripheral [J8]
•
CAN #1 expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J18]
•
CAN #2 expansion connector, to allow the user to connect his own CAN physical layer
peripheral [J19]
•
Timer A expansion connector, to allow the user to connect his own Timer A / Encoder
#0-compatible peripheral [J15]
•
Timer C expansion connector, to allow the user to connect his own Timer C-compatible
peripheral [J16]
•
Timer D expansion connector, to allow the user to connect his own Timer D-compatible
peripheral [J17]
•
ADC A expansion connector, to allow the user to attach his own A/D Port A-compatible
peripheral [J9]
•
ADC B expansion connector, to allow the user to attach his own A/D Port B-compatible
peripheral [J10]
MC56F8367EVM User Manual, Rev. 2
2-2
Freescale Semiconductor
Preliminary
•
Address bus expansion connector, to allow the user to monitor the external address bus
[J4]
•
Data bus expansion connector, to allow the user to monitor the external data bus [J5]
•
External memory bus control signal connector, to allow the user to monitor the external
memory bus [J6]
•
On-board power regulation provided from an external +12V DC-supplied power input
[P3]
•
Light Emitting Diode (LED) power indicator [LED13]
•
Six on-board real-time user debugging LEDs [LED1 - 6]
•
Six on-board Port A PWM monitoring LEDs [LED7 - 12]
•
Internal/external (EXTBOOT) boot mode selector [JG4]
•
Address range (EMI_MODE) boot mode selector [JG5]
•
Clock mode (CLKMODE) boot selector [JG6]
•
Temperature sense diode to ANA7 selector [JG12]
•
Manual reset push button [S1]
•
Manual interrupt push button for IRQA [S2]
•
Manual interrupt push button for IRQB [S3]
•
General-purpose jumper on GPIO PE4 [JG15]
•
General-purpose jumper on GPIO PE7 [JG16]
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-3
2.1 MC56F8367
The 56F8367EVM uses a Freescale MC56F8367VPY60 part, designated as U1 on the board and
in the schematics. This part will operate at a maximum external bus speed of 60MHz. A full
description of the 56F8367, including functionality and user information, is provided in these
documents:
•
56F8367 Technical Data Sheet, (MC56F8367): Electrical and timing specifications, pin
descriptions, device-specific peripheral information and package descriptions (this
document)
•
56F8300 Peripheral User Manual, (MC56F8300UM): Detailed description of peripherals
of the 56F8300 family of devices
•
DSP56800E Reference Manual, (DSP56800ERM): Detailed description of the 56800E
family architecture, 16-bit core processor, and the instruction set
Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:
www.freescale.com
2.2 Program and Data Memory
The 56F8367EVM contains two 128K x 16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS4. This provides a total of
256K x 16 bits of external memory.
MC56F8367EVM User Manual, Rev. 2
2-4
Freescale Semiconductor
Preliminary
Program and Data Memory
2.2.1 SRAM Bank 0
SRAM bank 0, which is controlled by CS0, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U2) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-1. CS0 can be configured to use this memory bank as 16 bits of Program memory, Data
memory, or both. Additionally, CS0 can be configured to assign this memory’s size and starting
address to any modulo address space.
This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumper at JG7.
MC56F8367
GS72116
A0 - A16
A0 - A16
D0 - D15
DQ0 - DQ15
RD
OE
WR
WE
PS / CS0
+3.3V
JG7
1
2
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
CE
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-5
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K x 16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-2. Using CS1 and CS4, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable Program memory, Data memory, or both. Additionally, CS1 and CS4 can be
configured to assign this memory’s size and starting address to any modulo address space.
This memory bank will operate with zero wait state access while the 56F8367 is running at
60MHz and can be disabled by removing the jumpers at JG8.
MC56F8367
GS72116
A0 - A16
A0 - A16
D0 - D15
DQ0 - DQ15
OE
RD
WR
JG8
DS / CS1
1 2
PD2 / CS4
3 4
WE
LB
HB
CE
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte
Figure 2-2. Schematic Diagram of the External CS1 / CS4 Memory Interface
MC56F8367EVM User Manual, Rev. 2
2-6
Freescale Semiconductor
Preliminary
RS-232 Serial Communications
2.3 RS-232 Serial Communications
The 56F8367EVM provides an RS-232 interface by the use of an RS-232 level converter, Maxim
MAX3245EEAI, designated as U4. Refer to the RS-232 schematic diagram in Figure 2-3. The
RS-232 level converter transitions the SCI port’s +3.3V signal levels to RS-232-compatible
signal levels and connects to the host’s serial port via connector P2. RTS/CTS flow control is
provided on JG11 as a jumper, but could be implemented using uncommitted GPIO signals. The
SCI port #0 signals can be isolated from the RS-232 level converter by removing the jumpers in
JG9; see Table 2-1. The pin-out of connector P2 is listed in Table 2-2. The RS-232 level
converter/transceiver can be disabled by placing a jumper at JG10.
RS-232
Level Converter
Interface
MC56F8367
JG9
TXD0
1
2
RXD0
3
4
TXD
T1 in
RXD
R1 out
R1 in
RTS
T2 in
R2 in
CTS
R2 out
P2
1
6
2
7
3
8
4
T1 out
JG11
1
2
T2 out
x
9
5
+3.3V
FORCEOFF
Jumper Removed:
Enable RS-232
Jumper Pin 1-2:
Disable RS-232
JG10
1
2
Figure 2-3. Schematic Diagram of the RS-232 Interface
Table 2-1. SCI #0 Jumper Options
JG9
Pin #
Signal
Pin #
Signal
1
TXD0
2
RS-232 TXD
3
RXD0
4
RS-232 RXD
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-7
Table 2-2. RS-232 Serial Connector Description
P2
Pin #
Signal
Pin #
Signal
1
Jumper to 6 & 4
6
Jumper to 1 & 4
2
TXD
7
CTS
3
RXD
8
RTS
4
Jumper to 1 & 6
9
NC
5
GND
2.4 Clock Source
The 56F8367EVM uses an 8.00MHz crystal, Y1, connected to its external crystal inputs, EXTAL
and XTAL. To achieve its maximum internal operating frequency, the 56F8367 uses its internal
PLL to multiply the input frequency. An external oscillator source can be connected to the
processor by using the oscillator bypass connectors, JG1 and JG2; see Figure 2-4. If the input
frequency is above 8MHz, then the EXTAL input should be jumpered to ground by adding a
jumper between JG1 pins 2 and 3. The input frequency would then be injected on JG2’s pin 2. If
the input frequency is below 4MHz, then the input frequency can be injected on JG1’s pin 2.
External
Oscillator
Headers
MC56F8367
JG1
1
2
EXTAL
3
8.00MHz
JG2
1
2
XTAL
Figure 2-4. Schematic Diagram of the Clock Interface
MC56F8367EVM User Manual, Rev. 2
2-8
Freescale Semiconductor
Preliminary
Operating Mode
2.5 Operating Mode
The 56F8367EVM provides three boot mode selection jumpers, EXTBOOT, EMI_MODE and
CLKMODE, to provide boot-up mode options.
2.5.1 EXTBOOT
The 56F8367EVM provides an external/internal boot mode jumper, JG4. This jumper is used to
select the internal or external memory operation of the processor as it exits reset. Refer to the
56F8300 Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete
description of the chip’s operating modes. Table 2-3 shows the two external boot operation
modes available on the 56F8367.
Table 2-3. EXTBOOT Operating Mode Selection
Operating Mode
JG4
Comment
0
1-2
3
No Jumper
Bootstrap from internal memory (GND)
Bootstrap from external memory (+3.3V)
2.5.2 EMI_MODE
The 56F8367EVM provides an EMI boot mode jumper, JG5. This jumper is used to select the
external memory addressing range operating mode of the processor as it exits reset. The user can
select between a 64K address space or an 8M address space. Refer to the 56F8300 Peripheral
User Manual and the 56F8367 Technical Data Sheet for a complete description of the chip’s
operating modes. Table 2-4 shows the two EMI operation modes available on the 56F8367.
Table 2-4. EMI Operating Mode Selection
Operating Mode
JG5
Comment
V1
1-2
A0 - A15 (64K) available for external memory bus (GND)
V2
No Jumper
A0 - A23 (8M) available for external memory bus (+3.3V)
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-9
2.5.3 CLKMODE
The 56F8367EVM provides a clock boot mode jumper, JG6. This jumper is used to select the
type of clock source being provided to the processor as it exits reset. The user can select between
the use of a crystal or an oscillator as the clock source for the processor. Refer to the 56F8300
Peripheral User Manual and the 56F8367 Technical Data Sheet for a complete description of
the chip’s operating modes. Table 2-5 shows the two CLKMODE operation modes available on
the 56F8367.
Table 2-5. EMI Operating Mode Selection
Operating Mode
JG6
Comment
Crystal
1-2
Enables the external clock drive logic so an external
crystal can be used as the input clock source. (GND)
Oscillator
No Jumper
Disables the external clock drive logic. Use oscillator
input on XTAL and Ground on EXTAL. (3.3V)
2.6 Debug LEDs
Six on-board Light Emitting Diodes, (LEDs), are provided to allow real-time debugging for user
programs. These LEDs will allow the programmer to monitor program execution without having
to stop the program during debugging; refer to Figure 2-5. Table 2-6 describes the control of
each LED.
Table 2-6. LED Control
Controlled by
User LED
Color
Signal
LED1
RED
Port C Bit 0 (PC0)
LED2
YELLOW
Port C Bit 1 (PC1)
LED3
GREEN
Port C Bit 2 (PC2)
LED4
RED
Port C Bit 3 (PC3)
LED5
YELLOW
Port D Bit 6 (PD6)
LED6
GREEN
Port D Bit 7 (PD7)
MC56F8367EVM User Manual, Rev. 2
2-10
Freescale Semiconductor
Preliminary
Debug Support
Setting PC0, PC1, PC2, PC3, PD6, or PD7 to a Logic One value will turn on the associated LED.
MC56F8367
INVERTING BUFFER
+3.3V
RED LED
PC0
YELLOW LED
PC1
GREEN LED
PC2
RED LED
PC3
YELLOW LED
PD6
GREEN LED
PD7
Figure 2-5. Schematic Diagram of the Debug LED Interface
2.7 Debug Support
The 56F8367EVM provides an on-board parallel JTAG host target interface and a JTAG
interface connector for external target interface support. Two interface connectors are provided to
support each of these debugging approaches. These two connectors are designated the JTAG
connector and the host parallel interface connector.
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-11
2.7.1 JTAG Connector
The JTAG connector on the 56F8367EVM allows the connection of an external host target
interface for downloading programs and working with the 56F8367’s registers. This connector is
used to communicate with an external host target interface, which passes information and data
back and forth with a host processor running a debugger program. Table 2-7 shows the pin-out
for this connector.
Table 2-7. JTAG Connector Description
J3
Pin #
Signal
Pin #
Signal
1
TDI
2
GND
3
TDO
4
GND
5
TCK
6
GND
7
NC
8
KEY
9
RESET
10
TMS
11
+3.3V
12
NC
13
DE
14
TRST
When this connector is used with an external host target interface, the parallel JTAG interface
should be disabled by placing a jumper in jumper block JG3. Reference Table 2-8 for this
jumper’s selection options.
Table 2-8. Parallel JTAG Interface Disable Jumper Selection
JG3
Comment
No jumpers
Enables On-board Parallel JTAG Interface
1-2
Disables on-board Parallel JTAG Interface
MC56F8367EVM User Manual, Rev. 2
2-12
Freescale Semiconductor
Preliminary
Debug Support
2.7.2 Parallel JTAG Interface Connector
The Parallel JTAG Interface Connector, P1, allows the 56F8367 to communicate with a parallel
printer port on a Windows PC; reference Figure 2-6. Using this connector, the user can
download programs and work with the 56F8367’s registers. Table 2-9 shows the pin-out for this
connector. When using the parallel JTAG interface, the jumper at JG3 should be removed, as
shown in Table 2-8. The printer port interface voltage of +3.3V or +5.0V can be selected by a
jumper on JG19, as shown in Table 2-10.
DB-25 Connector
Parallel JTAG Interface
MC56F8367
IN
OUT
OUT
IN
IN
OUT
TDI
TDO
TRST
TMS
IN
OUT
TMS
TCK
IN
OUT
TCK
P_RESET
IN
OUT
RESET
P_DE
IN
OUT
DE
EN
Vcc
TDI
TDO
P_TRST
+3.3V
Jumper Removed:
Enable JTAG I/F
Jumper Pin 1-2:
Disable JTAG I/F
JG3
1
2
JG19
1
2
3
+3.3V
+5.0V
Figure 2-6. Block Diagram of the Parallel JTAG Interface
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-13
Table 2-9. Parallel JTAG Interface Connector Description
P1
Pin #
Signal
Pin #
Signal
1
NC
14
NC
2
PORT_RESET
15
PORT_IDENT
3
PORT_TMS
16
NC
4
PORT_TCK
17
NC
5
PORT_TDI
18
GND
6
PORT_TRST
19
GND
7
PORT_DE
20
GND
8
PORT_IDENT
21
GND
9
PORT_VCC
22
GND
10
NC
23
GND
11
PORT_TDO
24
GND
12
NC
25
GND
13
PORT_CONNECT
Table 2-10. Parallel JTAG Interface Voltage Jumper Selection
JG19
Comment
1-2
Interface with the PC’s printer port using +3.3V signals
2-3
Interface with the PC’s printer port using +5.0V signals
MC56F8367EVM User Manual, Rev. 2
2-14
Freescale Semiconductor
Preliminary
External Interrupts
2.8 External Interrupts
Two on-board push button switches are provided for external interrupt generation, as shown in
Figure 2-7. S2 allows the user to generate a hardware interrupt for signal line IRQA. S3 allows
the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user
to generate interrupts for his user-specific programs.
+3.3V
MC56F8367
10K
S2
IRQA
0.1µF
+3.3V
10K
S3
IRQB
0.1µF
Figure 2-7. Schematic Diagram of the User Interrupt Interface
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-15
2.9 Reset
Logic is provided on the 56F8367 to generate an internal power-on reset. Additional reset logic is
provided to support the reset signals from the JTAG connector, the parallel JTAG interface and
the user reset push button, S1; refer to Figure 2-8.
JTAG_RESET
RESET
RESET
PUSHBUTTON
MANUAL RESET
S1
JTAG_TAP_RESET
TRST
Figure 2-8. Schematic Diagram of the Reset Interface
MC56F8367EVM User Manual, Rev. 2
2-16
Freescale Semiconductor
Preliminary
Power Supply
2.10 Power Supply
The main power input to the 56F8367EVM, +12V DC at 1.2A, is through a 2.1mm coax power
jack. This input power is rectified to provide a DC supply input. This allows a user the option to
use a +12V AC power supply. A 1.2 Amp power supply is provided with the 56F8367EVM;
however, less than 500mA is required by the EVM. The remaining current is available for custom
control applications when connected to the daughter card connectors. The 56F8367EVM
provides +5.0V DC regulation for the CAN interface and additional regulators. The
56F8367EVM provides +3.3V DC voltage regulation for the processor, memory, D/A, ADC,
parallel JTAG interface and supporting logic; refer to Figure 2-9. Additional voltage regulation
logic provides a low-noise +3.3V DC voltage reference to the processor’s A/D VREFH. A jumper,
JG18, and resistor, R66, are provided to allow the analog and digital grounds to be isolated on the
56F8367EVM board. This allows the analog ground reference point to be provided on a custom
board attached to the 56F8367EVM daughter card connectors. By removing R66, the AGND
reference is disconnected from the 56F8367EVM’s digital ground. By placing a jumper on JG18,
the AGND is reconnected to the 56F8367EVM’s digital ground. Power applied to the
56F8367EVM is indicated with a power-on LED, referenced as LED13. Optionally, the user can
provide the +2.5 DC voltage needed by the processor’s core on connector J24 and disable the
on-chip core voltage regulator by moving the resistor at R72 to R71. Additonally, four zero ohm
resistors or shorting wires must be added at R67, R68, R69, and R70 to allow the external +2.5V
DC to pass to the 56F8367.
+12V DC/AC
P3
Bridge
Rectifier
Input
+5.0V
Regulator
Power
Condition
+5.0V DC
+3.3V
Regulator
+3.3V DC
CAN
56F8367
VDD_IO & PLL
56F8367EVM
Parts
J24
+2.5V DC
Ext In
1
R67 - R70
56F8367
VDD Core
+3.3VA DC
56F8367
ADC
+3.3VA DC
56F8367
VREFH
2
Power On
+3.3V
Regulator
U15
+3.3V
Regulator
Figure 2-9. Schematic Diagram of the Power Supply
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-17
2.11 Daughter Card Connectors
The EVM board contains two daughter card connectors. One connector, J1, contains the
processor’s peripheral port signals. The second connector, J2, contains the processor’s external
memory bus signals.
2.11.1 Peripheral Daughter Card Connector
The processor’s peripheral port signals are connected to the peripheral daughter card connector,
J1. The peripheral daughter card connector is used to connect a daughter card or a user-specific
daughter card to the processor’s peripheral port signals. The peripheral port daughter card
connector is a 100-pin high-density connector with signals for the IRQs, reset, SPI, SCI, PWM,
ADC and Quad Timer ports. Table 2-11 shows the peripheral daughter card connector’s
signal-to-pin assignments.
Table 2-11. Peripheral Daughter Card Connector Description
J1
Pin #
Signal
Pin #
Signal
1
+12V
2
+12V
3
GND
4
GND
5
+5.0V
6
+5.0V
7
GND
8
GND
9
+3.3V
10
+3.3V
11
GND
12
GND
13
PHASEA0 / TA0 / PC4
14
PHASEB0 / TA1 / PC5
15
INDEX0 / TA2 / PC6
16
HOME0 / TA3 / PC7
17
GND
18
GND
19
PHASEA1 / PC0 / TB0 / SCLK1
20
PHASEB1 / PC1 / TB1 / MOSI1
21
INDEX1 / PC2 / TB2 / MISO1
22
HOME1 / PC3 / TB3 / SS1
23
TXD0 / PE0
24
TXD1 / PD6
25
TXD0 / PE0
26
TXD1 / PD6
27
RXD0 / PE1
28
RXD1 / PD7
MC56F8367EVM User Manual, Rev. 2
2-18
Freescale Semiconductor
Preliminary
Daughter Card Connectors
Table 2-11. Peripheral Daughter Card Connector Description (Continued)
J1
Pin #
Signal
Pin #
Signal
29
IRQA
30
IRQB
31
RXD0 / PE1
32
RXD1 / PD7
33
PWMB0
34
PWMB1
35
PWMB2
36
PWMB3
37
PWMB4
38
PWMB5
39
GND
40
GND
41
ISB0 / PD10
42
ISB1 / PD11
43
ISB2 / PD12
44
GND
45
FAULTB1
46
FAULTB0
47
FAULTB3
48
FAULTB2
49
GND
50
GND
51
PWMA0
52
PWMA1
53
PWMA2
54
PWMA3
55
PWMA4
56
PWMA5
57
GND
58
GND
59
FAULTA0
60
FAULTA1
61
FAULTA2
62
MISO0 / PE6
63
ISA0 / PC8
64
ISA1 / PC9
65
ISA2 / PC10
66
RSTO
67
MOSI0 / PE5
68
SS0 / PE7
69
TD0 / PE10
70
TD1 / PE11
71
SCLK0 / PE7
72
TC0 / PE8
73
CAN_TX
74
CAN_RX
75
MOSI0 / PE5
76
MISO0 / PE6
77
SCLK0 / PE4
78
SS0 / PE7
79
GND
80
GND
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-19
Table 2-11. Peripheral Daughter Card Connector Description (Continued)
J1
Pin #
Signal
Pin #
Signal
81
+VREFH
82
+VREFH
83
GNDA
84
GNDA
85
AN0
86
AN1
87
AN2
88
AN3
89
AN4
90
AN5
91
AN6
92
AN7
93
AN8
94
AN9
95
AN10
96
AN11
97
AN12
98
AN13
99
AN14
100
AN15
2.11.2 Memory Daughter Card Connector
The processor’s external memory bus signals are connected to the memory daughter card
connector, J2. Table 2-12 shows the port signal-to-pin assignments.
Table 2-12. Memory Daughter Card Connector Description
J2
Pin #
Signal
Pin #
Signal
1
A4 / PA12
2
A5 / PA13
3
A3 / PA11
4
A6 / PE2
5
A2 / PA10
6
A7 / PE3
7
A1 / PA9
8
RD
9
GND
10
GND
11
A0 / PA8
12
DS / CS1
13
PS / CS0
14
PD0 / CS2 / CAN2_TX
MC56F8367EVM User Manual, Rev. 2
2-20
Freescale Semiconductor
Preliminary
Daughter Card Connectors
Table 2-12. Memory Daughter Card Connector Description (Continued)
J2
Pin #
Signal
Pin #
Signal
15
D0 / PF9
16
D15 / PF8
17
D1 / PF10
18
D14 / PF7
19
GND
20
GND
21
GND
22
GND
23
D2 / PF11
24
D13 / PF6
25
D3 / PF12
26
D12 / PF5
27
D4 / PF13
28
D11 / PF4
29
D5 / PF14
30
D10 / PF3
31
GND
32
GND
33
GND
34
GND
35
D6 / PF15
36
D9 / PF2
37
D7 / PF0
38
D8 / PF1
39
WR
40
PD1 / CS3 / CAN2_RX
41
A15 / PA7
42
A8 / PA0
43
GND
44
GND
45
A14 / PA6
46
A9 / PA1
47
A13 / PA5
48
A10 / PA2
49
A12 / PA4
50
A11 / PA3
51
PB0 / A16
52
GND
53
GND
54
GND
55
+3.3V
56
+3.3V
57
GND
58
GND
59
+5.0V
60
+5.0V
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-21
2.12 Motor Control PWM Signals and LEDs
The 56F8367 has two independent groups of dedicated PWM units. Each unit contains six PWM,
three phase current sense inputs and four fault input lines. PWM group A’s PWM lines are
connected to a set of six PWM LEDs via inverting buffers. The buffers are used to isolate and
drive the Processor’s PWM group A’s outputs to the PWM LEDs. The PWM LEDs indicate the
status of PWM group A signals; refer to Figure 2-10. PWM Group A and B signals are routed
out to headers, J7 and J8 respectively, and to the peripheral daughter card connector for easy use
by the end user.
56F8367
PWMA0
PWMA0
PWMA1
PWMA1
PWMA2
PWMA2
PWMA3
PWMA3
PWMA4
PWMA4
PWMA5
PWMA5
+3.3V
LED
Buffer
Yellow LED
LED7
Green LED
LED8
Yellow LED
LED9
Green LED
LED10
Yellow LED
LED11
Phase C Top
Green LED
LED12
Phase C Bottom
Phase A Top
Phase A Bottom
Phase B Top
Phase B Bottom
Figure 2-10. PWM Group A Interface and LEDs
MC56F8367EVM User Manual, Rev. 2
2-22
Freescale Semiconductor
Preliminary
CAN Interfaces
2.13 CAN Interfaces
The 56F8367EVM board contains two FlexCAN interfaces. The primary CAN interface uses the
CAN1_RX and CAN1_TX pins on the 56F8367. The secondary CAN interface uses the
CAN2_RX and CAN2_TX pins on the 56F8367.
2.13.1 FlexCAN #1 Interface
The 56F8367EVM board contains a CAN physical-layer interface chip that is attached to the
FlexCAN port’s CAN1_RX and CAN1_TX pins on the 56F8367. The EVM board uses a Phillips
high-speed, 1.0Mbps, physical layer interface chip, PCA82C250. Due to the +5.0V operating
voltage of the CAN interface chip, a pull-up to +5.0V is required to level shift the transmit data
output line from the 56F8367. The CANH and CANL signals pass through inductors before
attaching to the CAN bus connectors. A primary, J20, and daisy-chain, J21, CAN connector are
provided to allow easy daisy-chaining of CAN devices. CAN bus termination of 120 ohms can be
provided by adding a jumper to JG13. Refer to Table 2-14 for the CAN connector signals and
Figure 2-12 for a connection diagram.
+5.0V
MC56F8367
1K
CAN1_TX
CAN1_RX
CAN Transceiver
TXD
J20
CANH
4
CANL
3
CAN #1 Bus
Connector
5
RXD
J21
PCA82C250
Daisy-Chain CAN #1
Connector
4
5
3
JG13
1
2
CAN Bus #1
Terminator
120
Figure 2-11. CAN #1 Interface
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-23
Table 2-13. CAN #1 Header Description
J20 and J21
Pin #
Signal
Pin #
Signal
1
NC
2
NC
3
CANL
4
CANH
5
GND
6
NC
7
NC
8
NC
9
NC
10
NC
2.13.2 FlexCAN #2 Interface
The 56F8367EVM board contains a second FlexCAN port, the CAN2_RX and CAN2_TX pins
on the 56F8367. These signals pass through an isolation jumper, JG14, before going to the CAN
physical layer interface. The EVM board uses a Phillips high-speed, 1.0Mbps, physical layer
interface chip, PCA82C250. Due to the +5.0V operating voltage of the CAN interface chip, a pull
up to +5.0V is required to level shift the transmit data output line from the 56F8367. The CAN2H
and CAN2L signals pass through inductors before attaching to the CAN bus connectors. A
primary, J22, and daisy-chain, J23, CAN connector are provided to allow easy daisy-chaining of
CAN devices. CAN bus termination of 120 ohms can be provided by adding a jumper to JG17.
Refer to Figure 2-12 for a connection diagram and to Table 2-14 and Table 2-15 for the CAN
connector signals.
MC56F8367EVM User Manual, Rev. 2
2-24
Freescale Semiconductor
Preliminary
CAN Interfaces
+5.0V
MC56F8367
1K
JG14
PD0 / CAN2_TX
1
PD1 / CAN2_RX
3
2
CAN Transceiver
TXD
4
J22
CANH
4
CANL
3
CAN #2 Bus
Connector
5
RXD
J23
PCA82C250
Daisy-Chain
CAN #2
Connector
4
5
3
JG17
1
2
CAN #2 Bus
Terminator
120
Figure 2-12. CAN #2 Interface
Table 2-14. CAN #2 Header Description
J22 and J23
Pin #
Signal
Pin #
Signal
1
NC
2
NC
3
CAN2L
4
CAN2H
5
GND
6
NC
7
NC
8
NC
9
NC
10
NC
Table 2-15. CAN #2 Pass-Through Jumper Description
JG14
Pin #
Signal
Pin #
Signal
1
PD0
2
CAN2_TX
3
PD1
4
CAN2_RX
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-25
2.14 Software Feature Jumpers
The 56F8367EVM board contains two software feature jumpers that allow the user to select
user-defined software features. Two GPIO port pins, PE4 and PE7, are pulled high or low with
10K ohm resistors on JG15 and JG16. Attaching a jumper between pins 1 and 2 will place a high
or 1 on the port pin. Attaching a jumper between pins 2 and 3 will place a low or 0 on the port
pin; see Figure 2-13.
MC56F8367
JG15
SCLK0 / PE4
2
10K
+3.3V
User Jumper
#0
1
3
10K
JG16
SS0 / PE7
2
1
10K
+3.3V
3
User Jumper
#1
10K
Figure 2-13. Software Feature Jumpers
MC56F8367EVM User Manual, Rev. 2
2-26
Freescale Semiconductor
Preliminary
Peripheral Expansion Connectors
2.15 Peripheral Expansion Connectors
The EVM board contains a group of peripheral expansion connectors used to gain access to the
resources of the 56F8367. The following signal groups have expansion connectors:
•
External Memory Address Bus (A0 - A23)
General Purpose Port A (bits 0 - 13)
General Purpose Port E (bits 2 & 3)
General Purpose Port B (bit 0 - 7)
•
External Memory Data Bus (D0 - D15)
General Purpose Port F (bits 0 - 15)
•
External Memory Control
General Purpose Port D (bits 0 - 5, 8 & 9)
•
Quadrature Decoder #0
Quad Timer Channel A
•
Quadrature Decoder #1
Serial Peripheral Interface Port #1
Quad Timer Channel B
General Purpose Port C (bits 0 - 3)
•
Quad Timer Channel C
General Purpose Port E (bits 8 & 9)
•
Quad Timer Channel D
General Purpose Port E (bits 10 - 13)
•
A/D Input Port A
•
A/D Input Port B
•
Serial Communications Port #0 / General Purpose Port E (bits 0 and 1)
•
Serial Communications Port #1 / General Purpose Port D (bits 6 and 7)
•
Serial Peripheral Interface Port #0 / General Purpose Port E (bits 4 - 7)
•
PWM Port A / General Purpose Port C (bits 8 - 10)
•
PWM Port B / General Purpose Port C (bits 0 - 3)
•
CAN Port #1
•
CAN Port #2
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-27
2.15.1 Address Bus Expansion Connector
The address bus expansion connector contains the 56F8367’s 24 external memory address signal
lines. Address lines A6 and A7 can optionally be used as GPIO Port E lines (bits 2 and 3).
Address lines A8 - A15 can optionally be used as GPIO Port A lines (bits 0 - 7). Address lines
A0 - A5 can optionally be used as GPIO Port A lines (bits 8 - 13). Address lines A16 - A23 are
MPIO signals, which can be configured as A16 - A23 or GPIO Port B bits 0 - 7. Refer to
Table 2-16 for the address bus connector information.
Table 2-16. External Memory Address Bus Connector Description
J4
Pin #
Signal
Pin #
Signal
1
A0 / PA8
2
A1 / PA9
3
A2 / PA10
4
A3 / PA11
5
A4 / PA12
6
A5 / PA13
7
A6 / PE2
8
A7 / PE3
9
A8 / PA0
10
A9 / PA1
11
A10 / PA2
12
A11 / PA3
13
A12 / PA4
14
A13 / PA5
15
A14 / PA6
16
A15 / PA7
17
PB0 / A16
18
PB1 / A17
19
PB2 / A18
20
PB3 / A19
21
PB4 / A20
22
PB5 / A21
23
PB6 / A22
24
PB7 / A23
19
GND
20
+3.3V
MC56F8367EVM User Manual, Rev. 2
2-28
Freescale Semiconductor
Preliminary
Peripheral Expansion Connectors
2.15.2 Data Bus Expansion Connector
The data bus expansion connector contains the 56F8367’s 16 external memory data signal lines.
Refer to Table 2-17 for the data bus connector information. Data lines D0 - D15 can also be used
as GPIO Port F lines (bits 0 - 15).
Table 2-17. External Memory Address Bus Connector Description
J5
Pin #
Signal
Pin #
Signal
1
D0 / PF9
2
D1 / PF10
3
D2 / PF11
4
D3 / PF12
5
D4 / PF13
6
D5 / PF14
7
D6 / PF15
8
D7 / PF0
9
D8 / PF1
10
D9 / PF2
11
D10 / PF3
12
D11 / PF4
13
D12 / PF5
14
D13 / PF6
15
D14 / PF7
16
D15 / PF8
17
GND
18
+3.3V
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-29
2.15.3 External Memory Control Signal Expansion Connector
The external memory control signal connector contains the 56F8367’s external memory control
signal lines. CS2 and CS3 are MPIO signals, which can be configured as GPIO Port D lines (bits
0 and 1). Refer to Table 2-18 for the names of these signals.
Table 2-18. External Memory Control Signal Connector Description
J6
Pin #
Signal
Pin #
Signal
1
RD
2
IRQA
3
WR
4
IRQB
5
PS / CS0
6
DS / CS1
7
PD0 / CS2 / CAN2_TX
8
PD1 / CS3 / CAN2_RX
PD2 / CS4
PD3 / CS5
PD4 / CS6
PD5 / CS7
9
CLKO
10
RESET
11
GND
12
RSTO
2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector
The Encoder #0 / Quad Timer Channel A port is an MPIO port attached to the Timer A expansion
connector. This port can be configured as a Quadrature Decoder interface port or as a Quad
Timer port. Refer to Table 2-19 for the signals attached to the connector.
Table 2-19. Timer A Signal Connector Description
J15
Pin #
Signal
Pin #
Signal
1
PHASEA0 / TA0
2
PHASEB0 / TA1
3
INDEX0 / TA2
4
HOME0 / TA3
5
GND
6
+3.3V
MC56F8367EVM User Manual, Rev. 2
2-30
Freescale Semiconductor
Preliminary
Peripheral Expansion Connectors
2.15.5 Encoder #1 / SPI #1 Expansion Connector
The Encoder #1 / SPI #1 port is an MPIO port attached to the SPI #1 expansion connector. This
port can be configured as a Quadrature Decoder interface port, a Serial Peripherial Interface,
Quad Timer port or General Purpose I/O port. Refer to Table 2-20 for the signals attached to the
connector.
Table 2-20. SPI #1 Signal Connector Description
J12
Pin #
Signal
Pin #
Signal
1
PHASEB1 / MOSI1 / TB1 / PC1
2
INDEX1 / MISO1 / TB2 / PC2
3
PHASEA1 / SCLK1 / TB0 / PC0
4
HOME1 / SS1 / TB3 / PC3
5
GND
6
+3.3V
2.15.6 Timer Channel C Expansion Connector
The Timer Channel C port is a Quad Timer port attached to the Timer C expansion connector.
This port can be configured as a Quad Timer port or a General Purpose I/O port. Refer to
Table 2-21 for the signals attached to the connector.
Table 2-21. Timer Channel C Connector Description
J16
Pin #
Signal
Pin #
Signal
1
TC0 / PE8
2
TC1 / PE9
3
GND
4
+3.3V
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-31
2.15.7 Timer Channel D Expansion Connector
The Timer Channel D port is a Quad Timer attached to the Timer D expansion connector. This
port can be configured as a Quad Timer port or a General Purpose I/O port. Refer to Table 2-22
for the signals attached to the connector.
Table 2-22. Timer Channel D Connector Description
J17
Pin #
Signal
Pin #
Signal
1
TD0 / PE10
2
TD1 / PE11
3
TD2 / PE12
4
TD3 / PE13
3
GND
4
+3.3V
MC56F8367EVM User Manual, Rev. 2
2-32
Freescale Semiconductor
Preliminary
Peripheral Expansion Connectors
2.15.8 A/D Port A Expansion Connector
The eight-channel Analog-to-Digital conversion Port A is attached to this connector. Refer to
Table 2-23 for connection information. There is a Resistor/Connector (R/C) network on each of
the Analog Port A input signals; see Figure 2-14.
Table 2-23. A/D Port A Connector Description
J9
Pin #
Signal
Pin #
Signal
1
AN0
2
AN1
3
AN2
4
AN3
5
AN4
6
AN5
7
AN6
8
AN7
9
GNDA
10
+VREFH
100 ohm
To Processor’s Analog
Port
Analog Input
0.0022uF
Figure 2-14. Typical Analog Input RC Filter
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-33
2.15.9 A/D Port B Expansion Connector
The eight-channel Analog-to-Digital conversion Port B is attached to this connector. Refer to
Table 2-24 for connection information. There is an R/C network on each of the Analog Port B
input signals; see Figure 2-14.
Table 2-24. A/D Port B Connector Description
J10
Pin #
Signal
Pin #
Signal
1
AN8
2
AN9
3
AN10
4
AN11
5
AN12
6
AN13
7
AN14
8
AN15
9
GNDA
10
+VREFH
2.15.10 Serial Communications Port #0 Expansion Connector
The Serial Communications Port #0 is an MPIO port attached to the SCI #0 expansion connector.
This port can be configured as a Serial Communications Interface or as a General Purpose I/O
port. Refer to Table 2-25 for connection information.
Table 2-25. SCI #0 Connector Description
J13
Pin #
Signal
Pin #
Signal
1
TXD0 / PE0
2
RXD0 / PE1
3
GND
4
+3.3V
5
GND
6
+5.0V
MC56F8367EVM User Manual, Rev. 2
2-34
Freescale Semiconductor
Preliminary
Peripheral Expansion Connectors
2.15.11 Serial Communications Port #1 Expansion Connector
The Serial Communications Port #1 is an MPIO port attached to the SCI #1 expansion connector.
This port can be configured as a Serial Communications Interface or as a General Purpose I/O
port. Refer to Table 2-26 for connection information.
Table 2-26. SCI #1 Connector Description
J14
Pin #
Signal
Pin #
Signal
1
TXD1 / PD6
2
RXD1 / PD7
3
GND
4
+3.3V
5
GND
6
+5.0V
2.15.12 Serial Peripheral Interface #0 Expansion Connector
The Serial Peripheral Interface #0 is an MPIO port attached to this connector. This port can be
configured as a Serial Peripheral Interface or as a General Purpose I/O port. Refer to Table 2-27
for the connection information.
Table 2-27. SPI #0 Connector Description
J11
Pin #
Signal
Pin #
Signal
1
MOSI0 / PE5
2
MISO0 / PE6
3
SCLK0 / PE4
4
SS0 / PE7
5
GND
6
+3.3V
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-35
2.15.13 FlexCAN #1 Expansion Connector
The FlexCAN Port #1 is attached to this connector. Refer to Table 2-28 for connection
information.
Table 2-28. CAN #1 Connector Description
J18
Pin #
Signal
Pin #
Signal
1
CAN1_TX
2
GND
3
CAN1_RX
4
GND
2.15.14 FlexCAN #2 Expansion Connector
The FlexCAN Port #2 is attached to this connector. Refer to Table 2-29 for connection
information.
Table 2-29. CAN #2 Connector Description
J19
Pin #
Signal
Pin #
Signal
1
CAN2_TX
2
GND
3
CAN2_RX
4
GND
MC56F8367EVM User Manual, Rev. 2
2-36
Freescale Semiconductor
Preliminary
Peripheral Expansion Connectors
2.15.15 PWM Port A Expansion Connector
The PWM Port A is attached to this connector. Refer to Table 2-30 for connection information.
Table 2-30. PWM Port A Connector Description
J7
Pin #
Signal
Pin #
Signal
1
PWMA0
2
PWMA1
3
PWMA2
4
PWMA3
5
PWMA4
6
PWMA5
7
FAULTA0
8
FAULTA1
9
FAULTA2
10
FAULTA3
11
ISA0 / PC8
12
ISA1 / PC9
13
ISA2 / PC10
14
GND
2.15.16 PWM Port B Expansion Connector
The PWM Port B is attached to this connector. Refer to Table 2-31 for connection information.
Table 2-31. PWM Port B Connector Description
J8
Pin #
Signal
Pin #
Signal
1
PWMB0
2
PWMB1
3
PWMB2
4
PWMB3
5
PWMB4
6
PWMB5
7
FAULTB0
8
FAULTB1
9
FAULTB2
10
FAULTB3
11
ISB0 / PD10
12
ISB1 / PD11
13
ISB2 / PD12
14
GND
Technical Summary, Rev. 2
Freescale Semiconductor
Preliminary
2-37
2.16 Test Points
The 56F8367EVM board has a total of seven test points:
•
Analog Ground (AGND)
•
Three Digital Grounds (GND)
•
+3.3V
•
+3.3VA
•
+5.0V
MC56F8367EVM User Manual, Rev. 2
2-38
Freescale Semiconductor
Preliminary
Appendix A
56F8367EVM Schematics
56F8367EVM Schematics, Rev. 2
Freescale Semiconductor
Preliminary
Appendix A-1
MC56F8367EVM User Manual, Rev. 2
Appendix A-2
Freescale Semiconductor
Preliminary
1
2
3
4
A
A
TDI
TDO
TCK
/TRST
TMS
MISO0
MOSI0
SCLK0
/SS0
/RESET
/RSTO
CLKO
CLKMODE
XTAL
EXTAL
EXTBOOT
EMI_MODE
/WR
/RD
/PS
/DS
PD0
PD1
PD2
PD3
PD4
PD5
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
139
140
137
136
138
147
148
146
145
98
97
3
99
93
94
124
159
51
52
53
54
55
56
57
58
59
60
70
71
83
86
88
89
90
28
29
30
32
149
150
151
152
153
154
10
11
12
13
14
17
18
19
20
21
22
23
24
25
26
33
34
35
36
37
46
47
48
U1A
ANB0
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
TDI
TDO
TCK
TRST
TMS
B
MC56F8367VPY60
IRQA
IRQB
TXD1/PD6
RXD1/PD7
PHASEA1/TB0/SCLK1/PC0
PHASEB1/TB1/MOSI1/PC1
INDEX1/TB2/MISO1/PC2
EXTBOOT
HOME1/TB3/SS1/PC3
EMI_MODE
TC0/PE8
TC1/PE9
XTAL
EXTAL
TD0/PE10
TD1/PE11
CLKO
TD2/PE12
CLKMODE
TD3/PE13
RESET
RSTO
CAN1_TX
CAN1_RX
MISO0/PE6
TEMP_SENSE
MOSI0/PE5
SCLK0/PE4
TXD0/PE0
SS0/PE7
RXD0/PE1
WR
RD
PS/CS0/PD8
DS/CS1/PD9
PD0/CS2/CAN2_TX
PD1/CS3/CAN2_RX
PD2/CS4
PD3/CS5
PD4/CS6
PD5/CS7
PWMA0
A0/PA8
PWMA1
A1/PA9
PWMA2
A2/PA10
PWMA3
A3/PA11
PWMA4
A4/PA12
PWMA5
A5/PA13
A6/PE2
ISA0/PC8
A7/PE3
ISA1/PC9
A8/PA0
ISA2/PC10
A9/PA1
FAULTA0
A10/PA2
FAULTA1
A11/PA3
FAULTA2
FAULTA3
A12/PA4
A13/PA5
A14/PA6
PHASEA0/TA0/PC4
A15/PA7
PHASEB0/TA1/PC5
PB0/A16
INDEX0/TA2/PC6
HOME0/TA3/PC7
PB1/A17
PB2/A18
ANA0
PB3/A19
ANA1
PB4/A20/Prescaler_Clock
PB5/A21/SYS_CLK
ANA2
PB6/A22/SYS_CLKx2
ANA3
PB7/A23/OSC_CLOCK
ANA4
ANA5
ANA6
D0/PF9
ANA7
D1/PF10
D2/PF11
PWMB0
D3/PF12
PWMB1
D4/PF13
PWMB2
D5/PF14
PWMB3
D6/PF15
PWMB4
D7/PF0
PWMB5
D8/PF1
ISB0/PD10
D9/PF2
ISB1/PD11
D10/PF3
ISB2/PD12
D11/PF4
D12/PF5
FAULTB0
D13/PF6
FAULTB1
D14/PF7
FAULTB2
D15/PF8
FAULTB3
B
65
66
49
50
4
5
/IRQA
/IRQB
TXD1
RXD1
TXD0
RXD0
TEMP_SENSE
CAN_TX
CAN_RX
TD0
TD1
TD2
TD3
TC0
TC1
PHASEA1
PHASEB1
INDEX1
HOME1
ANB0
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
PWMB0
PWMB1
PWMB2
PWMB3
PWMB4
PWMB5
ISB0
ISB1
ISB2
FAULTB0
FAULTB1
FAULTB2
FAULTB3
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
PHASEA0
PHASEB0
INDEX0
HOME0
PWMA0
PWMA1
PWMA2
PWMA3
PWMA4
PWMA5
ISA0
ISA1
ISA2
FAULTA0
FAULTA1
FAULTA2
FAULTA3
1
2
JG12
C
ANA7
C6
2.2uF
R67
0 Ohm
DNP
+2.5V
C7
2.2uF
C8
2.2uF
R69
0 Ohm
DNP
0 Ohm
DNP
R71
C9
2.2uF
R70
0 Ohm
DNP
OCR_DIS
VCAPC1
VCAPC2
VCAPC3
VCAPC4
B
Size
Title
U1B
FAULTA3
FAULTA2
FAULTA1
FAULTA0
MC56F8367EVM.DSN
47K
R18
47K
R17
47K
R16
47K
R15
Use on-chip
regulators
D
Date: Thursday, September 02, 2004
Document
Number
109
47K
R22
47K
R21
47K
R20
47K
R19
C16
0.1uF
C57
0.001uF
+3.3VA
Single trace
to GNDA
C58
100pF
Single trace
to GNDA
C17
0.1uF
E
(512) 895-7215
E
Sheet
1
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
FAULTB3
FAULTB2
FAULTB1
FAULTB0
C15
0.1uF
+VREFH
C14
0.1uF
+3.3V_PLL
112 VREFP
111 VREFMID
110 VREFN
113
115
114
92
Designer: DSCO Design
VREFLO
VREFP
VREFMID
VREFN
VREFH
VSSA_ADC
VDDA_ADC
VDDA_OSC_PLL
MC56F8367VPY60
OCR_DIS
VSS_IO1
VSS_IO2
VSS_IO3
VSS_IO4
VSS_IO5
VSS_IO6
VCAPC1
VCAPC2
VCAPC3
VCAPC4
VPP1
VPP2
VDD_IO1
VDD_IO2
VDD_IO3
VDD_IO4
VDD_IO5
VDD_IO6
VDD_IO7
R72
0 Ohm
91
27
41
74
80
125
160
62
144
95
15
141
2
1
16
31
42
77
96
134
D
MC56F8367 Processor
C77
0.1uF
TEMP_SENSE
Use external
+2.5V Supply
+3.3V
R68
0 Ohm
DNP
+3.3V
Figure A-1. 56F8367 Processor
108
142
143
129
130
131
132
133
135
6
7
8
9
116
117
118
119
120
121
122
123
38
39
40
43
44
45
61
63
64
67
68
69
72
100
101
102
103
104
105
106
107
155
156
157
158
73
75
76
78
79
81
126
127
128
82
84
85
87
C
1
2
3
4
56F8367EVM Schematics, Rev. 2
Freescale Semiconductor
Preliminary
Appendix A-3
1
2
3
4
2
1
JG4
INT BOOT
1 - 2
A
+3.3V
3
2
2
1
JG5
EMI A0-A23
EMI A0-A15
RST
1
2
DS1818
3
DS1818
GND
Vcc
U16
2
2
1
/POR
R6
10K
+3.3V
R5
10K
+3.3V
1
JG2
OPTIONAL
NC
1 - 2
3
1
JG1
OSC BYPASS
BOOT MODE JUMPER
EXT BOOT
NC
1M
R1
EMI MODE JUMPER
Y1
8.00MHz
A
XTAL
EXTAL
A
Size
Title
C19
0.1uF
R4
10K
+3.3V
C18
0.1uF
R3
10K
+3.3V
R2
10K
+3.3V
C
PE4
+3.3V
2
1
JG6
10K
R9
10K
R8
D
NC
1
2
3
JG15
CLKMODE
User
Jumper
#0
R7
10K
+3.3V
E
10K
R11
10K
R10
1
2
3
JG16
User
Jumper
#1
(512) 895-7215
Sheet
2
E
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
/SS0
PE7
+3.3V
SOFTWARE FEATURE JUMPERS
SCLK0
EXT OSC
CLOCK MODE JUMPER
USE CRYSTAL 1 - 2
D
Designer: DSCO Design
/IRQB
/IRQA
/POR
MC56F8367EVM.DSN
Date: Thursday, September 02, 2004
Document
Number
RESET, MODE, CLOCK & IRQS
S3
IRQB PUSHBUTTON
S2
IRQA PUSHBUTTON
RESET PUSHBUTTON
S1
C
Figure A-2. Reset, Mode, Clock & IRQs
B
EMI_MODE
EXTBOOT
B
1
2
3
4
MC56F8367EVM User Manual, Rev. 2
Appendix A-4
Freescale Semiconductor
Preliminary
1
2
3
4
/PS
2
/ECS0
R12
10K
+3.3V
R30
1K
/RD
/WR
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
PB0
PB1
PB2
1-2
NC
SRAM ENABLE
SRAM DISABLE
A
C
U2
VSS1
VSS2
VDD1
VDD2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
GS72116TP-7
OE
WE
CE
LB
UB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
12
34
11
33
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
B
A
Size
Title
Note: A17 & A18 are
N/C on GS72116.
41
17
6
39
40
5
4
3
2
1
44
43
42
27
26
25
24
21
20
19
18
22
23
28
1
3
2
4
R32
1K
VSS1
VSS2
VDD1
VDD2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
GS72116TP-7
OE
WE
CE
LB
UB
NC
NC
SRAM DISABLE
/ECS4
/ECS1
12
34
11
33
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
MC56F8367EVM.DSN
C
Date: Thursday, September 02, 2004
Document
Number
10K
R14
+3.3V
Sheet
3
E
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
(512) 895-7215
Designer: DSCO Design
D
+3.3V
10K
R13
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
1.0
Rev.
Digital Signal Controller Operation
NC
3-4
3-4
JG8
1-2
NC
SRAM UPPER BYTE ENABLE
U3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
Note: A17 & A18 are
N/C on GS72116.
41
17
6
39
40
5
4
3
2
1
44
43
42
27
26
25
24
21
20
19
18
22
23
28
SRAM LOWER BYTE ENABLE
1-2
SRAM WORD ENABLE
OPTION
CS1/CS4 ENABLE JUMPER
/DS
PD2
JG8
/RD
/WR
/CE
/ECS1
/ECS4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
PB0
PB1
PB2
PROGRAM [WORD] (CS0) and DATA [BYTE] (CS1/CS4) SRAM MEMORY
+3.3V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
E
128Kx16-bit Data Memory (CS1/CS4)
D
Figure A-3. Program [Word] (CS0) & Data [Byte] (CS1/CS4) SRAM Memory
GS71116ATP
GS72116ATP
GS74116ATP
IS61LV51216
R31
1K
/LB
/UB
A16
A17
A18
64Kx16-bit
128Kx16-bit
256Kx16-bit
512Kx16-bit
JG7
OPTION
Note:
B
128Kx16-bit Program Memory (CS0)
CS0 ENABLE JUMPER
1
JG7
A
1
2
3
4
56F8367EVM Schematics, Rev. 2
Freescale Semiconductor
Preliminary
Appendix A-5
1
2
3
4
TXD0
RXD0
1 - 2
RS-232 DISABLE
A
N/C
RS-232 ENABLE
RS-232 SHUTDOWN JUMPER
A
1
2
JG11
1
2
JG10
RS232EN
22
23
A
Size
Title
/EN
1
1
1
20
19
18
17
16
15
14
13
12
2
24
1
28
U4
GND
V+
V-
VCC
INVALID
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
T3OUT
21
4
5
6
7
8
9
10
11
25
27
3
26
1
RXD
CTS
R3IN
R4IN
R5IN
1
TXD
RTS
C13
1.0uF
1.0uF
C12
+3.3V
MC56F8367EVM.DSN
C
Date: Thursday, September 02, 2004
Document
Number
RS-232 AND SCI CONNECTORS
MAX3245EEAI
FORCEOFF
FORCEON
R2OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
T1IN
T2IN
T3IN
C2-
C1C2+
C1+
C
1
6
2
7
3
8
4
9
5
P2
GND
DCD
DSR
TXD
CTS
RXD
RTS
DTR
D
R5IN
R4IN
R3IN
T3IN
/EN
E
1K
R38
1K
R37
1K
R36
1K
R35
1K
R34
+3.3V
(512) 895-7215
Sheet
4
E
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
SCI #0
RS-232
CONNECTOR
D
Designer: DSCO Design
Figure A-4. RS-232 and SCI Connectors
B
RTS1
T3IN
RX_OUT 1
CTS1
TX_IN
R33
1K
+3.3V
2
4
RTS1
CTS1
1
3
JG9
C11
1.0uF
C10
1.0uF
B
1
2
3
4
MC56F8367EVM User Manual, Rev. 2
Appendix A-6
Freescale Semiconductor
Preliminary
1
2
3
4
A
A
RXD1
TXD1
HOME1
INDEX1
PHASEB1
PHASEA1
B
13
11
PD6
PD7
9
5
PC2
PC3
3
1
PC1
PC0
B
270
R63
270
R62
270
R61
270
R60
270
R59
270
R58
C
+3.3V
D
D
E
(512) 895-7215
Sheet
5
E
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
USER
LEDS
Designer: DSCO Design
GREEN LED
YELLOW LED
RED LED
GREEN LED
YELLOW LED
RED LED
MC56F8367EVM.DSN
LED6
LED5
LED4
LED3
LED2
LED1
Date: Thursday, September 02, 2004
Document
Number
USER DEBUG LEDS
12
10
8
6
4
2
Figure A-5. User Debug LEDs
A
Size
Title
74AC04
U6F
74AC04
U6E
74AC04
U6D
74AC04
U6C
74AC04
U6B
74AC04
U6A
C
1
2
3
4
56F8367EVM Schematics, Rev. 2
Freescale Semiconductor
Preliminary
Appendix A-7
1
2
3
4
A
A
PWMA5
PWMA4
PWMA3
PWMA2
PWMA1
PWMA0
B
B
12
10
270
R57
270
R56
270
R55
270
R54
270
R53
270
C
D
+3.3V
PWM STATE
LEDS
Sheet
6
E
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
(512) 895-7215
Designer: DSCO Design
D
E
1.0
Rev.
Digital Signal Controller Operation
GREEN LED
YELLOW LED
GREEN LED
YELLOW LED
GREEN LED
YELLOW LED
MC56F8367EVM.DSN
LED12
LED11
LED10
LED9
LED8
LED7
Date: Thursday, September 02, 2004
Document
Number
PWM PORT A STATE LEDS
74AC04
U5F
74AC04
U5E
74AC04
8
6
4
2
R52
Figure A-6. PWM Port A State LEDs
A
74AC04
U5C
74AC04
U5B
74AC04
U5D
Size
Title
13
11
9
5
3
1
U5A
C
1
2
3
4
MC56F8367EVM User Manual, Rev. 2
Appendix A-8
Freescale Semiconductor
Preliminary
1
2
3
4
A
CAN_TX
CAN_RX
B
1
3
5
7
9
J20
2
4
6
8
10
B
A
Size
Title
R28
1K
+5.0V
U10
GND
CANH
CANL
VCC
VREF
PCA82C250T
SLOPE
TXD
RXD
2
7
6
3
5
T1
CANH
CANL
1
+5.0V
2
4
6
8
10
BCANH
L6
MC56F8367EVM.DSN
C
Date: Thursday, September 02, 2004
Document
Number
R40
120
1/4W
1
2
JG13
D
CAN BUS
TERMINATION
E
(512) 895-7215
Sheet
7
E
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
BCANL
BCANH
BCANH
BCANL
D
Designer: DSCO Design
HIGH-SPEED CAN PORT #1 INTERFACE
BCANL
1
3
5
7
9
J21
DAISY-CHAIN
CAN BUS CONNECTOR
8
1
4
C
Figure A-7. High-Speed CAN Port #1 Interface
BCANH
CAN BUS CONNECTOR
BCANL
A
1
2
3
4
56F8367EVM Schematics, Rev. 2
Freescale Semiconductor
Preliminary
Appendix A-9
1
2
3
4
A
PD0
PD1
1
3
1
3
5
7
9
J22
2
4
6
8
10
B
A
Size
Title
CAN2_TX
CAN2_RX
U11
GND
CANH
CANL
VCC
VREF
PCA82C250T
SLOPE
TXD
RXD
2
7
6
3
5
T2
CAN2H
CAN2L
1
+5.0V
2
4
6
8
10
BCAN2H
L7
MC56F8367EVM.DSN
C
Date: Thursday, September 02, 2004
Document
Number
R41
120
1/4W
1
2
JG17
D
CAN BUS
TERMINATION
E
(512) 895-7215
Sheet
8
E
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
BCAN2L
BCAN2H
BCAN2H
BCAN2L
D
Designer: DSCO Design
HIGH-SPEED CAN PORT #2 INTERFACE
BCAN2L
1
3
5
7
9
J23
DAISY-CHAIN
CAN BUS CONNECTOR
8
1
4
R29
1K
+5.0V
C
Figure A-8. High-Speed CAN Port #2 Interface
BCAN2H
2
4
JG14
B
CAN BUS CONNECTOR
BCAN2L
A
1
2
3
4
MC56F8367EVM User Manual, Rev. 2
Appendix A-10
Freescale Semiconductor
Preliminary
1
2
3
4
GND
GND
+3.3VA
GND
PE4
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
+5.0V
+12V
GNDA
GND
GND
GND
GND
GND
GND
GND
GND
AN1
AN3
AN5
AN7
AN9
AN11
AN13
AN15
+3.3VA
PE7
PE6
PD7
+3.3V
GND
TA1
TA3
GND
PC1/TB1/MOSI1
PC3/TB3/SS1
GND
PD6
GND
GND
B
A
A
Size
Title
FAULTA1
MISO0
ISA1
/RSTO
/SS0
TD1
TC0
CAN_RX
MISO0
/SS0
PWMA1
PWMA3
PWMA5
FAULTB0
FAULTB2
ISB1
PHASEB1
HOME1
TXD1
TXD1
RXD1
/IRQB
RXD1
PWMB1
PWMB3
PWMB5
PHASEB0
HOME0
GND
A16
GND
A19
/CS5
GND
/CS6
GND
GNDA
MC56F8367EVM.DSN
C
Date: Thursday, September 02, 2004
Document
Number
J2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND
A17
GND
A18
+5.0V
+3.3V
/CS3/CAN2_RX
/CS4
GND
/CS7
GND
GND
/CS1
/CS2/CAN2_TX
D
D
E
(512) 895-7215
Sheet
9
E
of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
D9
D8
PD1
A8
PB2
A9
A10
A11
PB1
D13
D12
D11
D10
PD2
/DS
PD0
D15
D14
PD5
A5
A6
A7
/RD
Designer: DSCO Design
GND
Daughter Address/Data Connector
+5.0V
+3.3V
A20
/CS0
DAUGHTER CARD CONNECTORS
D6
D7
/WR
A15
PB3
A14
A13
A12
PB0
D2
D3
D4
D5
PD3
A4
A3
A2
A1
PB4
A0
/PS
D0
D1
PD4
C
Figure A-9. Daughter Card Connectors
B
Daughter Peripheral Port Connector
GNDA
GND
GND
GND
GND
GND
GND
PE5
PE1
GND
TA0
TA2
GND
PC0/TB0/SCLK1
PC2/TB2/MISO1
GND
PE0
+3.3V
AN0
AN2
AN4
AN6
AN8
AN10
AN12
AN14
FAULTA0
FAULTA2
ISA0
ISA2
MOSI0
TD0
SCLK0
CAN_TX
MOSI0
SCLK0
PWMA0
PWMA2
PWMA4
ISB0
ISB2
FAULTB1
FAULTB3
PHASEA1
INDEX1
TXD0
TXD0
RXD0
/IRQA
RXD0
PWMB0
PWMB2
PWMB4
PHASEA0
INDEX0
+5.0V
+12V
A
1
2
3
4
56F8367EVM Schematics, Rev. 2
Freescale Semiconductor
Preliminary
Appendix A-11
1
2
3
4
A
CAN_TX
CAN_RX
PHASEA0
INDEX0
MOSI0
SCLK0
PWMA0
PWMA2
PWMA4
FAULTA0
FAULTA2
ISA0
ISA2
A0
A2
A4
A6
A8
A10
A12
A14
PB0
PB2
PB4
PB6
A
1
3
5
TA1
TA3
2
4
6
J15
2
4
6
J18
2
4
CAN #1
1
3
B
MOSI1
SCLK1
J8
1
3
5
7
9
11
13
PHASEB0
HOME0
+3.3V
MISO1
/SS1
J16
2
4
CAN2_TX
CAN2_RX
2
4
CAN #2
1
3
J19
TIMER CHANNEL C
1
3
SPI #1
&
QUAD-DECODER #1
1
3
5
TC1
+3.3V
INDEX1
HOME1
+3.3V
PWMB1
PWMB3
PWMB5
FAULTB1
FAULTB3
ISB1
+3.3V
D1
D3
D5
D7
D9
D11
D13
D15
C
C
TD0
TD2
TXD0
/RD
/WR
/PS
PD0
PD2
PD4
CLKO
AN0
AN2
AN4
AN6
/CS0
/CS2
/CS4
/CS6
2
4
6
8
10
12
14
16
/CS1
/CS3
/CS5
/CS7
2
4
6
8
10
J13
2
4
6
J17
2
4
6
B
Size
Title
TD1
TD3
+3.3V
RXD0
+3.3V
+5.0V
AN1
AN3
AN5
AN7
+3.3VA
/IRQA
/IRQB
/DS
PD1
PD3
PD5
/RESET
/RSTO
TXD1
AN8
AN10
AN12
AN14
MC56F8367EVM.DSN
D
Date: Thursday, September 02, 2004
Document
Number
1
3
5
7
9
J10
2
4
6
8
10
J14
2
4
6
RXD1
+3.3V
+5.0V
AN9
AN11
AN13
AN15
+3.3VA
E
Designer: DSCO Design
(512) 895-7215
E
Sheet
10 of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
SCI #1
1
3
5
A/D PORT B
PROCESSOR PORT EXPANSION CONNECTORS
TIMER CHANNEL D
1
3
5
SCI #0
1
3
5
A/D PORT A
1
3
5
7
9
J9
ADDRESS CONTROL
1
3
5
7
9
11
13
15
J6
D
Figure A-10. Processor Port Expansion Connectors
PD0
PD1
TC0
PHASEB1
PHASEA1
2
4
6
2
4
6
8
10
12
14
J12
MISO0
/SS0
+3.3V
PWMB0
PWMB2
PWMB4
FAULTB0
FAULTB2
ISB0
ISB2
2
4
6
8
10
12
14
16
18
DATA BUS
1
3
5
7
9
11
13
15
17
J5
J11
SPI #0
1
3
5
PWMA1
PWMA3
PWMA5
FAULTA1
FAULTA3
ISA1
D0
D2
D4
D6
D8
D10
D12
D14
PWMB
2
4
6
8
10
12
14
A17
A19
A21
A23
A1
A3
A5
A7
A9
A11
A13
A15
PB1
PB3
PB5
PB7
+3.3V
PWMA
1
3
5
7
9
11
13
J7
ADDRESS BUS
2
4
6
8
10
12
14
16
18
20
22
24
26
TIMER CHANNEL A
&
QUAD-DECODER #0
TA0
TA2
A16
A18
A20
A22
1
3
5
7
9
11
13
15
17
19
21
23
25
J4
B
1
2
3
4
MC56F8367EVM User Manual, Rev. 2
1
2
3
4
A
A
P_RESET
R23
47K
25
24
23
22
21
20
19
18
17
16
15
14
5.1K
R48
13
12
11
10
9
8
7
6
5
4
3
2
1
Q1
2N2222A
/J_RESET
R42
5.1K
+3.3V
B
PORT_CONNECT
PORT_PU
PORT_TDO
PORT_VCC
PORT_DE
/PORT_TRST
PORT_TDI
PORT_TCK
PORT_TMS
PORT_RESET
51 Ohm
R50
51 Ohm
R51
+5.0V
+3.3V
5.1K
R43
3
1
2
3
5
20
/J_TRST
/POR
/J_RESET
JG19 +Vsel
13
11
8
6
4
2
GND
2G
1G
2A4
2A3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
PORT_PU
74AC00
R94
C
1K
DNP
R95
1K
74AC00
+Vsel
10
U7C
U7B
0 Ohm
R77
0 Ohm
R75
0 Ohm
R73
JG3
+3.3V
0 Ohm
R76
0 Ohm
R74
/CCEN
1
8
6
B
Size
Title
R46
5.1K
20
1
19
3
5
7
11
8
6
4
2
GND
2A4
2A3
2A2
2Y1
1Y4
1Y3
1Y2
1Y1
TCK
TDO
TDI
+3.3V
MC74LCX244DW
VCC
1G
2G
2Y4
2Y3
2Y2
2A1
1A4
1A3
1A2
1A1
U9
D
/DE
PWR
TDO
P_DE
14
12
10
8
6
4
2
KEY
/J_TRST
TMS
P_DE
/J_TRST
/DE
PWR
TDO
MC56F8367EVM.DSN
D
Date: Thursday, September 02, 2004
Document
Number
5.1K
R47
47K
R27
47K
R26
47K
R25
47K
R24
+3.3V
(512) 895-7215
Designer: DSCO Design
E
Sheet
11 of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
JTAG Connector
13
11
9
7
5
3
1
J3
/J_TRST
TDI
TCK
TMS
P_RESET
/J_RESET
10
17
15
13
9
12
14
16
18
E
PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
/TRST
/RESET
On-Board
Host Target Interface
Disable
R45
5.1K
74AC00
9
5
4
R44
5.1K
U7D
11
3
1
74AC00
U7A
10
19
1
17
15
7
9
12
14
16
18
PORT_CONNECT
13
12
2
1
MC74HC244DW
2Y4
2Y3
VCC
2A2
2A1
1A4
1A3
1A2
1A1
U8
Parallel JTAG Interface
C
Figure A-11. Parallel JTAG Host Target Interface and JTAG Connector
P1
PORT_IDENT
B
2
1
Appendix A-12
Freescale Semiconductor
Preliminary
1
2
3
4
56F8367EVM Schematics, Rev. 2
Freescale Semiconductor
Preliminary
Appendix A-13
1
2
3
4
AN6
AN5
AN4
AN3
AN2
AN1
AN0
A
A
100
R84
100
R83
100
R82
100
R81
100
R80
100
R79
100
R78
C65
0.0022uF
C64
0.0022uF
C63
0.0022uF
C62
0.0022uF
C61
0.0022uF
C60
0.0022uF
C59
0.0022uF
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
B
B
ANB3
ANB2
ANB1
ANB0
MC56F8367EVM.DSN
C70
0.0022uF
C69
0.0022uF
C68
0.0022uF
C67
0.0022uF
C66
0.0022uF
ANA7
C
Date: Thursday, September 02, 2004
Document
Number
A/D INPUT FILTERS
100
R89
100
R88
100
R87
100
R86
100
R85
Figure A-12. A/D Input Filters
A
Size
Title
AN11
AN10
AN9
AN8
AN7
C
100
R93
100
R92
100
R91
100
R90
C74
0.0022uF
C73
0.0022uF
C72
0.0022uF
ANB7
ANB6
ANB5
ANB4
(512) 895-7215
Sheet
E
12 of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
Designer: DSCO Design
D
E
C71
0.0022uF
NOTE: Use a single trace
for GNDA signals to the
common GNDA point.
AN15
AN14
AN13
AN12
D
1
2
3
4
MC56F8367EVM User Manual, Rev. 2
1
2
+3.3V
TP4
+3.3V
TEST POINT
1
3
A
+3.3VA
TP5
+3.3VA
TEST POINT
+3.3V
+5.0V
U14
VOUT
VOUT
4
2
D1
+ 1
FERRITE BEAD
L4
+ C1
470uF
16VDC
+12V
L5
C5
47uF
10VDC
TP1
GROUND
TEST POINT
+
B
TP2
GROUND
TEST POINT
C21
0.1uF
+
VCC
U12
VOUT
VOUT
MC33269DT-5.0
GND
VIN
+3.3V
Typ 135mA
1
3
FM4001
D2
4
2
+5.0V
+5.0V
2
3
1
1
3
C
VOUT
VOUT
NR
VOUT
REG113NA-3.3/3K
GND
EN
VIN
U15
MC33269DT-3.3
GND
VIN
U13
DNP
FM4001
D3
FERRITE BEAD
L1
TP6
C
+5.0V
TP7
B
Size
Title
L2
C75
10uF
6VDC
+
C4
47uF
10VDC
1
2
JG18
+3.3VA
+VREFH
Single trace
to GNDA.
R66
0 Ohm
+2.5V Input
+2.5V Ground Reference
MC56F8367EVM.DSN
D
4
5
2
3
MC33269
1
4
3.3V AND 5.0V
REGULATOR
Designer: DSCO Design
(512) 895-7215
E
Sheet
13 of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
REG113NA3/3K
1
2
3
3.3V REF
REGULATOR
POWER GOOD LED
E
LED13
GREEN LED
R64
270
+5.0V
NOTE: Remove 0 OHM
resistor to use Analog
GND isolation jumper.
External +2.5V
Power Supply
Input
1
2
J24
Date: Thursday, September 02, 2004
Document
Number
D
+2.5V
POWER SUPPLIES
+
10 Ohm
R65
FERRITE BEAD
L3
FERRITE BEAD
C2
47uF
10VDC
+3.3V
+
+5.0V
Figure A-13. Power Supplies
TP3
C76
0.01uF
4
5
C22
0.1uF
4
2
GROUND ANALOG GROUND
+5.0V
TEST POINT TEST POINT TEST POINT
C3
47uF
10VDC
C20
0.1uF
+3.3V_PLL
NOTE: To measure +3.3V supply
current, remove L2 and replace
with amp meter.
MC33269DT-3.3
GND
VIN
D4
2 -
1
DNP
FM4001
3
FERRITE BEAD
2
1
3
1
4
P3
1
4
1
3
EXTERNAL POWER INPUT
7-12V DC/AC
1
B
1
A
1
Appendix A-14
Freescale Semiconductor
Preliminary
1
2
3
4
56F8367EVM Schematics, Rev. 2
Freescale Semiconductor
Preliminary
Appendix A-15
1
2
3
4
C24
0.1uF
C55
0.01uF
C25
0.1uF
+3.3V
+5.0V
A
C40
0.1uF
+3.3V
C41
0.1uF
+12V
C42
0.1uF
+3.3VA
C26
0.1uF
C30
0.1uF
B
+3.3V
+3.3V
C51
0.1uF
DNP
U4
MAX3245
C53
0.01uF
C54
0.01uF
B
+5.0V
C44
0.1uF
+3.3V
C46
0.1uF
C27
0.1uF
+3.3V
+3.3V
C39
0.1uF
U6
74AC04
C28
0.1uF
+3.3V
C
C47
0.1uF
J4
ADDRESS BUS
CONNECTOR
C38
0.1uF
U5
74AC04
+VREFH
C
C37
0.1uF
B
Size
+3.3VA
D
C31
0.1uF
+5.0V
C50
0.1uF
E
Designer: DSCO Design
(512) 895-7215
E
Sheet
14 of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
+3.3VA
C32
0.1uF
U11
PCA82C250
J10
A/D CONNECTOR
+5.0V
U10
PCA82C250
MC56F8367EVM.DSN
C49
0.1uF
Date: Thursday, September 02, 2004
Document
Number
C35
0.1uF
J9
A/D CONNECTOR
C36
0.1uF
+3.3V
U9
74LCX244
D
BYPASS CAPACITORS
C48
0.1uF
Title
+3.3V
+Vsel
U8
74HC244
J5
DATA BUS
CONNECTOR
+3.3V
U7
74AC00
Figure A-14. Bypass Capacitors
C45
0.1uF
+3.3V
J2
MEMORY CONNECTOR
C56
0.01uF
C52
0.01uF
U1
MC56F8367
U3
GS72116
C43
0.1uF
J1
PERIPHERAL CONNECTOR
C29
0.1uF
+3.3V
U2
GS72116
C23
0.1uF
+3.3V
+3.3V
A
1
2
3
4
MC56F8367EVM User Manual, Rev. 2
Appendix A-16
Freescale Semiconductor
Preliminary
Appendix B
56F8367EVM Bill of Material
Qty
Description
Ref. Designators
Vendor Part #
Integrated Circuits
1
MC56F8367
U1
2
128K x 16-Bit SRAM
U2, U3
1
RS-232 Transceiver
U4
2
74AC04
U5, U6
1
74AC00
U7
Fairchild, 74AC00SC
1
74HC244
U8
ON Semiconductor, MC74LHC44AADW
1
74LCX244
U9
ON Semiconductor, MC74LCX244ADW
2
CAN Transceiver
1
+5.0V Voltage Regulator
U12
2
+3.3V Voltage Regulator
U13, U14
1
+3.3V Voltage Regulator
U15
0
Power-On Reset
U10, U11
U16 (Optional)
Freescale, MC56F8367VPY60
GSI, GS72116ATP-8
Maxim, MAX3245EEAI
ON Semiconductor, MC74AC04AD
Philips Semiconductor, PCA82C250T
ON Semiconductor, MC33269DT-5
ON Semiconductor, MC33269DT-3.3
Burr-Brown, REG113NA-3.3
Dallas Semiconductor, DS1818
Resistors
1
1MΩ
R1
SMEC, RC73L2A105OHMJT
13
10KΩ
R2 - R14
SMEC, RC73L2A103OHMJT
13
47KΩ
R15 - R27
SMEC, RC73L2A473OHMJT
12
1KΩ
R28 - R38, R94
SMEC, RC73L2A103OHMJT
0
1KΩ
R95 (Optional)
SMEC, RC73L2A103OHMJT
2
120Ω, 1/4W
R40, R41
YAGEO, CFR 120QBK
56F8367EVM Bill of Material, Rev. 2
Freescale Semiconductor
Preliminary
Appendix B-1
Qty
Description
Ref. Designators
Vendor Part #
Resistors (Continued)
7
5.1KΩ
R42 - R48
SMEC, RC73L2A512OHMJT
2
51Ω
R50, R51
SMEC, RC73L2A51OHMJT
13
270Ω
R52 - R64
SMEC, RC73L2A271OHMJT
1
10Ω
R65
SMEC, RC73L2A100OHMJT
7
0Ω
R66, R72 - R77
SMEC, RC73JP2A
0
0Ω
R67 - R71 (Optional)
SMEC, RC73JP2A
16
100Ω
R78 - R93
SMEC, RC73L2A101OHMJT
Inductors
5
1.0mH FERRITE BEAD
L1 - L5
Panasonic, EXC-ELSA35V
2
CAN Bus Filter
L6, L7
EPCOS, B82790-S0513-N201
LEDs
2
Red LED
LED1, LED4
Hewlett-Packard, HSMS-C650
5
Yellow LED
LED2, LED5, LED7, LED9,
LED11
Hewlett-Packard, HSMY-C650
6
Green LED
LED3, LED6, LED8, LED10,
LED12, LED13
Hewlett-Packard, HSMG-C650
Diode
1
+50V 1A BRIDGE RECT
D1
DIODES, DF02S
1
S2B-FM401
D2
Vishay, DL4001DICT
0
S2B-FM401
D3, D4 (Optional)
Vishay, DL4001DICT
Capacitors
1
470µF, +16V DC
C1
ELMA, RV-16V471MH10R
4
47µF, +16V DC
C2 - C5
ELMA, RV2-16V470M-R
4
2.2µF, +25V DC
(Low ESR)
C6 - C9
TAIYO YUDEN, CELMK212BJ225MG-T
4
1.0µF, +25V DC
C10 - C13
SMEC, MCCE105K3NR-T1
37
0.1µF
C14 - C32, C35 - C51, C77
SMEC, MCCE104K2NR-T1
6
0.01µF
C52 - C56, C76
SMEC, MCCE103K2NR-T1
MC56F8367EVM User Manual, Rev. 2
Appendix B-2
Freescale Semiconductor
Preliminary
Qty
Description
Ref. Designators
Vendor Part #
Capacitors (Continued)
1
0.001µF
C57
SMEC, MCCE102K2NR-T1
1
100pF
C58
SMEC, MCCE101K2NR-T1
16
0.0022µF
C59 - C74
SMEC, MCCE222K2NR-T1
1
10µF, +10V DC
C75
KEMET, T494B106M010AS
Jumpers
4
3 × 1 Bergstick
JG1, JG15, JG16, JG19
SAMTEC, TSW-103-07-S-S
12
1 × 2 Bergstick
JG2 - JG7, JG10 - JG13, JG17,
JG18
SAMTEC, TSW-102-07-S-S
3
2 × 2 Bergstick
JG8, JG9, JG14
SAMTEC, TSW-102-07-S-D
Test Points
3
GND Test Point
TP1, TP2, TP3
KEYSTONE, 5001, BLACK
1
+3.3V Test Point
TP4
KEYSTONE, 5000, RED
1
+3.3V A Test Point
TP5
KEYSTONE, 5004, YELLOW
1
GNDA Test Point
TP6
KEYSTONE, 5002, WHITE
1
+5.0V Test Point
TP7
KEYSTONE, 5003, ORANGE
Crystals
1
8.00MHz Crystal
Y1
CTS, ATS08ASM-T
Connectors
1
DB25M Connector
P1
AMPHENOL, 617-C025P-AJ121
1
DE9S Connector
P2
AMPHENOL, 617-C009S-AJ120
1
2.1mm coax
Power Connector
P3
Switchcraft, RAPC-722
1
Peripheral Daughter Card
Connector
J1
HRS, FX6-100P-0.8SV2
1
Memory Bus Daughter
Card Connector
J2
HRS, FX6-60P-0.8SV2
1
7 x 2 JTAG Header
J3
SAMTEC, TSW-106-07-S-D
1
13 x 2 Header
J4
SAMTEC, TSW-106-13-S-D
56F8367EVM Bill of Material, Rev. 2
Freescale Semiconductor
Preliminary
Appendix B-3
Qty
Description
Ref. Designators
Vendor Part #
Connectors (Continued)
1
9 x 2 Header
J5
SAMTEC, TSW-106-09-S-D
1
8 x 2 Header
J6
SAMTEC, TSW-106-08-S-D
2
7 x 2 Header
J7, J8
SAMTEC, TSW-106-07-S-D
6
5 x 2 Header
J9, J10, J20 - J23
SAMTEC, TSW-106-05-S-D
6
3 x 2 Header
J11 - J15, J17
SAMTEC, TSW-106-03-S-D
3
2 x 2 Header
J16, J18, J19
SAMTEC, TSW-106-02-S-D
Switches
3
SPST Push button
S1 - S3
Panasonic, EVQ-PAD05R
Transistors
1
2N2222A
Q1
ZETEX, FMMT2222ACT
Miscellaneous
18
Shunt
4
Rubber Feet
SH1 - SH13
RF1 - RF4
Samtec, SNT-100-BL-T
3M, SJ5018BLKC
MC56F8367EVM User Manual, Rev. 2
Appendix B-4
Freescale Semiconductor
Preliminary
INDEX
Numerics
F
1.2 Amp power supply 2-17
56F8300 Peripheral User Manual 2-4
56F8357 Technical Data Sheet 2-4
8.00MHz crystal oscillator 2-1
FlexCAN Preface-ix
FlexCAN Interface Module
FlexCAN Preface-ix
FSRAM 2-1, 2-5, 2-6
A
G
A/D Preface-ix
ADC Preface-ix
Analog-to-Digital
A/D Preface-ix
Analog-to-Digital Converter
ADC Preface-ix
General Purpose Input and Output
GPIO Preface-ix
GPIO Preface-ix, 2-28
C
CAN Preface-ix
bus termination 2-1, 2-2
bypass 2-1, 2-2
interface 2-1
CAN in Automation
CiA Preface-ix
CAN physical layer peripheral 2-2
CiA Preface-ix
Controller Area Network
CAN Preface-ix
D
D/A Preface-ix
Daughter Card Expansion
interface 2-1
Debugging 2-10
Digital-to-Analog
D/A Preface-ix
DSP56800E Reference Manual 2-4
E
Enhanced On-Chip Emulation
EOnCE Preface-ix
EOnce Preface-ix
Evaluation Module
EVM Preface-ix
EVM Preface-ix
External oscillator frequency input 2-1
H
Host Parallel Interface Connector 2-11
Host Target Interface 2-11
I
IC Preface-ix
Integrated Circuit
IC Preface-ix
J
Joint Test Action Group
JTAG Preface-ix
JTAG Preface-ix, 2-1
JTAG/Enhanced OnCE (EOnCE) 1-1
Jumper Group 1-4
JG1 1-4
JG10 1-4
JG11 1-4
JG12 1-4
JG13 1-4
JG14 1-4
JG15 1-4
JG16 1-4
JG17 1-4
JG18 1-4
JG19 1-4
JG2 1-4
JG3 1-4
JG4 1-4
JG5 1-4
JG6 1-4
JG7 1-4
JG8 1-4
JG9 1-4
Index, Rev. 2
Freescale Semiconductor
Preliminary
Index-1
L
R
LED Preface-ix
Light Emitting Diode
LED Preface-ix
Low-profile Quad Flat Package
LQFP Preface-ix
LQFP Preface-ix
R/C Preface-x
RAM Preface-x
Random Access Memory
RAM Preface-x
Read-Only Memory
ROM Preface-x
real-time debugging 2-10
Resistor/Capacitor Network
R/C Preface-x
ROM Preface-x
RS-232 2-1
level converter 2-7
schematic diagram 2-7
M
MPIO Preface-ix, 2-31
Multi Purpose Input and Output
MPIO Preface-ix
O
On-board power regulation 2-3
OnCE Preface-ix
On-Chip Emulation
OnCE Preface-ix
P
Parallel JTAG Host Target Interface 2-1
PCB Preface-ix
peripheral port signals 2-18
Phase Locked Loop
PLL Preface-ix
PLL Preface-ix
Printed Circuit Board
PCB Preface-ix
Pulse Width Modulation
PWM Preface-ix
PWM Preface-ix
PWMA-compatible peripheral 2-2
PWMB-compatible peripheral 2-2
Q
QuadDec Preface-ix
Quadrature Decoder
interface port 2-30
QuadDec Preface-ix
S
SCI Preface-x
SCI/MPIO-compatible peripheral 2-2
Serial Communications Interface
SCI Preface-x
Serial Peripheral Interface
SPI Preface-x
SPI Preface-x
SPI/MPIO-compatible peripheral 2-2
SRAM Preface-x
external data 2-1
external program 2-1
Static Random Access Memory
SRAM Preface-x
T
Timer-compatible peripheral 2-2
W
Wait State
WS Preface-x
WS Preface-x
MC56F8367EVM User Manual, Rev. 2
Index-2
Freescale Semiconductor
Preliminary
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© Freescale Semiconductor, Inc. 2005. All rights reserved.
MC56F8367EVMUM
Rev. 2
07/2005