Download RM 380Z Service Manual

aoz
SER ICEUAL
~....~.
.
'I
380Z AND 480Z 8YSTBMS
SBRVICB IlANUAL
PM 13821
CoPyri9ht
•
1984
....arch Machin.. Limit.d
All right. re.erved. Copies of thi. publicat.ion "1' be . .de by
CWltoaers .xclusivelyfor their own aile, but otherwise no part of
it "1' be reproduced, transadt.t.ed, transcribed, stored in a
retrieval
or tr.nsl.ted into any language or coaput.er
la1~Gtmg~ w,ltl,o~lt the prior writt.en per.ission of . .search
Lia1ted, Mill St.., OXford, Jb'l91and. OX2 OBW.
~ell
Oxford (0865) 249866 •
....archllachin.. has a policy of continuoWl developaent and
iaprov. .ent. of it. product. and .ervic.. and the ri9ht 1.
r ••erv.d to revi..
..nual or t.o . .ke chan9.. in the
coaput.r software it d••cribe. without not.ice. ...e.rch Machin••
• n4eavour to en.ure the accuracy of thi. ..nual and th.t. the
product.. de.cribed perfor. corr.ctly accordin9 to t.heir
4e.cript.lon.. How.v.r, .....rch Machine. Limit.ed do not .ccept.
liability for th. con••qu.nce. of any error or . .i ••ion.
Addition.l copie. of this
aaybe ordered from
".earch Machine. L1a1t.d at the .ddr... abov.. Pl.... ..k for
the t.itl. as 9iven above.
1
CPU
•1
1.1
SECTION
2
2.1
.1
2.1
2.2
2.3
2.3
2
SECTION
3
BOARD
scroll
SBCTION
4
BOARD
Introduction
4.1
4.
4.
4 2
4.2
4.3
4.3
380Z Service
SECTION
5
INTELLIGENT DISC
vVI~~~~£'~tn
'
...
BOARD
Introduction
51
5.2
5.2
Hardware
Bus
Bus interface
External
Clock
Serial interface
.3
5.4
5.
.6
5.6
5.6
5.7
5.8
Internal
Control
Disc control
SECTION
6
INTELLIGENT
CONTROLLER
How to Use These Notes
Further
Hints
Z80
Modifications
SECTION
7
NETWORK
TRJ~S:CE :IVE~R
- DIAGNOSTIC NOTES
6.
6.2
.15
6.16
OPERATION
Interface Board
Network interface
RS232 interface
1
7.2
.2
.3
7.3
4
DMA controller
the
the SIO
the CTC
Connectors
480Z Hardware
Transceiver connection
cable
SECTION
8
7.4
5
7 5
.6
7.
7.9
7.9
7.9
9
HOST INTERFACE BOARD
Introduction
8.
8. 1
The Hardware Modules
Bus
Bus
Interface to
8.
B.2
B.2
8.3
8.3
Service .......
l&WU.....
1.1
RAM
1.2
.3
1.4
3801 Use
Use
................ above FOOD
380Z
380Z
Board
section deecr
versions
0, 3.4
4.
three COS version CPU boards al1:ftc,••rft
COS 2.3 or earlier. No a1:'CelllD1:
boards as so few are
use
Circuit
380Z
380Z
CPU board
•
•
•
•
•
•
•
an
Circuit
380Z
CPU-2)
to
sequences
bwlallows
Non-maskable
service t.he
in
)
act.ive
.
MMI-.
or
of
on
•1
)
.
380Z
Board
a processor reset
is
to address
the first two M1
NMI. If these instructions
condition, the
NMI results
cleared and
" is
cleared and NMIEN- is active.
on page 0 where instructions are
to initialize
0 and
ex,eCU1:. ea, due to a fault
in which the screen is not
l
VDU board where a 2400Hz
so that
processor
receives active
ensures that RAM contents are not
due
board fault
to enable
, M1
to
reset. Absence of power
'reset'
the processor will
result in inactive M1 and no response to the RESET button. The situation
can
very "Catch 22"
not borne in mind when
faults
Bus reset is buffered
a transistor
drive the
around
a
of IC 20 to drive
26
bus processor reset is inverted
the
cpu.
of memory
appears as a
it
absence
processor is
will be
external
future
the
e'l'lII!, ... a,1'IA
bus
the
resistor AND
select the
buffers, ICs 14 and 15
into
the
from
sections:
•
•
The data bus
buffered
processor
2
ICs 14 and
AllS
380Z
EPROM
RIB and CAS
.3
Board
380ZCPU Board
shown in
1• •
are
0103
o
the
t.he
bus
a coara.
and
way
•
•
SVR1":Am
Clock
(Circuit
380Z
CPU-2
.4
3801
Board
and
is
1.5
380Z CPU Board
Ii
1.
Board
PPPF
PI'
AGeS-CO RAM
cooo
16lC
64K
8000
16K
4000............t--"
RAM
1
•2
Standard 380Z U.. of ..........'v
Row 2
380Z CPU Board
FBAO
FB90
- PBBF
1 memory
reserved for
user aIJIIJ .......L...,:Cil .........U&1
FB70
FB60
FBSO
Low address
address
Data
o
1
.8
10
1
(
•
•
•
•
•
••
380Z VDU-40
FRAME SYNC to
convention
LINE and FRAME ACCESS are
tested
open the Video RAM
television
1 and can be
A 7-bit word read
the video RAM is decoded in the character
IC 27 and identifies a
character. The five
, Y1 to Y5 are
the row dot
to the row within the character selected
ReO to RC3.
Y1 to Y5 are latched
IC 28 at the start of each
new
29
select
demu
the
column bits to uansfer
to ou
data
IC
of
GRAPH ICS38,
the
be
and R25
mixer
buffer.
common collector
video
and level 1V
from
video
UHF modulator
modulated copy. Carrier channel is
D1, D2
The character
character
dance is
-ve sync.
R35 and D3
A
a UHF
which
a teletextIt
ASCIIAbove these values, codes are
characters. These are
35 and IC 42
array
codes
11<
to
lines.
necessary to
the square
and
••
screen results.
is
Board
380Z VDU-40 Board
•
Power-on Reset
of
and does
A
and
'low',
SYSTEM
•
Manual Reset
Users can
button.
RESET
21C
the
goes
and
4
memory map:
3
PC.lRT
lBFFH
Write
Port 0
PORT
5
2.4
o
BIT 3
2
3
2
1
00
1
Read: COIUft1:.er
BIT
o
3
4
5
6
2
2
READ
ACCESS
4
3
2
1
Board
24
charac~er8
24
charac~er8
comp......,_... "'.V~
with
c
vou
VOU 80- ,
The
)
380Z VDU-SO Board
4K7 SIP
without
on
to allow use of open collector
resistor network.
the
Hardware
Hardware
the
the
number
row
that
in the low
bits
Ho,,,e,,er, the
cannot be done
(74LS2S3) and FR
is not necessary to
This is achieved
character and once
AR (
the translation
The
CS and
per character. The
). When
SO-character
).
mode
YOU SO-2
VDU 80-3)
116) while the attribute bits are held
are
74LS273
the
74LS374)
characters
read and
character
the
are
thea.elves to be
of
(74LS373) and
(74LS244). BR is a
for a write to take
when
3 2
Board
380Z VDU-80 Board
from the latched
BP (74221).
The
40-character
and combine
to
board.
deal with twice
It must
from
HRG
the
Inverse video
collector
Dim video works
the
~n~i~hu
~~e
for "wire frame" monitor
that from the VDU. Further,
attribute
(
... •.
, """' """"
introduced at
Two currents are
'_".";::'IdF'"'2)
R20, and
an address
and
contains the
common base
the BRa
follower' •
collector
which are added in
resistor
D3,
and D5.
Diodes D2 and
that sync
T4 is used to disable
smooth
hardware which
described.
4
1.
as
MDS
1
380Z
Board
select line decoder) decode
IC BR
four
Each of these
space
and
4
to IA 7 to estab lish the map in
All
8251 EN-
C'1'C
1
1EN-
a block of four
outDut;s are ORed
the bOard
to be
disc-controller
Data
transferred via the bi-directional tristate
direction of
is selected
and
This
on the bOard
with IIOR
that the direction
are buffered
the
Bus and
IC AP.
CP
On the circuit
decoded
it.
is active
1 to enable
o
a
the contents.
write
which the contents
the
and cannot be read
All software access to the
Port 0 Bit Allocations
Write
Read
6
bit)
5
4
(Circuit
2
2
o
0)
FDC
a
4.2
380Z FOC Board
Channel 1
software
2:
for
Baud rate
Channel 4:
1
via RS232
in
transfer is
2.
a dedicated IC
Access to the
map. Disc
ICs AS and
4.3
380Z FDC Board
circuit i.
from the
into the POD and
the 1771
It
way: an active
is
loads a 4-bit
) with 12. The
a clock
or SOOns
its count
a BCD to decimal decoder
is Eero the zero
of DT goes 'low' and is
) whose
are DATA WINDOW and NOT
reset when the
count reaches
and DATA WINDOW
the next clock
, and the
is
Data and clock
time constant
(approx1mate~
WINDOW and NOT DATA WINDOW.
and •clock
, FDD and FDC.
is
WINDOW
sector header before the
IC BT is used to
to MSEL
active with STEP,
the disc drive and
a monostable of
(
with DATA
'data'
of DATA
direction and
information
Direction 1s decoded on the drive to
is assumed.
4.4
IDCBoard
INTELLIGENT DISC
INTRODUCTION
the
covered with the
interface is
OBJECTIVES
most
uses.
a serial
is
As
more
there are
in fact
480Z.
host processor
of the serial
As the
an on-board
to,
disc
processor
380Z
Board
THE HARDWARE
( Circuits
380Z Bus Interface and Decode:
Disc Drive Interface:
CPU Serial Interface & Clocks
Wait State and Internal Decode
The circuit consists of several clear-cut modules
with a small
amount of TTL'
'to
the various modules with each other
The
main
are as follows:
to the
• Bus
• Bus Interface
the
method
380Z.
1•
2.
of transfer of data and commands to
includes two sub-modules:
Data and
Wait-state
to decode the
• Clock Generation
to
all clocks for the
for the serial interface, CPU
• Serial Interface
two channels
•
on-board
·~~;~V'~.U~
the
time-out
• External
• Internal
ZSO bus.
used
the 380Z.
with
and
to
the
on the IDC board.
• Control Ports:
to hold static values which control the disc drives
• Disc Control
which consists of two sub-modules:
2.
These
modules
FDC
Data
and buffers.
now be described in more detail.
Bus
to
which drives the
for the
CTC is also buffered
74ALS1244N
buffer
the addresses and one 74ALS1245
transfer channel
In
used
invert.er IC 3
one element
AND
(IC 29
on the bus, and a
INT- from the
chain. The
of IC
BINT-
380Z
Board
IC
the IDe and (
otherwise BDIR-
and
are 1mPiell,en1:.ea as
It
in
(
(ii)
or (iii
the alternate
a processor tries
state is
2.
A and Bone
each direction
are
of the data
3
the state
'A'CLEAR
380Z IDC Board
is • low', DRDWT- is
to the
and 1:hus cannot
1:0
host Z80A.
CLBAR
is • low', HRDWT- i.
') when
is available
the host Z80A and t.hus cannot bewritt.en t.o
1:he internal Z80A.
internal
Take the
the data
tries to
If
recover
The 'wait'
board alone
to have
the
for
there has
software.
avoided,
when the host Z80A writes to
set CLEAR
end of
write
ea,ae-ae~ec~~lon mechanism.
When the internal Z80A
is SET at
of
read
clock
If the host Z80A
whilst the
is CLEAR
when
'B' is set) then a
and a time-out is initiated
for
then 200us or so, a fault
123 will terminate
cut-off the 'wait'
Z80A. It is conceivable 1:hat the software could
in some circumstances so a
is set
occurs. Also to
up any
this
further 'wait'
been read
the host
a 74LS107 as the
'wait' states
and time-out structure for both
for the
time
the host
may be
will leave the IDC
it is
IDC board
IDC
communications
'time-outs' are
where RRG
The bus
lines, IA2 to IA7
done
and
The PAL decodes
as follows:
5.4
CTC
BOH
to
B3H
channel 0
81
channel
B2: CTC channel 2
83 CTC channel 3
CTC
SIO channel A
SIO channel A
SIO channel B
£4
~W.'&~.'W.
B ·~""'.&L,""""'.
Status
B8
IDe
E8.; IDC
IDC
EA.: IDe
ED: IDC
interface
reset
reset
reset
reset
to
-
2
read
write
write
write
write
to
IDe
ED
IDe
IDe
IDe
the host tries
BWR- and HSTRD- are
write to
interface status
which cause the
Generation
DC
clocks
•
on the board
into three classes
clocks
•
A
•
"Times 16"
of 4MHz
clocks
IC 45 is
buffered and passea
74LS393 (IC 28
to
(IC
the standard
a
and 3
"times
Ohm
380Z IDC Board
clocks for the serial channel
serial channel IB I •
, transmit and receive, ·and also for the
: DC
The serial interface
of an SIO
(IC 40)
88
drivers (IC 15 and
and 75 89 line receivers
6 and IC 7). The
levels on the
+12V and -12V. The channel'
is
selectable to use
Indicate whilst the
B'
is used for Data Set
the
serial control lines have
4K7
resistors to enable sensible use of the interface without the
use of the handshake lines.
channel 'A' times 6 clocks are also
selectable to come from an external
with the
Indicate.
DC
There are two sockets
is for EPROMs IC
)
memory devices.
One
take any sort of
These links are
other devices, areas
The internal
8
means of a set
2764 EPROMs. The
EPROM
,
3-5,
5-6,
2-4,
3-4
5-7
251
2532
2732
2564
2764
68764
8-10
6-8
8- 0
, 6-8
5-6 7-9
8K
buffer
can be either a 2K
these are as follows:
or
8K
(IC46
PAL 10L8)
lines RD-, WR-
13
decodes
and CTLWR- as well as
There are two internal control
DRD-
8
1-2
2-3
8
8
for all the
is done
and
(this is the default __ ~~·_u
6-8
The internal ..I1_,.......·a_........'a.
8 RAM. The links
2K
9-10
8-10
The
PAL
DWR-
s.
FDCEN -
DSTRD-
ROMEN- and RAMEN-.
lines AO
380Z8oard
andA1.
can
The
code.
t:he
are a.
follow.
PDC
DOH
to
03B
to
04:
07:
08H
to
08R
09
OA
08
Port OOBR
Port 1
ODH
RAM
Internal
to PPFFH
00008 to 1PFPH
a
'wait'
cleared
Control
)
two
a. .ide
with a
two
of the
380Z IOCBoard
34 SN74LS379N)
Port
drive size bit
use' •
for 'IDe
for
All
1) •
The
5.25-inch
the
from Port
74LS157
(IC 1 is used to select the different
for use with 5.25-inch or 8-inch drives. The links
for a YE-Data
but, to enable use with the
and
drives, a set of links is
the functions
YE-data
SMC
16B
handle
on
The
link LK3 2-3, LK3 5-6, LK4 1-2
link LK3 -2 LK3 4-5 disconnect LK4
For 5 25-inch drives:
2.
BASF
08
YE Data YO 274
link LK3 8-9
link LK3 7-8
For 8-inch drives:
link LK3 8-9
are two
•
•
The
of data
for in the
set
device.
The SMC9216B
The
with
necessary to
that are not
Therefore
remove the 92
(IC 32
remove the MB4393 (IC
), MB14323
also
the two
are described
remove the data
for use with the YE-Oata
for use with the SMC 921
(IC 26) and MB14324 (IC 33
several other
tolerance. The two
IC 24) and MONOS (IC 25)
of 2.5us and
Ous
data is used to
non-cr'~~,~c~a~), which decreases the
)
The
free-run
5.
380Z
the various
t.race the
of t.he
en lat.er
of ICs
These
a
of a
the cause
int.o t.he
Use these not.e.
t.he board schemat.ic
and each is
are
1.
on power-up.
2.
3
3.
3
3.
4.
3.3
3.4
5.
6.
. .v ..........'v. .
on
2.
no boot.
4.
5.
6.
error ae.8age.
to boot. or does
boot..
the
•
•
of
•
Further
•
Z80
•
hints
•
6.
IDC
IDe
No COS
on
Tests:
Press RESET
N
~
~
Check for correct
connections to, or
shorts on, J3
IC4
IC ._-_ ..
ICS -ALS1244
IC11-ALS1
,;:o...
y
-~
IC9 -ALS574
IC19-IDCEXT
IC10-ALS 244
remove IC 35.
when RESET, check between
IWAITO & IWAIT1 from
&
0,
.
)
6.2
6VJIlDt~om
2
LED
not on.
Run
y
ADDPLASH
fault
See p.14)
IC39 -LS377
IDCINT PAL
IC 42
y
9!Rlrl'~"""---_'"
CLOCK CCTRY
IC45 - LS 04
- LS 393
-LS 11
IC46
Check PCB for shorts
IDe
D1'.CIlo.Ollt1.CS
LED
-FAULT 2' (RAM fault).
Tests
Check LK 10
IDCINT PAL IC42
RAM
ADDFLASH
see p.14
Run
6.4
LBD ......
~1I!!I
• PAULT 3
1lI. . . . & . . . . .
IC42
6.
( ROM
LED
'FAULT 4 1
IC 42
FOC
IC 41
Check FCLK
IC
IC 3
2MHz - 8" selected
1MHz - 5" selected
6.6
FOC fault).
5'
6.
•
IDe
D1..lQI'Jt08~t.1(:S
'FAULT 6
IDCEXT
SIO
IC 40
Check CLOCK CCTRY
IC 4S - LS 04
IC 28
393
IC
11
.8
).
S
4
Press
Press "B"
y
L1C10
N
Short DRVO(
2
to OV.
N
dl:ive
6.
5
appears
No boot - error
Press
IB
to boot
I
Go to Front Panel
)
&
look at
E8:
y
1"""""~,,,.. rtt..1
y
y
_ ......
_&&_~
host interface
3BOZ IDe
Breaks t.o Pronto
.. <boot.
on boot.
) or <boot
U1IlGl1l0S11:1C:.
an unformat.ted disc.
or no
I>
,
480Z .. <drive not
480Z
<boot error>
disc or bad
33
2S
480Z .. <disc error>
IC 36,
IC 32)
that. the
(IC40
IC
2".)
-_...._- or bad
480Z" <?boot?>
1
380Z IDC
5V1DDt:om
6
D1~!lQJ~Oa:I1:1.CS
takes a
time to boot or does not
Tests
Check LX 6
size select)
Check R3-R5
R47
Data
17- MB4393
IC 33- MB14324
IC
IC
in
cct.
IC 26- MB
(IC 32- SMC9216)
IC 21,24,25- LS123
IC 38- LS27
6.12
boot.
3aoz
Insert
and 8Witch on •••••
ROM
y
All data bits are
ZaOdat.a bus
AD - A4
on Z80
bus
on
zaD
LED
. . . . . . . . . . . . . . .10 _ _
Bad
around ZaD
shorts,
J3.
, control
ZaD •••
6.13
on
•
AS - A12zao
not. shorted
be
low.
Drive select
decoded OIt.
on
~
but. could
39
380Z IDC
IDe
Notes on the
Insert ADDFLASH in ROM socket and switch on •••
y
Z80 data bus OK
Z90 addr.
OK
- D7)
- A12)
host interface
N
If IDCFLASH
check AS & A6.
The LED flashes
pauses
for about 3 sees and flashes
the
Z80 address bus faults:
2
3
4
5
6
flash
flashes
flashes
flashes
flashes
flashes
A7
AS
A9
A10
A11
A12
if address line short circuits
to +5 then next address up will be
indicated as
, so check: both.
NB
6.14
380Z IDe
PALs
)
wn~LeE~-DUrl).Llt-Oralrlae
CTCEN-
SIOBN-
BWR-, HRD-,
ROMEN-, RAMEN-, FDCBNO-, DWR-
DRD- ,
devices on the
interfere with
CTC
as these
Links.
L1C6
.'rrL:
It
- select
for
)
(link
LJC9
select ROM
(now
LIC10
select
(
of
RAM for 2k
that there is no LS where
worth
PCB
should
be.
Clock:
An
is used rather thanS04.
also that 1lt2 resistors are
for R28 29.
Errors
the
could be due to
wrong value.
Ohm.
Shorts:
for shorts
tracks
, where there are 'tn]~O~lan holes
modifications have
done
PCB
on the
• 5
380Z IOC
U14lgnLOS~t.1C:S
IDC DIAGNOSTICS
on the Z80
A7-13
AO-6
A14, 5
PHI
DO-7
Vee
INT
NMI
IDCFLASH is used.
1
30-36
4
6
7-10 12-14
11
L
16
17
L
H
18
19
H
I
I
I
H
20
2
22
I
H
WAIT
24
I
H
BUSAK
RESET
26
M1
RFSH
28
GND
29
H -
L - low,
L
I-
.16
A
IDC
The current ...,·
,
"""".1iJi
are
FDS
IC
IC
IC
to IC
to IC 2
to
side CS
sideCS1 TO IC
IC 2
to IC
Under IC 21 to IC2
104
IC
IC
IC
to IC
to IC
to IC
MDS
As FDS + IC
toR26
As FDS
tolC
IC
As PDS.
6.17
near C48
3
Network
SECTION
A transceiver
carrier and
electronics
8MHzclock
receive. a
defined in
an
as
The
Rl'S
to
the
_ f t...,...........
DTR
used
paCKel:
and
• ·transceiver
be
bus cable.
an
transceivers should
line on the net.work
7.1
380Z Network Transceiver
380Z NETWORK INTERFACE BOARD
This board is a
Network Interface
relevant circuit
board and
be
either as a
or as a Dual Serial Interface Board. The
380Z-NET-1 Version I
March 1982
380Z-NET-2 Version F 30th March 1982
380Z-NET-3
H
March 1982
Version B 30th
In this
standard
Internal
The
the
Baud rate
is
38k4 baud may be used. Channel
and receive baud rates.
channel 0 or the transmit
CTC2 channel 1 or the
baud rate is controlled
as
a
The Network Interface
NET-2)
This
based on an
rate 800kHz. Data
are buffered and
or
••
inSOLe mode at the
Clock
and Out RTS, CTS, DTR and
ribbon cable to either
rear
a
an
is
to power the transceiver.
to
7.2
A
380Z Network Transceiver
Tx
This is
rates
driven
DIL header
via a "User
the
are dealt with
confusion
noraal DTB
cut and
the current
can
3.n1t.e J~r~lD't, or
Standard data
may be
via a
to a
This is a
cable. All
for
PCB links should be
should be wired
c:
B
RxD
Rl'S
1
2
14
3
CA
eTS
4
CB
DTIt
DCD
6
DF
This is
baud clock
channels. All
counts are
clock and another
).
CTC is intended
B:>st usual
PCB lints and
HeilCle~r
B:
3
4
5
6
15
14
13
**
1
ZC1
**
5kHz
8
*
TrO
**
baud
380Z Network Transceiver
Full-standard
with all
other boards
connected
board
PCB links and
will be:
DMA
CTC 1
is
CTC2
A:
CTC2EO
CTC
2
DMAEO
SIOEO
BIEI
3
DMAEO
7
CTC2BI
DMABI
SEOEI
8
DHAEI
and DHAEI are shorted with a
Header A.
If the DMA
link between
installed this link must be cut.
7 and 8 of
are
and
a PAL. The CTCs (8
), the
, the DMA 1
switch
( ) and control
( ) are all
from DOH to DFH
between the two standard FOC blocks. The PAL
is
a number POn, where n shows the
The
current correct version is PD7 revision C
DF
DO
SIO-B Control
SIO-B Data
Control
Data
07
06
04
D3
02
00
Channel 3
CTC2 Channel 2
CTC2
1
Channel 0
3
CTC
CTC
CTC1
CTC1
2
.4
baud rate
380Z Network Transceiver
on standard
DNA Controller
NET-1 )
When the DNA controller is
two
the
chain and the other in the
links must be cut
one in
chain.
chain has been introduced, to enable
(or server). BBAI
and BBAO
for
and are similar to the
for
A link
the ZSO bus to the
on the first (or
Red
Wait states are introduced on
when the DMA has control of
bus to make memory
the same as the CPO. The
each SIO channel are routed to either the Wait line or
under the control of seven bits in the control
on standard __ ~__
the Control Port
w••
The WRSx
control the
selection Bit 6 is an enable and
bits 5 to 0 select any of the 32
combinations of SIO channels A
B
under Wait-state or Kelaa'y-'t.r1crcrerea. modes. The
selections are in a
but for fixed
a OIL
header may be substituted for the PROM.
connected
a
cutable link on the standard
2
3
A
B
16
15
14
4
3
5
6
12
11
8
10
9
Wait
SIO and DMA
The SIO and DMAdevices are treated as a series of internal
accessible
address. Each SIO channel
two
data
) and control (seven write
and three read
~~-~~~.~~~).
However these are
with certain
both channels. The DNA
one
which all 21
are accessed
sequences; the maximum
is five
Care should be taken in the initialization and
of
these devices, and
use of tables is
in all but the most timecritical
The SIO can
order of
up to
these are
vectored
7.
(four per channel).
In
Network Transceiver
•
Conditions (Receive overrun, End of frame,
Receive Character Available
•
Transmit Buffer
•
error)
•
has
Ch.annel
B.
TheDMA
•
On
•
On Match
•
On End of
•
a data
Block.
Match
connected to
baudclock standard
rates
division. ratios. The control
and t.ime
standard rates are as follows:
When
may be
constants to
10 Baud
078
150 Baud
478
478
478
478
478
478
478
The relevant
28
64
32
4
should
300
600
200
2400
4800
Baud
Baud
Baud
Baud
Baud
Baud
19k2 Baud
38k4 Baud
loaded to CTC2
2.
380Z Network Transceiver
J1
3M
SA
1
3
BB
5
AA
CA
9
cc
1
AS
13
Header
2
4
8
10
12
14
CD
CF
18
20
J3
Network
3M Header
Clock Out
Clock In
TxD
3
12
RxD
Rl'S
DTR
OV
OV
OV
4
8
9
CTS
12
4
+12V
J4
Present
16
Z50 BUS
3M
Header
2
4
BD2
BD4
BD6
1
3
5
7
9
8
10
'BAD
BA2
1
13
12
14
BA4
BA6
BA8
15
16
17
19
20
BOO
BA10
BA12
BA14
BUSAKBNMI-
BRDBRPSHOV
+5V
+5V
ov
OV
2
23
18
24
26
28
30
32
34
36
25
27
29
31
33
35
37
39
41
40
42
43
44
45
47
49
46
48
50
BPAGE
BD1
BD3
BD5
BD7
BA1
BA3
BAS
BA7
BA9
SAl
BA13
BWAITBHALTBWR-
BMlBCLK
+SV
2V
OV
OV
380Z Network Transceiver
J5
BBAI
2mm Yellow
J6
BBAO
2mm Blue
J7
BIEI
2mm Red
J8
BIEO
2mm Black
The standard
ICs
AP
AR
AS
AT
AU
BP
BR
BS
BT
BV
CP
CR
74LS244
omit
898-3-R330
74LS244
omit
omit
74LS244
omit
74LS245
omit
omit
75 88
89
4L4 DMALOGc
PAL10L8 PD7c
omit
CS
DR
EP
FP
FR
FS
FT
FU
GR
74LS32
74S04
74LS244
74LS74
74LS244
74LS 23
74L07
Z80A-CTC
Z80A-CTC
omit
switch
74LS161
CD4040
74LS30
GT
GV
GW
GX
omit
omit
omit
74LS04
Power
SOOmA
15mA
(omitted on standard board)
on standard board)
Network Interface Board
.....-."_...._ . . . """"_ with the
380Z Network
"'''1110_.11 __
480Z BAJRD1'AFtE
All
are
• •)De~d
and controlled
a PROM
2 4 S I O - A Data
25
SIO-8
SIO-A "_.,,.....SIO-8 Control
27
480Zs have a
transceiver board.
of DIL sockets
1
2
3
4
5
-12V
OV
SOOkHz
IN1
6
CUT0
7
RxD
NET 1
2
DTR
CTS
3
4
5
6
a
14
1
10
S
14
3
12
11
8MHz
IN2
WaitSWait-
RxC
TxD
RTS
DCD
10
9
8
Por
OV
3
&MHz
with a 3S0Z Network Interface board:
&MHz
1
J2-S
800kHz
OV
2
3
4
J2-14
ov
6
J2- 3
RxD
OV
RrS
CTS
DTR
DCD
+12V
J2-1
8
9
10
1
12
13
+12V
14
Trev Present
Chassis
1
16
J2-12
J2-4
J2-3
J2- 1
380ZRost.
Board
DIOdules.
When
t:hat:
t:o SASI. This new
environaent and at
available
The HIB circuit
1:.0trre':ftltr
to interface the
HIB
•
•
•
is
Bus
with soae
on
connect t:he BIB to the 380Z bus.
and ae-.oiry. . .ppea
oD,-Doara RAM.
8.1
•
380Z Host
Board
PIO
SASI data
SASI
SASI termination
A full
The
of these modules is
below.
address
is
IC
of an inverter IC AK
BINT- are
an open
chain
is serviced
the data
The
Addresses
M1- are used
MCONTROLcontrol
as
PIOM1PIOEN-
IORD-
When this
is active
bus.
MEMRD-
Indicates that on-board RAM is read
active.
DBMEMEN-
Enables on-board RAM for
fed
an
taken care of
be activE! when
when the 380Z is
table shows
8.2
the 380Z and that
and AH
is in the process of an
either the on-board RAM
of the
380Z
'B'
8IC
•
RAM
all be read at once the
RAM to be
memory
chunks.
internal
an internal refresh
onto the bus. Some
Toshiba
as
RAM
DBBNlow'
and a WAIT will be
also be
such as the
on
The PIO IC
is
and co-ands
channel 'B
channel for
defines the
channel 'A
to BASI. It handles
and control
from and to SASI
is used to select
Z80A-CPO and Z80A-PIO,
to be
i.e.
8
in
and B07 are u8ed &S
The
clock is fed ~jrOtlan
bits are used as
an open
buffer with the
lled up
resistor, to DrC)CltICe ZCLOCK for the PIO.
BOO,
1, B02,
MSB
uses
, B06
via IC
Data transfer
t.ransceiver
ca, an
channel '.
and BDS
of IC
3300ha
collector
Control to
control
unless
RDAClCDBL but
1s enabled
IC CBwhen IN
8.3
is
SDBUFENlow'
to SASI) and
3BOZ
Host Interface
RDACK or RDACKDEL enable IC CB when IN is
WRACKDEK and RDACKDEL are
the
sides of the
network,
bus to
resistor
SASI side and co~nn.!ct:1n,q to a 2.9V
is derived
a three diode
7V
across each diode). Particular
SASI control
: a 0.56 Ohm resistor
noise elimination.
and HIB
for
8.4
from SASI).
SASI.
•
«''I.&''
.-
At
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It
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..
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