Download Dataram DTM64330A memory module

DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
Identification
DTM64330A 1Gx72
8GB 4Rx8 PC3-8500R-7-10-H0
Performance range
Clock / Module Speed / CL-tRCD -tRP
533 MHz / PC3-8500 / 8-8-8
533 MHz / PC3-8500 / 7-7-7
400 MHz / PC3-6400 / 6-6-6
Features
Description
240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm high
DTM64330A is a registered 1Gx72 memory
module, which conforms to JEDEC's DDR3, PC38500 standard. The assembly is Quad-Rank.
Each Rank is comprised of nine 256Mx8 DDR3
Hynix SDRAMs. One 2K-bit EEPROM is used for
Serial Presence Detect and a combination
register/PLL, with Address and Command Parity,
is also used.
Operating Voltage: 1.5V ±0.075
I/O Type: SSTL_15
2
On-board I C temperature sensor with integrated Serial Presence-Detect
(SPD) EEPROM
Data Transfer Rate: 8.5 Gigabytes/sec
Data Bursts: 8 and burst chop 4 mode
Both output driver strength and input termination
impedance are programmable to maintain signal
integrity on the I/O signals in a Fly-by topology. A
thermal sensor accurately monitors the DIMM
module and can prevent exceeding the maximum
operating temperature of 95C. A Heat Spreader is
attached to improve the thermal characteristics of
the module.
ZQ Calibration for Output Driver and On-Die Termination (ODT)
Programmable ODT / Dynamic ODT during Writes
Programmable CAS Latency: 6, 7, and 8
Bi-directional Differential Data Strobe signals
SDRAM Addressing (Row/Col/Bank): 15/10/3
Fully RoHS Compliant
Pin Configuration
Front Side
Pin Description
Back Side
Name
Function
1
VREFDQ 31 DQ25
61
A2
91 DQ41 121 VSS
151 VSS
181 A1
211 VSS
CB[7:0]
Data Check Bits
2
VSS
32 VSS
62
VDD
92 VSS
152 DM3
182 VDD
212 DM5
DQ[63:0]
Data Bits
3
4
5
6
DQ0
DQ1
VSS
/DQS0
33
34
35
36
63
64
65
66
CK1*
/CK1*
VDD
VDD
93
94
95
96
153 / TDQS12
154 VSS
155 DQ30
156 DQ31
183 VDD
184 CK0
185 /CK0
186 VDD
213
214
215
216
DQS[8:0], /DQS[8:0]
DM[8:0]
/TDQS[17:9]
CK[1:0], /CK[1:0]
Differential Data Strobes
Data Mask
Termination Data Strobes
Differential Clock Inputs
7
8
9
DQS0 37 DQ27
VSS
38 VSS
DQ2
39 CB0
67
68
69
VREFCA
PAR_IN
VDD
97 DQ43 127 VSS
98 VSS
128 DQ6
99 DQ48 129 DQ7
157 VSS
158 CB4
159 CB5
187 /Event
188 A0
189 VDD
217 VSS
218 DQ52
219 DQ53
CKE[1:0]
/CAS
/RAS
Clock Enables
Column Address Strobe
Row Address Strobe
A10/AP
BA0
VDD
100 DQ49 130 VSS
101 VSS
131 DQ12
102 /DQS6 132 DQ13
160 VSS
190 BA1
161 DM8
191 VDD
162 / TDQS17 192 /RAS
163 VSS
/DQS3
DQS3
VSS
DQ26
122 DQ4
/DQS5 123 DQ5
DQS5 124 VSS
VSS
125 DM0
DQ42 126 /TDQS9
/ TDQS14
VSS
DQ46
DQ47
10 DQ3
11 VSS
12 DQ8
40 CB1
41 VSS
42 /DQS8
70
71
72
13 DQ9
43 DQS8
73
/WE
103 DQS6 133 VSS
14
15
16
17
44
45
46
47
74
75
76
77
/CAS
VDD
/S1
ODT1
104 VSS
105 DQ50
106 DQ51
107 VSS
78
79
80
VDD
/S2
VSS
108 DQ56 138 DQ15
109 DQ57 139 VSS
110 VSS
140 DQ20
168 /RESET
169 CKE1
170 VDD
198 /S3
199 VSS
200 DQ36
228 DQ61
229 VSS
230 DM7
21 DQ16 51 VDD
81
DQ32
111 /DQS7 141 DQ21
171 A15
201 DQ37
231 / TDQS16 VREFDQ
Reference Voltage for DQ
22
23
24
25
26
27
82
83
84
85
86
87
DQ33
VSS
/DQS4
DQS4
VSS
DQ34
112 DQS7
113 VSS
114 DQ58
115 DQ59
116 VSS
117 SA0
142 VSS
172 A14
143 DM2
173 VDD
144 / TDQS11 174 A12/ /BC
145 VSS
175 A9
146 DQ22
176 VDD
147 DQ23
177 A8
202 VSS
203 DM4
204 /TDQS13
205 VSS
206 DQ38
207 DQ39
232
233
234
235
236
237
Reference Voltage for CA
Termination Voltage
Temperature Sensing
No Connection
28 DQ19 58 A5
88
DQ35
118 SCL
148 VSS
178 A6
208 VSS
238 SDA
29 VSS
59 A4
30 DQ24 60 VDD
89
90
VSS
DQ40
119 SA2
120 VTT
149 DQ28
150 DQ29
179 VDD
180 A3
209 DQ44
210 DQ45
239 VSS
240 VTT
VSS
/DQS1
DQS1
VSS
VSS
CB2
CB3
VSS
18 DQ10 48 VTT
19 DQ11 49 VTT
20 VSS
50 CKE0
DQ17
VSS
/DQS2
DQS2
VSS
DQ18
52
53
54
55
56
57
BA2
/ERR_OUT
VDD
A11
A7
VDD
193 /S0
134 DM1
164 CB6
194 VDD
135 / TDQS10 165 CB7
195 ODT0
136 VSS
166 VSS
196 A13
137 DQ14
167 NC (TEST) 197 VDD
220 VSS
/S[3:0]
221 DM6
/WE
222 / TDQS15 A[15:0]
Chip Selects
Write Enable
Address Inputs
223 VSS
BA[2:0]
Bank Addresses
224
225
226
227
ODT[1:0]
SA[2:0]
SCL
SDA
On Die Termination Inputs
SPD Address
SPD Clock Input
SPD Data Input/Output
VSS
VDD
VDDSPD
Ground
Power
SPD EEPROM Power
DQ54
DQ55
VSS
DQ60
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
VREFCA
VTT
/Event
NC
* Not used
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
Page 1
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
Front view
133.35
[5.250]
9.50
[0.374]
30.00
[1.181]
17.30
[0.681]
5.00
[0.197]
5.175
[0.204]
47.00
[1.850]
71.00
[2.795]
2.50
[0.098]
123.00
[4.843]
Back view
Side view
7.493 Max
[0.295] Max
w/heatspreader
4.00 Min
[0.157] Min
1.27 ±.10
[0.0500 ±0.0040]
Notes
Tolerances on all dimensions except where otherwise
indicated are ±.13 (.005).
All dimensions are expressed: millimeters [inches]
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
Page 2
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
/RS3
/RS2
/RS1
/RS0
DQSR0
/DQSR0
DMR0
/TDQSR9
I/O[7:0]
DQR[39:32]
RANK 2
RANK 3
/DQS
DQS
I/O[7:0]
DQR[55:48]
I/O[7:0]
/DQS
DQS
DM
TDQS
/CS
NU
/TDQS
/DQS
DQS
DM
TDQS
/CS
NU
/TDQS
DQSR6
/DQSR6
DMR6
/TDQSR15
I/O[7:0]
NU
/TDQS
DM
TDQS
/CS
NU
/TDQS
/DQS
DQS
DQR[56:63]
I/O[7:0]
/DQS
DQS
DQSR7
/DQSR7
DMR7
/TDQSR16
DQSR3
/DQSR3
DMR3
/TDQSR12
DQR[31:24]
DM
TDQS
/CS
NU
/TDQS
DM
TDQS
/CS
NU
/TDQS
/DQS
DQS
DQR[47:40]
I/O[7:0]
DQSR2
/DQSR2
DMR2
/TDQSR11
DQR[23:16]
RANK 1
RANK 0
DQSR5
/DQSR5
DMR5
/TDQSR14
DQSR1
/DQSR1
DMR1
/TDQSR10
DQR[15:8]
I/O[7:0]
/DQS
DQS
RANK 3
DM
TDQS
/CS
RANK 2
NU
/TDQS
RANK 1
RANK 0
DM
TDQS
/CS
DQR[7:0]
/DQS
DQS
DM
TDQS
/CS
NU
/TDQS
DQSR4
/DQSR4
DMR4
/TDQSR13
I/O[7:0]
CBR[7:0]
/DQS
DQS
DM
TDQS
/CS
NU
/TDQS
DQSR8
/DQSR8
DMR8
/TDQSR17
I/O[7:0]
V DD
TO SDRAMS
All 15 OHMS
DQR[63:0]
CB[7:0]
BA[2:0]
CBR[7:0]
DQS[8:0]
/DQS[8:0]
DM[8:0]
/TDQS[17:9]
/RS[3:0]
/S[3:0]
BA[2:0]R
/RAS
/DQSR[8:0]
/CAS
/WE
DMR[8:0]
CKE0
/TDQSR[17:9]
CKE1
ODT0
All 22 OHMS
BA[2:0]R
LCLK[3:0]
RCLK[3:0]
/LCLK[3:0]
/RCLK[3:0]
/RASR
/CASR
ODT1
PAR_IN
GLOBAL SDRAM CONNECTS
CK0
120
OHMS
/CK0
/WER
CKE0R RANK 0 & 2
CKE1R RANK 1 & 3
ODT0R RANK 0
ODT1R RANK 2
/ERR_OUT
L,R(CLK)[3:0]
/L,R(CLK)[3:0]
DECOUPLING
V DDSPD
V DD
V REF_DQ
V SS
VREF_CA
V TT
Serial PD
All Devices
All SDRAMs
All Devices
All SDRAMs
All SDRAMs
/RESET
A[15:0]R
/RASR
SDRAMS
/CASR
/WER
VTT
/EVENT
All 240 OHMS
All 22 OHMS
CKE[1:0]R
ODT[1:0]R
RS[1:0]
All 39 OHMS 100 nF
A[15:0]R
A[15:0]
DQSR[8:0]
REG / PLL
DQ[63:0]
VDD
All 39 OHMS 100 nF
All
22 OHMS
SCL
ZQ
VTT
VSS
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
TEMPERATURE MONITOR/
SERIAL PD
SA0
SA1
SDA
SA2
Page 3
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
Absolute Maximum Ratings
(Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.)
PARAMETER
Symbol
Minimum
Maximum
Unit
Temperature, non-Operating
TSTORAGE
-55
100
C
TA
0
70
C
Ambient Temperature, Operating
TCASE
0
95
C
VDD
-0.4
1.975
V
VIN,VOUT
-0.4
1.975
V
DRAM Case Temperature, Operating
Voltage on VDD relative to VSS
Voltage on Any Pin relative to VSS
Notes:
DRAM Operating Case Temperature above 85C requires 2X refresh.
Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Power Supply Voltage
Symbol
VDD
Minimum
1.425
Typical
1.5
Maximum
1.575
Unit
V
Note
I/O Reference Voltage
VREFDQ
0.49 VDD
0.50 VDD
0.51 VDD
V
1
I/O Reference Voltage
VREFCA
0.49 VDD
0.50 VDD
0.51 VDD
V
1
Notes:
1) The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may
not exceed ±1% of its DC value.
DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Logical High (Logic 1)
Symbol
VIH(DC)
Minimum
VREF + 0.1
Maximum
VDD
Unit
V
Logical Low (Logic 0)
VIL(DC)
VSS
VREF - 0.1
V
AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Logical High (Logic 1)
Symbol
VIH(AC)
Minimum
VREF + 0.175
Maximum
-
Unit
V
Logical Low (Logic 0)
VIL(AC)
-
VREF - 0.175
V
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
Page 4
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Differential Input Logic High
Differential Input Logic Low
Differential Input Cross Point Voltage
relative to VDD/2
Symbol
VIH.DIFF
Minimum
+0.200
Maximum
DC:VDD AC:VDD+0.4
Unit
V
VIL.DIFF
DC:VSS AC:VSS-0.4
-0.200
V
VIX
- 0.150
+ 0.150
V
Capacitance (TA = 25 C, f = 100 MHz)
PARAMETER
Pin
Symbol
Minimum
Maximum
Unit
CCK
1.5
2.5
pF
Input Capacitance, Clock
CK0, /CK0
Input Capacitance, Address
BA[2:0], A[15:0], /RAS, /CAS, /WE
CI
1.5
2.5
pF
Input Capacitance Control
/S[3:0], CKE[1:0], ODT[1:0]
CI
1.5
2.5
pF
Input/Output Capacitance
DQ[63:0], CB[7:0] DQS[8:0], /DQS[8:0],
DM[8:0], /TDQS[17:9]
CIO
6
10
pF
DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Input Leakage Current
Symbol
Minimum
Maximum
Unit
Note
IIL
-18
+18
μA
1,2
IOL
-10
+10
μA
2,3
(Any input 0 V < VIN < VDD)
Output Leakage Current
(0V < VOUT < VDDQ)
Notes:
1) All other pins not under test = 0 V
2) Values are shown per pin
3) DQ, DQS, DQS and ODT are disabled
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
Page 5
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Operating One
Bank ActivePrecharge Current
Operating One
Bank Active-ReadPrecharge Current
Precharge PowerDown Current
Precharge PowerDown Current
Precharge Standby
Current
Active Power-Down
Current
Active Standby
Current
Operating Burst
Write Current
Operating Burst
Read Current
Burst Refresh
Current
Self Refresh
Current
Operating Bank
Interleave Read
Current
Symbol
Test Condition
Max
Value
Unit
IDD0*
Operating current : One bank ACTIVATE-to-PRECHARGE
999
mA
IDD1*
Operating current : One bank ACTIVATE-to-READ-toPRECHARGE
1089
mA
IDD2P**
Precharge power down current: (Slow exit)
432
mA
IDD2P**
Precharge power down current: (Fast exit)
1080
mA
IDD2N**
Precharge standby current
1620
mA
IDD3P**
Active power-down current
1260
mA
IDD3N**
Active standby current
1980
mA
IDD4W*
Burst write operating current
1629
mA
IDD4R*
Burst read operating current
1584
mA
IDD5B**
Refresh current
7560
mA
IDD6**
Self-refresh temperature current: MAX TC = 85°C
432
mA
IDD7*
All bank interleaved read current
2214
mA
* One module rank in this operation, the rest in IDD2P slow exit.
** All module ranks in this operation.
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
Page 6
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
AC Operating Conditions
PARAMETER
Symbol
Min
Max
Unit
Internal read command to first data
tAA
13.125
20
ns
CAS-to-CAS Command Delay
tCCD
4
-
tCK
Clock High Level Width
tCH(avg)
0.47
0.53
tCK
tCK
1.875
2.500
ns
tCL(avg)
0.47
0.53
tCK
tDH
100
-
ps
Clock Cycle Time
Clock Low Level Width
Data Input Hold Time after DQS Strobe
tDIPW
490
-
ps
DQS Output Access Time from Clock
tDQSCK
-300
+300
ps
Write DQS High Level Width
tDQSH
0.45
0.55
tCK(avg)
Write DQS Low Level Width
tDQSL
0.45
0.55
tCK(avg)
DQS-Out Edge to Data-Out Edge Skew
tDQSQ
-
150
ps
Data Input Setup Time Before DQS Strobe
tDS
25
-
ps
DQS Falling Edge from Clock, Hold Time
tDSH
0.2
-
tCK(avg)
DQS Falling Edge to Clock, Setup Time
DQ Input Pulse Width
tDSS
0.2
-
tCK(avg)
Address and Command Hold Time after Clock
tIH
200
-
ps
Address and Command Setup Time before Clock
tIS
125
-
ps
Load Mode Command Cycle Time
tMRD
4
-
tCK
DQ-to-DQS Hold
tQH
0.38
-
tCK(avg)
Active-to-Precharge Time
tRAS
37.5
9*tREFI
ns
Active-to-Active / Auto Refresh Time
tRC
50.625
-
ns
RAS-to-CAS Delay
tRCD
13.125
-
ns
Average Periodic Refresh Interval 0o C < TCASE < 85o C
tREFI
-
7.8
μs
Average Periodic Refresh Interval 85o C < TCASE < 95o C
tREFI
-
3.9
μs
Auto Refresh Row Cycle Time
tRFC
160
-
ns
Row Precharge Time
tRP
13.125
-
ns
Read DQS Preamble Time
tRPRE
0.9
Note 1
tCK(avg)
Read DQS Postamble Time
tRPST
0.3
Note 2
tCK(avg)
Row Active to Row Active Delay
tRRD
Max(4nCK, 7.5ns)
-
ns
Internal Read to Precharge Command Delay
tRTP
Max(4nCK, 7.5ns)
-
ns
Write DQS Preamble Setup Time
tWPRE
0.9
-
tCK(avg)
Write DQS Postamble Time
tWPST
0.3
-
tCK(avg)
Write Recovery Time
tWR
15
-
ns
Internal Write to Read Command Delay
tWTR
Max(4nCK, 7.5ns)
-
ns
Notes:
1.
2.
The maximum preamble is bound by tLZDQS(min)
The maximum postamble is bound by tHZDQS(max)
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
Page 7
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
SERIAL PRESENCE DETECT
MATRIX
Byte#
0
Function.
Value
Hex
0x92
1
Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage.
Bit 3 ~ Bit 0. SPD Bytes Used 176
Bit 6 ~ Bit 4. SPD Bytes Total 256
Bit 7. CRC Coverage Bytes 0-116
SPD Revision.
Rev. 1.0
2
Key Byte / DRAM Device Type.
0x0B
3
Key Byte / Module Type.
DDR3
SDRAM
0x01
Bit 3 ~ Bit 0. Module Type Bit 7 ~ Bit 4. Reserved -
4
6
SDRAM Density and Banks.
Bit 3 ~ Bit 0. Total SDRAM capacity, in megabits Bit 6 ~ Bit 4. Bank Address Bits Bit 7. Reserved SDRAM Addressing.
Bit 2 ~ Bit 0. Column Address Bits Bit 5 ~ Bit 3. Row Address Bits Bit 7, 6. Reserved
Reserved.
7
Module Organization.
5
RDIMM
0
0x03
2Gb
8 banks
0
0x19
10
15
0
UNUSED
10
11
Medium Timebase (MTB) Divisor.
12
SDRAM Minimum Cycle Time (tCKmin).
2
5
1 (MTB =
0.125ns)
8 (MTB =
0.125ns)
1.875ns
13
Reserved.
UNUSED
14
CAS Latencies Supported, Least Significant Byte.
Bit 0. CL = 4 Bit 1. CL = 5 Bit 2. CL = 6 Bit 3. CL = 7 Bit 4. CL = 8 -
9
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
0x00
0x19
Bit 2 ~ Bit 0. SDRAM Device Width Bit 5 ~ Bit 3. Number of Ranks Bit 7, 6. Reserved
Module Memory Bus Width.
Bit 2 ~ Bit 0. Primary bus width, in bits Bit 4, Bit 3. Bus width extension, in bits Bit 7 ~ Bit 5. Reserved Fine Timebase (FTB) Dividend / Divisor.
Bit 3 ~ Bit 0. Fine Timebase (FTB) Divisor
Bit 7 ~ Bit 4. Fine Timebase (FTB) Dividend
Medium Timebase (MTB) Dividend.
8
0x10
8-Bits
4-Rank
0
0x0B
64-Bits
8-Bits
0
0x52
0x01
0x08
0x0F
0x00
0x1C
X
X
X
Page 8
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
16
Bit 5. CL = 9 Bit 6. CL = 10 Bit 7. CL = 11 CAS Latencies Supported, Most Significant Byte.
Bit 0. CL = 12 Bit 1. CL = 13 Bit 2. CL =14 Bit 3. CL = 15 Bit 4. CL = 16 Bit 5. CL = 17 Bit 6. CL = 18 Bit 7. Reserved.
Minimum CAS Latency Time (tAAmin).
17
Minimum Write Recovery Time (tWRmin).
18
Minimum RAS# to CAS# Delay Time (tRCDmin).
19
Minimum Row Active to Row Active Delay Time (tRRDmin).
20
Minimum Row Precharge Delay Time (tRPmin).
21
15
22
23
24
25
26
27
28
29
30
31
0x00
13.125ns
0x69
15.0ns
0x78
13.125ns
0x69
7.5ns
0x3C
13.125ns
0x69
Upper Nibbles for tRAS and tRC.
Bit 3 ~ Bit 0. tRAS Most Significant Nibble 1
Bit 7 ~ Bit 4. tRC Most Significant Nibble 1
Minimum Active to Precharge Delay Time (tRASmin), Least
37.5ns
Significant Byte.
Minimum Active to Active/Refresh Delay Time (tRCmin),
50.625ns
Least Significant Byte.
Minimum Refresh Recovery Delay Time (tRFCmin), Least
160.0ns
Significant Byte.
Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte.
0x11
Minimum Internal Write to Read Command Delay Time
7.5ns
(tWTRmin).
Minimum Internal Read to Precharge Command Delay Time
7.5ns
(tRTPmin).
Upper Nibble for tFAW.
Bit 3 ~ Bit 0. tFAW Most Significant Nibble 1
Bit 7 ~ Bit 4. Reserved 0
Minimum Four Activate Window Delay Time (tFAWmin),
37.5
Least Significant Byte.
SDRAM Optional Features.
Bit 0. RZQ / 6 X
Bit 1. RZQ / 7 X
Bit 6 ~ Bit 2. Reserved Bit 7. DLL-Off Mode Support
SDRAM Drivers Supported.
Extended Temperature Range X
Extended Temperature Refresh Rate with standard 1X refresh rate Auto Self Refresh (ASR) X
On-die Thermal Sensor (ODTS) Readout Reserved Reserved Reserved -
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
0x2C
0x95
0x00
0x05
0x3C
0x3C
0x01
0x2C
0x83
0x05
Page 9
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
Reserved 32
Reserved
33-59
Reserved
60
0x80
UNUSED
0x00
64
Module Nominal Height.
Bit 4 ~ Bit 0. Module Nominal Height max, in mm Bit 7 ~ Bit5. Reserved Module Maximum Thickness.
Bit 3 ~ Bit 0. Front, in mm (baseline thickness = 1 mm) Bit 7 ~ Bit 4. Back, in mm (baseline thickness = 1 mm) Reference Raw Card Used.
Bit 4 ~ Bit 0. Reference Raw Card Bit 6, Bit 5. Reference Raw Card Revision Bit 7. Reserved DIMM Module Attributes.
Bit 1, Bit 0. # of Registers used on RDIMM Bit 3, Bit 2. # of Rows of DRAMs on RDIMM Bit 7 ~ Bit 1. Reserved Module-Specific Section
65
Module-Specific Section
0x00
66
Module-Specific Section
0x00
67
Module-Specific Section
0xFF
68,69
Module-Specific Section
70
Module-Specific Section
0x50
71
Module-Specific Section
0x55
72-112
Module-Specific Section
UNUSED
0x00
113
114-116
117
118
119
120,121
122-125
126
127
128-131
132
133
134
135
136
137
138
139
140
141
Module-Specific Section.
Module-Specific Section
Module Manufacturer ID Code, Least Significant Byte
Module Manufacturer ID Code, Most Significant Byte
Module Manufacturing Location
Module Manufacturing Date
Module Serial Number
Cyclical Redundancy Code (CRC).
Cyclical Redundancy Code (CRC).
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
UNUSED
UNUSED
0x00
0x00
0x01
0x91
0x00
0x20
0x20
0x6E
0xA9
0x20
0x44
0x41
0x54
0x41
0x52
0x41
0x4D
0x20
0x36
0x34
61
62
63
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
0x10
30<h<=31
0
0x22
2<th<=3
2<th<=3
0x07
R/C H
Rev.0
0
0x09
1
2
0x80
UNUSED
UNUSED
CRC
CRC
D
A
T
A
R
A
M
6
4
0x00
Page 10
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
142
143
144
145
146,147
148
149
150-175
176-255
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Revision Code
DRAM Manufacturer ID Code, Least Significant Byte
DRAM Manufacturer ID Code, Most Significant Byte
Manufacturer’s Specific Data
Open for customer use
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
3
3
0
UNUSED
UNUSED
UNUSED
UNUSED
0x33
0x33
0x30
0x20
0x20
0x00
0x00
0x00
0x00
Page 11
DTM64330A
8GB - 240-Pin 4Rx8 Registered ECC DDR3 DIMM
DATARAM CORPORATION, USA Corporate Headquarters, P.O.Box 7528, Princeton, NJ 08543-7528;
Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com
All rights reserved.
The information contained in this document has been carefully checked and is believed to be reliable. However,
Dataram assumes no responsibility for inaccuracies.
The information contained in this document does not convey any license under the copyrights, patent rights or
trademarks claimed and owned by Dataram.
No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party
without prior written consent of Dataram.
Document 06588, Revision A, 15-May-10, Dataram Corporation © 2010
Page 12