Download Transcend JetRam 128MB SDRAM 168pin DIMM

128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
Description
Placement
The JM317S643A-75 is a 16M bit x 64 Synchronous
Dynamic
RAM
high
density
for
PC-133.
The
JM317S643A-75 consists of 8pcs CMOS 16Mx8 bits
Synchronous DRAMs in TSOP-II 400mil packages and
a 2048 bits serial EEPROM on a 168-pin printed circuit
board. The JM317S643A-75 is a Dual In-Line Memory
Module and is intended for mounting into 168-pin edge
connector sockets.
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible
on every clock cycle. Range of operation frequencies,
A
programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• Performance Range : PC-133.
• Conformed to JEDEC Standard 4 clocks.
B
• Burst Mode Operation.
D
• Auto and Self Refresh.
• CKE Power Down Mode.
E
• DQM Byte Masking (Read/Write)
C
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
H
• MRS cycle with address key programs.
G
Latency (Access from column address)
F
Burst Length (1,2,4,8 & Full Page)
PCB : 09-7303
• All inputs are sampled at the positive going edge of
system clock.
Data Sequence (Sequential & Interleave)
Transcend Information Inc.
I
E
• Single 3.3V ± 0.3V power supply.
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
Dimensions
Pin Identification
Side
Millimeters
Inches
A
133.35±0.40
5.250±0.016
B
65.67000
2.585000
C
23.49000
0.925000
D
8.89000
E
Symbol
Function
A0~A11,BA0,BA1 Address input
DQ0~DQ63
Data Input / Output.
0.350000
CLK0,CLK2
Clock Input.
3.00000
0.118000
CKE0
Clock Enable Input.
F
29.21±0.200
1.150±0.00800
/CS0,/CS2
Chip Select Input.
G
19.8000
0.788000
H
15.80
0.622
/RAS
Row Address Strobe
I
1.27±0.10
0.050±0.004
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
(Refer Placement)
NC
No Connection
(Refer Block Diagram AND Pinouts)
Transcend Information Inc.
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
Pinouts:
Pin
No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin
Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
Vss
NC
NC
Vcc
/WE
DQM0
DQM1
/CS0
NC
Vss
A0
A2
A4
A6
A8
A10
BA1
Vcc
Vcc
CLK0
Transcend Information Inc.
Pin
No
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin
Name
Vss
NC
/CS2
DQM2
DQM3
NC
Vcc
NC
NC
NC
NC
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
CLK2
NC
NC
SDA
SCL
Vcc
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
NC
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
NC
NC
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
NC
DQM6
DQM7
NC
Vcc
NC
NC
NC
NC
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
NC
NC
SA0
SA1
SA2
Vcc
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
JM317S643A-75-- Block Diagram
A0~A11,
BA0,BA1
DQ0~DQ7
A0~A11,
BA0,BA1
DQ0~DQ7
A0~A11,
BA0,BA1
DQ0~DQ7
A0~A11,
BA0,BA1
DQ0~DQ7
/RAS
/RAS
/RAS
/RAS
/CAS
/WE
/CS
/CKE
/CAS
/WE
/CS
/CKE
16Mx8
SDRAM
DQM
/WE
/CS
/CLK
/CAS
16Mx8
SDRAM
DQM
/CKE
/CLK
/CS
DQM
/CKE
/CLK
/CAS
16Mx8
SDRAM
/WE
DQM
16Mx8
SDRAM
/CLK
DQM0
DQM1
DQM2
DQM3
A0~A11,
BA0,BA1
DQ0~DQ7
A0~A11,
BA0,BA1
DQ0~DQ7
A0~A11,
BA0,BA1
DQ0~DQ7
A0~A11,
BA0,BA1
DQ0~DQ7
/RAS
16Mx8
/RAS
16Mx8
/RAS
16Mx8
/RAS
16Mx8
/CAS
SDRAM
/CAS
SDRAM
/CAS
SDRAM
/CAS
SDRAM
DQM4
DQM5
SCL
DQM6
Serial EEPROM
SCL
SDA
A0 A1 A2
SA0 SA1 SA2
/CKE
/CLK
/WE
/CS
DQM
/CKE
/CLK
/CKE
/CLK
/CLK
DQM
/CKE
/WE
/CS
DQM
/WE
/CS
/WE
/CS
DQM
DQM7
SDA
This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties, either
expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make
changes in specifications at any time without prior notice.
Transcend Information Inc.
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0~4.6
V
Voltage on VDD supply to Vss
VDD, VDDQ
-1.0~4.6
V
TSTG
-55~+150
°C
Power dissipation
PD
8
W
Short circuit current
IOS
50
mA
Storage temperature
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°°C)
Parameter
Symbol
Min
Type
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH=-2mA
Output low voltage
VOL
-
-
0.4
V
IOL=2mA
IIL
-10
-
10
uA
3
Input leakage current (Inputs)
Note
Note: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Transcend Information Inc.
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
CAPACITANCE (TA = 25°C, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A11, BA0~ BA1)
CIN1
30
45
pF
Input capacitance (/RAS, /CAS, /WE)
CIN2
30
45
pF
Input capacitance (CKE0)
CIN3
30
45
pF
Input capacitance (CLK0,CLK2)
CIN4
22
30
pF
Input capacitance (/CS0,/CS2)
CIN5
15
25
pF
Input capacitance (DQM0~DQM7)
CIN6
6
8
pF
Data input/output capacitance (DQ0~DQ63)
COUT
6
8
pF
Transcend Information Inc.
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
ICC1
Precharge Standby Current ICC2P
in power-down mode
ICC2PS
ICC2N
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Burst Length =1
tRC≥tRC(min)
IOL=0mA
Unit
Note
960
mA
1
CKE≤VIL(max), tCC=10ns
8
CKE & CLK≤VIL(max), tCC=
8
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input singals are changed one time during 30ns
CKE≥VIH(min), CLK≤VIL(max), tCC=
mA
Input singals are stable
56
ICC3P
CKE≤VIL(max), tCC=10ns
40
ICC3PS
CKE & CLK≤VIL(max), tCC=
40
ICC3N
Input singals are changed one time during 30ns
ICC3NS
Input singals are stable
mA
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
240
CKE≥VIH(min), CLK≤VIL(max), tCC=
IOL= 0 mA
Page Burst
Operating Current
(Bust Mode)
ICC4
Refresh Current
ICC5
tRC≥tRC(min)
Self Refresh Current
ICC6
CKE≤0.2V
Transcend Information Inc.
mA
160
ICC2NS
160
mA
600
mA
1
1160
mA
2
16
mA
tccD = 2CLKs
Note: 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL=VDDQ/VSSQ)
Value
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
Output
V O H (DC)=2.4V, IO H = - 2 m A
V O L (DC)=0.4V, IO L = 2 m A
Z0=50 Ohm
50pF
50pF
870 Ohm
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
(Fig. 1) DC Output Load Circuit
Parameter
Symbol
(Fig. 2) AC Output Load Circuit
Value
Unit
Note
Row active to row active delay
tRRD(min)
15
ns
1
/RAS to /CAS delay
tRCD(min)
20
ns
1
Row precharge time
tRP(min)
20
ns
1
tRAS(min)
45
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
65
ns
1
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
Row active time
Number of valid
CAS latency=3
2
-
-
output data
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend Information Inc.
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
(value)Min
(Valure)Max
Unit
Note
CLK cycle time
tCC
7.5
1000
ns
1
CLK to valid output delay
tSAC
5.4
ns
1, 2
Output data hold time
tOH
3.0
ns
2
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
tSHZ
5.4
in Hi-Z
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the paremeter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend Information Inc.
ns
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Refresh
Auto Refresh
Entry
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
/CS
/RAS
/CAS
/WE
DQM
BA0,1
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
Clock Suspend or Entry
Active
Power
Down
Exit
Entry
X
H
X
H
L
L
H
H
L
Precharge Power
Down Mode
L
H
H
L
L
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
3
3
3
3
L
Column
Adress
(A0~A8)
X
L
H
4
4, 5
4
4, 5
6
X
X
X
X
X
X
Exit
DQM
No Operation Command
L
H
X
H
H
X
H
X
X
X
L
H
H
H
X
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note: 1. OP Code : Operand Code
A0~A11, BA0~BA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend Information Inc.
1,2
Column
Adress
(A0~A8)
H
X
V
X
Note
Row Adress
H
H
Bank Selection
Both Banks
A10/AP A11, A0~A9
H
Auto Precharge Enable
Burst Stop
Precharge
CKEn-1 CKEn
7
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
Function Described
0
1
2
3
4
5
6
7
8
9
10
11
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
12
Refresh Rate Type
13
14
15
16
17
18
19
20
21
22
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes : General
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
73-90
91-92
93-94
95-98
Transcend Information Inc.
nd
SDRAM Cycle Time (2 highest CL)
nd
SDRAM Access from Clock (2 highest CL)
rd
SDRAM Cycle Time (3 highest CL)
rd
SDRAM Access from Clock (3 highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID Dode per JEP-108E
Man Manufacturers ufacturing Location
Part Number
Revision Code
Manufacturing Date
Assembly Serial Number
Standard
Specification
128bytes
256bytes
SDRAM
12
10
1 bank
64bits
0
LVTTL3.3V
7.5ns
5.4ns
None
15.625us/Self
Refresh
X8
none
1 clock
1,2,4,8 & Full page
4 bank
3
0 clock
0 clock
Non Buffer
Prec All, Auto Prec,
R/W Burst
0
0
0
0
20ns
15ns
20ns
45ns
128MB
1.5ns
0.8ns
1.5ns
0.8ns
JEDEC2
Transcend
-
Vendor Part
80
08
04
0C
0A
01
40
00
01
75
54
00
80
08
00
01
8F
04
04
01
01
00
0E
00
00
00
00
14
0F
14
2D
20
15
08
15
08
00
02
9D
7F, 4F
00
00
00
00
00
128MB 168Pin PC133 CL3
SDRAM DIMM With 16Mx8 3.3VOLT
JM317S643A-75
99-125
126
127
128~
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend Information Inc.
CL=3 Clock 0~3
Open
00
64
F4
FF