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TRM-915-R250
RF Transceiver Module
Data Guide
!
Warning: Linx radio frequency ("RF") products may be
used to control machinery or devices remotely, including machinery
or devices that can cause death, bodily injuries, and/or property
damage if improperly or inadvertently triggered, particularly in industrial
settings or other applications implicating life-safety concerns. No Linx
Technologies product is intended for use in any application without
redundancies where the safety of life or property is at risk.
The customers and users of devices and machinery controlled with
RF products must understand and must use all appropriate safety
procedures in connection with the devices, including without limitation,
using appropriate safety procedures to prevent inadvertent triggering by
the user of the device and using appropriate security codes to prevent
triggering of the remote controlled machine or device by users of other
remote controllers.
Do not use this or any Linx product to trigger an action directly
from the data line or RSSI lines without a protocol or encoder/
decoder to validate the data. Without validation, any signal from
another unrelated transmitter in the environment received by the module
could inadvertently trigger the action.
All RF products are susceptible to RF interference that can prevent
communication. RF products without frequency agility or hopping
implemented are more subject to interference. This module does have
a frequency hopping protocol built in, but the developer should still be
aware of the risk of interference.
Do not use any Linx product over the limits in this data guide.
Excessive voltage or extended operation at the maximum voltage could
cause product failure. Exceeding the reflow temperature profile could
cause product failure which is not immediately evident.
Do not make any physical or electrical modifications to any Linx
product. This will void the warranty and regulatory and UL certifications
and may cause product failure which is not immediately evident.
Table of Contents
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Description
Ordering Information
Absolute Maximum Ratings
Electrical Specifications
Pin Assignments
Pin Descriptions
Theory of Operation
Module Description
Module Operation
Low-Power States
Reset to Factory Default
Compatibility Mode
Automatic Gain Control and Manual Gain Control
Exception Engine
Networking Modes
Extended Preamble
Voltage Supply Rise Time
Using the Buffer Empty (BE) Line
Using the Exception (EX) Line
Using the Processing Incoming Packet (PR_PKT) Line
Receive Signal Strength Indication (RSSI)
Using the RESET Line
Using the Command Response (CMD_RSP) Line
The CMD Line
The UART Interface
Configuration Command Formatting
Module Configuration
Writing to Registers
Reading from Registers
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Configuration Registers
Typical Applications
Power Supply Requirements
Antenna Considerations
Helpful Application Notes from Linx
Interference Considerations
Microstrip Details
Pad Layout
Board Layout Guidelines
Production Guidelines
Hand Assembly
Automated Assembly
General Antenna Rules
Common Antenna Styles
Regulatory Considerations
A large-print version of this document is available at
www.linxtechnologies.com.
TRM-915-R250
RF Transceiver Module
Data Guide
Description
1.200”
(30.48mm)
The 250 Series RF transceiver module is
designed for reliable bi-directional transfer
of serial data over distances of up to 4 miles
(6.4km) line of sight. Operating in the 902 to
928MHz frequency band, the module is capable
of generating +23.5dBm into a 50-ohm load
and achieves an outstanding typical sensitivity
of –105dBm. This high output power gives
the module exceptional range and also helps
overcome noisy environments at shorter ranges.
1.200”
(30.48mm)
0.170”
(4.32mm)
Figure 1: Package Dimensions
The module implements a Frequency Hopping Spread Spectrum (FHSS)
protocol along with networking and assured delivery features. It has a
Universal Asynchronous Receiver Transmitter (UART) serial interface that
can be directly connected to microcontrollers, RS-232 converters or USB
adaptors. The module automatically handles all radio functions resulting
in a UART-to-antenna wireless link. All configuration settings and data are
accessed through the UART interface.
Features
• True UART to antenna solution
• Frequency Hopping (FHSS)
• 153.6kbps max RF data rate
• Includes robust protocol (CSMA,
assured delivery, addressing)
• Low Power Standby, Sleep and
Deep Sleep modes
• Adjustable output power
• 32-bit unique address
• 5 volt tolerant I/O
Applications
• Direct RS-232/422/485 Wire
replacement
• Asset tracking
• Automated meter reading
• Industrial/home automation
• Wireless sensors
•
•
•
•
•
•
– 1 –
Remote data logging
Fleet management
Traffic and display signs
Mass-transit communications
Oil and gas sensing
Long-range data links
Revised 3/18/2015
Ordering Information
Electrical Specifications
Ordering Information
250 Series Transceiver Specifications
Product Part No.
Description
TRM-915-R250
Embedded Wireless
Module, 250mW (900MHz)
TRM-915-R250-CFT
Embedded Wireless
Module, 250mW
(900MHz), Mexico
Wi.232-FHSS-250-CFTC-R
EVM-915-250-FCx
Pinned, Pre-Certified
Module, 250mW (900MHz)
Wi.232FHSS-250-FCC-xx-R
EVM-915-250-CFx
Radiotronix Part No.
Parameter
Wi.232FHSS-250-R
Power Supply
Symbol
Min.
Typ.
Max.
Units
Operating Voltage
VCC
2.7
3.3
3.6
VDC
TX Supply Current
lCCTX
1,2
@+8dBm
Pinned, Pre-Certified
Module, 250mW
(900MHz), Mexico
Wi.232FHSS-250-FCC-CFTC-xx-R
x = ‘R’ for right angle connector, ‘S’ for straight connector
Transceivers are supplied in trays of 50 pieces
Figure 2: Ordering Information
Notes
54
mA
@+13dBm
71
mA
@+18dBm
109
mA
190
mA
RX Supply Current
@+23.5dBm
lCCRX
25
mA
1
Standby Current
lSTD
1.5
mA
1
Sleep Current
lSLP
1.5
mA
1
Deep Sleep Current
IDSLP
3
µA
1
RF Section
Absolute Maximum Ratings
Operating Frequency Band
Absolute Maximum Ratings
Supply Voltage Vcc
0
to
4.2
VDC
Any Input or Output Pin
0
to
5.0
VDC
1
ms
Max Supply Voltage Rise Time (GND to 2.7V)
Max RF Input
12
dBm
Operating Temperature
–40
to
+85
ºC
Storage Temperature
–40
to
+85
ºC
Exceeding any of the limits of this section may lead to permanent damage to the device.
Furthermore, extended operation at these maximum ratings may reduce the life of this
device.
FC
902.2
927.8
Center Frequency Accuracy
2
Number of Channels
32
Chan.
Channel Spacing
750
kHz
Hop Sequences
4
MHz
PPM
6
Max Data Rate
4
115.2
kbps
Antenna Port
RF Impedance
RI N
Ω
50
Environmental
Operating Temp. Range
-40
+85
ºC
Receiver Section
Receiver Sensitivity
Figure 3: Absolute Maximum Ratings
Warning: This product incorporates numerous static-sensitive
components. Always wear an ESD wrist strap and observe proper ESD
handling procedures when working with this device. Failure to observe
this precaution may result in module damage or failure.
3
5
9.6kbps
–105
dBm
38.4kbps
–102
dBm
153.6kbps
–100
dBm
Input IP3
–24
dBm
6
Adjacent Channel Rejection
60
dBc
7
IF Bandwidth
200
kHz
Transmitter Section
Max Output Power
– 2 –
PO
23.5
Harmonic Emissions
PH
Frequency Deviation
FDEV
– 3 –
24
dBm
2
–50
dBc
2
50
kHz
Pin Descriptions
250 Series Transceiver Specifications
Parameter
Symbol
Min.
Input Logic Low
VI L
Input Logic High
VI H
Output Logic Low
VOL
Typ.
Max.
Units
0
0.8
VDC
2.0
VCC
VDC
IOL = 8.5mA
0.6
VDC
IOL = 10µA
0.1
VDC
Notes
Interface Section
IOL = 25mA
1.0
Output Logic High
VDC
VOH
IOH = -3mA
VCC–0.7
IOH = -10µA
VCC–0.1
IOH = -10mA
VDC
VCC-0.8
Pin Descriptions
Pin Number
Name
I/O
1
PR_PKT
O
Processing Packet Indicator. This line goes
high when the module is processing a valid
or potentially valid packet.
2
TXD
O
UART Transmit Data Output. This is the
output line for the configuration command
responses as well as the data received over
the air.
3, 4, 5, 8, 17,
18
NC
—
No Electrical Connection. Do not connect
any traces to these lines.
6
RESET
I/O
Reset line. This line is normally an input that
acts as an active low hardware reset line.
It does occasionally act as an output, so
please see the Reset section for details.
7
C2D
—
Reserved
9
CMD_RSP
O
Command Response. This line is low when
the data on the TXD line is a response to a
command and not data received over the
air.
10
EX
O
Exception Output. A mask can be set
to take this line high when an exception
occurs. The line is lowered when the
exception register is read (regEXCEPTION)
11, 12, 13, 23
GND
—
Ground
14
RSSI
O
This line outputs an analog voltage that is
proportional to the strength of the incoming
signal.
Flash Specifications (Non-Volatile Registers)
Flash Write Duration
Flash Write Cycles
1.
2.
3.
4.
5.
6.
20k
VCC = 3.3V
Into a 50-ohm load
At 25ºC
26 channels each
At 10-3 BER
Pin = -20dBm, 2 CW interferers, FRF =
915MHz, F1 = FRF + 3MHz, F2 = FRF +
6MHz, max gain, high-sensitivity
7.
16
ms
100k
cycles
Desired signal 3dB above input
sensitivity level, CW interferer power
level increased until BER = 10-2,
+/–1MHz
Figure 4: Electrical Specifications
15
CMD
I
Command Input. This line sets the serial
data as either command data to configure
the module or packet data to be sent over
the air. Pull low for command data; pull high
for packet data.
16
BE
O
Buffer Empty. This line goes high when the
UART input buffer is empty, indicating that
all data has been transmitted.
Pin Assignments
TXD
3
24
VCC
PR_PKT
2
25
VCC
1
VCC
26
GND
21
4
NC
RXD
20
5
NC
CTS
19
6
RESET
NC
18
7
C2D
NC
17
8
NC
BE
16
9
CMD_RSP
CMD
15
10
EX
GND
22
NC
GND
23
ANT
GND
GND
11
12
13
RSSI
14
Description
19
CTS
O
UART Clear To Send, active low. This line
indicates to the host microcontroller when
the module is ready to accept data. When
CTS is high, the module is busy. When CTS
is low, the module is ready for data.
20
RXD
I
UART Receive Data Input. This is the input
line for the configuration commands as well
as data to be sent over the air.
22
ANT
—
50-ohm RF Antenna Port
24, 25, 26
VCC
—
Supply Voltage
Figure 6: 250 Series Transceiver Pin Descriptions
Figure 5: 250 Series Transceiver Pin Assignments (Top View)
– 4 –
– 5 –
Theory of Operation
Module Description
The 250 Series transceiver is a low-cost, high-performance synthesized
FSK transceiver. Its wideband operation gives it outstanding range while
still meeting regulatory requirements. Figure 7 shows a block diagram for
the module.
The 250 Series RF transceiver module has a Universal Asynchronous
Receiver Transmitter (UART) serial interface and is designed to create
a complete UART-to-antenna wireless solution capable of direct wire
replacement in most embedded RS-232/422/485 applications.
TEMP
SENSOR
OFFSET
CORRECTION
LNA
FILTER
MUX
RSSI
IF FILTER
7-BIT ADC
FSK/ASK
DEMODULATOR
Note: Although the module is capable of supporting the serial data
communications required by RS-232, RS-422, and RS-485 networks,
it is not compatible with the electrical interfaces for these types of
networks. The module has CMOS inputs and outputs and requires an
appropriate converter for the particular type of network being used.
DATA
SYNCHRONIZER
GAIN
OFFSET
CORRECTION
ANTENNA
AGC
CONTROL
SWITCH
FSK MOD
CONTROL
Σ-Δ
MODULATOR
GAUSSIAN
FILTER
Tx/Rx
CONTROL
UART /
INTERFACE
AFC
CONTROL
PROCESSOR
FILTER
PA
FILTER
DIVIDERS/
MUXING
DIV P
N/N + 1
SERIAL
PORT
VCO
FILTER
CP
PFD
DIV R
OSC
CLK
DIV
Figure 7: 250 Series Transceiver Block Diagram
The 250 Series transceiver is designed for operation in the 902 to 928MHz
frequency band. The RF synthesizer contains a VCO and a low-noise
fractional-N PLL. The receive and transmit synthesizers are integrated,
enabling them to be automatically configured to achieve optimum phase
noise, modulation quality and settling time.
The transmitter output power is programmable from +8dBm to +23.5dBm
with automatic PA ramping to meet transient spurious specifications.
The ramping and frequency deviation are optimized to deliver the highest
performance over a wide range of data rates.
The receiver incorporates highly efficient low-noise amplifiers that provide
up to –105dBm sensitivity.
An onboard controller performs the radio control and management
functions. A processor performs the higher level protocol functions and
controls the serial and hardware interfaces.
The module is designed to interface directly to a host UART. Three lines are
used to transfer data between the module and the host UART: TXD, RXD,
and CTS. TXD is the data output from the module. RXD is the data input
to the module. The CTS output indicates if the module is ready to accept
data. The UART interface is capable of operating in full duplex at baud
rates from 2.4 to 115.2kbps.
The module has a built-in protocol that automatically transmits the data
input on the UART. All encoding, transmitting, receiving and decoding
functions are handled by the internal processor, so no overhead is required
by an external processor. The networking modes in the protocol allow
for point-to-point and broadcast transmissions as well as allowing for the
creation of subnets and more complicated network topologies.
The module can be put into a Sleep mode through serial commands. In
Sleep mode, the RF section is completely shut down and the protocol
processor is in an idle state. Once the module has been placed in the sleep
mode, it can be awakened by sending a power-up sequence through the
serial port.
If the current draw in sleep mode is too high for a particular application,
power to the module can be switched through an external FET to turn off
the module when it is not needed. If this technique is used, the volatile
registers are reset to the values in their non-volatile mirrors, so any changes
from the default will have to be reloaded.
Every module has a 32-bit GUID address that can be used by the host
application to uniquely identify each module. This address can be read
through the serial interface.
– 6 –
– 7 –
Module Operation
The module employs a Frequency Hopping Spread Spectrum (FHSS)
algorithm. It has 32 channels spaced on 750kHz boundaries with a guard
band on either side. These channels are pseudo-randomly arranged into
six unique hopping tables comprised of 26 channels. The order of these
tables is chosen so that cross-correlation is minimized, allowing multiple
networks to operate in proximity with minimal interference.
When the module is not actively transmitting or receiving packets, it is in a
scan state. It cycles through the channels in the hop sequence looking for
a synchronizing packet. If it detects a preamble, it pauses to wait for the
start code and packet header. If the packet is addressed to it, the module
processes the packet and outputs the payload on the UART. If the packet
is not addressed to the module or the start code and header fail their
checks, the module resumes scanning for another packet.
When data is input on the RXD line for transmission, the module fills
a buffer. Once the UART has buffered enough data to send (either
regUARTMTU bytes input or regTXTO has expired between bytes on the
RXD line), it transmits the data. The protocol engine makes a best-effort
attempt to keep the data in at least regUARTMTU-sized packets, but splits
the data based on the remaining dwell time before hopping. New data is
not sent within the last 5% of the hop sequence, but data which is already
in the process of being sent is processed normally.
The module prefixes the data with a packet header and postfixes the data
with a 16-bit CRC. The 16-bit CRC error checking can be disabled to allow
the host application to do its own error checking.
If acknowledgements are enabled for assured delivery, then once the
packet is sent the module looks for an ACK from the other side. If the
ACK is not received, a retry is performed and the transmission is sent
again. If the number of transmission retries exceeds the value in the
regMAXTXRETRY register, an exception (EX_NORFACK) is raised.
Once the packet is sent, the transmitter deactivates but remains tuned to
the current channel until its hop time expires. If another packet is queued
for transmission, the module transmits this packet once the CSMA
mechanism allows access to the channel. Once the hop timer expires, the
module hops to the next channel.
Synchronization is lost whenever there is no more data to transfer and the
module has detected two consecutive hop indices without data present.
The module then returns to scan mode.
If another unit is transmitting when the module is ready to transmit a
packet, the module receives that data before attempting to transmit its
data. If the UART receive buffer gets full, the CTS line goes high to prevent
the host UART from over-running the receive buffer.
The CSMA mechanism introduces a variable delay to the transmission if
it detects that the channel is occupied. This delay is the sum of a random
period and a weighted period that is dependent on the number of times
that the module has tried and failed to access the channel. For applications
that guarantee that only one module is transmitting at any given time, the
CSMA mechanism can be turned off to avoid this delay.
Initially, the transmission of the packet begins on a random hop index within
the current hop sequence, and follows the hop sequence thereafter until
synchronization is lost. The module uses a Carrier-Sense-Multiple-Access
(CSMA) protocol to determine if another module is already transmitting on
the selected channel. If the channel is occupied then the module waits for it
to clear before transmitting its data.
Once the module gains access to the channel, if it is not already
synchronized, it assigns itself master status, and sends a synchronizing
preamble. Following a hop, the module that sends the first transmission
assigns itself master status, sends a synchronizing preamble, and
communications resume.
– 8 –
– 9 –
Low-Power States
The module supports three power saving modes: Standby, Sleep and Deep
Sleep. Standby and Sleep are included primarily for legacy compatibility
with DTS and EUR Series modules. The hardware required to support
these two low-power modes fully is not present in the 25 Series modules.
As a result, the current consumption in these two modes is considerably
higher than their DTS / EUR counterparts. It is recommended that
applications utilize the Deep Sleep mode for power savings.
In the Sleep and Deep Sleep modes, the transceiver is powered down
and does not synchronize with other modules. Sleep mode draws more
current than Deep Sleep mode. In Deep Sleep mode the module draws the
least current. To wake the module up from this mode the RESET line must
be held low for at least 20μs and then taken high. The module does not
monitor the receive channel in either mode. Therefore, a sleeping module
cannot be woken through the RF interface.
If regACKONWAKE is enabled, the module transmits a 0x06 character on
the TXD line once awakened from a low-power mode or power-off state.
This indicates that the module is ready to resume operations.
Figure 8 indicates the line states while in a low-power mode.
250 Series Transceiver Low-Power Line States
Line Name
Pin Number
Pin State
PR_PKT
1
Driven low
TXD
2
Input with weak pull-up
RESET
6
Input with weak pull-up
C2D
7
Input with weak pull-up
CMD_RSP
9
Input with weak pull-up
EX
10
Driven low
RSSI
14
Driven low
CMD
15
Input with weak pull-up
BE
16
Input with weak pull-up
CTS
19
In Standby, Sleep: Driven Low, In Deep Sleep: Driven High
RXD
20
Input with weak pull-up
Figure 8: 250 Series Transceiver Low-Power Line States
– 10 –
Standby
Standby is selected by writing a 0x02 to regOPMODE. In this mode,
the internal oscillator of the module’s protocol controller is lowered to its
slowest setting. The transmitter and receiver hardware is in power-down,
but the radio’s oscillator is enabled and running. The module wakes from
standby in less than 6ms. A low pulse on the RXD line wakes the module.
This pulse should be at least 1 bit-time in duration, so sending any byte to
the UART wakes it with the low start bit. Because the module’s oscillator
is not capable at running at ultra-low speeds, use of this mode is not
recommended for new applications. The RAM contents are preserved
during standby. If the RAM fails an integrity check, the module issues itself
a software reset to force re-initialization.
Sleep
Sleep is selected by writing a 0x01 to regOPMODE. The internal oscillator
of the module’s protocol controller is lowered to its slowest setting, and
all radio services are stopped (receiver, transmitter, oscillator, etc.). The
module wakes from sleep in less than 6ms. A low pulse on the RXD line
wakes the module. This pulse should be at least 1 bit-time in duration, so
sending any byte to the UART wakes it with the low start bit. Because the
module’s oscillator is not capable at running at ultra-low speeds, use of
this mode is not recommended for new applications. The RAM contents
are preserved during sleep. If the RAM fails an integrity check, the module
issues itself a software reset to force re-initialization.
Deep Sleep
Deep sleep is selected by writing a 0x03 to regOPMODE. When the
module is put into deep sleep, the CTS line is brought high to indicate that
the module is not ready to accept UART data. The radio is placed in its
lowest power mode and all services are stopped. The protocol controller’s
oscillator is also stopped and all non-essential functions are turned off.
While powered, this mode consumes the least amount of current. The
module wakes from deep sleep in less than 6ms. A low pulse of at least
20μs on the RESET line starts the waking process, but the module doesn’t
begin executing wake instructions until the RESET line is returned high.
As with the other low-power modes, the RAM contents are preserved.
If the RAM fails an integrity check, the module issues itself a software
reset to force re-initialization. Note that, if the volatile data rate register is
changed during the host application initialization (regUARTDATARATE),
the re-initialization returns the module to the value in the non-volatile
counterpart (regNVUSERDATARATE).
– 11 –
Reset to Factory Default
It may be necessary to reset the non-volatile registers to their factory
defaults. To reset the module, hold the CMD line low and cycle power to
hardware-reset the module. The CMD line must remain low for a minimum
of 600ms after resetting the module. Once the CMD line is released, the
module’s non-volatile registers are reset to factory defaults.
Exception Codes
Exception codes are organized by type for ease of masking. Figure 9 lists
the exception codes and their meanings. All other values are reserved.
250 Series Transceiver Exception Codes
Exception Code
Compatibility Mode
The 250 Series modules support a mode that allows them to communicate
with the smaller, lower power 25 Series modules. The 250 Series operates
at a much narrower receive bandwidth (200kHz) than the 25 Series
(600kHz). To allow interoperability, the 250 and 25 Series transceivers
support a compatibility mode that allows the modules to communicate
effectively with each other.
Compatibility mode reduces the maximum RF data rate to 76.8kbps. All
UART baud rates are supported, although the RF data rates associated
with baud rates 31,250; 38,400; 57,600 and 115,200 are reduced.
Automatic Gain Control and Manual Gain Control
The gain setting of the receiver’s low noise amplifier (LNA) is adjustable.
By default, the 250 Series is factory-configured to use its internal automatic
gain control (AGC) circuit to manage receiver sensitivity. Reducing the gain
increases the linearity of the receiver, but reduces maximum sensitivity;
increasing the gain does the opposite. Generally speaking, higher
linearity (increased third order input intercept point, IIP3) gives improved
performance in high-interference environments; high gain yields better
performance in low-interference environments.
Exception Name
Description
0x08
EX_BUFOVFL
Internal UART buffers overflowed.
0x09
EX_RFOVFL
Internal RF packet buffer overflowed.
0x13
EX_WRITEREGFAILED
Attempted write to register failed.
0x20
EX_NORFACK
Acknowledgement packet not received
after maximum number of retries.
0x40
EX_BADCRC
Bad CRC detected on incoming packet.
0x42
EX_BADHEADER
Bad CRC detected in packet header.
0x43
EX_BADSEQID
Sequence ID was incorrect in ACK packet.
0x44
EX_BADFRAMETYPE
Unsupported frame type specified.
Figure 9: 250 Series Transceiver Exception Codes
Exception Masking
The EX line can be asserted to indicate to the host that an error has
occurred. The exception mask provides a simple method of choosing
which errors cause the line to toggle. If the result of ANDing the exception
code with the exception mask is non-zero, the EX line is asserted. The
regEXCEPTION register must be read to reset the line. Figure 10 lists some
example exception masks.
250 Series Transceiver Example Exception Masks
Exception Mask
Exception Name
0x08
Allows only EX_BUFOVFL and EX_RFOVFL to trigger the EX line
The module contains an AGC circuit that manages these settings
automatically, and it should be used whenever possible. However, when
attempting to make analog RSSI measurements, fixing the LNA gain
produces more meaningful results. Digital RSSI readings are internally
compensated and may be taken with AGC enabled.
0x10
Allows only EX_WRITEREGFAILED to trigger the EX line
0x20
Allows only EX_NORFACK to trigger the EX line
0x40
Allows only EX_BADCRC, EX_BADHEADER, EX_BADSEQID and
EX_BADFRAMETYPE exceptions to trigger the EX line
0x60
Allows EX_BADCRC, EX_BADHEADER, EX_BADSEQID, EX_
BADFRAMETYPE and EX_NORFACK exceptions to trigger the EX
line
Exception Engine
0xFF
Allows all exceptions to trigger the EX line
The modules are equipped with an internal exception engine. If errors occur
during module operation, an exception is raised. Exception codes are
stored in the regEXCEPTION register and are cleared once they are read.
If an exception code is already present in regEXCEPTION when an error
occurs, the new exception code overwrites the old value.
– 12 –
Figure 10: 250 Series Transceiver Example Exception Masks
The exception mask has no effect on the exceptions stored in the
exception register. It only controls which exceptions affect the EX line.
– 13 –
Networking Modes
The module has a very flexible addressing and networking scheme selected
with the regNVNETWORKMODE and regNETWORKMODE registers. It
can be changed during operation. The transmitting module addresses
packets according to the network mode configuration. The receiving
module processes all addressing types regardless of the network mode
configuration. If the received message matches the addressing criteria, it is
output on the UART. Otherwise it is discarded.
There are three networking modes: GUID, User and Extended User. Each
mode offers different communications schemes, but all use source and
destination addressing. The source address is for the transmitting unit,
the destination address is the intended receiver. Each mode uses different
registers for the source and destination addresses.
The module supports an automatic addressing mode that reads the
Source Address from a received packet and uses it to fill the Destination
Address register. This makes sure that a response is sent to the device that
transmitted the original message. This also allows the host microcontroller
to read out the address of the sending unit.
The automatic addressing is enabled for the different networking modes
with register regAUTADD and regNVAUTADD.
GUID Networking Mode
GUID networking mode is the simplest mode and supports point-to-point
and broadcast communications. Each module is programmed at
the factory with a unique 4-byte ID number that cannot be changed.
These bytes are found in the non-volatile read only MYGUID registers
(regMYGUID[0-3]). GUID networking mode uses these IDs as addresses.
The transmitting unit’s GUID is used as the source address and the
intended receiver’s GUID is written into the destination address register
(regDESTGUID[0-3]). All modules within range hear the transmission, but
only the module with the ID that matches the destination address outputs
the data on its UART. All others ignore the transmission.
A broadcast message is created when the destination address is
0xFFFFFFFF. In this case, all modules within range output the data. It is not
recommended to send broadcast messages when acknowledgements are
enabled. Figure 11 lists some examples of how GUID networking works.
250 Series Transceiver GUID Network Mode Examples
Sender
Receiver
Network
Mode
MyGUID
Destination
GUID
0x04
(GUID)
0x00001000
0xFFFFFFFF
0x14
(GUID +
ACK)
0x00001000
0xFFFFFFFF
0x14
(GUID +
ACK)
0x00001000
0x00003000
0x04
(GUID)
0x00001000
0x00002000
MyGUID
Response
0x00002000
Data output by both modules.
No RF ACK sent by either
module.
0x00003000
0x00002000
0x00003000
0x00002000
Not processed – discarded.
0x00003000
Data output. RF ACK sent to
0x00001000
0x00002000
Data output. No RF ACK sent.
0x00003000
Not processed – discarded.
Figure 11: 250 Series Transceiver GUID Network Mode Examples
– 14 –
Data output by both modules.
No ACK sent by either module.
This configuration causes
transmission problems.
– 15 –
User Networking Mode
User Networking Mode is a more complicated scheme than GUID
mode. It uses the customer ID bytes (regCUSTID[0-1]) and two of the
user destination bytes (regUSERDESTID[0-1]) as a destination address.
The customer ID bytes are programmed at the factory and cannot be
changed. The module’s local address is contained in two of the user
source ID registers (regUSERSRCID[0-1]). Each module also has a user ID
mask (regUSERIDMASK[0-1]) that provides an additional logical layer of
addressing and can be used to create sub-networks. The receiving module
masks its local address and the received destination address by calculating
the logical AND with the user ID mask. If the results are equal, then the
payload is output on the UART. The customer ID bytes are not masked, but
must match the local value.
If acknowledgements are enabled, only the module with a user source ID
that matches the transmitted user destination ID responds. The mask is not
used for this determination.
250 Series Transceiver User Network Mode Examples
Destination Receiver Receiver Result of Result of
ID from
Dest
Source Action
Source
User ID
Received
AND
AND
ID
Mask
Packet
Mask
Mask
3000
3000
If the result of the user ID Mask AND the received user destination address
equals the same value as the user ID mask, then the payload data is output
on the UART. This acts as a broadcast message to the network.
Setting the mask to 0xFFFF removes the mask and only the source and
destination addresses are used for networking. When using user network
mode to send packets to multiple users and the mask is not equal to
0xFFFF, acknowledgements must be disabled. Failure to do so could cause
extreme delays in transmission and loss of data.
2000
The results are equal, so
the payload is output on
the UART.
2000
The results are equal, so
the payload is output on
the UART. The destination
ID and the source ID
match, so an ACK is
transmitted if enabled.
4000
4000
The results do not match,
so the packet is discarded.
2000
2000
The results do not match,
so the packet is discarded.
3000
The results are equal, so
the payload is output on
the UART. The destination
ID and the source ID
match, so an ACK is
transmitted if enabled.
4000
The results do not match,
so the packet is discarded.
2000
3000
3000
E000
F000
2000
3000
4000
2000
E000
3000
2000
E000
E000
4000
2000
4000
The destination ID matches
the user ID mask, so the
data is output on the UART.
Figure 12: 250 Series Transceiver User Network Mode Examples
250 Series Transceiver User Network Mode Examples
As an example, if the mask is 0xFFF0 and the destination address
transmitted by the sender is 1234, then all modules with a source ID of
123x respond. This gives a subnet of 16 modules (where x = 0 to F) and
acts as a broadcast message to the sub-net. Acknowledgements should
be disabled.
Figure 14 shows this example and Figure 12 and Figure 13 show some
more examples of user networking mode.
Sender
Receiver
Network
Mode
User
SRCID
User
DESTID
0x06
(User)
0x1000
0xFFFF
0x16
(User +
ACK)
0x1000
0xFFFF
0x16
(User +
ACK)
0x1000
0x3000
0x6
(User)
0x1000
0x3000
User
SRCID
User
IDMASK
Response
0x2000
0XFFFF
0x3000
0xFFFF
Data output by both modules. No
ACK sent by either module.
0x2000
0xFFFF
0x3000
0xFFFF
0x2000
0xE000
Data output. No ACK sent.
0x3000
0xE000
Data output. ACK sent to
0x1000.
0x2000
0xF000
Not processed – discarded.
0x3000
0xF000
Data output. No ACK sent.
Figure 13: 250 Series Transceiver User Network Mode Examples
– 16 –
– 17 –
Data output by both modules. No
ACK sent by either module. This
configuration causes transmission
problems.
250 Series Transceiver User Network Mode Examples
Destination Receiver Receiver Result of Result of
ID from
Dest
Source Action
Source
User ID
Received
AND
AND
ID
Mask
Packet
Mask
Mask
1234
Any
module
with
123x
FFF0
1230
1230
The results are equal, so
the payload is output on
the UART.
Do not enable
acknowledgements
Figure 14: 250 Series Transceiver User Network Mode Examples
Extended User Addressing Mode
Extended User Networking Mode is the same as User Networking Mode
but uses longer addresses. The two customer ID bytes are still used
(regCUSTID[0-1]) but all four bytes are used for the user destination
address (regUSERDESTID[0-3]), user source ID (regUSERSRCID[0-3])
and user ID mask (regUSERIDMASK[0-3]). This provides more addressing
capabilities at the expense of more overhead in the packet. Otherwise all
functionality is the same.
250 Series Transceiver Extended User Network Mode Examples
Sender
Receiver
Network User
Mode
SRCID
User
DESTID
User
SRCID
User
IDMASK
Response
0x20000001 0XFFFFFFFF Data output by
both modules. No
0x20000002 0xFFFFFFFF ACK sent by either
module.
0x07
0x10000000 0xFFFFFFFF
0x17
0x20000001 0xFFFFFFFF Data output by
both modules.
No ACK sent by
0x10000000 0xFFFFFFFF
either module. This
0x20000002 0xFFFFFFFF configuration will
cause transmission
problems.
0x17
0x10000000 0x30000001
0x07
0x10000000 0x30000002
output. No
0x20000001 0xE0000000 Data
ACK sent.
output. ACK
0x30000001 0xE0000000 Data
sent to 0x1000.
processed –
0x20000001 0xF0000000 Not
discarded.
Assured Delivery (Acknowledgement)
While not an addressing mode on its own, assured delivery can be
enabled for each of the addressing modes. When a module transmits
with assured delivery enabled, it obligates the receiving module to return
an acknowledgement packet. The transmitting module waits for this
acknowledgement for a preset amount of time based on the data rate.
If an acknowledgement is not received, it retransmits the packet. If the
receiver receives more than one of the same packet, it discards the packet
contents but sends an acknowledgment. This way, duplicate data is not
output by the module. It is extremely important that assured delivery be
used only when the unmasked user/extended user Destination ID or
Destination GUID points to a specific module. Failure to specifically address
a valid module could cause the module to appear slow or unresponsive
due to repeated retransmissions. This also serves to congest the network,
impeding valid communications.
If the received destination address matches the local address, the receiving
module immediately sends an RF ACK packet. This packet lets the sending
module know that the message has been received. An RF ACK packet is
sent immediately following reception; CSMA delay is not applied to RF ACK
packets. When the sending module receives the RF ACK packet, it marks
the current block of data as completed. If this is the last message in the
queue, the sending module asserts the BE line to indicate the state of the
incoming buffer.
Troubleshooting Hint: If modules are unable to communicate with each
other, check the following:
•
Check to make sure that both modules are set to the same data rate.
Modules programmed with different data rates will not communicate or
share an RF channel with one another.
•
Ensure that the network mode and addressing is configured to properly
access the module of interest. Also, ensure that a specific module is
addressed when using acknowledgment. Failure to do so causes large
delays and loss of data.
output. No
0x30000001 0xF0000000 Data
ACK sent.
Figure 15: 250 Series Transceiver Extended User Network Mode Examples
– 18 –
– 19 –
Extended Preamble
As the receivers scan the hop sequence channels they look for the
preamble from a transmitter. When they detect this preamble, they stop
scanning and wait for a packet header. From the packet header they are
able to lock on to the transmitter and synchronize the timing.
It is an advantage in some applications to keep the receivers asleep for
long periods of time and wake them up only periodically to look for data. In
this scenario it is quite possible for the receivers to miss the preamble from
the transmitter and go to sleep without finding the transmission.
To address this issue, the modules can send an extended preamble. The
extended preamble is much longer than the normal preamble and gives
modules a larger window to detect and lock on to the transmitter.
There are two types of packets sent by the transmitter: synchronizing
packets and data packets. The receivers use the synchronizing packets
to lock on to the transmitters and follow them through the next hop. This
packet is the first packet sent after every hop. The packets sent after the
synchronizing packet and before the next hop are data packets. Receivers
can catch and process data packets, but do not lock on and follow the
transmitter unless they process the synchronizing packet.
It is important to note that an extended preamble packet may not be
a synchronizing packet. If it is a data packet the receiver processes
the packet and begins scanning again. It is important for the external
processor or application to keep modules awake long enough to catch the
synchronizing packet on the next hop. This ensures that the modules lock
on to the transmitting module and receive all of the data.
The dwell time on each channel is approximately 395ms plus the times per
baud rate shown in Figure 39. This can be shorter if the host processor
determines that the necessary information has been received. Additionally
the PR_PKT line can be used to determine that the module is processing a
packet and keep it awake.
This page is intentionally blank.
– 20 –
– 21 –
Voltage Supply Rise Time
Receive Signal Strength Indication (RSSI)
The power supply rise time is extremely important. It must rise from ground
to 2.7V in less than 1ms. If this specification cannot be met, an external
reset supervisor circuit must be used to hold the module in reset until the
power supply stabilizes. Failure to ensure adequate power supply rise time
can result in loss of important module configuration information.
The RSSI line outputs an analog voltage that is proportional to the signal
strength present on the channel at the time. In normal operation, the
module is hopping rapidly from channel to channel. In this case, the
RSSI value varies greatly and does not provide much useful information.
However, it can be used to keep a module awake by sampling the RSSI
line to determine if the module is processing a packet before putting it to
sleep.
Using the Buffer Empty (BE) Line
The BE line indicates the state of the module’s UART buffer. When the
module receives data in the RXD line and the CMD line is high, the BE line
is lowered until all data in the buffer has been processed by the protocol
engine. If acknowledgement is not enabled, the BE line is raised as soon as
the protocol engine processes the outgoing packets. If acknowledgement
is enabled, the buffer is not updated until either the data transmissions
are acknowledged by the remote end or delivery fails after the maximum
number of retries. When the BE line returns high, the EX line may be
sampled, or the regEXCEPTION register polled to determine if an error
occurred during transmission.
The 250 Series module has an internal digital RSSI indication of the
immediate ambient environment and of the last good packet received.
Additionally, the PR_PKT line can be used to indicate the state of the
protocol engine.
RSSI level is dependent on the power of the signal received at the antenna
port and the mode the LNA is in. regLNAMODE controls the mode of the
internal LNA. Figure 16 shows typical traces of RSSI voltage versus signal
strength.
2500
Using the Exception (EX) Line
Using the Processing Incoming Packet (PR_PKT) Line
The PR_PKT line indicates whether the protocol engine has determined
there to be valid or potentially valid data incoming. The line is normally low
(not processing). When awake and not transmitting, the protocol engine
is constantly searching for incoming data. When scoring indicates that a
potential packet is inbound, this line is raised until either the scoring falls
below a given threshold or the complete packet is received. It is possible
that the packet scoring will fall below the threshold during reception,
causing the line to be lowered. Such an instance can occur when the
module hops to a channel late in the transmitter’s extended preamble.
Since there aren’t a large number of valid bits to score, the line may fall
during the packet start sequence. Once this sequence arrives, the PR_PKT
signal rises and latches for the duration of the packet reception.
– 22 –
High Sens
Mid IIP3
2000
High IIP3
Auto Gain
RSSI OUT (mV)
The EX line indicates whether or not a module exception has occurred.
The line is normally low, but it is raised if an exception occurs that passes
masking. When the regEXCEPTION register is read, the exception is
cleared and the EX line returns low. If more than one exception occurs
before the regEXCEPTION register is read, the old exception is overwritten
by the new one. Please see the Exception Engine section for more details.
1500
1000
500
0
-102 -98
-94
-90
-86
-82
-78
-74
-70
-66
-62
-58
RF IN (dBm)
Figure 16: 250 Series Transceiver PIN vs RSSI Voltage
– 23 –
-54
-50
-46
-42
-38
-34
-30
-26
-22
Hardware Reset (Input)
During normal operation, the RESET line functions as an active-low
hardware reset input. Taking this line low for at least 15μs forces the
module’s controller into hardware reset. While the line is low, execution of
module operations are suspended and all module lines revert to open-drain
inputs with weak pull-ups. This behavior can be exploited during power-up
if the VCC ramp time exceeds 1ms. By suspending execution, the dangers
associated with slow VCC ramp are eliminated.
Wake from Deep Sleep (Input)
When the module is in deep sleep, all execution is suspended in the
controller and the radio is in its lowest power mode. The RESET line must
be lowered for at least 15μs to wake the module. When the RESET line is
raised, execution begins in the controller. The module maintains its state
engine while asleep. Because of this, it can detect whether the hardware
reset was intended to cause a hard reset or wake the module. The
controller’s RAM is preserved during deep sleep. The RAM is checked prior
to entering deep sleep, and examined upon waking. If the RAM contents
are corrupted upon wake, the module issues itself a software reset to
reinitialize the module.
Hardware Reset Indicator (Output)
When the module starts from power-off, or is reset by the internal VCC
monitor circuitry, the RESET line is driven low to indicate the reset state.
During power-on reset, assuming the VCC ramp time is valid, RESET is
driven low from the time that VCC reaches approximately 1V until VCC
reaches VRST + TPORDelay. TPORDelay is the power-on reset delay imposed by the
controller’s hardware.
The other event that drives the RESET line low is a low-voltage or
brown-out condition. In this case, the VCC monitor holds the module in
reset, thus driving the RESET line low. It remains low until the power drops
below the operating threshold for that circuit (becoming indeterminate),
or until the module’s power supply returns to VRST. Figure 17 illustrates the
operation of RESET as an output.
– 24 –
VCC
2.70
2.55
VRST
2.0
VC
C
The RESET line has different functions depending on the state the module
is in. It is an open-drain input/output line with an integrated weak pull-up,
so it is normally high. Because it periodically operates as an output,
external control should only pull this line low, not high.
volts
Using the RESET Line
1.0
t
Logic HIGH
RESET
TPORDelay
Logic LOW
VCC
Monitor
Reset
Power-On
Reset
Figure 17: 250 Series Transceiver Reset Timing Diagram
250 Series Transceiver Reset Circuit Specifications
Parameter
Min.
Typ.
RESET Output Low Voltage
RESET Input Pull-up Current
VCC Monitor Threshold (VRST)
Minimum RESET Low Time to
Generate a Hardware Reset
Power-on Reset Delay (TPORDelay)
2.40
Max.
Units
Notes
0.6
V
VCC = 2.7 – 3.6V
25
40
µA
RESET = 0.0V
2.55
2.70
V
15
µs
<300
Allowed/Valid VCC Ramp Time
µs
1
VCC Ramp Time is Valid
ms
Figure 18: 250 Series Transceiver Reset Circuit Specifications
Warning: If the RESET line experiences noise, it can cause multiple
triggers (wake from sleep, hardware reset, hardware reset, etc.) and
cause the volatile registers to be reloaded with their non-volatile values. If
the circuit introduces noise onto this line, a bypass capacitor or RC filter
should be placed on the line as close to the module as is practical.
– 25 –
Using the Command Response (CMD_RSP) Line
The CMD Line
The CMD_RSP line is normally high, but the module lowers this line when
responding to a UART command. This indicates to an external processor
that the data on the TXD line is a response to a command and not data
received over-the-air.
The CMD line is used to inform the module where incoming UART data
should be routed. When the line is high or left floating, all incoming UART
data is treated as payload data and is routed to the transmitter to be sent
over the air. If the CMD line is low, the incoming UART data is routed to
the command parser for processing. Since the module’s controller looks
at UART data one byte at a time, the CMD line must be held low for the
entire duration of the command plus a 20μs margin for processing. Leaving
the line low for additional time (for example, until the ACK byte is received
by the application) does not adversely affect the module. If RF packets are
received while the CMD line is active, they are still processed and output on
the module’s UART. Figure 19 shows this timing.
The module outputs received RF data immediately following the command
response. The CMD_RSP line does rise before resuming RF data, but
some processors cannot react quickly enough to this signal and may not
able to separate the command responses from RF data.
The regCMDHALT register controls the behavior of the TXD line when the
CMD line is low and the external processor is configuring the module.
If this register is set to 0x01 and the CMD line is low, the module stops
outputting the RF data and internally buffers it. Once the CMD line is raised,
the buffered RF data is output on the TXD line. This allows the external
processor to have separate configuration times and data times instead of
potentially having to handle both at once.
RXD
0xFF
...
B1
B0
≥20µs
CMD
Figure 19: 250 Series Transceiver CMD Line Timing
The CMD line is also used during the module startup process to determine
whether or not to reload the non-volatile registers with factory defaults. The
module startup process is executed when the module is powered on from
an off state or is issued a software or hardware reset. When the module
goes through this startup process, it checks the state of the CMD line. If it
is low, the module clears the non-volatile registers and re-populates them
with factory default values. It is important to ensure that CMD is held high
or left floating during power-up under normal conditions.
Possible reset sources that could cause the module to reboot are power
supply brown-out, power supply instability and noise present on the RESET
line, noise/voltage spikes on digital I/O lines, issuing a reset command
through the command interface, and toggling the RESET line when not in
deep sleep.
– 26 –
– 27 –
The UART Interface
The module uses a standard UART interface for both data to be sent over
the air and for configuring the module. The CMD line is used to tell the
module if the data on the UART is for configuration or transmission. The
lines follow the standard UART naming convention, so RXD is the data
input into the module and TXD is the data output from the module. The
UART interface expects 1 start bit, 8 data bits (LSB first), and 1 stop bit per
byte with no parity (8-N-1).
src_len) or the register number and value to write (two bytes, pass 2 into
src_len). It is also assumed that the *dest buffer has enough space for the
two header characters plus the encoded command and the null terminator.
int EscapeString(char *src, char src_len, char *dest)
{
// The following function copies and encodes the first
// src_len characters from *src into *dest. This
// encoding is necessary for module command formats.
The module has a 256 byte buffer for incoming data. The module can be
programmed to automatically transmit when the buffer reaches a limit or
based on the time between bytes on the UART. This allows the designer to
optimize the module for fixed length and variable length data. The module
supports streaming data as well. To optimize the module for streaming
data, regUARTMTU should be set to 128, and regTXTO should be set to a
value greater than 1 UART byte time at the current UART data rate (10 bit
times rounded up) or 2, whichever is greater.
// The resulting string is null terminated. The size
// of this string is the function return value.
// --------------------------------------------------char src_idx, dest_idx;
// Save space for the command header and size bytes
// -----------------------------------------------dest_idx = 2;
// Loop through source string and copy/encode
// ------------------------------------------
If the buffer gets nearly full (about 224 bytes), the module pulls the CTS line
high, indicating that the host should not send any more data. Data sent
by the host while the buffer is full is lost, so the the CTS line provides a
warning and should be monitored. When there is data in the UART receive
buffer, the BE line is low; when this buffer is empty, BE is high.
for (src_idx = 0; src_idx < src_len; src_idx++)
{
if (src[src_idx] > 127)
{
dest[dest_idx++] = 0xFE;
}/*if*/
Configuration Command Formatting
dest[dest_idx++] = (src[src_idx] & 0x7F);
The 250 Series module contains several volatile and non-volatile registers
that control its configuration and operation. The volatile registers all
have non-volatile mirror registers that are used to determine the default
configuration when power is applied to the module. During normal
operation, the volatile registers are used to control the module.
}/*for*/
// Add null terminator
// ------------------dest[dest_idx] = 0;
// Add command header
// ------------------
Placing the module in the command mode allows these registers to be
programmed. Byte values in excess of 127 (0x80 or greater) must be
changed into a two-byte escape sequence of the format:
dest[0] = 0xFF;
dest[1] = dest_idx – 2;
// Return escape string size
// -------------------------
0xFE, [value - 128]
return dest_idx;
For example, the value 0x83 becomes 0xFE, 0x03. The function in Figure
20 prepends a 0xFF header and size specifier to a command sequence
and creates escape sequences as needed. It is assumed that *src is
populated with either the register number to read (one byte, pass 1 into
– 28 –
}
Figure 20: Command Conversion Code
– 29 –
Module Configuration
The 250 Series module contains several registers that control its
configuration and operation. The module’s default settings allow it to
operate out of the box without any changes; however the registers allow
the link to be customized to better suit the application if necessary. The
register settings are stored in two types of memory inside the module.
Volatile memory is quick to access, but it is lost when power is removed
from the module. Non-volatile memory takes longer to access, but is
retained when power is removed.
250 Series Volatile Read / Write Configuration Registers Continued
Name
Address
Description
regOPMODE
0x58
Sets operating mode
regACKONWAKE
0x59
Enable / Disable ACK sent to UART upon wake
regUSERDESTID[3]
0x5A
Destination Address for Extended User Networking
Mode
regUSERDESTID[2]
0x5B
Destination Address for Extended User Networking
Mode
regUSERDESTID[1]
0x5C
Destination Address for User and Extended User
Networking Mode
regUSERDESTID[0]
0x5D
Destination Address for User and Extended User
Networking Mode
regUSERSRCID[3]
0x5E
Source Address for Extended User Networking
Mode
regUSERSRCID[2]
0x5F
Source Address for Extended User Networking
Mode
regUSERSRCID[1]
0x60
Source Address for User and Extended User
Networking Mode
regUSERSRCID[0]
0x61
Source Address for User and Extended User
Networking Mode
regUSERIDMASK[3]
0x62
Address Mask for Extended User Networking Mode
250 Series Volatile Read-Only Configuration Registers
regUSERIDMASK[2]
0x63
Address Mask for Extended User Networking Mode
Name
regUSERIDMASK[1]
0x64
Address Mask for User and Extended User
Networking Mode
All of the configuration settings have registers in both types of memory.
The settings are read from non-volatile registers on power up and saved in
volatile registers. The values in the volatile registers are used during normal
operation since it is faster to read and write the volatile memory locations.
There are commands to read and write both locations.
Figure 21 shows the volatile read-only registers. Figure 22 shows the
volatile read and write registers. Figure 23 shows the non-volatile read-only
registers. Figure 24 shows the non-volatile read and write registers.
Address
Description
regEXCEPTION
0x79
Stores latest exception code
regLGPRSSI
0x7B
Last Good Packet RSSI value
regUSERIDMASK[0]
0x65
Address Mask for User and Extended User
Networking Mode
regIMMEDRSSI
0x7C
Current RSSI value
regDESTGUID[3]
0x68
GUID Networking Mode Destination Address
regDESTGUID[2]
0x69
GUID Networking Mode Destination Address
regDESTGUID[1]
0x6A
GUID Networking Mode Destination Address
regDESTGUID[0]
0x6B
GUID Networking Mode Destination Address
Figure 21: 250 Series Volatile Read Only Configuration Registers
250 Series Volatile Read / Write Configuration Registers
Name
Address
regEXCEPTIONMASK
0x6C
Exception and Mask used to activate the EX line
Description
regCMDHALT
0x6E
Half RF traffic when the CMD line is low
regLNAMODE
0x6F
Receiver LNA gain / linearity setting
regCOMPATMODE
0x70
Compatibility mode for 25 and 250
intercommunication
regAUTADD
0x71
Sets automatic addressing
regCRCERRCOUNT
0x40
CRC error count value
regHOPTABLE
0x4B
Hop table
regPWRMODE
0x4D
Power amplifier setting
regUARTDATARATE
0x4E
UART data rate
regNETWORKMODE
0x4F
Sets the networking mode
regTXTO
0x50
UART to transmit timeout
regMAXTXRETRY
0x52
Maximum times to retry packet transmission
regUSECRC
0x53
Enable / Disable CRC checking
regUARTMTU
0x54
Minimum transmission unit
regCSMAMODE
0x56
Enable / Disable CSMA
– 30 –
Figure 22: 250 Series Volatile Read / Write Configuration Registers
Warning: Modules that are not configured in the same way will not be
able to communicate reliably, causing poor performance or outright
failure of the wireless link. All modules in a network must have compatible
configurations to ensure interoperability.
– 31 –
250 Series Non-Volatile Read-Only Registers
250 Series Non-Volatile Read / Write Registers Continued
Name
Name
Address
Description
Address
Description
Factory Default
regMyGUID[3]
0x34
Factory programmed GUID used in GUID Networking
Mode
regNVUSERDESTID[0]
0x12
regMYGUID[2]
0x35
Factory programmed GUID used in GUID Networking
Mode
Destination Address for
User and Extended User
Networking Mode
regNVUSERSRCID[3]
0x13
0xFF
0x36
Factory programmed GUID used in GUID Networking
Mode
Source Address for Extended
User Networking Mode
regNVUSERSRCID[2]
0x14
0xFF
0x37
Factory programmed GUID used in GUID Networking
Mode
Source Address for Extended
User Networking Mode
regNVUSERSRCID[1]
0x15
Source Address for User and
Extended User Networking
Mode
0xFF
regNVUSERSRCID[0]
0x16
Source Address for User and
Extended User Networking
Mode
0xFF
regNVUSERIDMASK[3]
0x17
Address Mask for Extended
User Networking Mode
0xFF
regNVUSERIDMASK[2]
0x18
Address Mask for Extended
User Networking Mode
0xFF
regNVUSERIDMASK[1]
0x19
Address Mask for User and
Extended User Networking
Mode
0xFF
regNVUSERIDMASK[0]
0x1A
Address Mask for User and
Extended User Networking
Mode
0xFF
regNVDESTGUID[3]
0x1D
GUID Networking Mode
Destination Address
0xFF
regNVDESTGUID[2]
0x1E
GUID Networking Mode
Destination Address
0xFF
regNVDESTGUID[1]
0x1F
GUID Networking Mode
Destination Address
0xFF
regNVDESTGUID[0]
0x20
GUID Networking Mode
Destination Address
0xFF
regNVEXCEPTIONMASK
0x21
Used to mask exception for
the EX line
regNVCMDHALT
0x23
Halt RF traffic when the CMD
line is low
0 (Disabled)
regNVLNAMODE
0x24
Receiver LNA gain / linearity
setting
0 (Auto)
regNVCOMPATMODE
0x25
Compatibility mode for 25 and
250 intercommunication
0 (Disabled)
regNVAUTADD
0x26
Sets automatic addressing
0 (Disabled)
regMYGUID[1]
regMYGUID[0]
regCUSTID[1]
0x39
Factory programmed customer ID, default 0xFF
regCUSTID[0]
0x3A
Factory programmed customer ID, default 0xFF
regRELEASENUM
0x78
Holds release number indicating h/w and f/w
Figure 23: 250 Series Non-volatile Read-Only Configuration Registers
250 Series Non-Volatile Read / Write Registers
Name
Address
Description
Factory Default
regNVHOPTABLE
0x00
Hop table
regNVPWRMODE
0x02
Power amplifier setting
regNVUARTDATARATE
0x03
UART data rate
regNVNETWORKMODE
0x04
Sets the networking mode
4 (MAC/GUID)
regNVTXTO
0x05
UART to transmitter timeout
16 (15–16ms)
regNVMAXTXRETRY
0x07
Maximum times to retry packet
transmission
26
regNVUSECRC
0x08
Enable/Disable CRC checking
1 (Enable)
regNVUARTMTU
0x09
Minimum transmission unit
regNVSHOWVERSION
0x0A
Enable/disable startup
message
1 (Enabled)
regNVCSMAMODE
0x0B
Enable/Disable CSMA
1 (Enable)
regNVOPMODE
0x0D
Sets operating mode
0 (Awake)
regNVACKONWAKE
0x0E
Enable/Disable ACK sent to
UART upon wake from
1 (Enable)
regNVUSERDESTID[3]
0x0F
Destination Address for
Extended User Networking
Mode
0xFF
0x10
Destination Address for
Extended User Networking
Mode
0xFF
0x11
Destination Address for
User and Extended User
Networking Mode
0xFF
regNVUSERDESTID[2]
regNVUSERDESTID[1]
– 32 –
0
3 (High Power)
0 (2400)
64 (64 bytes)
Figure 24: 250 Series Non-volatile Read / Write Configuration Registers
– 33 –
0xFF
0xFF (All)
Writing to Registers
Configuration Registers
Writing to a volatile register is nearly instantaneous. Writing to a non-volatile
register typically takes 16ms. Because the packet size can vary based on
the need for encoding, there are two possible packet structures. The first
structure writes a value that is less than 128 (0x80) and the second writes
a value that is higher. The higher value must be split into two values. Figure
25 shows the byte sequences for writing a register in each case.
The following sections give details on each configuration register. Green
addresses in the tables are volatile locations and blue are non-volatile.
250 Series Write to Configuration Register Command
CRC Error Count - Address = 0x40
The value in the regCRCERRCOUNT register is incremented each time
a packet is received that fails CRC check. Writing 0x00 to this register
initializes the count. Figure 27 shows the command and response.
Command for a Value less than 128 (0x80)
250 Series CRC Error Count
Header
Size
Address
Value
Read Command
0xFF
0x02
REG
V1
Command for a Value greater than 128 (0x80)
Header
Size
Address
Value
1
0xFF
0x03
REG
0xFE
Value
2
V2
Figure 25: 250 Series Write to Configuration Register Command
The module responds with an ACK (0x06). If it is not received, the
command should be resent. The module responds with a NACK (0x15) if a
write is attempted to a read-only or invalid register.
Warning: The module must remain powered for the duration of the
register write or important configuration information could be lost.
Reading from Registers
A register read command is constructed by placing an escape character
(0xFE) before the register number. The module responds by sending an
ACK (0x06) followed by the register number and register value. The register
value is sent unmodified, so if the register value is 0x83, 0x83 is returned.
If the register number is invalid, the module responds with a NACK (0x15).
The command and response are shown in Figure 26.
250 Series Read From Configuration Register
Command
Header
Size
Escape
Address
0xFF
0x02
0xFE
REG
ACK
Address
Value
0x06
REG
V1
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x40
0x06
0x40
V1
Write Command
Header
Size
Address
Value
0xFF
0x02
0x40
V1
Figure 27: 250 Series CRC Error Count Command and Response
Channel Hop Table - Address = 0x4B; NV Address = 0x00
The module supports 6 different hop sequences with minimal correlation.
The sequence is set by the value in the regHOPTABLE register. Changing
the hop sequence changes the physical band utilization, much the same
way that a channel does in a static transmitter. Valid values are 0-5. Figure
28 shows the command and response.
250 Series Channel Hop Table
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x4B
0x00
0x06
0x4B
0x00
V1
Write Command
Header
Size
Address
Value
0xFF
0x02
0x4B
0x00
V1
Figure 28: 250 Series Channel Hop Table Command and Response
Response
Figure 29 shows the RF channels used by the 250 Series and the hop
sequences referenced by channel number. The default hop sequence is 0.
Figure 26: 250 Series Read from Configuration Register Command and Response
– 34 –
– 35 –
Power Mode - Address = 0x4D; NV Address = 0x02
The value in the regPWRMODE register sets the module’s output power.
250 Series RF Channels and Hop Sequences
Channel Frequency
Number
(MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
902.971
903.723
904.475
905.226
905.978
906.730
907.482
908.234
908.986
909.737
910.489
911.241
911.993
912.745
913.496
914.248
915.000
915.752
916.504
917.255
918.007
918.759
919.511
920.263
921.015
921.766
922.518
923.270
924.022
924.774
925.525
926.277
Hop Sequence by Channel Number
0
1
2
3
4
5
16
1
2
5
10
21
11
23
14
29
27
22
12
24
17
3
7
15
31
30
28
25
19
6
13
26
15
30
29
26
21
10
20
8
17
2
4
9
19
7
14
28
24
16
0
1
3
6
12
25
18
5
3
20
21
24
29
8
30
10
1
16
14
9
31
11
4
22
26
2
18
17
15
12
6
25
0
13
28
11
10
7
2
23
1
21
30
15
17
22
0
20
27
9
5
29
13
14
16
19
25
6
31
18
22
7
8
11
16
27
17
29
20
3
1
28
18
30
23
9
13
21
5
4
2
31
25
12
19
0
9
24
23
20
15
4
14
2
11
28
30
3
13
1
8
22
18
10
26
27
29
0
6
19
12
31
Figure 30 shows the command and response and Figure 31 available
power settings and typical power outputs for the module. The default
setting is 0x03.
250 Series Power Mode
Read Command
Header
0xFF
Size
0x02
Read Response
Escape
Address
0xFE
0x4D
0x02
Address
Value
0x06
0x4D
0x02
PWR
Write Command
Header
Size
Address
Value
0xFF
0x02
0x4D
0x02
PWR
Figure 30: 250 Series Power Mode Command and Response
250 Series Power Mode Register Settings
PWR
Power Setting
Typical Output Power (dBm)
0x00
Low
+8
0x01
Mid – Low
+13
0x02
Mid – High
+18
0x03
High
+23.5
Figure 31: 250 Series Power Mode Settings
Figure 29: 250 Series RF Channels and Hop Sequences
– 36 –
ACK
– 37 –
UART Data Rate - Address = 0x4E; NV Address = 0x03
The value in regUARTDATARATE sets the data rate of the UART interface.
Changing the non-volatile register changes the data rate on the following
power-up or reset. Changing the volatile register changes the data rate
immediately following the command acknowledgement. Figure 32 shows
the command and response and Figure 33 shows the valid settings.
250 Series UART Data Rate
Read Command
Header
0xFF
Size
0x02
Read Response
Escape
Address
0xFE
0x4E
0x03
ACK
Address
0x06
0x4E
0x03
0xFF
Size
Address
Value
0x02
0x4E
0x03
V1
Figure 34 shows the command and response and Figure 35 shows the
valid settings.
250 Series Network Mode
Value
V1
Write Command
Header
Network Mode - Address = 0x4F; NV Address = 0x04
The module supports three networking modes: GUID, User, and Extended
User. For each of these modes, assured delivery (acknowledgement) and
extended preamble can be either enabled or disabled.
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x4F
0x04
0x06
0x4F
0x04
V1
Write Command
Header
Size
Address
Value
0xFF
0x02
0x4F
0x04
V1
Figure 32: 250 Series UART Data Rate Command and Response
Figure 34: 250 Series Network Mode Command and Response
250 Series UART Data Rate Register Settings
V1
250 Series Network Mode Register Settings
Baud Rate
0x00
2,400
Network Mode
0x01
9,600
0x04
GUID Networking Mode
0x02
19,200
0x06
User Networking Mode
0x03
38,400
0x07
Extended User Networking Mode
0x04
57,600
0x0C
GUID Networking Mode with Extended Preamble
0x05
115,200
0x0E
User Networking Mode with Extended Preamble
0x06
10,400*
0x0F
Extended User Network Mode with Extended Preamble
0x07
31,250*
0x14
GUID Networking Mode with Acknowledgement
0x16
User Networking Mode with Acknowledgement
0x17
Extended User Networking Mode with Acknowledgement
0x1C
GUID Networking Mode with Acknowledgement & Extended
Preamble
0x1E
User Networking Mode with Acknowledgement & Extended
Preamble
0x1F
Extended User Networking Mode with Acknowledgement &
Extended Preamble
* These data rates are not supported by PC serial ports.
Selection of these rates may cause the module to fail to
respond to a PC, requiring a reset to factory defaults.
Figure 33: 250 Series UART Data Rate Settings
If the UART rate is different than the host processor UART rate then the
module will not communicate correctly. If mismatched, every rate can be
tested until the correct one is found or the module can be reset to factory
defaults.
– 38 –
Meaning
Figure 35: 250 Series Network Mode Register Settings
– 39 –
Transmit Wait Timeout - Address = 0x50; NV Address = 0x05
When a byte is received from the UART, the module starts a timer that
counts down every millisecond. The timer is restarted when each byte is
received. The value for the regTXTO register is the number of milliseconds
to wait before transmitting the data in the UART receive buffer. The default
setting for this register is 0x10 (~16ms delay).
If the timer reaches zero before the next byte is received from the UART,
the module begins transmitting the data in the buffer. This timeout value
should be greater than one byte time at the current UART data rate with a
minimum of 0x02. It should not be set to a value of 0x01 or any value less
than one byte time as unpredictable results could occur.
Maximum Transmit Retries - Address = 0x52; NV Address = 0x07
regMAXTXRETRY sets the number of transmission retries if an
acknowledgement is not received. If an acknowledgement is not received
after the last retry, EX_NORFACK is raised. Figure 38 shows examples of
the command.
250 Series Maximum Transmit Retries
Read Command
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x52
0x07
0x06
0x52
0x07
V1
Size
Address
Value
0x02
0x52
0x07
V1
Write Command
Header
If the timeout value is set to 0x00, the transmit wait timeout is deactivated.
In this case, the transceiver waits until a number of bytes equal to the
Minimum Transmission Unit (MTU) have been received by the UART. All
of the bytes are sent once the MTU has been reached. Figure 36 shows
examples of the commands. Figure 37 shows the minimum timeout values
based on baud rate.
250 Series Transmit Wait Timeout
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x50
0x05
0x06
0x50
0x05
V1
Write Command
Header
0xFF
Read Response
0xFF
Figure 38: 250 Series Maximum Transmit Retries Command and Response
The time between retries depends on the current baud rate. Figure 39
shows the time between retries based on baud rate. The retry number
times the timeout times gives the potential latency before a new message
can be sent.
250 Series Acknowledgement Timeout Times
Baud Rate
Timeout Time
2400
170ms
Size
Address
Value
9600
75ms
0x02
0x50
0x05
V1
19200
45ms
38400
30ms
57600
30ms
115200
30ms
Figure 36: 250 Series Transmit Wait Timeout Command and Response
250 Series Minimum TXTO Values
Baud Rate
Minimum TXTO
2,400
6ms
9,600
3ms
19,200
2ms
38,400
2ms
57,600
2ms
115,200
2ms
Figure 39: 250 Series Acknowledgement Timeout Times
Figure 37: 250 Series Transmit Wait Timeout Minimum Values
– 40 –
– 41 –
CRC Control - Address = 0x53; NV Address = 0x08
The 250 Series protocol includes a Cyclic Redundancy Check on the
received packets to make sure that there are no errors. Any packets
with errors are discarded and not output on the UART. This feature can
be disabled if it is desired to perform error checking outside the module.
Set the regUSECRC register to 0x01 to enable CRC checking, or 0x00
to disable it. The default CRC mode setting is enabled. Figure 40 shows
examples of the commands and Figure 41 shows the available values.
250 Series CRC Control
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x53
0x08
0x06
0x53
0x08
V1
Write Command
Header
Size
Address
Value
0xFF
0x02
0x53
0x08
V1
250 Series UART MTU
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x54
0x09
0x06
0x54
0x09
V1
Size
Address
Value
0x02
0x54
0x09
V1
Write Command
Header
Figure 40: 250 Series CRC Control Command and Response
250 Series CRC Control Register Settings
V1
UART Minimum Transmission Unit - Addr = 0x54; NV Addr = 0x09
This register determines the UART buffer level that triggers the transmission
of a packet. The minimum value is decimal 1 and the maximum value
is 192. The default value for this register is 64, which provides a good
mix of throughput and latency. At the maximum data rate, a value of
128 optimizes throughput. This register does not guarantee a particular
transmission unit size; rather, it specifies the minimum desired size. If there
is not enough time left in a hop, for instance, the protocol engine sends as
many characters as it can to fill the current hop, and sends the remaining
characters in the next hop. Figure 42 shows examples of the commands.
0xFF
Figure 42: 250 Series UART MTU Command and Response
Mode
0x00
CRC Disabled
0x01
CRC Enabled
Figure 41: 250 Series CRC Control Register Settings
– 42 –
– 43 –
Show Version - Address = 0x0A
Setting this register to 0x00 suppresses the start-up message, including
firmware version, which is sent to the UART when the module is reset. A
value of 0x01 causes the message to be output after reset. By default,
the module start-up message is output. Figure 43 shows examples of the
commands and Figure 44 shows the available values.
250 Series Show Version
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x0A
0x06
0x0A
V1
0xFF
Size
0x02
Address
0x0A
Header
Value
V1
0xFF
Figure 43: 250 Series Show Version Command and Response
250 Series Show Version Register Settings
V1
250 Series CSMA Enable
Read Command
Write Command
Header
CSMA Enable - Address = 0x56; NV Address = 0x0B
Carrier-Sense Multiple Access (CSMA) is a transmission protocol that
listens to the channel before transmitting a message. If another module is
already transmitting when a message is queued, the module waits before
sending its payload. This helps to eliminate RF message corruption at the
expense of additional latency. Setting the regCSMAMODE register to 0x01
enables CSMA and 0x00 disables CSMA. By default, CSMA is enabled.
Figure 45 shows examples of the commands and Figure 46 shows the
available values.
Size
0x02
Read Response
Escape
Address
0xFE
0x56
0x0B
Write Command
Header
Size
Address
Value
0xFF
0x02
0x56
0x0B
V1
Meaning
0x00
Startup message is NOT output on reset or power-up.
0x01
Startup message is output on reset or power-up. This is a blocking
call, and any incoming UART data is lost during the transmission of
this message through the TXD line. All UART commands must be
sent after this message has completed.
0x02
Startup message is displayed upon reset or power-up. This is
a non-blocking call. Any incoming UART data is buffered, and
incoming UART commands are processed. If a change of baud
rate is commanded while the startup message is being output, the
current byte finishes at the current baud rate, and subsequent bytes
are transmitted at the new baud rate.
Figure 45: 250 Series CSMA Enable Command and Response
250 Series CSMA Enable Register Settings
V1
Mode
0x00
Disable CSMA
0x01
Enable CSMA
Figure 46: 250 Series CSMA Enable Register Settings
Figure 44: 250 Series Show Version Register Settings
– 44 –
– 45 –
ACK
Address
Value
0x06
0x56
0x0B
V1
Operating Mode - Address = 0x58; NV Address = 0x0D
The value in the regOPMODE register sets the operating mode of the
transceiver. If the module remains properly powered, and is awakened from
a low power mode properly, the volatile registers retain their values when
awakened. If the volatile registers become corrupted during low power, a
software reset is forced and the module reboots.
Awake mode is the normal operating mode. This is the only mode in which
the RF circuitry is able to receive and transmit RF messages.
ACK on Wake - Address = 0x59; NV Address = 0x0E
When the module powers up and is ready for operation, it can output an
acknowledge (ACK) character (0x06) on the TXD line. This indicates that
the module is ready to accept data and commands. Setting this register to
0x00 disables the ACK, 0x01 enables the ACK. The default value is 0x01.
Figure 49 shows examples of the commands and Figure 50 shows the
available values.
250 Series ACK on Wake
Read Command
Standby leaves the RF oscillator circuit operating for faster wakeup,
whereas Sleep does not. One byte of 0x0F to the module’s RXD line at the
current baud rate wakes the modules.
Header
0xFF
Size
Read Response
Escape
Address
0xFE
0x59
0x0E
Size
Address
Value
0x02
0x59
0x0E
V1
0x02
Write Command
Deep Sleep mode disables all circuitry on-board the module. This is the
lowest-power mode available for the module. A low pulse on the RESET
line of at least 15μs wakes the module. The module begins the wake
process once the RESET line is returned high.
Please see the Low Power States section for more details. Figure 47 shows
examples of the commands and Figure 48 shows the available values.
Header
0xFF
Figure 49: 250 Series ACK on Wake Command and Response
250 Series ACK on Wake Register Settings
V1
250 Series Operating Mode
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x58
0x0D
0x06
0x58
0x0D
V1
Size
Address
Value
0x02
0x58
0x0D
V1
Mode
0x00
Disable ACK
0x01
Enable ACK
Figure 50: 250 Series ACK on Wake Register Settings
Write Command
Header
0xFF
Figure 47: 250 Series Operating Mode Command and Response
250 Series Operating Mode Register Settings
V1
Mode
0x00
Awake Mode
0x01
Sleep Mode
0x02
Standby Mode
0x03
Deep Sleep Mode
Figure 48: 250 Series Operating Mode Register Settings
– 46 –
– 47 –
ACK
Address
Value
0x06
0x59
0x0E
V1
User Destination ID
These registers contain the address of the destination module when
User Networking mode or Extended User Networking mode are enabled.
User Networking mode uses bytes 0 and 1 to determine the destination
address. Extended User Networking mode uses all four bytes. Please see
the Networking Modes section for more details. Each register byte is read
and written separately.
User ID Mask
These registers contain the user ID mask when User Networking mode
or Extended User Networking mode are enabled. User Networking mode
uses bytes 0 and 1 and Extended User Networking mode uses all four
bytes. Please see the Networking Modes section for more details. Each
register byte is read and written separately.
Figure 53 shows the User ID Mask Registers.
Figure 51 shows the User Destination ID Registers.
250 Series User Destination ID Registers
Name
Volatile
Address
Non-Volatile
Address
Description
250 Series User ID Mask Registers
Name
Volatile
Address
Non-Volatile
Address
Description
regUSERIDMASK[3]
0x62
0x17
MSB of the extended mask
regUSERIDMASK[2]
0x63
0x18
Byte 2 of the extended mask
regUSERDESTID[3]
0x5A
0x0F
MSB of the extended destination
address
regUSERDESTID[2]
0x5B
0x10
Byte 2 of the extended destination
address
regUSERIDMASK[1]
0x64
0x19
Byte 1 of the extended mask
MSB of the short mask
regUSERDESTID[1]
0x5C
0x11
Byte 1 of the extended destination
address, MSB of the short destination
address
regUSERIDMASK[0]
0x65
0x1A
LSB of the extended mask and short
mask
regUSERDESTID[0]
0x5D
0x12
LSB of the extended destination
address and short destination address
Figure 51: 250 Series User Destination ID Registers
User Source ID
These registers contain the address of the source module when User
Networking mode or Extended User Networking mode are enabled. User
Networking mode uses bytes 0 and 1 to determine the source address.
Extended User Networking mode uses all four bytes. Please see the
Networking Modes section for more details. Each register byte is read and
written separately.
Figure 52 shows the User Source ID Registers.
250 Series User Source ID Registers
Name
Volatile
Address
Non-Volatile
Address
regUSERSRCID[3]
0x5E
0x13
MSB of the extended source address
regUSERSRCID[2]
0x5F
0x14
Byte 2 of the extended source address
regUSERSRCID[1]
0x60
0x15
Byte 1 of the extended source address
MSB of the short source address
0x16
LSB of the extended source address
and short source address
regUSERSRCID[0]
0x61
Description
Figure 53: 250 Series User ID Mask Registers
Destination GUID
These registers contain the address of the destination module when GUID
Networking Mode is enabled. Please see the Networking Modes section for
more details. Each register byte is read and written separately.
Figure 54 shows the Destination ID Registers.
250 Series Destination GUID Registers
Name
Volatile
Address
Non-Volatile
Address
regDESTGUID[3]
0x68
0x1D
MSB of the destination GUID
regDESTGUID[2]
0x69
0x1E
Byte 2 of the destination GUID
regDESTGUID[1]
0x6A
0x1F
Byte 1 of the destination GUID
MSB of the short destination GUID
regDESTGUID[0]
0x6B
0x20
LSB of the extended and short
destination GUID
Figure 54: 250 Series Destination GUID Registers
Figure 52: 250 Series User Source ID Registers
– 48 –
– 49 –
Description
Exception Mask - Address = 0x6C; NV Address = 0x21
The module has a built-in exception engine that can notify the host
processor of an unexpected event. When an exception occurs, this register
is ANDed with the exception code. A non-zero result causes the EX line to
be asserted. Reading the regEXCEPTION register clears the exception and
resets the EX line. If the result is zero, the EX line is not asserted but the
exception code is stored in the regEXCEPTION register.
CMD Halts Traffic- Address = 0x6E; NV Address = 0x23
When configuring the module’s register settings, it is possible that incoming
RF transmissions can intermix with the module’s response, making it
difficult to determine if your commands were successfully processed.
Changing this register setting to 0x01 causes the module to store incoming
RF traffic (up to the RF buffer overflow) while the CMD line is low. When the
CMD line is returned high, the module outputs all buffered data.
Figure 55 shows examples of the commands and Figure 56 shows the
available values.
Figure 57 shows examples of the commands and Figure 58 shows the
available values.
250 Series Exception Masks
250 Series CMD Halts Traffic
Read Command
Header
0xFF
Size
0x02
Read Response
Escape
Address
0xFE
0x6C
0x21
Read Command
Address
Value
Header
Size
Escape
Address
ACK
Address
Value
0x06
0x6C
0x21
V1
0xFF
0x02
0xFE
0x6E
0x23
0x06
0x6E
0x23
V1
Write Command
Header
0xFF
Write Command
Size
Address
Value
Header
Size
Address
Value
0x02
0x6C
0x21
V1
0xFF
0x02
0x6E
0x23
V1
Figure 55: 250 Series Transceiver Exception Mask Command and Response
250 Series Example Exception Masks
V1
Read Response
ACK
Figure 57: 250 Series Transceiver CMD Halts Traffic Command and Response
250 Series CMD Halts Traffic Register Settings
Exception Name
0x08
Allows only EX_BUFOVFL and EX_RFOVFL to trigger the EX line
0x10
Allows only EX_WRITEREGFAILED to trigger the EX line
0x20
Allows only EX_NORFACK to trigger the EX line
0x40
Allows only EX_BADCRC, EX_BADHEADER, EX_BADSEQID and EX_
BADFRAMETYPE exceptions to trigger the EX line
0x60
Allows EX_BADCRC, EX_BADHEADER, EX_BADSEQID, EX_BADFRAMETYPE
and EX_NORFACK exceptions to trigger the EX line
0xFF
Allows all exceptions to trigger the EX line
V1
Mode
0x00
Disable Halt
0x01
Enable Halt
Figure 58: 250 Series CMD Halts Traffic Register Settings
Figure 56: 250 Series Transceiver Example Exception Masks
– 50 –
– 51 –
Receiver LNA Mode - Address = 0x6F; NV Address = 0x24
By default, the module is factory-configured to use its internal Automatic
Gain Control (AGC) circuit to manage receiver sensitivity. Reducing the gain
increases the linearity of the receiver, but reduces maximum sensitivity;
increasing the gain does the opposite. Generally speaking, higher
linearity (increased third order input intercept point, IIP3) gives improved
performance in high-interference environments; high gain yields better
performance in low-interference environments.
Compatibility Mode - Address = 0x70; NV Address = 0x25
Compatibility mode allows the 250 Series modules to communicate with
the 25 Series modules. Please see the Compatibility Mode section for more
details. Figure 61 shows examples of the commands and Figure 62 shows
the available values.
250 Series Compatibility Mode
Read Command
Header
The module contains an AGC circuit that manages these settings
automatically, and it should be used whenever possible. When reading the
digital RSSI registers (regIMMEDRSSI, regLGPRSSI), the internal calculation
automatically compensates for the current LNA gain setting. However,
when attempting to make analog RSSI measurements, fixing the LNA gain
produces more meaningful results.
Figure 59 shows examples of the commands and Figure 60 shows the
available values.
250 Series LNA Mode
0xFF
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x6F
0x24
0x06
0x6F
0x24
V1
Size
Address
Value
0x02
0x6F
0x24
V1
Escape
Address
0xFE
0x70
0x25
Size
Address
Value
0x02
0x70
0x25
V1
0x02
ACK
Address
Value
0x06
0x70
0x25
V1
Write Command
Header
0xFF
Figure 61: 250 Series Transceiver Compatibility Mode Command and Response
250 Series Compatibility Mode Register Settings
V1
Read Command
Size
Read Response
Mode
0x00
Disable Compatibility Mode
0x01
Enable Compatibility Mode
Figure 62: 250 Series Compatibility Mode Register Settings
Write Command
Header
0xFF
Auto Addressing - Address = 0x71; NV Address = 0x26
When this register is enabled, the module reads the Source Address from
a received packet and uses it to fill the Destination Address registers.
This makes sure that a response is sent to the device that transmitted the
original message.
Figure 59: 250 Series Transceiver LNA Mode Command and Response
250 Series LNA Mode Register Settings
V1
Meaning
IIP3 Increase
Sensitivity Decrease
0x00
AGC Enabled
Variable
Variable
0x01
High Sensitivity
Reference
Reference
0x02
Mid Linearity
19.1dB
6.5dB
0x03
High Linearity
41.8dB
9.5dB
Figure 60: 250 Series Transceiver LNA Mode Register Settings
– 52 –
The non-volatile register only uses the lower 4 bits to configure the
automatic addressing. The upper 4 bits are not used.
The volatile register is split in half with the lower 4 bits configuring the
automatic addressing, the same as the non-volatile register.
The upper 4 bits indicate the type of packet that was last received. This
indication is the same as the Network Mode register setting. These bits
are not used by the module and are only written by the module after
successfully receiving a packet.
– 53 –
As an example, if regAUTADD is set to 0x0F (Any Auto Address) and a
GUID packet is received from another module, then regAUTADD reads
back as 0x4F. The lower 4 bits indicate that the module is set to any auto
address (0xF). The upper 4 bits indicate that the packet that was just
received was a GUID Network Mode packet (0x4).
My GUID
These registers contain the factory-programmed read-only GUID address.
This address is unique for each module and is used by all packet types as
a unique origination address.
Figure 65 shows the GUID Registers.
Figure 63 summarizes the configuration values for the lower 4 bits of the
register.
250 Series GUID Registers
Name
Non-Volatile
Address
regMYGUID[3]
0x34
MSB of the GUID address
regMYGUID[2]
0x35
Byte 2 of the GUID address
regMYGUID[1]
0x36
Byte 1 of the GUID address
regMYGUID[0]
0x37
LSB of the GUID address
250 Series Auto Addressing Register Settings
Auto Address Value
Meaning
Action
0x00
Auto Addressing disabled
Destination Registers not
populated
0x04
GUID Auto Address
Auto-populates GUID Address
Destination Register Only
0x06
User Auto Address Mode
Auto-populates User Address
Destination Register
0x07
Extended User Auto Address
Mode
Auto-populates User Address
Destination Register
Any Auto Address Mode
Auto-populates GUID Address
Destination Register
0x0F
Figure 63: 250 Series Transceiver Auto Addressing Register Settings
Figure 64 shows the Network Mode values that the module writes to the
upper 4 bits after successfully receiving a packet.
250 Series Auto Addressing Network Mode Indicator
Network Mode
Description
Figure 65: 250 Series GUID Registers
Release Number - NV Address = 0x78
This register contains a hard-coded release number corresponding to a
firmware version and hardware platform. Figure 66 shows examples of the
commands and Figure 67 lists current releases to date.
250 Series Release Number
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x78
0x06
0x78
V1
Meaning
0x4
GUID Networking Mode
0x6
User Networking Mode
0x7
Extended User Networking Mode
Figure 64: 250 Series Transceiver Auto Addressing Network Mode Indicator
Figure 66: 250 Series Transceiver Release Number Command and Response
250 Series Release Number Register Settings
V1
Release Number
0x0D
1.0.5
0x10
1.0.5a
0x11
1.1.0
0x14
1.1.0 (Brazil)
Figure 67: 250 Series Transceiver Release Number Register Settings
– 54 –
– 55 –
Exception - Address = 0x79
The module has a built-in exception engine that can notify the host
processor of an unexpected event. If an exception occurs, the exception
code is stored in this register. Reading from this register clears the
exception and, if applicable, resets the EX line. If an exception occurs
before the previous exception code is read, the previous value is
overwritten. Figure 68 shows examples of the commands and Figure 69
shows the available values.
250 Series Last Good Packet RSSI
250 Series Exception
Read Command
Header
0xFF
Size
0x02
Read Command
Read Response
Escape
Address
0xFE
ACK
0x79
0x06
Address
0x79
Read Response
Value
Header
Size
Escape
Address
ACK
Address
Value
V1
0xFF
0x02
0xFE
0x7B
0x06
0x7B
V1
Figure 68: 250 Series Transceiver Exception Command and Response
250 Series Transceiver Exception Codes
V1
Last Good Packet RSSI - Address = 0x7B
This register holds the received signal strength in dBm of the last
successful received packet. A successful packet reception is one that
causes payload data to be output on the UART interface. The value in this
register is overwritten each time a new packet is successfully processed.
The register value is an 8-bit signed integer representing the RSSI in dBm.
It is accurate to ±3dB and has ±2dB linearity. The values take the LNA gain
into account.
Exception Name
Description
0x08
EX_BUFOVFL
Internal UART buffers overflowed.
0x09
EX_RFOVFL
Internal RF packet buffer overflowed.
0x13
EX_WRITEREGFAILED
Attempted write to register failed.
0x20
EX_NORFACK
Acknowledgement packet not received
after maximum number of retries.
0x40
EX_BADCRC
Bad CRC detected on incoming packet.
0x42
EX_BADHEADER
Bad CRC detected in packet header.
0x43
EX_BADSEQID
Sequence ID was incorrect in ACK packet.
0x44
EX_BADFRAMETYPE
Unsupported frame type specified.
Figure 71: 250 Series Transceiver Last Good Packet RSSI Command and Response
Immediate RSSI - Address = 0x7C
This register returns the current receive signal strength indication in dBm.
The signal strength is measured as soon as the command is registered and
the value is loaded into the regIMMEDRSSI register. The register value is an
8-bit signed integer representing the RSSI in dBm. It is accurate to ±3dB
and has ±2dB linearity. The values take the LNA gain into account.
250 Series Immediate RSSI
Read Command
Read Response
Header
Size
Escape
Address
ACK
Address
Value
0xFF
0x02
0xFE
0x7C
0x06
0x7C
V1
Figure 72: 250 Series Transceiver Immediate RSSI Command and Response
Figure 69: 250 Series Transceiver Exception Codes
Custom ID
These registers contain the factory-programmed custom ID. A value is
assigned to OEM customer with a custom version of the module. Contact
Linx for details. Figure 70 shows the GUID Registers.
250 Series Custom ID Registers
Name
Non-Volatile
Address
regCUSTID[1]
0x39
MSB of the custom ID
regCUSTID[0]
0x3A
LSB of the custom ID
Description
Figure 70: 250 Series Transceiver Custom ID
– 56 –
– 57 –
Typical Applications
Antenna Considerations
Figure 73 shows a circuit using the 250 Series transceiver.
The choice of antennas is a critical and
often overlooked design consideration.
The range, performance and legality of
an RF link are critically dependent upon
the antenna. While adequate antenna
performance can often be obtained by
trial and error methods, antenna design
Figure 75: Linx Antennas
and matching is a complex task.
Professionally designed antennas such as those from Linx (Figure 75) help
ensure maximum performance and FCC and other regulatory compliance.
GPIO
GPIO
GPIO
NC
TXD
NC
NC
NC
RESET
C2D
NC
CMD_RSP
EX
GND
ANT
GND
RXD
CTS
NC
NC
BE
CMD
RSSI
23
22
21
20
19
18
17
16
15
14
GND
GND
11
12
13
TXD
GPIO
GPIO
GPIO
GPIO
µ
1
2
3
4
5
6
7
8
9
10
GND
GND
GND
GND
RXD
VCC
VCC
VCC
26
25
24
VCC
Linx transmitter modules typically have an output power that is higher
than the legal limits. This allows the designer to use an inefficient antenna
such as a loop trace or helical to meet size, cost or cosmetic requirements
and still achieve full legal output power for maximum range. If an efficient
antenna is used, then some attenuation may be needed.
GND
Figure 73: 250 Series Transceiver Basic Application Circuit
The transceiver UART is connected to a microcontroller UART for
communication of configuration data and data to be sent over the air. The
microcontroller is connected to the CMD-RSP, EX, CMD, BE and CTS
lines to monitor the current state of the module. It monitors the RSSI line to
monitor the strength of the incoming RF signal.
There is no need for buffering or other circuitry between the transceiver and
microcontroller provided that both are operating on the same voltage.
Power Supply Requirements
Vcc TO
MODULE
10Ω
10µF
Figure 74: Supply Filter
A 10Ω resistor in series with the supply followed by a 10μF tantalum
capacitor from Vcc to ground helps in cases where the quality of supply
power is poor (Figure 74). This filter should be placed close to the module’s
supply lines. These values may need to be adjusted depending on the
noise present on the supply line.
– 58 –
Helpful Application Notes from Linx
It is not the intention of this manual to address in depth many of the issues
that should be considered to ensure that the modules function correctly
and deliver the maximum possible performance. We recommend reading
the application notes listed in Figure 76 which address in depth key areas
of RF design and application of Linx products. These applications notes
are available online at www.linxtechnologies.com or by contacting the Linx
literature department.
Vcc IN
+
The module does not have an internal
voltage regulator, therefore it requires a clean,
well-regulated power source. The power supply
noise should be less than 20mV. Power supply
noise can significantly affect the module’s
performance, so providing a clean power supply
for the module should be a high priority during
design.
It is usually best to utilize a basic quarter-wave whip until your prototype
product is operating satisfactorily. Other antennas can then be evaluated
based on the cost, size and cosmetic requirements of the product.
Helpful Application Note Titles
Note Number
Note Title
AN-00100
RF 101: Information for the RF Challenged
AN-00126
Considerations for Operation Within the 902–928MHz Band
AN-00130
Modulation Techniques for Low-Cost RF Data Links
AN-00140
The FCC Road: Part 15 from Concept to Approval
AN-00500
Antennas: Design, Application, Performance
AN-00501
Understanding Antenna Specifications and Operation
Figure 76: Helpful Application Note Titles
– 59 –
Interference Considerations
Microstrip Details
The RF spectrum is crowded and the potential for conflict with unwanted
sources of RF is very real. While all RF products are at risk from
interference, its effects can be minimized by better understanding its
characteristics.
A transmission line is a medium whereby RF energy is transferred from
one place to another with minimal loss. This is a critical factor, especially
in high-frequency products like Linx RF modules, because the trace
leading to the module’s antenna can effectively contribute to the length
of the antenna, changing its resonant bandwidth. In order to minimize
loss and detuning, some form of transmission line between the antenna
and the module should be used unless the antenna can be placed very
close (<1/8in) to the module. One common form of transmission line is a
coax cable and another is the microstrip. This term refers to a PCB trace
running over a ground plane that is designed to serve as a transmission line
between the module and the antenna. The width is based on the desired
characteristic impedance of the line, the thickness of the PCB and the
dielectric constant of the board material. For standard 0.062in thick FR-4
board material, the trace width would be 111 mils. The correct trace width
can be calculated for other widths and materials using the information in
Figure 77 and examples are provided in Figure 78. Software for calculating
microstrip lines is also available on the Linx website.
Interference may come from internal or external sources. The first step
is to eliminate interference from noise sources on the board. This means
paying careful attention to layout, grounding, filtering and bypassing in
order to eliminate all radiated and conducted interference paths. For
many products, this is straightforward; however, products containing
components such as switching power supplies, motors, crystals and other
potential sources of noise must be approached with care. Comparing your
own design with a Linx evaluation board can help to determine if and at
what level design-specific interference is present.
External interference can manifest itself in a variety of ways. Low-level
interference produces noise and hashing on the output and reduces the
link’s overall range.
Trace
Board
High-level interference is caused by nearby products sharing the same
frequency or from near-band high-power devices. It can even come from
your own products if more than one transmitter is active in the same area.
It is important to remember that only one transmitter at a time can occupy
a frequency, regardless of the coding of the transmitted signal. This type of
interference is less common than those mentioned previously, but in severe
cases it can prevent all useful function of the affected device.
Although technically not interference, multipath is also a factor to be
understood. Multipath is a term used to refer to the signal cancellation
effects that occur when RF waves arrive at the receiver in different phase
relationships. This effect is a particularly significant factor in interior
environments where objects provide many different signal reflection paths.
Multipath cancellation results in lowered signal levels at the receiver and
shorter useful distances for the link.
Ground plane
Figure 77: Microstrip Formulas
Example Microstrip Calculations
Dielectric Constant
Width / Height
Ratio (W / d)
Effective Dielectric
Constant
Characteristic
Impedance (Ω)
4.80
1.8
3.59
50.0
4.00
2.0
3.07
51.0
2.55
3.0
2.12
48.8
Figure 78: Example Microstrip Calculations
– 60 –
– 61 –
Pad Layout
The pad layout diagram in Figure 79 is designed to facilitate both hand and
automated assembly.
1.200”
(30.48mm)
0.400”
(10.16mm)
0.200”
(5.08mm)
0.120”
(3.04mm)
Do not route PCB traces directly under the module. There should not be
any copper or traces under the module on the same layer as the module,
just bare PCB. The underside of the module has traces and vias that could
short or couple to traces on the product’s circuit board.
0.400”
(10.16mm)
0.150”
(3.81mm)
0.130”
(3.30mm)
0.100”
(2.54mm)
0.075”
(1.91mm)
0.120”
(3.04mm)
Make sure internal wiring is routed away from the module and antenna and
is secured to prevent displacement.
1.200”
(30.48mm)
0.150”
(3.81mm)
Figure 79: Recommended PCB Layout
Board Layout Guidelines
The module’s design makes integration straightforward; however, it
is still critical to exercise care in PCB layout. Failure to observe good
layout techniques can result in a significant degradation of the module’s
performance. A primary layout goal is to maintain a characteristic
50-ohm impedance throughout the path from the antenna to the module.
Grounding, filtering, decoupling, routing and PCB stack-up are also
important considerations for any RF design. The following section provides
some basic design guidelines.
During prototyping, the module should be soldered to a properly laid-out
circuit board. The use of prototyping or “perf” boards results in poor
performance and is strongly discouraged. Likewise, the use of sockets
can have a negative impact on the performance of the module and is
discouraged.
The module should, as much as reasonably possible, be isolated from
other components on your PCB, especially high-frequency circuitry such as
crystal oscillators, switching power supplies, and high-speed bus lines.
The Pad Layout section shows a typical PCB footprint for the module. A
ground plane (as large and uninterrupted as possible) should be placed on
a lower layer of your PC board opposite the module. This plane is essential
for creating a low impedance return for ground and consistent stripline
performance.
Use care in routing the RF trace between the module and the antenna
or connector. Keep the trace as short as possible. Do not pass it under
the module or any other component. Do not route the antenna trace on
multiple PCB layers as vias add inductance. Vias are acceptable for tying
together ground layers and component grounds and should be used in
multiples.
Each of the module’s ground pins should have short traces tying
immediately to the ground plane through a via.
Bypass caps should be low ESR ceramic types and located directly
adjacent to the pin they are serving.
A 50-ohm coax should be used for connection to an external antenna.
A 50-ohm transmission line, such as a microstrip, stripline or coplanar
waveguide should be used for routing RF on the PCB. The Microstrip
Details section provides additional information.
In some instances, a designer may wish to encapsulate or “pot” the
product. There are a wide variety of potting compounds with varying
dielectric properties. Since such compounds can considerably impact
RF performance and the ability to rework or service the product, it is
the responsibility of the designer to evaluate and qualify the impact and
suitability of such materials.
When possible, separate RF and digital circuits into different PCB regions.
– 62 –
– 63 –
The module is housed in a hybrid SMD package that supports hand and
automated assembly techniques. Since the modules contain discrete
components internally, the assembly procedures are critical to ensuring
the reliable function of the modules. The following procedures should be
reviewed with and practiced by all assembly personnel.
Hand Assembly
Pads located on the bottom
Soldering Iron
of the module are the primary
Tip
mounting surface (Figure 80).
Since these pads are inaccessible
during mounting, castellations
that run up the side of the module Solder
have been provided to facilitate
PCB Pads
Castellations
solder wicking to the module’s
Figure 80: Soldering Technique
underside. This allows for very
quick hand soldering for prototyping and small volume production. If the
recommended pad guidelines have been followed, the pads will protrude
slightly past the edge of the module. Use a fine soldering tip to heat the
board pad and the castellation, then introduce solder to the pad at the
module’s edge. The solder will wick underneath the module, providing
reliable attachment. Tack one module corner first and then work around the
device, taking care not to exceed the times in Figure 81.
Warning: Pay attention to the absolute maximum solder times.
Absolute Maximum Solder Times
Hand Solder Temperature: +225ºC for 10 seconds
Reflow Oven: +225ºC max (see Figure 82)
Figure 81: Absolute Maximum Solder Times
Automated Assembly
For high-volume assembly, the modules are generally auto-placed.
The modules have been designed to maintain compatibility with reflow
processing techniques; however, due to their hybrid nature, certain aspects
of the assembly process are far more critical than for other component
types. Following are brief discussions of the three primary areas where
caution must be observed.
– 64 –
Reflow Temperature Profile
The single most critical stage in the automated assembly process is the
reflow stage. The reflow profile in Figure 82 should not be exceeded
because excessive temperatures or transport times during reflow will
irreparably damage the modules. Assembly personnel need to pay careful
attention to the oven’s profile to ensure that it meets the requirements
necessary to successfully reflow all components while still remaining
within the limits mandated by the modules. The figure below shows the
recommended reflow oven profile for the modules.
300
Recommended RoHS Profile
Max RoHS Profile
Recommended Non-RoHS Profile
255°C
250
235°C
217°C
Temperature (oC)
Production Guidelines
200
185°C
180°C
150
125°C
100
50
0
30
60
90
120
150
180
210
240
270
300
330
360
Time (Seconds)
Figure 82: Maximum Reflow Temperature Profile
Shock During Reflow Transport
Since some internal module components may reflow along with the
components placed on the board being assembled, it is imperative that
the modules not be subjected to shock or vibration during the time solder
is liquid. Should a shock be applied, some internal components could be
lifted from their pads, causing the module to not function properly.
Washability
The modules are wash-resistant, but are not hermetically sealed. Linx
recommends wash-free manufacturing; however, the modules can be
subjected to a wash cycle provided that a drying time is allowed prior
to applying electrical power to the modules. The drying time should be
sufficient to allow any moisture that may have migrated into the module
to evaporate, thus eliminating the potential for shorting damage during
power-up or testing. If the wash contains contaminants, the performance
may be adversely affected, even after drying.
– 65 –
General Antenna Rules
The following general rules should help in maximizing antenna performance.
1. Proximity to objects such as a user’s hand, body or metal objects will
cause an antenna to detune. For this reason, the antenna shaft and tip
should be positioned as far away from such objects as possible.
2. Optimum performance is obtained from a ¼- or ½-wave straight whip
mounted at a right angle to the ground plane (Figure 83). In many
cases, this isn’t desirable for practical or ergonomic reasons, thus,
an alternative antenna style such as a helical, loop or patch may be
utilized and the corresponding sacrifice in performance accepted.
OPTIMUM
USABLE
NOT RECOMMENDED
Figure 83: Ground Plane Orientation
plane as possible in proximity to the base of the antenna. In cases
where the antenna is remotely located or the antenna is not in close
proximity to a circuit board, ground plane or grounded metal case, a
metal plate may be used to maximize the antenna’s performance.
5. Remove the antenna as far as possible from potential interference
sources. Any frequency of sufficient amplitude to enter the receiver’s
front end will reduce system range and can even prevent reception
entirely. Switching power supplies, oscillators or even relays can also
be significant sources of potential interference. The single best weapon
against such problems is attention to placement and layout. Filter the
module’s power supply with a high-frequency bypass capacitor. Place
adequate ground plane under potential sources of noise to shunt noise
to ground and prevent it from coupling to the RF stage. Shield noisy
board areas whenever practical.
6. In some applications, it is advantageous to place the module and
antenna away from the main equipment (Figure 85). This can avoid
interference problems and allows the antenna to be oriented for
optimum performance. Always use 50Ω coax, like RG-174, for the
OPTIMUM
remote feed.
NOT RECOMMENDED
USABLE
CASE
3. If an internal antenna is to be used, keep it away
from other metal
components, particularly large items like
transformers,
batteries,
GROUND PLANE
NUT
PCB tracks and ground planes. In many
the space around the
(MAYcases,
BE NEEDED)
antenna is as important as the antenna itself. Objects in close proximity
to the antenna can cause direct detuning, while those farther away will
alter the antenna’s symmetry.
CASE
GROUND PLANE
(MAY BE NEEDED)
NUT
4. In many antenna designs, particularly ¼-wave whips, the ground plane
acts as a counterpoise, forming, in essence,
VERTICAL λ/4 GROUNDED
a ½-wave dipole (Figure 84). For this reason,
ANTENNA (MARCONI)
adequate ground plane area is essential.
DIPOLE
ELEMENT
The ground plane can be a metal case or
λ/4
ground-fill areas on a circuit board. Ideally, it
should have a surface area less than or equal
to the overall length of the ¼-wave radiating
element. This is often not practical due to
GROUND
PLANE
size and configuration constraints. In these
VIRTUAL λ/4
λ/4
instances, a designer must make the best use
DIPOLE
of the area available to create as much ground
Figure 85: Remote Ground Plane
E
I
Figure 84: Dipole Antenna
– 66 –
– 67 –
Common Antenna Styles
There are hundreds of antenna styles and variations that can be employed
with Linx RF modules. Following is a brief discussion of the styles most
commonly utilized. Additional antenna information can be found in Linx
Application Notes AN-00100, AN-00140, AN-00500 and AN-00501. Linx
antennas and connectors offer outstanding performance at a low price.
Whip Style
A whip style antenna (Figure 86) provides
outstanding overall performance and stability.
A low-cost whip can be easily fabricated from
a wire or rod, but most designers opt for the
consistent performance and cosmetic appeal of
a professionally-made model. To meet this need,
Linx offers a wide variety of straight and reduced
height whip style antennas in permanent and
connectorized mounting styles.
Figure 86: Whip Style Antennas
The wavelength of the operational frequency determines
234
an antenna’s overall length. Since a full wavelength
L=
F
MHz
is often quite long, a partial ½- or ¼-wave antenna
Figure 87:
is normally employed. Its size and natural radiation
L = length in feet of
resistance make it well matched to Linx modules.
quarter-wave length
The proper length for a straight ¼-wave can be easily
F = operating frequency
in megahertz
determined using the formula in Figure 87. It is also
possible to reduce the overall height of the antenna by
using a helical winding. This reduces the antenna’s bandwidth but is a great
way to minimize the antenna’s physical size for compact applications. This
also means that the physical appearance is not always an indicator of the
antenna’s frequency.
Specialty Styles
Linx offers a wide variety of specialized antenna
styles (Figure 88). Many of these styles utilize helical
elements to reduce the overall antenna size while
maintaining reasonable performance. A helical
antenna’s bandwidth is often quite narrow and the
antenna can detune in proximity to other objects, so
care must be exercised in layout and placement.
– 68 –
Loop Style
A loop or trace style antenna is normally printed
directly on a product’s PCB (Figure 89). This
makes it the most cost-effective of antenna
styles. The element can be made self-resonant or
externally resonated with discrete components,
but its actual layout is usually product specific.
Despite the cost advantages, loop style antennas Figure 89: Loop or Trace Antenna
are generally inefficient and useful only for short
range applications. They are also very sensitive to changes in layout and
PCB dielectric, which can cause consistency issues during production.
In addition, printed styles are difficult to engineer, requiring the use of
expensive equipment including a network analyzer. An improperly designed
loop will have a high VSWR at the desired frequency which can cause
instability in the RF stage.
Linx offers low-cost planar (Figure 90) and chip
antennas that mount directly to a product’s PCB.
These tiny antennas do not require testing and
provide excellent performance despite their small
size. They offer a preferable alternative to the often
problematic “printed” antenna.
Figure 90: SP Series
“Splatch” Antenna
Figure 88: Specialty Style
Antennas
– 69 –
Regulatory Considerations
Note: Linx RF modules are designed as component devices that require
external components to function. The purchaser understands that
additional approvals may be required prior to the sale or operation of
the device, and agrees to utilize the component in keeping with all laws
governing its use in the country of operation.
When working with RF, a clear distinction must be made between what
is technically possible and what is legally acceptable in the country where
operation is intended. Many manufacturers have avoided incorporating RF
into their products as a result of uncertainty and even fear of the approval
and certification process. Here at Linx, our desire is not only to expedite the
design process, but also to assist you in achieving a clear idea of what is
involved in obtaining the necessary approvals to legally market a completed
product.
For information about regulatory approval, read AN-00142 on the Linx
website or call Linx. Linx designs products with worldwide regulatory
approval in mind.
In the United States, the approval process is actually quite straightforward.
The regulations governing RF devices and the enforcement of them are
the responsibility of the Federal Communications Commission (FCC). The
regulations are contained in Title 47 of the United States Code of Federal
Regulations (CFR). Title 47 is made up of numerous volumes; however,
all regulations applicable to this module are contained in Volume 0-19.
It is strongly recommended that a copy be obtained from the FCC’s
website, the Government Printing Office in Washington or from your local
government bookstore. Excerpts of applicable sections are included
with Linx evaluation kits or may be obtained from the Linx Technologies
website, www.linxtechnologies.com. In brief, these rules require that any
device that intentionally radiates RF energy be approved, that is, tested for
compliance and issued a unique identification number. This is a relatively
painless process. Final compliance testing is performed by one of the many
independent testing laboratories across the country. Many labs can also
provide other certifications that the product may require at the same time,
such as UL, CLASS A / B, etc. Once the completed product has passed,
an ID number is issued that is to be clearly placed on each product
manufactured.
– 70 –
Questions regarding interpretations of the Part 2 and Part 15 rules or the
measurement procedures used to test intentional radiators such as Linx RF
modules for compliance with the technical standards of Part 15 should be
addressed to:
Federal Communications Commission
Equipment Authorization Division
Customer Service Branch, MS 1300F2
7435 Oakland Mills Road
Columbia, MD, US 21046
Phone: + 1 301 725 585 | Fax: + 1 301 344 2050
Email: [email protected]
ETSI Secretaria
650, Route des Lucioles
06921 Sophia-Antipolis Cedex
FRANCE
Phone: +33 (0)4 92 94 42 00
Fax: +33 (0)4 93 65 47 16
International approvals are slightly more complex, although Linx modules
are designed to allow all international standards to be met. If the end
product is to be exported to other countries, contact Linx to determine the
specific suitability of the module to the application.
All Linx modules are designed with the approval process in mind and thus
much of the frustration that is typically experienced with a discrete design is
eliminated. Approval is still dependent on many factors, such as the choice
of antennas, correct use of the frequency selected and physical packaging.
While some extra cost and design effort are required to address these
issues, the additional usefulness and profitability added to a product by RF
makes the effort more than worthwhile.
– 71 –
Linx Technologies
159 Ort Lane
Merlin, OR, US 97532
Phone: +1 541 471 6256
Fax: +1 541 471 6251
www.linxtechnologies.com
Disclaimer
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reserve the right to make changes to our products without notice. The information contained in this Data Guide
is believed to be accurate as of the time of publication. Specifications are based on representative lot samples.
Values may vary from lot-to-lot and are not guaranteed. “Typical” parameters can and do vary over lots and
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