Download EUROCOM M770CU Service manual

Preface
Notebook Computer
X8100
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publication, except for copies kept by the user for backup purposes.
Preface
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Version 1.0
February 2010
Trademarks
Intel and Intel Core are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and/or registered trademarks of their respective companies.
II
Preface
About this Manual
This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the X8100 series
notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Preface
Appendix A, Part Lists
Appendix B, Schematic Diagrams
III
Preface
IMPORTANT SAFETY INSTRUCTIONS
Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to persons when using any electrical equipment:
Preface
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of electrical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit (Full Range AC/DC Adapter – AC Input 100 - 240V,
50 - 60Hz, DC Output 19V, 11.57A).
This Computer’s Optical Device is a Laser Class 1 Product
IV
Preface
Instructions for Care and Operation
The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1.
Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer
to any shock or vibration.
2.
Do not place anything heavy
on the computer.
Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not leave it in a place
where foreign matter or moisture may affect the system.
Don’t use or store the computer in a humid environment.
Do not place the computer on
any surface which will block
the vents.
Preface
Do not expose it to excessive
heat or direct sunlight.
3.
Do not place it on an unstable
surface.
Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power
until you properly shut down
all programs.
Do not turn off any peripheral
devices when the computer is
on.
Do not disassemble the computer by yourself.
Perform routine maintenance
on your computer.
V
Preface
4.
5.
Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage your data.
Take care when using peripheral devices.
Use only approved brands of
peripherals.
Unplug the power cord before
attaching peripheral devices.
Preface
Power Safety
The computer has specific power requirements:

VI
•
•
Power Safety
Warning
•
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.
•
•
•
Only use a power adapter approved for use with this computer.
Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
Before cleaning the computer, make sure it is disconnected from any external power supplies.
Do not plug in the power
cord if you are wet.
Do not use the power cord if
it is broken.
Do not place heavy objects
on the power cord.
Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
Preface
The following can also apply to any backup batteries you may have.
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.
Battery Level
Click the battery icon
in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
Preface
User’s Manual on CD
This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup program. It also describes the installation and operation of the utility programs provided with the notebook PC.
VIII
Preface
Contents
Introduction ..............................................1-1
Overview .........................................................................................1-1
System Specifications .....................................................................1-2
External Locator - Top View with LCD Panel Open ......................1-4
External Locator - Front & Right side Views .................................1-5
External Locator - Left Side & Rear View .....................................1-6
External Locator - Bottom View .....................................................1-7
Mainboard Overview - Top (Key Parts) .........................................1-8
Mainboard Overview - Bottom (Key Parts) ....................................1-9
Mainboard Overview - Top (Connectors) .....................................1-10
Mainboard Overview - Bottom (Connectors) ...............................1-11
Overview .........................................................................................2-1
Maintenance Tools ..........................................................................2-2
Connections .....................................................................................2-2
Maintenance Precautions .................................................................2-3
Disassembly Steps ...........................................................................2-4
Removing the Battery ......................................................................2-5
Removing the Optical (CD/DVD) Device ......................................2-6
Removing the Hard Disk Drive .......................................................2-7
Removing the System Memory (RAM) -1 ......................................2-9
Removing the System Memory (RAM) - 2 ...................................2-11
Removing and Installing the Processor .........................................2-14
Removing the VGA Card ..............................................................2-17
Installing the VGA Card ...............................................................2-19
Removing the Wireless LAN Module ...........................................2-20
Removing the Bluetooth Module ..................................................2-21
Removing the TV Tuner Card .......................................................2-22
Part Lists ..................................................A-1
Schematic Diagrams................................. B-1
System Block Diagram ...................................................................B-2
Processor 1/7 DMI, PEG ................................................................B-3
Processor 2/7 CLK, MISC ..............................................................B-4
Processor 3/7 DDR3I ......................................................................B-5
Processor 4/7 Power .......................................................................B-6
Processor 5/7 GFX PWR ................................................................B-7
Processor 6/7 GND, 7/7 RSVD ......................................................B-8
DDR3 SO-DIMM_0 REV ..............................................................B-9
DDR SO-DIMM_1 REV ..............................................................B-10
MXM 3.0 Master ..........................................................................B-11
MXM 3.0 Slave ............................................................................B-12
PCH 1/8 RTC, HDA, SATA .........................................................B-13
PCH 2/8 PCIE, SMBUS, CLK .....................................................B-14
PCH 3/8 DMI, PWRGD ...............................................................B-15
PCH 4/8 LVDS, DDI, GND .........................................................B-16
PCH 5/8 PCI, USB, NVRAM .......................................................B-17
PCH 6/8 GPIO, CPU ....................................................................B-18
PCH 7/8 PWR ...............................................................................B-19
PCH 8/8 PWR ...............................................................................B-20
CLK GEN, HDMI-In ....................................................................B-21
IX
Preface
Disassembly ...............................................2-1
Part List Illustration Location ........................................................ A-2
Top with Fingerprint ...................................................................... A-3
Top without Fingerprint ................................................................. A-4
Bottom ........................................................................................... A-5
LCD - CCFL Panel ........................................................................ A-6
LCD - LED Panel .......................................................................... A-7
Mainboard ...................................................................................... A-8
DVD Super Multi .......................................................................... A-9
DVD Super Multi - HLDS ........................................................... A-10
Preface
Preface
CRT, DVI ..................................................................................... B-22
Panel, Inverter, TPM .................................................................... B-23
HDMI Repeater, Fan Control ....................................................... B-24
HDMI Switch ............................................................................... B-25
ODD, CCD, BT, USB2.0 ............................................................. B-26
Codec, Subwoofer, DMIC ............................................................ B-27
Audio AMP .................................................................................. B-28
New Card, Mini Card ................................................................... B-29
LAN-RTL8111DL, RJ45 ............................................................. B-30
Card Reader, IEEE1394 ............................................................... B-31
KBC ITE IT8512-J ....................................................................... B-32
MB to Small B’d Connector A ..................................................... B-33
MB to Small B’d Connector B ..................................................... B-34
Power System ............................................................................... B-35
Power VCore ................................................................................ B-36
Power 1.1V_VTT, Screw Hole .................................................... B-37
Power 1.5V/0.75VS ...................................................................... B-38
Power 1.8VS/1.5VS ..................................................................... B-39
Power 3.3V/5V ............................................................................. B-40
Power Charger, DC-In .................................................................. B-41
Single HDD Board ....................................................................... B-42
Dual HDD Board .......................................................................... B-43
Audio Board ................................................................................. B-44
Power Button Board ..................................................................... B-45
Click & FP Board ......................................................................... B-46
Game Key Board .......................................................................... B-47
Front R Side LED Board .............................................................. B-48
Front L Side LED Board .............................................................. B-49
CIR Board .................................................................................... B-50
Finger Board ................................................................................. B-51
V1.0 Power on SEQ Diagram ...................................................... B-52
V1.0 Power_SEQ S3 .................................................................... B-53
X
V1.0 Power_SEQ S4 ....................................................................B-54
Power Block Diagram ...................................................................B-55
V2.0 Power_SEQ S3 ....................................................................B-56
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the X8100 series notebook computer. Information
about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information about drivers (e.g. VGA & audio) is also found in User’s Manual. That manual is shipped with the computer.
Operating systems (e.g. Windows 7, etc.) have their own manuals as do application software (e.g. word processing and
database programs). If you have questions about those programs, you should consult those manuals.
1.Introduction
The X8100 series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed description of
the upgrade procedures for each specific component. Please note the warning and safety information indicated by the
“” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1
Introduction
1.Introduction
System Specifications
Processor
Video Adapter Options
Keyboard & Pointing Device
Intel® Core i7-720QM Processor:
1.6GHz
45nm (45 Nanometer) Process Technology,
6M L3 Cache &
FSB 1333MHz - TDP 45W
rPGA988A Package
nVIDIA® GeForce GTX 280M SLI PCIe
Video Card
1GB GDDR3 Video RAM On Board
Supports PCIe * 8 (SLI - 2 * PCIe * 8)
Supports Microsoft DirectX® 10.0
Supports HDCP
Intel® Core i7-820QM Processor:
1.73GHz
45nm (45 Nanometer) Process Technology,
8M L3 Cache &
FSB 1333MHz - TDP 45W
rPGA988A Package
nVIDIA® GeForce GTX 285M SLI PCIe
Video Card
1GB GDDR3 Video RAM On Board
Supports PCIe * 8 (SLI - 2 * PCIe * 8)
Supports Microsoft DirectX® 11.0
Supports HDCP
Full Size Winkey Keyboard with Numeric
Keypad
Built-In TouchPad (with Multi Gesture
Functionality)
Eight Touch Sensor Instant Keys (Color,
CCD, Bluetooth, WLAN, Internet, Silent
Mode, Sound Effect, Mute)
Eight Gaming Keys G1 ~ G8
Intel® Core i7-920XM Processor:
2.00GHz
45nm (45 Nanometer) Process Technology,
8M L3 Cache & FSB 1333MHz - TDP 55W
rPGA988A Package
BIOS
Core Logic
18.4" HD+/ FHD (1920 * 1080) TFT LCD
Up to three (Factory Option) Changeable
2.5" 9.5 mm (h) SATA (Serial) Hard Disk
Drives supporting RAID level 0/1
One 12.7 mm Super Multi/Blu-Ray Combo/
Blu-Ray Writer SATA Optical Device Drive
(Factory Option)
Memory
Audio
DDRIII (DDR3) Dual Channels
Two 204 Pin SO-DIMM Sockets Supporting
DDRIII (DDR3) 1066MHz/1333MHz Memory
Modules
Memory Expandable up to 8GB
Compatible with 2GB or 4GB Modules
High Definition Audio
3D Enhanced Sound System
S/PDIF Digital Output
Built-In Microphone
5.1 Channel Speakers (with Subwoofer)
Dolby Home Theater Certified
Intel® PM55 Chipset
Display
1 - 2 System Specifications
One 32Mb Flash ROM
Phoenix™ BIOS
Storage
Card Reader
Embedded 7-in-1 Card Reader (MS/ MS Pro/
SD/ Mini SD/ MMC/ RS MMC/ MS Duo)
Note: MS Duo/ Mini SD/ RS MMC Cards
require a PC adapter
Slots
One ExpressCard/34 Slot
Two Mini Card Slots:
Slot 1 for PCIe WLAN Module
Slot 2 for PCIe TV Tuner Module
Introduction
Interface
Security
Four USB 2.0 Ports
One eSATA Port
One Mini-IEEE1394a Port
One DVI-Out Port (with CRT out)
One HDMI-Out (High-Definition Multimedia
Interface) Port (with HDCP Support)
One HDMI-In (High-Definition Multimedia
Interface) Port (with HDCP Support)
One RJ-45 LAN Jack
One Headphone/Speaker-Out Jack
One Microphone-In Jack
One Line-In Jack
One S/PDIF Out Jack
One DC-In Jack
One Consumer Infrared Port for TV Tuner
Remote Controller
One CATV-In Jack (for TV Tuner)
Security (Kensington® Type) Lock Slot
BIOS Password
Fingerprint Reader Module (Factory Option)
Communication
Full Range AC/DC Adapter – AC in 100 240V, 50 - 60Hz DC Output 19V, 11.57A (220
Watts)
Removable Polymer Smart Lithium-Ion
68.82Wh Main Battery
Bluetooth 2.1 + EDR (Enhanced Data Rate)
Module (Factory Option)
Intel® WiFi Link 5300 Series (3*3 - 802.11a/
g/n) Wireless LAN PCIe Interface Half MiniCard Module (Factory Option)
3rd Party 802.11b/g/n Wireless LAN PCIe
Interface Half Mini-Card Module (Factory
Option)
2.0M Pixel PC Video Camera Module
(Factory Option)
Mini-Card TV Tuner Module (Factory
Option)
Windows® 7
Note that the TV Tuner module (factory)
option in is supported by the Windows
Media Center software. Windows Media
Center is not included in Starter or Home
Basic versions of Windows 7.
Power Management
1.Introduction
Built-In 10/100/100 Base-TX Ethernet LAN
Operating System
Supports Wake on LAN
Supports Wake on USB
Power
Environmental Spec
Temperature
Operating:
5°C - 35°C
Non-Operating: -20°C - 60°C
Relative Humidity
Operating:
20% - 80%
Non-Operating: 10% - 90%
Physical Dimensions & Weight
439mm (w) * 299mm (d) * 44mm (h)
Around 5.6kg with Battery and ODD
System Specifications 1 - 3
Introduction
Figure 1
External Locator - Top View with LCD Panel Open
1.Introduction
Top View
1
1. Optional Built-In
PC Camera
2. LCD
3. LED Status
Indicators
4. Touch Sensor
Instant Keys
5. 8 * Gaming Keys
6. Keyboard
7. TouchPad and
Buttons
8. Fingerprint
Reader Module
(optional)
9. LED Power
Indicators
2
3
4
6
5
7
8
9
1 - 4 External Locator - Top View with LCD Panel Open
Introduction
External Locator - Front & Right side Views
Figure 2
Front Views
1
4
2
3
2
1. Color LEDs
2. Speakers
3. LED Power
Indicators
4. Consumer
Infrared
Transceiver
(enabled with
optional TV Tuner
only)
1
13
10
5
6
7
8
9
11
12
5. Headphone-In
Jack
6. Microphone-In
Jack
7. Line-In Jack
8. S/PDIF-Out Jack
9. Cable (CATV)
Antenna Jack*
10. Combined
eSATA/USB Port
11. USB 2.0 Port
12. Security Lock
Slot
13. Power Button
External Locator - Front & Right side Views 1 - 5
1.Introduction
Figure 3
Right Side Views
Introduction
External Locator - Left Side & Rear View
Figure 4
Left Side View
1.
2.
3.
4.
5.
1.Introduction
6.
7.
8.
9.
DVI-Out Port
2 * USB 2.0 Ports
RJ-45 LAN Jack
HDMI-Out Port
7-in-1 Card
Reader
ExpressCard Slot
HDMI-In Port
Mini-IEEE 1394
Port
Optional Device
Drive Bay
5
1
2
3
4
6
7
8
9
Figure 5
Rear View
10. Color LEDs
11. Speakers
12. DC-In Jack
10
1 - 6 External Locator - Left Side & Rear View
11
12
11
10
Introduction
External Locator - Bottom View
Figure 6
Bottom View
1
3
2
2
4
5

Overheating
To prevent your computer from overheating
make sure nothing
blocks the vent/fan intakes while the computer is in use.
External Locator - Bottom View 1 - 7
1.Introduction
2
1. Sub Woofer
2. Fan Outlet/Intake
3. Component Bay
Cover
4. Battery
(Secondary HDD
Bay - HDD3)
5. Primary HDD
Bay (HDD1 & 2)
Introduction
Figure 7
Mainboard Overview - Top (Key Parts)
1.Introduction
Mainboard Top
Key Parts
1. North Bridge
2. Memory Slots
DDR3 So-DIMM
3. Mini-Card
Connector (WLAN
Module)
4. Mini-Card
Connector (TV
Module)
3
2
1
1 - 8 Mainboard Overview - Top (Key Parts)
4
Introduction
Mainboard Overview - Bottom (Key Parts)
Figure 8
Mainboard Bottom
Key Parts
1. CPU Socket
2. VGA Socket
3. Memory Slots
DDR3 So-DIMM
2
2
1
1.Introduction
3
Mainboard Overview - Bottom (Key Parts) 1 - 9
Introduction
Figure 9
Mainboard Overview - Top (Connectors)
1.Introduction
Mainboard Top
Connectors
1. CCD Cable Connector
2. LCD Cable Connector
3. Side L Cable
Connector
4. Inverter Cable
Connector
5. LED Cable Connector
6. Subwoofer Connector
7. Power Button
Connector
8. Game-Key Cable
Connector
9. Bluetooth Module
Connector
10. LED Cable Connector
11. Touch Pad Connector
12. USB Cable Connector
13. Audio Cable
Connector
14. SW Connector
15. Fingerprint Connector
16. Keyboard Cable
Connector
17. Audio Cable
Connector
1
2
6
4 5
7
8
10
9
11
12
13
14
1 - 10 Mainboard Overview - Top (Connectors)
3
15
16
17
Introduction
Mainboard Overview - Bottom (Connectors)
Figure 10
Mainboard Bottom
Connectors
1. Battery
Connector
2. DC-In Jack
3. CRT Port
2
3
1.Introduction
1
Mainboard Overview - Bottom (Connectors) 1 - 11
1.Introduction
Introduction
1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the X8100 series notebook’s parts and subsystems.
When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a 
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the disassembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previous disassembly procedure. The amount of screws you should be left with will be listed here also.

Information
A box with a  will also provide any possible helpful information. A box with a  contains warnings.
An example of these types of boxes are shown in the sidebar.

Warning
Overview 2 - 1
2.Disassembly
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
2.Disassembly
•
•
•
•
•
•
M3 Philips-head screwdriver
M2.5 Philips-head screwdriver (magnetized)
M2 Philips-head screwdriver
Small flat-head screwdriver
Pair of needle-nose pliers
Anti-static wrist-strap
Connections
Connections within the computer are one of four types:
2 - 2 Overview
Locking collar sockets for ribbon connectors
To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replacing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors
To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors
To release these connectors, use a small pair of needle-nose pliers to gently lift the connector away from its socket. When replacing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets
To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or replacement job, take the following precautions:
Power Safety
Warning
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3
2.Disassembly
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
components could be damaged.
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight.
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage components and/or data. You should also monitor
the position of magnetized tools (i.e. screwdrivers).
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly
damaged.
5. Be careful with power. Avoid accidental shocks, discharges or explosions.
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies.
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire.
6. Peripherals – Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.

Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery:
1. Remove the battery
To remove the Wireless LAN Module:
page 2 - 5
To remove the Optical Device:
2.Disassembly
1. Remove the battery
2. Remove the Optical device
page 2 - 5
page 2 - 6
To remove the HDD:
1. Remove the battery
2. Remove the HDD
page 2 - 5
page 2 - 7
To remove the System Memory:
1. Remove the battery
2. Remove the System Memory
page 2 - 5
page 2 - 9
To remove and install the Processor:
1. Remove the battery
2. Remove the Processor
3. Install the Processor
page 2 - 5
page 2 - 14
page 2 - 16
To remove the VGA card:
1. Remove the battery
2. Remove the VGA card
2 - 4 Disassembly Steps
page 2 - 5
page 2 - 17
1. Remove the battery
2. Remove the System Memory
3. Remove the Wireless LAN
page 2 - 5
page 2 - 9
page 2 - 20
To remove the Bluetooth Module:
1. Remove the battery
2. Remove the System Memory
3. Remove the Bluetooth
page 2 - 5
page 2 - 9
page 2 - 21
To remove the TV Tuner Card:
1. Remove the battery
2. Remove the TV tuner card
page 2 - 5
page 2 - 22
Disassembly
Removing the Battery
Figure 1
If you are confident in undertaking upgrade procedures yourself, for safety reasons it is best to remove the battery.
a. Loosen screws.
b. Release the battery.
c. Lift the battery out of the
bay as indicated.
1. Turn the computer off, and turn it over.
2. Loosen screws 1 - 3 and carefully lift the battery 4 up (Figure b) .
3. Remove the battery from the battery bay.
a.
Battery Removal
c.
2.Disassembly
1
3
2
b.
4
4

4. Battery
• 3 Screws
Removing the Battery 2 - 5
Disassembly
Figure 2
Optical Device
Removal
1.
2.
3.
4.
5.
Turn off the computer, and turn it over and remove the battery (page 2 - 5).
Locate the hard disk bay cover and remove screws 1 & 2 , and remove the bay cover 3 .
Remove screw 4 .
Use the screwdriver to push the optical device 6 out of the computer at point 5 .
Reverse the process to install the new device.
a.
b.
2.Disassembly
a. Remove the screws.
b. Remove the cover.
c. Remove the screw and
push the optical device
out of the computer at
point 5.
Removing the Optical (CD/DVD) Device
1
2
3

c.

3. Hard Disk Bay Cover
6. Optical Device
Blu-Ray Device Bezel Removal
5
5
6
4
• 3 Screws
2 - 6 Removing the Optical (CD/DVD) Device
Note that some Blu-Ray modules (e.g. Pioneer) have a small piece of mylar inserted in
the left side (as viewed front on) of the bezel
cover; in order to prevent the bezel cover of
the module from being removed accidentally.
If you need to replace the bezel cover, you will
need to use a screwdriver to ease out and remove the mylar before attempting to remove
the bezel cover. You will need to re-insert the
mylar when replacing the bezel cover.
Disassembly
Removing the Hard Disk Drive
Figure 3
The hard disk drive is mounted in a removable case and can be taken out to accommodate other 2.5" SATA hard disk
drives with a height of 9.5mm (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in Chapter 4 of the User’s Manual) when setting up a new hard disk.
Turn off the computer, and turn it over and remove the battery (page 2 - 5).
Locate the hard disk bay cover and remove screws 1 & 2 .
Remove the bay cover 3 .
Remove screws 4 - 9 and pull the tab to disconnect the connector 10 from hard disk assembly.
Lift the hard disk assembly 11 out of the computer.
Remove screws 12 - 21 (depending on how many hard disks you have installed in the assembly).
Separate the hard disk board connector 22 from the case 23 .
Separate the hard disk(s) 24 from the case.
Reverse the process to install a new hard disk(s).
c.
a.
d.
19
4
1
5
6
18
16
11
2
10
b.
23
12
7
8
17
9
13
21
14
15
22
24
20
3

3. Hard Disk Bay Cover
11. Hard Disk Assembly
22. HDD connector
23. HDD case
24. HDD
• 18 Screws
3
Removing the Hard Disk Drive 2 - 7
2.Disassembly
a. Remove the screws.
b. Remove the cover
c. Remove the screws and
lift the hard disk assembly up out off the computer.
d. Remove the screws and
separate the HDD(s)
from the connector and
case.
Hard Disk Upgrade Process
1.
2.
3.
4.
5.
6.
7.
8.
9.
HDD Assembly
Removal
Disassembly
Removing the Hard Disk(s) in the Secondary HDD Bay
Figure 4
Secondary HDD
Assembly Removal
Turn off the computer, and turn it over and remove the battery.
The secondary hard disk bay is located under the battery compartment.
Remove screw 1 - 4 .
Slide the hard disk assembly in the direction of the arrow 5 .
Lift the hard disk assembly 6 out of the compartment.
Remove the screws 7 - 10 to release the hard disk from the case 11 .
7.
Reverse the process to install any new hard disk(s).
a.
2.Disassembly
a. Remove the screws and
slide the hard disk assembly in the direction of
the arrow.
b. Lift the hard disk assembly out off the computer.
c. Remove the screws to release the hard disk from
the case.
1.
2.
3.
4.
5.
6.
1
10
c.
b.
2
9
11
7
4
3
8
6
5

6. Hard Disk Assembly
11. Hard Disk Case
• 8 Screws
2 - 8 Removing the Hard Disk Drive
Disassembly
Removing the System Memory (RAM) -1
Figure 5
The computer has two memory sockets for 204 pin Small Outline Dual In-line Memory Modules (SO-DIMM) DDR III
(DDR3) supporting 1066/1333 MHz. The main memory can be expanded up to 8GB. The total memory size is automatically detected by the POST routine once you turn on your computer.
Memory Upgrade Process
1.
2.
3.
4.
5.
6.
Turn off the computer, and turn it over and remove the battery (page 2 - 5).
Locate the component bay cover and remove screws 1 - 5 .
Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
Carefully disconnect the fan cable 6 , and remove the bay cover 7 .
Loosen the CPU heat sink screws 8 - 11 .
Carefully (it may be hot) lift up the heat sink 12 off the computer.
a. Remove the screws.
b. Lift the cover and
disconnect the fan
cable.
c. Loosen the screws
and remove the heat
sink..
2.Disassembly
a.
RAM-1 Module
Removal
c.
11
9
8
10
3
1
2
4
5
b.
6
7
12

7. Bay Cover
12. Heat Sink
6
• 5 Screws
Removing the System Memory (RAM) -1 2 - 9
Disassembly
Figure 6
RAM-1 Module
Removal (cont’d.)
7. Gently pull the two release latches 13 & 14 on the sides of the memory socket in the direction indicated by
the arrows (Figure f).
8. The RAM module 15 will pop-up (Figure g), and you can then remove it.
d.
e.
d. Pull the release
latch.
e. Remove the module.
f Replace the heatsink
and
tighten
the
screws.
Single Memory Module
Installation
13
15
2.Disassembly
14

Contact Warning
Be careful not to touch
the metal pins on the
module’s
connecting
edge. Even the cleanest hands have oils
which can attract particles, and degrade the
module’s performance.

If your computer has a single memory module, then insert the module
into the Channel 0 (JDIMM1)
socket as shown in Figure 6 g.
9. Pull the latches to release the second module if necessary.
10. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
11. The module’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the socket
as it will go. DO NOT FORCE the module; it should fit without much pressure.
12. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
13. Replace the heat sink (make sure you tighten the screws in the order indicated on the label as below).
f.
16

15. RAM Module
16. Heat Sink
17
19
20
18
14. Replace the component bay cover and make sure you reconnect the fan cable (see Figure 6 on page 2 - 10).
15. Replace all the component bay cover screws.
16. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
2 - 10 Removing the System Memory (RAM) -1
Disassembly
Removing the System Memory (RAM) - 2
Figure 7
The computer has two memory sockets for 204 pin Small Outline Dual In-line Memory Modules (SO-DIMM) DDR III
(DDR3) supporting 1066/1333 MHz. The main memory can be expanded up to 4GB. The SO-DIMM modules supported
are 1024MB and 2048MB DDR Modules. The total memory size is automatically detected by the POST routine once
you turn on your computer.
Memory Upgrade Process
c.
a.
1
2
a. Remove the screws
from the bottom of
the computer.
b. Turn the computer
over, open the lid/
LCD and unsnap the
LED cover at point 3.
c. Lift the LED cover
module and disconnect the cable.
d. Remove the screws
from the keyboard.
5
4
b.
d.
3
6
7
8
9
10

• 7 Screws
Removing the System Memory (RAM) - 2 2 - 11
2.Disassembly
1. Turn off the computer, and turn it over and remove the battery (page 2 - 5).
2. Remove screws 1 & 2 from the bottom of the computer.
3. Turn the computer over, open the Lid/LCD, and carefully (a cable is connected to the underside of the LED cover
module) unsnap up the LED cover module from point 3 on the right.
4. Lift up the LED cover module 4 and disconnect the cable 5 .
5. Remove screws 6 - 10 from the keyboard.
RAM-2 Module
Removal
Disassembly
Figure 8
2.Disassembly
RAM-2 Module
Removal (cont’d.)
e. Disconnect the cable
from the locking collar.
f. Remove the keyboard.
g. Remove screws and
keyboard plate.
g Pull the release
latch(es).
i. Remove the module(s).
6.
7.
8.
9.
Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable.
Disconnect the keyboard ribbon cable 11 from the locking collar socket 12 .
Remove the keyboard 13 .
Remove screws 14 - 17 from the keyboard shielding plate 18 and remove the keyboard shielding plate.
f.
e.
g.
14
16
17
11
12
15
13
18

Contact Warning
Be careful not to touch
the metal pins on the
module’s
connecting
edge. Even the cleanest hands have oils
which can attract particles, and degrade the
module’s performance.

13. Keyboard
18. Keyboard Shielding Plate
21. RAM Module(s)
• 4 Screws
10. Gently pull the two release latches 19 & 20 on the sides of the memory socket in the direction indicated by
the arrows (Figure h).
11. The RAM module 21 will pop-up (Figure i), and you can then remove it.
h.
i.

Single Memory Module
Installation
19
21
20
If your computer has a single memory module, then insert the module
into the Channel 0 (JDIMM1)
socket as shown in Figure 6 g.
12. Pull the latches to release the second module if necessary.
13. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
14. The module’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the socket
as it will go. DO NOT FORCE the module; it should fit without much pressure.
15. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
2 - 12 Removing the System Memory (RAM) - 2
Disassembly
16. Replace the shielding plate, keyboard and screws (make sure to reconnect the keyboard cable).
17. Snap the LED cover module down at the top fo the module at point 22 & 23 .
j.
22
Figure 9
RAM-2 Module
Removal (cont’d.)
j. Snap down the LED
cover at point 22 &
23.
k. Push the LED cover
on the left side at
point 24 and the slide
toward the right to
secure it in place.
23
k.
24
19. Replace the scews on the bottom of the computer ().
20. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
Removing the System Memory (RAM) - 2 2 - 13
2.Disassembly
18. Push the LED cover module down on the left side at point 24 , and then slide the module to the right (as illustrated)
and snap down to secure it in place.
Disassembly
Figure 10
Processor Removal
a. Remove the screws.
b. Lift the cover and disconnect the fan cable.
c. Loosen the screws and
remove the heat sink..
Removing and Installing the Processor
Processor Removal Procedure
1.
2.
3.
4.
5.
6.
Turn off the computer, and turn it over, remove the battery (page 2 - 5).
Locate the component bay cover and remove screws 1 - 5 .
Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
Carefully disconnect the fan cable 6 , and remove the bay cover 7 .
Loosen the CPU heat sink screws 8 - 11 .
Carefully (it may be hot) lift up the heat sink 12 off the computer.
2.Disassembly
a.
c.


7. Bay Cover
12. CPU Heat Sink
9
8
10
3
Caution
The heat sink, and CPU
area in general, contains parts which are
subject to high temperatures. Allow the area
time to cool before removing these parts.
11
1
2
4
5
b.
6
7
12
6
• 5 Screws
2 - 14 Removing and Installing the Processor
Disassembly
7.
8.
9.
10.
11.
Turn the release latch 13 towards the unlock symbol
, to release the CPU (Figure 11a).
Carefully (it may be hot) lift the CPU 14 up out of the socket (Figure 11b).
See page 2 - 16 for information on inserting a new CPU.
Reverse the process to install a new CPU.
When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
Figure 11
Processor Removal
(cont’d)
d. Turn the release latch to
unlock the CPU.
e. Lift the CPU out of the
socket.
d.
13
Unlock
2.Disassembly
13
Lock
e.
14

Caution
The heat sink, and CPU area in
general, contains parts which are
subject to high temperatures. Allow the area time to cool before removing these parts.

14. CPU
Removing and Installing the Processor 2 - 15
Disassembly
Figure 12
Processor
Installation
a. Insert the CPU.
b. Turn the release latch towards the lock symbol.
c. Remove the sticker from
the heat sink and insert
the heat sink.
d. Tighten the screws.
Processor Installation Procedure
1. Insert the CPU A , pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!), and turn
the release latch B towards the lock symbol
(Figure 12b).
2. Remove the sticker C (Figure 12c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 12c.
4. Tighten the CPU heat sink screws 1 , 2 , 3 , & 4 (Figure 12d).
5. Replace the component bay cover and tighten the screws (page 2 - 14).
a.
c.
C
A
2.Disassembly
D
b.

C
d.
1
3
4
2
B
A. CPU
D. Heat Sink
• 4 Screws
2 - 16 Removing and Installing the Processor
Disassembly
Removing the VGA Card
Figure 13
1.
2.
3.
4.
5.
Turn off the computer, and turn it over and remove the battery (page 2 - 5).
Locate the component bay cover and remove screws 1 - 5
Carefully (a fan and cable are attached to the under side of the cover) lift up the bay cover.
Carefully disconnect the fan cable 6 , and remove the bay cover 7 .
Remove screws 8 - 10 (two video cards are pictured here) from the video card fan(s) and disconnect the fan
cable(s) 11 (if two cards are present).
6. Remove the VGA card fan 12 .
a.
VGA Card Removal
a. Remove the screws.
b. Remove the cover and
disconnect the cable(s).
c. Remove the screws and
release the VGA card
fan.
c.
2
4
3
5
10
2.Disassembly
1
10
11
11
9
8
8
9
b.
6
7
12
12

6
7. Bay Cover
12. VGA card fan
• 11 Screws
VGA Card Fans
Removing the VGA Card 2 - 17
Disassembly
Figure 14
VGA Card Removal
(cont’d.)
d. Remove the screws.
e. Remove the VGA heatsink.
f. Remove the VGA module.
7. Remove screws 13 - 16 from the heatsink in the order indicated on the label (two video cards are pictured
here).
8. Grip the handle 17 and carefully remove the heatsink 18 .
9. Remove screws 19 - 20 from the video card.
10. Carefully remove the VGA card module 21 from the mainboard.
d.
e.
14
16
14
16
18
2.Disassembly
15
13
15
17
18
13
17
f.
21
21

18. VGA Card Heatsink
21. VGA Card Module
• 16 Screws
11. Reverse the process to install a new VGA card modules.
2 - 18 Removing the VGA Card
19
20 19
20
Disassembly
Installing the VGA Card
Figure 15
VGA Card
Installation
a. Carefully Insert the VGA
Card.
2.Disassembly
1. Prepare to fit the VGA card 22 into the slot by holding it at about a 30° angle.
2. The card needs to be fully into the slot, and the VGA card and socket have a guide-key and pin which align to allow
the card to fit securely.
3. Fit the connectors firmly into the socket, straight and evenly.
4. DO NOT attempt to push one end of the card in ahead of the other.
5. The card’s pin alignment will allow it to only fit one way. Make sure the module is seated as far into the socket
as it will go (none of the gold colored contact should be showing). DO NOT FORCE the card; it should fit without
much pressure.
6. Secure the card with screws 19 - 21 (Figure 14e on page 2 - 18).
7. Place the heatsink 18 back on the card, and secure the screws in the order indicated in Figure 14e on page 2 18.
8. Attach the VGA card fan and secure with the screws as indicated in Figure 13 on page 2 - 17.
9. Reinsert the component bay cover, and secure with the screws as indicated in Figure 13 on page 2 - 17.
a.
22

22. VGA card Module
Removing the VGA Card 2 - 19
Disassembly
Figure 16
Removing the Wireless LAN Module
Wireless LAN
Module Removal
1. Turn off the computer, and turn it over, remove the battery (page 2 - 5), keyboard and keyboard shielding plate
(page 2 - 9).
2. The Wireless LAN Module will be visible at point 1 .
a. Locate the WLAN mod3. Remove the screw 2 and carefully disconnect cables 3 - 4 .
ule.
b. Remove the screw and 4. The Wireless LAN Module 5 (Figure c) will pop-up, and you can remove it.
disconnect the cables.
c. Remove the WLAN
module.
a.
2.Disassembly
1
Note: Make sure you
reconnect the antenna
cables.
c.
b.
5

5. Wireless LAN Module
• 1 Screw
2 - 20 Removing the Wireless LAN Module
2
3
4
Disassembly
Removing the Bluetooth Module
Figure 17
1. Turn off the computer, and turn it over, remove the battery (page 2 - 5), keyboard and keyboard shielding plate
(page 2 - 9).
2. The Bluetooth module is visible at point 1 .
3. Carefully disconnect cables 2 & 3 and remove the screw 4 .
4. Lift the Bluetooth module 5 off the computer.
a.
c.
Bluetooth Module
Removal
a. Locate the module.
b. Disconnect the cables
and remove the screw.
c. Remove the Bluetooth
module.
1
b.
5
2
4
3

5. Bluetooth Module
• 1 Screw
Removing the Bluetooth Module 2 - 21
2.Disassembly
Note: Make sure you
reconnect the antenna
cables to the socket
(Figure a).
Disassembly
Figure 18
TV Tuner Card
Removal
a. Locate the module.
b. Remove the screws and
disconnect the cable.
c. The TV tuner card will
pop up and remove it.
Removing the TV Tuner Card
1. Turn off the computer, and turn it over, remove the battery (page 2 - 5), keyboard and keyboard shielding plate
(page 2 - 9).
2. The TV tuner card is visible at point 1 .
3. Remove the screw 2 from the TV tuner module and disconnect the cable 3 .
4. The TV tuner card 4 will pop-up and and you can remove it.
.
a.
b.
2.Disassembly
1
3
2
c.

4. TV tuner card
• 1 Screw
2 - 22 Removing the TV Tuner Card
4
Part Lists
Appendix A: Part Lists
This appendix breaks down the X8100 series notebook’s construction into a series of illustrations. The component part
numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
A.Part Lists
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part Lists
Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A- 1
Part List Illustration
Location
A.Part Lists
Parts
A - 2 Part List Illustration Location
X8100
Top with Fingerprint
page A - 3
Top without Fingerprint
page A - 4
Bottom
page A - 5
LCD - CCFL Panel
page A - 6
LCD - LED Panel
page A - 7
Mainboard
page A - 8
DVD Super Multi
page A - 9
DVD Super Multi - HLDS
page A - 10
Part Lists
Top with Fingerprint
Figure A - 1
無鉛
無鉛
無鉛
Top with
Fingerprint
無鉛
無鉛
無鉛
無鉛
(非耐落)
無鉛
無鉛
無鉛
黑色
(無鉛)
無鉛
無鉛
無鉛
無鉛
(無鉛)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
頭厚
無鉛
無鉛
無鉛
無鉛
Top with Fingerprint A - 3
A.Part Lists
無鉛
Part Lists
A.Part Lists
Top without Fingerprint
Figure A - 2
無鉛
Top without
Fingerprint
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
(非耐落)
無鉛
Ω 鴻立
藍天7 互億
(無鉛)
無鉛
無鉛
無鉛
無鉛
黑色
(無鉛)
無鉛
無鉛
無鉛
無鉛
(無鉛)
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
頭厚
無鉛
無鉛
無鉛
無鉛
A - 4 Top without Fingerprint
Part Lists
Bottom
Figure A - 3
無鉛
Ω
鴻立
無鉛
無鉛
(非耐落)
無鉛
無鉛
無鉛
無鉛
精乘
無鉛
無鉛
無鉛
無鉛
Ω
鴻立
無鉛
無鉛
無鉛
無鉛
精乘
無鉛
鐵網封精油 無鉛
鐵網封精油 無鉛
信越
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
Bottom A - 5
A.Part Lists
Bottom
無鉛
Part Lists
LCD - CCFL Panel
A.Part Lists
Figure A - 4
LCD - CCFL Panel
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
度
無鉛
無鉛
(非耐落)
無鉛
無鉛
無鉛
無鉛
度
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
定位柱加高
中性
無鉛
無鉛
無鉛
無鉛
A - 6 LCD - CCFL Panel
Part Lists
LCD - LED Panel
Figure A - 5
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
(非耐落)
無鉛
無鉛
無鉛
華力
醋酸布包覆
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
定位柱加高
中性
無鉛
無鉛
無鉛
無鉛
LCD - LED Panel A - 7
A.Part Lists
LCD - LED Panel
Part Lists
Mainboard
A.Part Lists
Figure A - 6
Mainboard
無鉛
無鉛
無鉛
無鉛
無鉛
(半卡)
海華
無鉛
無鉛
展達
電容變更無鉛
增加
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
A - 8 Mainboard
Part Lists
DVD Super Multi
Figure A - 7
無鉛
無鉛
已內縮
無鉛
內縮
無鉛
無鉛
DVD Super Multi A - 9
A.Part Lists
DVD Super Multi
Part Lists
DVD Super Multi - HLDS
A.Part Lists
Figure A - 8
DVD Super Multi HLDS
無鉛
無鉛
無鉛
無鉛
無鉛
無鉛
A - 10 DVD Super Multi - HLDS
Schematic Diagrams
Appendix B: Schematic Diagrams
This appendix has circuit diagrams of the X8100 notebook’s PCB’s. The following table indicates where to find the appropriate schematic diagram.
Diagram - Page
Diagram - Page
Diagram - Page
PCH 7/8 PWR - Page B - 19
Power VCore - Page B - 36
Processor 1/7 DMI, PEG - Page B - 3
PCH 8/8 PWR - Page B - 20
Power 1.1V_VTT, Screw Hole - Page B - 37
Processor 2/7 CLK, MISC - Page B - 4
CLK GEN, HDMI-In - Page B - 21
Power 1.5V/0.75VS - Page B - 38
Processor 3/7 DDR3I - Page B - 5
CRT, DVI - Page B - 22
Power 1.8VS/1.5VS - Page B - 39
Processor 4/7 Power - Page B - 6
Panel, Inverter, TPM - Page B - 23
Power 3.3V/5V - Page B - 40
Processor 5/7 GFX PWR - Page B - 7
HDMI Repeater, Fan Control - Page B - 24
Power Charger, DC-In - Page B - 41
Processor 6/7 GND, 7/7 RSVD - Page B - 8
HDMI Switch - Page B - 25
Single HDD Board - Page B - 42
DDR3 SO-DIMM_0 REV - Page B - 9
ODD, CCD, BT, USB2.0 - Page B - 26
Dual HDD Board - Page B - 43
DDR SO-DIMM_1 REV - Page B - 10
Codec, Subwoofer, DMIC - Page B - 27
Audio Board - Page B - 44
MXM 3.0 Master - Page B - 11
Audio AMP - Page B - 28
Power Button Board - Page B - 45
MXM 3.0 Slave - Page B - 12
New Card, Mini Card - Page B - 29
Click & FP Board - Page B - 46
PCH 1/8 RTC, HDA, SATA - Page B - 13
LAN-RTL8111DL, RJ45 - Page B - 30
Game Key Board - Page B - 47
PCH 2/8 PCIE, SMBUS, CLK - Page B - 14
Card Reader, IEEE1394 - Page B - 31
Front R Side LED Board - Page B - 48
PCH 3/8 DMI, PWRGD - Page B - 15
KBC ITE IT8512-J - Page B - 32
Front L Side LED Board - Page B - 49
PCH 4/8 LVDS, DDI, GND - Page B - 16
MB to Small B’d Connector A - Page B - 33
CIR Board - Page B - 50
PCH 5/8 PCI, USB, NVRAM - Page B - 17
MB to Small B’d Connector B - Page B - 34
Finger Board - Page B - 51
PCH 6/8 GPIO, CPU - Page B - 18
Power System - Page B - 35
V1.0 Power on SEQ Diagram - Page B - 52
Table B - 1
Schematic
Diagrams
B.Schematic Diagrams
System Block Diagram - Page B - 2

Version Note
The schematic diagrams in this chapter
are based upon version 6-7P-X810B-007.
If your mainboard (or
other boards) are a later version, please
check with the Service
Center for updated diagrams (if required).
B - 1
Schematic Diagrams
System Block Diagram
SY ST EM P OW ER
14.318 MHz
PO WE R VC OR E
PO WE R 1. 1V S_ VT T
DDR3 SDRAM SOCKET
PO WE R 1. 5V /0 .7 5V
MX M- II I VG A
ma st er
HDMI SW
PO WE R 3. 3V /5 V
HDMI
B.Schematic Diagrams
PO WE R CH AR GE R/ DC IN
QUAD CORE
PROCESSOR
MX M- II I VG A
sl av e
SO-DIMM0
SO-DIMM1
PCIEx16
DDR3 1333MHz
BACK L SIDE LED
4 IN 1
SYSTEM SMBUS
LOGO LED
4 IN 1
SUBWOOFER
DMI*4
TP A6 21 1
<= 8"
LVDS/INV
Sheet 1 of 55
System Block
Diagram
4 IN 1
FRONT L SIDE LED
rPGA 988
PCIEx8
DVI/RGB
TOUCH PAD LED
FRONT R SIDE LED
Clarksfield
PO WE R 1. 8V S, 1 .5 VS
Power Button BOARD
CLEVO X8100 System Block Diagram
Cl oc k Ge ne ra to r
SL G8 SP 58 5V
AUDIO BOARD
PCIEx8
CENTER
TP A6 21 1
32.768KHz
25MHZ
B RA ID WO OD
TOUCH SENSOR BOARD
Click BOARD
BI OS
SP I
4IN 1
CI R
S PI
EC
I T8 51 2E /J X
Internal
Keyboard
EC SMBUS
THERMAL
SENSOR
Game Key
BOARD
MXM1
LPC
Redriv e
SA TA
HD D3
SA TA
HD D2
S AT A
H DD 1
B - 2 System Block Diagram
HDDx1
BOARD
24MHz
T PA 60 17
USB3
MIC
IN
e -S AT A
HP
OUT
Red rive
100MHz
LAN
M in i CA RD
S OC KE T
REALTEK
RTL8111DL
SMART
BATTERY
CARD
READER
7 IN 1
USB7
25
M Hz
IEEE
1394
NEW
CARD
USB5
W LA N
RJ-45
MM C/ SD /M S/ MS P ro
CCD
USB8
HDDx2 BOARD
HDA
AMPLIFY
ALAZIA
CODEC
JMB380 24.576MHz
USB2.0
Red rive
SPDIF
OUT
USB2
PCIE
SATA I/II 3.0Gb/s
Red rive
AN T.
TP A6 01 7
Di gi ta l
MI C
33MHz
AD M1 03 2
LINE
IN
AL C8 88
32.768KHz
MXM2
REAR
25x27mm
1071 Ball
FCBGA
EC SMBUS
TOUCH
PAD
Ibex Peak-M
Platform
Controller
Hub (PCH)
PM55
BT
PORT2
PORT3
M in i CA RD
S OC KE T
USB12
USB0
USB1
USB6
Fi ng er
Pr in te r
USB10
TV
SA TA
OD D
SATA-II 3G/S
Finger
Printer
Module
6- 7P- X810B-004: PCB11? 1? ? :6-7 1-X8 100-D03/6-7 1-X8108-D03/6- 71-X810J-D02/6- 71-X810K- D02/6 -71- M9805- D03A/6- 71-M 9807- D03/6 -71- M9804- D03A/6- 71-M 980W-D03A/6-71- M980 F-D0 2/6-71- M98 0H-D03/6- 71-M 9802- D03A
Schematic Diagrams
Processor 1/7 DMI, PEG
P E G _R X N [ 0 . . 7]
P E G _R X N [ 0 . . 7 ]
P E G _R X P [ 0 . . 7 ]
PROCESSOR
1/7
( DMI,PEG,FDI )
10
P E G _R X P [ 0 . . 7 ] 1 0
P E G _T X N [ 0 . . 7 ]
P E G _T X N [ 0 . . 7 ] 1 0
P E G _T X P [ 0 . . 7 ]
P E G _T X P [ 0 . . 7 ]
P E G _R X N [ 8 . . 15 ]
10
P E G _R X N [ 8 . . 1 5 ] 1 1
P E G _R X P [ 8 . . 1 5 ]
P E G _R X P [ 8 . . 1 5 ] 1 1
P E G _T X N [ 8 . . 1 5]
P E G _T X N [ 8 . . 1 5]
P E G _T X P [ 8 . . 1 5 ]
U3 8 A
Thermal Sensor
D
D
D
D
MI _ R
MI _ R
MI _ R
MI _ R
XN
XN
XN
XN
0
1
2
3
14
14
14
14
D
D
D
D
MI _ R
MI _ R
MI _ R
MI _ R
XP
XP
XP
XP
0
1
2
3
D 25
F 24
E 23
G 23
R 3 43
1 0 K_ 0 4
R3 4 4
* 1 0m i l _ 04
U 37
D G ND
SD ATA
SC L K
4
6
T H E R M _ A L E R T#
C
R3 4 5
A
*0 _ 0 4
D3 6
31
P M _ E X T T S # _E C 3
R B 7 5 1 V -4 0
22
21
19
18
21
19
21
18
D
C
D
C
G
E
F
G
22
21
20
18
22
20
20
19
C
T HE RM
AL ER T
E
D
D
D
G
E
F
G
DM I_ RX # [0 ]
DM I_ RX # [1 ]
DM I_ RX # [2 ]
DM I_ RX # [3 ]
DM
DM
DM
DM
I_ RX [0 ]
I_ RX [1 ]
I_ RX [2 ]
I_ RX [3 ]
DM
DM
DM
DM
I _ T X# [ 0 ]
I _ T X# [ 1 ]
I _ T X# [ 2 ]
I _ T X# [ 3 ]
DM
DM
DM
DM
I _ T X[
I _ T X[
I _ T X[
I _ T X[
F DI
F DI
F DI
F DI
F DI
F DI
F DI
F DI
_T X # [ 0 ]
_T X # [ 1 ]
_T X # [ 2 ]
_T X # [ 3 ]
_T X # [ 4 ]
_T X # [ 5 ]
_T X # [ 6 ]
_T X # [ 7 ]
F DI
F DI
F DI
F DI
F DI
F DI
F DI
F DI
_T X [ 0 ]
_T X [ 1 ]
_T X [ 2 ]
_T X [ 3 ]
_T X [ 4 ]
_T X [ 5 ]
_T X [ 6 ]
_T X [ 7 ]
B
3
5
E
Q 36
2N 3 9 04
7
8
S MD _T H E R M_ 1 1 1 , 1 3 , 31
S MC _T H E R M_ 1 1 1 , 1 3 , 31
A D M 10 3 2 A R M
It applies to Auburndale and Clarksfield discrete graphic designs.
If discrete graphic chip is used for Auburndale, VAXG (GFX core) rail can be connected
to GND if motherboard only supports discrete graphics and also in a common
motherboard design if GFX VR is not stuffed. On the other hand, if the VR is stuffed,
VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from
floating).
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Auburndale.
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and
FDI_INT signals should be tied to GND (through 1K ? % resistors) in the common
R 3 46
4
3
2
1
1 K_ 0 4
5
6
7
8
F 17
E 17
C 17
F 18
D 17
F D I _F S Y N C [ 0]
F D I _F S Y N C [ 1]
F D I _I N T
F D I _L S Y N C [ 0 ]
F D I _L S Y N C [ 1 ]
RN 1 6
1 K _ 8 P 4 R _0 4
motherboard design case. Please not that if these signals are left floating, there are no
functional impacts but a small amount of power (~15 mW) maybe wasted. VAXG_SENSE
and VSSAXG_SENSE on Auburndale can be left as no connect.
P E G _ RX [ 0 ]
P E G _ RX [ 1 ]
P E G _ RX [ 2 ]
P E G _ RX [ 3 ]
P E G _ RX [ 4 ]
P E G _ RX [ 5 ]
P E G _ RX [ 6 ]
P E G _ RX [ 7 ]
P E G _ RX [ 8 ]
P E G _ RX [ 9 ]
PE G _ RX[1 0 ]
PE G _ RX[1 1 ]
PE G _ RX[1 2 ]
PE G _ RX[1 3 ]
PE G _ RX[1 4 ]
PE G _ RX[1 5 ]
P E G _T X # [ 0 ]
P E G _T X # [ 1 ]
P E G _T X # [ 2 ]
P E G _T X # [ 3 ]
P E G _T X # [ 4 ]
P E G _T X # [ 5 ]
P E G _T X # [ 6 ]
P E G _T X # [ 7 ]
P E G _T X # [ 8 ]
P E G _T X # [ 9 ]
P E G _ TX # [ 1 0 ]
P E G _ TX # [ 1 1 ]
P E G _ TX # [ 1 2 ]
P E G _ TX # [ 1 3 ]
P E G _ TX # [ 1 4 ]
P E G _ TX # [ 1 5 ]
P E G_ T X [ 0 ]
P E G_ T X [ 1 ]
P E G_ T X [ 2 ]
P E G_ T X [ 3 ]
P E G_ T X [ 4 ]
P E G_ T X [ 5 ]
P E G_ T X [ 6 ]
P E G_ T X [ 7 ]
P E G_ T X [ 8 ]
P E G_ T X [ 9 ]
P E G _T X [ 1 0 ]
P E G _T X [ 1 1 ]
P E G _T X [ 1 2 ]
P E G _T X [ 1 3 ]
P E G _T X [ 1 4 ]
P E G _T X [ 1 5 ]
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Auburndale
directly if motherboard only supports discrete graphics. In a common motherboard
design, these pins are driven via PCH (even if Graphics is disabled by BIOS) thus no
external termination is required.
Analog Thermal Sensor
PE G _ RX# [0 ]
PE G _ RX# [1 ]
PE G _ RX# [2 ]
PE G _ RX# [3 ]
PE G _ RX# [4 ]
PE G _ RX# [5 ]
PE G _ RX# [6 ]
PE G _ RX# [7 ]
PE G _ RX# [8 ]
PE G _ RX# [9 ]
P E G_ R X # [ 1 0 ]
P E G_ R X # [ 1 1 ]
P E G_ R X # [ 1 2 ]
P E G_ R X # [ 1 3 ]
P E G_ R X # [ 1 4 ]
P E G_ R X # [ 1 5 ]
0]
1]
2]
3]
Intel(R) FDI
VD D
D +
24
23
23
22
D 24
G 24
F 23
H 23
3. 3V
1
2
B
D
B
A
R ev _ 3. 0
20 mil
B 26
A 26
B 27
A 25
P E G _ I R C O MP _ R
EXP_ R BIAS
K 35
J34
J33
G 35
G 32
F 34
F 31
D 35
E 33
C 33
D 32
B 32
C 31
B 28
B 30
A 31
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
_ RX N
J35
H 34
H 33
F 35
G 33
E 34
F 32
D 34
F 33
B 33
D 31
A 32
C 30
A 28
B 29
A 30
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
_ RX P 0
_ RX P 1
_ RX P 2
_ RX P 3
_ RX P 4
_ RX P 5
_ RX P 6
_ RX P 7
_ RX P 8
_ RX P 9
_ RX P 1 0
_ RX P 1 1
_ RX P 1 2
_ RX P 1 3
_ RX P 1 4
_ RX P 1 5
R3 4 9
4 9 . 9_ 1 % _ 0 4
Sheet 2 of 55
Processor 1/7
DMI, PEG
R3 5 0
7 5 0_ 1 % _ 0 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L33
M 35
M 33
M 30
L31
K 32
M 29
J31
K 29
H 30
H 29
F 29
E 28
D 29
D 27
C 26
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
_T X # _ 0
_T X # _ 1
_T X # _ 2
_T X # _ 3
_T X # _ 4
_T X # _ 5
_T X # _ 6
_T X # _ 7
_T X # _ 8
_T X # _ 9
_T X # _ 1 0
_T X # _ 1 1
_T X # _ 1 2
_T X # _ 1 3
_T X # _ 1 4
_T X # _ 1 5
C1 1 2
C1 0 3
C9 9
C9 6
C9 3
C8 9
C8 6
C8 3
C6 7
C6 0
C5 4
C5 0
C4 4
C3 9
C4 6
C4 0
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
G_ T X N 0
G_ T X N 1
G_ T X N 2
G_ T X N 3
G_ T X N 4
G_ T X N 5
G_ T X N 6
G_ T X N 7
G_ T X N 8
G_ T X N 9
G_ T X N 1 0
G_ T X N 1 1
G_ T X N 1 2
G_ T X N 1 3
G_ T X N 1 4
G_ T X N 1 5
L34
M 34
M 32
L30
M 31
K 31
M 28
H 31
K 28
G 30
G 29
F 28
E 27
D 28
C 27
C 25
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
_T X _ 0
_T X _ 1
_T X _ 2
_T X _ 3
_T X _ 4
_T X _ 5
_T X _ 6
_T X _ 7
_T X _ 8
_T X _ 9
_T X _ 1 0
_T X _ 1 1
_T X _ 1 2
_T X _ 1 3
_T X _ 1 4
_T X _ 1 5
C1 1 7
C1 1 1
C1 0 5
C1 0 0
C9 7
C9 4
C9 1
C8 7
C7 0
C6 4
C5 7
C5 3
C4 8
C4 2
C5 2
C4 3
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
0 . 1 u _ 10 V _ X 7 R
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
_0 4
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
PE
G_ T X P 0
G_ T X P 1
G_ T X P 2
G_ T X P 3
G_ T X P 4
G_ T X P 5
G_ T X P 6
G_ T X P 7
G_ T X P 8
G_ T X P 9
G_ T X P 1 0
G_ T X P 1 1
G_ T X P 1 2
G_ T X P 1 3
G_ T X P 1 4
G_ T X P 1 5
B.Schematic Diagrams
3 .3 V
14
14
14
14
24
23
22
21
DMI
1 4 D M I _ T XP 0
1 4 D M I _ T XP 1
1 4 D M I _ T XP 2
1 4 D M I _ T XP 3
A
C
B
A
PCI EXPRESS -- GRAPHICS
1 4 D M I _ T XN 0
1 4 D M I _ T XN 1
1 4 D M I _ T XN 2
1 4 D M I _ T XN 3
P E G_ I C OM P I
P E G _I C O MP O
P E G_ R C O MP O
PE G _ RB IA S
11
P E G _T X P [ 8 . . 1 5 ] 1 1
3. 3V
Q5 3
2
3
C5 9 5
0 . 1 u _1 6 V _ Y 5V _0 4
V CC
OU T
G N D
* G7 1 1 S T 9 U
1
1:2 (4mils:8mils)
C P U _T H E R M 3 1
MO L E X 4 7 98 9 -0 1 3 2
6-86-27989-004
C 5 96
* 0 . 1u _ 1 6 V _ Y 5 V _ 0 4
1
3
PLACE NEAR U38
2
3 . 3 V 3 , 1 2 . . 1 4 , 16 , 1 7 , 1 9 , 2 2 , 2 5, 2 8 , 2 9 , 3 5 . . 3 9
V D D 3 1 2 , 2 8 , 3 1. . 3 4, 3 9 , 4 0
Processor 1/7 DMI, PEG B - 3
Schematic Diagrams
Processor 2/7 CLK, MISC
D DR 3 Co mp en sa ti on S ig na ls
P ro ce ss or C om pe ns at io n Si gn al s
H _ C O MP 1
2 0 _1 % _ 04
H _ C O MP 2
H _ C OM P 1
G1 6
R 37 2
2 0 _1 % _ 04
H _ C O MP 3
H _ C OM P 0
AT2 6
A H2 4
R5 0 9
1 7 H_ P E CI
Zo= 50 O? 5%
P ro ce ss or P ul lu ps
AK1 4
H _ CA T E RR #
R 38 7
35 H _P R OC H O T#
0_ 0 4
0 _ 04
A N2 6
H _ P R O C H O T #_ D
I f P RO CH OT # is no t us ed, t he n it mu st b e ter mi na te d
w ith a 5 0- O pul l- up r esi st or t o VTT _1 .1 r ail .
1 . 1 V S _ V TT
1 7 H _ T H R MT R I P #
R 10 2
4 9 . 9_ 1 % _ 04
H _ CA T E RR #
R 37 0
6 8 _0 4
H _ P R O C H O T #_ D
R 36 9
* 68 _ 0 4
H _ CP U RS T #
AT1 5
AK1 5
C O MP 1
C O MP 0
S K T OC C #
CA T E R R#
THERMAL
3 98 905 D G1 .5 :
1 0m il wi de , <50 0m il l eng th o r
2 0m il wi de , 500 mi l< le ngt h< 10 0m il
k ee p 2 0m il s pac in g
C O MP 2
PEC I
P R O C H OT #
B CL K
B C LK #
CLOCKS
R 37 1
C O MP 3
MISC
AT2 4
H _ C OM P 2
B C L K _I T P
B C L K _ I TP #
P E G_ C L K
P E G _C LK #
D P L L _R E F _ S S C L K
D P L L _ R E F _ S S C LK #
R3 6 1
10 0 _ 1% _ 0 4
S M _ R C O MP _ 1
R3 6 0
24 . 9 _ 1% _ 0 4
S M _ R C O MP _ 2
R3 5 9
13 0 _ 1% _ 0 4
S M_ D R A MR S T #
S M _ R C O MP [ 0]
S M _ R C O MP [ 1]
S M _ R C O MP [ 2]
P M _ E XT _ T S #[ 0]
P M _ E XT _ T S #[ 1]
*0 _ 04
R3 9 5
P M_ S Y N C
S Y S _ A GE N T _P W R OK A N 1 4
A N2 7
R3 9 3
0_ 0 4
V D D P W R GOO D _ R
AK1 3
A M1 5
1 4 H _ V T T P W R GD
A M2 6
H _ P W RG D_ X DP
1 6 , 2 0, 2 8 . . 3 1 B U F _ P L T _R S T #
R3 7 6
V C C P W R GOO D _ 1
0_ 0 4
1 7 H _ C P U P W R GD
14 P M _ D R A M_ P W R GD
R E S E T_ O B S #
AL 1 5
1 4 H _ P M_ S Y N C
R3 9 4
1 4 , 35 D E L A Y _ P W R GD
P L T _ R S T # _R
1. 5 K _ 1 % _0 4
AL 1 4
B CL K _ IT P _ P
B CL K _ IT P _ N
E 16
D1 6
C L K _ E X P _ P 13
CL K _ E X P _ N 1 3
A 18
A 17
C LK _D P _ P
C LK _D P _ N
R 50 7
R 50 8
0_ 0 4
0_ 0 4
C P U D R A MR S T #
F6
A L1
A M1
A N1
S M_ R C OM P _ 0
S M_ R C OM P _ 1
S M_ R C OM P _ 2
A N1 5
A P 15
P M_ E X T TS #[ 0 ]
P M_ E X T TS #[ 1 ]
1. 1 V S _ V T T
3
1. 1 V S _ V T T
R 37 5
R 37 4
1 0 K _0 4
1 0 K _0 4
R 39 1
R 39 2
0 _ 04
0 _ 04
P M _ E XT T S # _E C 2
T S # _ D I M M0 _1 8 , 9
R 11 2
P R DY #
P RE Q #
AP2 6
A R3 0
A T3 0
B CL K _ CP U _ P 1 7
B CL K _ CP U _ N 1 7
S3 Powe r Re duct ion w hit e pape r
FO R X DP
H _ C P U R S T#
A 16
B 16
T H E R MT R I P #
PWR MANAGEMENT
V C C P W R GOO D _ 0
S M_ D R A M P W R O K
V T TP W R G OO D
T A P P W R GOO D
T CK
T MS
TR S T #
T DI
TD O
T DI_ M
T D O_ M
DB R #
BPM
BPM
BPM
BPM
BPM
BPM
BPM
BPM
#[
#[
#[
#[
#[
#[
#[
#[
0]
1]
2]
3]
4]
5]
6]
7]
A T2 8
A P 27
X DP _ P RD Y #
X DP _ P RE Q #
A N2 8
A P 28
A T2 7
X DP _ T CL K
X D P _ T MS
X DP _ T RS T #
A T2 9
A R2 7
A R2 9
A P 29
X DP _ T DI_ R
X D P _ T D O_ R
X DP _ T DI_ M
X D P _ T D O_ M
A N2 5
H _ D B R # _R
A J2 2
A K 22
A K 24
A J2 4
A J2 5
A H2 2
A K 23
A H2 3
X D P _ OB S 0 _ R
X D P _ OB S 1 _ R
X D P _ OB S 2 _ R
X D P _ OB S 3 _ R
X D P _ OB S 4 _ R
X D P _ OB S 5 _ R
X D P _ OB S 6 _ R
X D P _ OB S 7 _ R
*1 2 . 4 K _ 1% _ 0 4
1 . 1 V S _V TT
R3 8 3
R3 8 8
*1 0 m li _ 0 4
*1 K _ 04
X D P _P R E Q#
R 36 8
*5 1 _ 04
X D P _T M S
R 36 6
*5 1 _ 04
X D P _T D I _R
R 36 5
*5 1 _ 04
X D P _T D O_ R
R 38 5
*5 1 _ 04
X D P _T D O_ M
R 38 2
*5 1 _ 04
X D P _T C LK
R 38 4
*5 1 _ 04
X D P _T R S T#
R 36 7
5 1 _0 4
XD P _ TD I _ M
3 .3 V S
RS T IN #
R1 0 9
M OL E X 47 9 8 9-0 1 3 2
75 0 _ 1% _ 0 4
S3 Pow e r Re duc ti on w hi te pa pe r
1. 5 V
3
R4 8 8
3 .3 V
5
0 _ 04
6
C 5 8 0 * 0. 1 u _ 10 V _ X 7R _ 04
R4 8 9
5
*1 K _ 04
Q4 3
MT N 7 0 0 2Z H S 3
S
D
C P U D R A MR S T #
D D R 3 _ D R A MR S T # 8, 9
1 .5 V S _ CP U
U 43
* 74 A H C 1 G0 8 GW
4
D R A MP W R GD _ C P U
2
R 49 2
* 0_ 0 4
C5 8 1
R 49 0
1 . 1 K _1 % _ 0 4
*1 . 5 K _ 1 %_ 0 4
3 .3 V
D R A M R S T _ C N TR L_ P C H 1 7
V D D P W R G OO D _ R
R4 9 3
1 .5 V S _ CP U
*1 0 K _0 4
*4 7 0P _ 5 0 V _X 7 R _ 0 4
R 49 4
*1 K _ 04
R 10 3
D
1 . 5S _ C P U _ P W R GD
* 10 K _ 0 4
R5 1 2
37
3 K _ 1% _ 0 4
Q4 4
G
*MT N 70 0 2 Z H S 3
S
C
B
Q 45
E
* 2N 39 0 4
B - 4 Processor 2/7 CLK, MISC
R 37 7
3 .3 V
D R A M R S T _ C N TR L 7
*1 0 0K _ 0 4
3
R4 9 1
D RA M P W RG D_ C P U
1
1 4 , 3 6 1. 1 V S _ V T T _P W R G D
G
B.Schematic Diagrams
S M _ R C O MP _ 0
U 38 B
AT2 3
DDR3
MISC
4 9 . 9_ 1 % _ 04
H _ C OM P 3
Sheet 3 of 55
Processor 2/7
CLK, MISC
( CLK,MISC,JTAG )
H _ C O MP 0
4 9 . 9_ 1 % _ 04
R 59
2/7
JTAG & BPM
R 38 6
PROCESSOR
R4 90 ? ? ? ? , R1 03 = 75 0_1 %_ 04
R4 90 ? ? ? ? , R1 03 = 3K_ 1%_0 4
1 .5 V S _ CP U 6 ,3 4
3 . 3 V 2 , 1 2 . . 14 , 1 6 , 17 , 1 9 , 2 2, 2 5 , 2 8, 2 9 , 3 5 . . 39
3 . 3 V S 8 . . 1 2 , 14 , 1 6 . . 2 4, 2 6 . . 3 5
1 . 1 V S _ V T T 5, 6 , 1 2 . . 1 4, 1 7 . . 2 0 , 35 , 3 6
1 . 5 V 8 , 9 , 1 9, 3 7
Schematic Diagrams
Processor 3/7 DDR3I
PROCESSOR
3/7
( DDR3 )
U38C
U38D
8 M_A_BS0
8 M_A_BS1
8 M_A_BS2
8 M_A_CAS#
8 M_A_RAS#
8 M
_A_
WE#
AC3
AB2
U7
AE1
AB3
AE9
SA_DQ
[0]
SA_DQ
[1]
SA_DQ
[2]
SA_DQ
[3]
SA_DQ
[4]
SA_DQ
[5]
SA_DQ
[6]
SA_DQ
[7]
SA_DQ
[8]
SA_DQ
[9]
SA_DQ
[10]
SA_DQ
[11]
SA_DQ
[12]
SA_DQ
[13]
SA_DQ
[14]
SA_DQ
[15]
SA_DQ
[16]
SA_DQ
[17]
SA_DQ
[18]
SA_DQ
[19]
SA_DQ
[20]
SA_DQ
[21]
SA_DQ
[22]
SA_DQ
[23]
SA_DQ
[24]
SA_DQ
[25]
SA_DQ
[26]
SA_DQ
[27]
SA_DQ
[28]
SA_DQ
[29]
SA_DQ
[30]
SA_DQ
[31]
SA_DQ
[32]
SA_DQ
[33]
SA_DQ
[34]
SA_DQ
[35]
SA_DQ
[36]
SA_DQ
[37]
SA_DQ
[38]
SA_DQ
[39]
SA_DQ
[40]
SA_DQ
[41]
SA_DQ
[42]
SA_DQ
[43]
SA_DQ
[44]
SA_DQ
[45]
SA_DQ
[46]
SA_DQ
[47]
SA_DQ
[48]
SA_DQ
[49]
SA_DQ
[50]
SA_DQ
[51]
SA_DQ
[52]
SA_DQ
[53]
SA_DQ
[54]
SA_DQ
[55]
SA_DQ
[56]
SA_DQ
[57]
SA_DQ
[58]
SA_DQ
[59]
SA_DQ
[60]
SA_DQ
[61]
SA_DQ
[62]
SA_DQ
[63]
SA_BS[ 0]
SA_BS[ 1]
SA_BS[ 2]
SA_CAS#
SA_RAS#
SA_WE#
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
DDR SYS TEM MEM ORY A
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
SA_
DQS#[0]
SA_
DQS#[1]
SA_
DQS#[2]
SA_
DQS#[3]
SA_
DQS#[4]
SA_
DQS#[5]
SA_
DQS#[6]
SA_
DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AA6
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
M_CLK_DDR0 8
M_CLK_DDR#0 8
M_CKE0 8
9 M_B_DQ[63:0]
M_CLK_DDR1 8
M_CLK_DDR#1 8
M_CKE1 8
M_CS#0 8
M_CS#1 8
M_O
DT0 8
M_O
DT1 8
B9
D7
H7
M7
AG6
AM7
AN10
AN13
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
C9
F8
J9
N9
AH7
AK9
AP11
AT13
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
C8
F9
H9
M9
AH8
AK10
AN11
AR13
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_
A_DM[7:0] 8
M_
A_DQS#[ 7
: 0] 8
M_
A_DQS[ 7:0] 8
M_
A_A[15:0] 8
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
9 M_
B_BS0
9 M_
B_BS1
9 M_
B_BS2
9 M
_B_CAS#
9 M
_B_RAS#
9 M_B_WE#
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G
4
H6
G
2
J6
J3
G
1
G
5
J2
J1
J5
K2
L3
M
1
K5
K4
M
4
N5
AF3
AG
1
AJ3
AK1
AG
4
AG
3
AJ4
AH4
AK3
AK4
AM
6
AN2
AK5
AK2
AM
4
AM
3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT
10
AB1
W5
R7
AC5
Y7
AC6
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_O
DT[0]
SB_O
DT[1]
SB_
DM[0]
SB_
DM[1]
SB_
DM[2]
SB_
DM[3]
SB_
DM[4]
SB_
DM[5]
SB_
DM[6]
SB_
DM[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
W8
W9
M
3
V7
V6
M
2
AB8
AD6
AC7
AD1
M_
CLK_DDR2 9
M_
CLK_DDR#2 9
M_
CKE2 9
M_
CLK_DDR3 9
M_
CLK_DDR#3 9
M_
CKE3 9
M_
CS#2 9
M_
CS#3 9
M_
ODT2 9
M_
ODT3 9
M
_B_DM[7:0] 9
D4
E1
H3
K1
AH1
AL2
AR4
AT8
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
D5
F4
J4
L4
AH2
AL4
AR5
AR8
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M
_B_DQS#[7:0] 9
C5
E3
H4
M
5
AG2
AL5
AP5
AR7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M
_B_DQS[7:0] 9
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M
_B_A[15:0] 9
Sheet 4 of 55
Processor 3/7
DDR3
MOLEX47989-0132
MO
LEX47989
- 013
2
Processor 3/7 DDR3I B - 5
B.Schematic Diagrams
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DDR SYS TEM MEMO RY - B
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
8 M
_A_DQ[63:0]
Schematic Diagrams
Processor 4/7 Power
PR OCESS OR CO RE PO WER
PROCESSOR
U38F
4/7
( POWER )
1. 1
VS_VTT
M
OLEX47989-0132
B - 6 Processor 4/7 Power
1.1V RAIL POWE R
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
PRO CESSO R UNC ORE P OWER
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
C468
C458
C475
C456
C454
C465
C461
C106
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6
. 3V_X5R_06
*10u_6.3V_X5R_06
*10u_6.3V_X5R_06
22u_6. 3
V_X5
R_08
22u_6.3V_X5R_08
22u_6.3V_X5R_
08
C479
C477
C455
C457
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6
. 3V_X5R_06
10u_6.3V_X5R_0
6
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
The decoupling ca pacitors, filter
recommendations a nd sense resistors on the
CPU/PCH Rails are specific to the C RB
Implementation. C ustomers need to f ollow the
recommendations i n the Calpella Pla tform
Design Guide
1.1VS_VTT
Pl ease note that the
VT T Rail Values are
1.1VS_VCCTTA_QPI
R356
*32mil_short
C1
28
C138
22u_6. 3
V_X5
R_08
22u_6.3V_X5R_08
+VTT_43
+VTT_44
1.1VS_VTT
Au burndale/Arrandale is 1.05 V
Cl arksfield VTT=1.1V
C15
7
R353
R60
22u_6. 3V_X5R_08
0_04
0_04
1.1VS_VTT
R379
*1K_0
4
PSI#
AN33
PSI#
PSI# 35
POWER
1.1VS_VTT
CPU VIDS
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
AK35
AK33
AK34
AL35
AL33
AM
33
AM
35
AM
34
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
35
35
35
35
35
35
35
R362
1K_04
R357
1K_04
PM_
DPRSLPVR 35
R358
VTT_
SELECT
G15
H_VTTVID1 36
*1K_04
1K PU to VTT and
1K PD to GND for POC
TO VCORE POWER
CONTROL
ISENSE
SENSE LI NES
Sheet 5 of 55
Processor 4/7
Power
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
CPU C ORE SUPPLY
B.Schematic Diagrams
VCORE
AN35
IMON 3
5
AJ34
VCC_SENSE
AJ35
VSS_SENSE
B15
VTT_SENSE
A15
VSS_SENSE_VTT
VCC_SENSE 35
VSS_SENSE 35
VTT_SENSE_R
R347
TP_VSS_
SENSE_VT
T
0_04
VTT1.1VS
VTT1.1VS 36
VCO
RE 35
1.1VS_VT
T 3,6,12..14,17..20,35,36
Schematic Diagrams
Processor 5/7 GFX PWR
PROCESSOR
5/7
( GRAPHICS POWER )
U38G
1. 1VS_VCC_FDI
R355
0_06
C464
C469
22u_6.3V_X5R_08
22u_6.3V_X5R_08
J24
J23 VTT1_45
H25 VTT1_46
VTT1_47
FDI
1.1VS_VTT
AM22
AP22
AN22
AP23
AM23
AP24
AN24
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
AR25
AT25
AM24
R373
R390
TP_GFX_I MON
R389
*0_04
*0_04
S3 Pow e r Re du ct i on w hi te pa pe r
1K_04
1
FOR DISABLE
1.5VS_CPU
- 1.5V RAILS
GRAPHICS VIDs
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
VAXG_SENSE
VSSAXG_SENSE
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VTT0_59
VTT0_60
VTT0_61
VTT0_62
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
C145
C155
C121
1u_6.3V_X5R_04
22u_6.3V_X5R_08
22u_6.3V_X5R_08
+ C123
330u_2. 5V_V_A
C143
C129
C116
C101
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1u_6.3V_X5R_04
Sheet 6 of 55
Processor 5/7
GFX PWR
C582
*22u_6.3V_X5R_08
1.1VS_VTT
P10
N10
L10
K10
C147
C148
10u_6.3V_X5R_06
10u_6.3V_X5R_06
1.1VS_VCCTTA_DDR
C107
22u_6.3V_X5R_08
22u_6.3V_X5R_08
C462
C108
22u_6.3V_X5R_08
22u_6.3V_X5R_08
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25
VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58
PEG & DMI
C463
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
R66
J22
J20
J18
H21
H20
H19
C109
C110
22u_6.3V_X5R_08
22u_6.3V_X5R_08
0_06
1.1VS_VTT
1. 8VS
1.8V
*32mil_short
1.1V
1.1VS_VCC_PEG_DMI
R354
1.1VS_VTT
VCCPLL1
VCCPLL2
VCCPLL3
L26
L27
M26
C467
C470
C466
C471
C472
1u_6.3V_X5R_04
1u_6.3V_X5R_04
2.2u_6.3V_X5R_04
4.7u_6.3V_Y5V_06
22u_6. 3V_X5R_08
MOLEX 47989-0132
1.8VS 16,18,38
1.1VS_VTT 3,5,12. .14,17..20,35, 36
1.5V 3,8, 9,19,37
1.5VS_CPU 3,34
Processor 5/7 GFX PWR B - 7
B.Schematic Diagrams
Au burnda le VT T=1.0 5V
Cl arksfi eld V TT=1. 1V
GRAPHICS
Pl ease n ote t hat t he
VT T Rail Valu es ar e
VAXG_SENSE AR22
AT22
VSSAXG_SENSE
DDR3
*20mil_short
POWER
R378
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
SE NSE
LINES
FOR DISABLE
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
Schematic Diagrams
Processor 6/7 GND, 7/7 RSVD
PROCESSOR
6/7
PROCESSOR
( GND )
7/7
( RESERVED )
S 3 Po w e r Re d uc tio n w h it e p ap e r
MOL E X 4 79 8 9 -01 3 2
R4 9 5
4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 1
16 2
16 3
16 4
16 5
16 6
16 7
16 8
16 9
17 0
17 1
17 2
17 3
17 4
17 5
17 6
17 7
17 8
17 9
18 0
18 1
18 2
18 3
18 4
18 5
18 6
18 7
18 8
18 9
19 0
19 1
19 2
19 3
19 4
19 5
19 6
19 7
19 8
19 9
20 0
20 1
20 2
20 3
20 4
20 5
20 6
20 7
20 8
20 9
21 0
21 1
21 2
21 3
21 4
21 5
21 6
21 7
21 8
21 9
22 0
22 1
22 2
22 3
22 4
22 5
22 6
22 7
22 8
22 9
23 0
23 1
23 2
23 3
0 _ 04
D
MV R E F _ D Q _D I M0
K 27
K9
K6
K3
J 32
J 30
J 21
J 19
H 35
H 32
H 28
H 26
H 24
H 22
H 18
H 15
H 13
H 11
H8
H5
H2
G 34
G 31
G 20
G9
G6
G3
F 30
F 27
F 25
F 22
F 19
F 16
E 35
E 32
E 29
E 24
E 21
E 18
E 13
E 11
E8
E5
E2
D 33
D 30
D 26
D9
D6
D3
C 34
C 32
C 29
C 28
C 24
C 22
C 20
C 19
C 16
B 31
B 25
B 21
B 18
B 17
B 13
B 11
B8
B6
B4
A 29
A 27
A 23
A9
S
V R E F _ C H _ A _ D I MM
Q4 6
*A O 34 0 2 L
D R A MR S T _C N T R L
3 D R A MR S T _C N T R L
R S V D 32
R S V D 33
* 1 00 K _ 0 4
R 4 97
MV R E F _ D Q _D I M1
U 38 E
R 4 96
AP2 5
A L2 5
A L2 4
A L2 2
A J3 3
A G9
M2 7
L2 8
J1 7
H1 7
G2 5
G1 7
E3 1
E3 0
0_ 0 4
D
S
V R E F _ C H _B _ D I MM
Q4 7
*A O 34 0 2 L
R 4 98
* 1 00 K _ 0 4
D R A MR S T _C N T R L
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
RS
R S V D 34
R S V D 35
R S V D 36
R S V D _N C T F _ 37
R S V D 38
R S V D 39
R S V D _N C T F _ 40
R S V D _N C T F _ 41
R S V D _N C T F _ 42
R S V D _N C T F _ 43
CFG Straps for Processor
CF G 0
PCI-Express Configuration Select
VSS
MOL E X 4 79 8 9 -01 3 2
V S S _ NC
V S S _ NC
V S S _ NC
V S S _ NC
V S S _ NC
V S S _ NC
V S S _ NC
TF 1
TF 2
TF 3
TF 4
TF 5
TF 6
TF 7
AT3 5
AT1
AR 3 4
B3 4
B2
B1
A3 5
T P _ MC P _ V S S _ N C T F 1
T P _ MC P _ V S S _ N C T F 2
T P _M C P _ V S S _ N C T F 6
T P _M C P _ V S S _ N C T F 7
CF G 7
0 :
Bifurcation
enable
CF G 0
A ll N CTF p ins s ho uld
b e Te st Po int s an d
s ho ul d b e rou te d as
t ra ce .
R3 6 4
3. 0 1 K _ 1% _ 0 4
CFG3 - PCI-Express Static Lane Reversal
Ch eck li st 1. 5:
VS S_N CT F Pin s
ca n b e co nne ct ed
to GN D or le ft
as NC
(f loa ti ng ).
Wh en ti ed to G ND
th ey sh ou ld be
ro ute d as tr ac e
an d n ot a s a G ND
pl ane .
M770CU? :
R58? ? ? ? ,
? ? ? ?
? W860CU? ? !
C FG 3
C F G3
1 : Normal Operation
0 : Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
R 38 0
C FG 4
R5 8
* 0_ 0 4
RSV D 8 6
A M3 0
A M2 8
AP3 1
A L3 2
A L3 0
A M3 1
A N2 9
A M3 2
AK3 2
AK3 1
AK2 8
A J2 8
A N3 0
A N3 2
A J3 2
A J2 9
A J3 0
AK3 0
H1 6
*3 . 0 1 K _1 % _ 04
1 : Disablled; No physical
Display Port attached to
Embedded Display Port
0 : Enabled; An external
Display Port device is
connected to the Embedded
Display Port
R3 5 2
R3 5 1
* 0_ 0 4
* 0_ 0 4
H _ R S V D 1 7_ R A 2 0
H _ R S V D 1 8_ R B 2 0
Cus to mer s do
not n eed t o
imp le men t th e
pul l- dow n
res is tor s. T his
is fo r i nt er nal
val id ati on
pur po se on ly .
U9
T9
A C9
AB9
C1
A3
J2 9
J2 8
C F G4
R 38 1
*3 . 0 1 K _1 % _ 04
A3 4
A3 3
CFG7 - Reserved - Temporarily used for
early Clarksfield samples.
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
CF
RS
G[ 0 ]
G[ 1 ]
G[ 2 ]
G[ 3 ]
G[ 4 ]
G[ 5 ]
G[ 6 ]
G[ 7 ]
G[ 8 ]
G[ 9 ]
G[ 1 0]
G[ 1 1]
G[ 1 2]
G[ 1 3]
G[ 1 4]
G[ 1 5]
G[ 1 6]
G[ 1 7]
V D _ T P _8 6
RSV D8 6
Con ne ct to G ND
B1 9
A1 9
CFG4 - Display Port Presence
Cu sto me rs do n ot
me ed to p ull
do wn an y of th e
VS S_N CT F pin s.
CF G 3
CF G 4
1 : Single PEG
CF G0
C3 5
B3 5
C FG 7
CF G 7
R3 6 3
R S V D _ T P _ 59
R S V D _ T P _ 60
KEY
R S V D 62
R S V D 63
R S V D 64
R S V D 65
RS VD1 7
RS VD1 8
RS VD1 9
RS VD2 0
RS VD2 1
RS VD2 2
R S V D _ N C TF _ 2 3
R S V D _ N C TF _ 2 4
RS VD2 6
RS VD2 7
R S V D _ N C TF _ 2 8
R S V D _ N C TF _ 2 9
R S V D _ N C TF _ 3 0
R S V D _ N C TF _ 3 1
R
R
R
R
R
R
R
R
R
R
S V D _ T P _ 66
S V D _ T P _ 67
S V D _ T P _ 68
S V D _ T P _ 69
S V D _ T P _ 70
S V D _ T P _ 71
S V D _ T P _ 72
S V D _ T P _ 73
S V D _ T P _ 74
S V D _ T P _ 75
R
R
R
R
R
R
R
R
R
R
S V D _ T P _ 76
S V D _ T P _ 77
S V D _ T P _ 78
S V D _ T P _ 79
S V D _ T P _ 80
S V D _ T P _ 81
S V D _ T P _ 82
S V D _ T P _ 83
S V D _ T P _ 84
S V D _ T P _ 85
VSS
M OL E X 47 9 8 9-0 1 3 2
N ot e: On ly te mp ora ry f or ea rl y C FD
s am ple s (r PGA /B GA) [ Fo r d et ai ls
p le ase r ef er to th e WW 33 Mo W and
s ig hti ng r epo rt ].
F or a co mm on mo the rb oa rd de si gn (f or
A UB an d CF D), t he pu ll -do wn r esi st or
s ho uld b e use d. Do es n ot im pa ct AU B
f un cti on al ity .
RS V D
RS V D
RS V D
RS V D
R S V D 45
R S V D 46
R S V D 47
R S V D 48
R S V D 49
R S V D 50
R S V D 51
R S V D 52
R S V D 53
_N C T F _ 54
_N C T F _ 55
_N C T F _ 56
_N C T F _ 57
R S V D 58
AJ 1 3
AJ 1 2
AH 2 5
AK2 6
AL 2 6
AR 2
AJ 2 6
AJ 2 7
AP1
AT2
AT3
AR 1
AL 2 8
AL 2 9
AP3 0
AP3 2
AL 2 7
AT3 1
AT3 2
AP3 3
AR 3 3
AT3 3
AT3 4
AP3 5
AR 3 5
AR 3 2
E1 5
F15
A2
D 15
C 15
AJ 1 5
AH 1 5
RS VD1 5
RS VD1 6
C la rks fi el d ( on ly fo r ear ly s amp le s
p re -ES 1) - Co nn ect t o GND w it h 3 .0 1K
O hm /5% r es ist or
R363
M770CU? ? ?
W860CU? ?
Che ck li st 1. 5:
RSV D_ 86
Con ne ct to G ND or l eav e it NC ( fl oat in g).
Not e: C RB ha s lef t thi s pi n N C (f loa ti ng) .
*3 . 0 1K _1 % _0 4
8 MV R E F _D Q_ D I M 0
9 MV R E F _D Q_ D I M 1
B - 8 Processor 6/7 GND, 7/7 RSVD
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VD8
VD9
VD1 0
VD1 1
VD1 2
VD1 3
VD1 4
RESERVED
AE3 4
AE3 3
AE3 2
AE3 1
AE3 0
AE2 9
AE2 8
AE2 7
AE2 6
AE6
AD1 0
AC8
AC4
AC2
AB3 5
AB3 4
AB3 3
AB3 2
AB3 1
AB3 0
AB2 9
AB2 8
AB2 7
AB2 6
AB6
AA1 0
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V1 0
U8
U4
U2
T 35
T 34
T 33
T 32
T 31
T 30
T 29
T 28
T 27
T 26
T6
R1 0
P8
P4
P2
N3 5
N3 4
N3 3
N3 2
N3 1
N3 0
N2 9
N2 8
N2 7
N2 6
N6
M1 0
L 35
L 32
L 29
L8
L5
L2
K3 4
K3 3
K3 0
G
VSS8 1
VSS8 2
VSS8 3
VSS8 4
VSS8 5
VSS8 6
VSS8 7
VSS8 8
VSS8 9
VSS9 0
VSS9 1
VSS9 2
VSS9 3
VSS9 4
VSS9 5
VSS9 6
VSS9 7
VSS9 8
VSS9 9
V S S 10 0
V S S 10 1
V S S 10 2
V S S 10 3
V S S 10 4
V S S 10 5
V S S 10 6
V S S 10 7
V S S 10 8
V S S 10 9
V S S 11 0
V S S 11 1
V S S 11 2
V S S 11 3
V S S 11 4
V S S 11 5
V S S 11 6
V S S 11 7
V S S 11 8
V S S 11 9
V S S 12 0
V S S 12 1
V S S 12 2
V S S 12 3
V S S 12 4
V S S 12 5
V S S 12 6
V S S 12 7
V S S 12 8
V S S 12 9
V S S 13 0
V S S 13 1
V S S 13 2
V S S 13 3
V S S 13 4
V S S 13 5
V S S 13 6
V S S 13 7
V S S 13 8
V S S 13 9
V S S 14 0
V S S 14 1
V S S 14 2
V S S 14 3
V S S 14 4
V S S 14 5
V S S 14 6
V S S 14 7
V S S 14 8
V S S 14 9
V S S 15 0
V S S 15 1
V S S 15 2
V S S 15 3
V S S 15 4
V S S 15 5
V S S 15 6
V S S 15 7
V S S 15 8
V S S 15 9
V S S 16 0
G
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2
VSS5 3
VSS5 4
VSS5 5
VSS5 6
VSS5 7
VSS5 8
VSS5 9
VSS6 0
VSS6 1
VSS6 2
VSS6 3
VSS6 4
VSS6 5
VSS6 6
VSS6 7
VSS6 8
VSS6 9
VSS7 0
VSS7 1
VSS7 2
VSS7 3
VSS7 4
VSS7 5
VSS7 6
VSS7 7
VSS7 8
VSS7 9
VSS8 0
NCTF
Sheet 7 of 55
Processor 6/7 GND,
7/7 RSVD
A T 20
A T 17
A R 31
A R 28
A R 26
A R 24
A R 23
A R 20
A R 17
A R 15
A R 12
A R9
A R6
A R3
A P 20
A P 17
A P 13
A P 10
AP7
AP4
AP2
A N 34
A N 31
A N 23
A N 20
A N 17
A M 29
A M 27
A M 25
A M 20
A M 17
A M 14
A M 11
A M8
A M5
A M2
A L 34
A L 31
A L 23
A L 20
A L 17
A L 12
A L9
A L6
A L3
A K 29
A K 27
A K 25
A K 20
A K 17
A J 31
A J 23
A J 20
A J 17
A J 14
A J 11
A J8
A J5
A J2
A H 35
A H 34
A H 33
A H 32
A H 31
A H 30
A H 29
A H 28
A H 27
A H 26
A H 20
A H 17
A H 13
A H9
A H6
A H3
A G 10
AF8
AF4
AF2
A E 35
U 3 8I
VSS
B.Schematic Diagrams
U 3 8H
AA5
AA4
R 8
AD 3
AD 2
AA2
AA1
R 9
AG 7
AE3
R S V D 6 4_ R
R S V D 6 5_ R
R1 0 6
R1 0 1
*0 _ 04
*0 _ 04
C ust om er s d o not
n eed t o imp le men t
t he pu ll -do wn
r esi st or s. Th is is
f or in te rna l
v ali da ti on pu rpo se
o nly .
V4
V5
N 2
AD 5
AD 7
W3
W2
N 3
AE5
AD 9
AP3 4
V SS (A P3 4) ca n b e
l eft N C is CR B
i mpl em en tat io n ;
E DS/ DG
r eco mm en dat io n t o
G ND
Schematic Diagrams
DDR3 SO-DIMM_0 REV
SO-DIMM 0
REVERSE TYPE
H=4.0mm
J D I M M2 A
4 M_ A _ A [ 1 5 : 0 ]
pin 1
pin 2
4 M_ A _ B S 0
4 M_ A _ B S 1
4 M_ A _ B S 2
4 M _ CS # 0
4 M _ CS # 1
4 M _C L K _D D R 0
4 M_ C L K _ D D R #0
4 M _C L K _D D R 1
4 M_ C L K _ D D R #1
4 M _ CK E 0
4 M _ CK E 1
4 M _A _ C A S #
4 M _A _ R A S #
4 M _ A_ W E#
S A 0 _ DIM 0
S A 1 _ DIM 0
9 , 1 3, 2 0 , 3 5 S MB _C L K _D D R 3
9 , 1 3, 2 0 , 3 5 S MB _ D A T A _D D R 3
R4 5 2
R4 5 1
1 0 K _0 4
1 0K _ 0 4
98
97
96
95
92
91
90
86
89
85
1 07
84
83
1 19
80
78
1 09
1 08
79
1 14
1 21
1 01
1 03
1 02
1 04
73
74
1 15
1 10
1 13
1 97
2 01
2 02
2 00
1 16
1 20
4 M _ OD T0
4 M _ OD T1
4 M _A _D M[ 7 : 0 ]
4 M _A _ D QS [ 7 : 0 ]
4 M _ A _D QS #[ 7 : 0 ]
V T T_ M E M
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M0
M1
M2
M3
M4
M5
M6
M7
11
28
46
63
1 36
1 53
1 70
1 87
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
QS 0
QS 1
QS 2
QS 3
QS 4
QS 5
QS 6
QS 7
12
29
47
64
1 37
1 54
1 71
1 88
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
M_ A _ D
QS # 0
QS # 1
QS # 2
QS # 3
QS # 4
QS # 5
QS # 6
QS # 7
10
27
45
62
1 35
1 52
1 69
1 86
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10 / A P
A 11
A 12 / B C #
A 13
A 14
A 15
BA0
BA1
BA2
S 0#
S 1#
CK 0
CK 0 #
CK 1
CK 1 #
CK E 0
CK E 1
CA S #
RA S #
W E#
SA0
SA1
S CL
S DA
OD T 0
OD T 1
D M0
D M1
D M2
D M3
D M4
D M5
D M6
D M7
D QS
D QS
D QS
D QS
D QS
D QS
D QS
D QS
0
1
2
3
4
5
6
7
D QS
D QS
D QS
D QS
D QS
D QS
D QS
D QS
0#
1#
2#
3#
4#
5#
6#
7#
D Q0
D Q1
D Q2
D Q3
D Q4
D Q5
D Q6
D Q7
D Q8
D Q9
D Q1 0
D Q1 1
D Q1 2
D Q1 3
D Q1 4
D Q1 5
D Q1 6
D Q1 7
D Q1 8
D Q1 9
D Q2 0
D Q2 1
D Q2 2
D Q2 3
D Q2 4
D Q2 5
D Q2 6
D Q2 7
D Q2 8
D Q2 9
D Q3 0
D Q3 1
D Q3 2
D Q3 3
D Q3 4
D Q3 5
D Q3 6
D Q3 7
D Q3 8
D Q3 9
D Q4 0
D Q4 1
D Q4 2
D Q4 3
D Q4 4
D Q4 5
D Q4 6
D Q4 7
D Q4 8
D Q4 9
D Q5 0
D Q5 1
D Q5 2
D Q5 3
D Q5 4
D Q5 5
D Q5 6
D Q5 7
D Q5 8
D Q5 9
D Q6 0
D Q6 1
D Q6 2
D Q6 3
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
_ A _D
M _ A _ D Q [ 63 : 0 ] 4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q1 0
Q1 1
Q1 2
Q1 3
Q1 4
Q1 5
Q1 6
Q1 7
Q1 8
Q1 9
Q2 0
Q2 1
Q2 2
Q2 3
Q2 4
Q2 5
Q2 6
Q2 7
Q2 8
Q2 9
Q3 0
Q3 1
Q3 2
Q3 3
Q3 4
Q3 5
Q3 6
Q3 7
Q3 8
Q3 9
Q4 0
Q4 1
Q4 2
Q4 3
Q4 4
Q4 5
Q4 6
Q4 7
Q4 8
Q4 9
Q5 0
Q5 1
Q5 2
Q5 3
Q5 4
Q5 5
Q5 6
Q5 7
Q5 8
Q5 9
Q6 0
Q6 1
Q6 2
Q6 3
J D I M M2 B
1 .5 V
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
3 .3 VS
2 0 mi ls
C5 0 6
C 51 1
2. 2u _ 6 . 3V _Y 5 V _ 06
0 . 1 u _1 0 V _ X 7R _ 04
199
3. 3 V S
77
122
125
R 4 41
*1 0 K _ 04
198
30
3 , 9 T S # _D I MM 0 _1
3 , 9 D D R 3_ D R A M R S T #
C 45 9
C 46 0
4
R 4 03
MV R E F _ D Q _D I M0
MV R E F _ D I M0
*2 . 2 u _6 . 3 V _ Y 5 V _ 0 6
0 . 1u _ 1 0 V _X 7 R _0 4
C 50 2
C 5 15
C 5 16
C 5 22
1 0 u _ 6. 3 V _ X 5 R _ 0 6
1 u _ 6 . 3V _Y 5 V _0 4
1 u _ 6 . 3V _ Y 5 V _0 4
1 u _ 6. 3V _ Y 5V _0 4
1 u _ 6. 3V _ Y 5V _0 4
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
*2 . 2 u _6 . 3 V _ Y 5 V _ 0 6
S3 Pow e r Re du ct ion w h it e pa per
NC 1
NC 2
N C TE S T
E V E N T#
R E S E T#
V R E F _D Q
V R E F _C A
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
Sheet 8 of 55
DDR3 SO-DIMM_0
REV
V T T _ ME M
V T T1
V T T2
G1
G2
203
204
G ND 1
G ND 2
T Y C O_ J P N _ C D _ 2 01 3 2 87 _ B 1
6-86-24204-007
C LO SE T O SO -D IM M_0
1 . 5V
1. 5V
+
V DD SP D
*0 _ 04
T Y C O _ J P N _ C D _ 20 1 3 2 87 _ B 1
C 5 21
2 2 0 u _4 V _ V _ A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
6-86-24204-007
C 541
C4 8 6
+
1
126
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
C4 9 9
C 4 92
C 4 89
C 4 85
C 49 5
C4 9 8
C 4 74
C 49 1
C 48 8
2 20 u _ 4 V _V _A
1 0 u _6 . 3 V _ X 5R _ 0 6
1 0 u _6 . 3 V _ X 5R _ 06
1 0 u _6 . 3 V _ X 5R _ 06
4 . 7 u _6 . 3 V _ Y 5 V _ 0 6
4 . 7u _ 6 . 3 V _Y 5 V _ 06
1 u _ 6. 3 V _ Y 5V _ 0 4
1 u _ 6. 3 V _ Y 5V _ 0 4
1 u _ 6. 3 V _ Y 5V _ 0 4
R 39 6
1 K _ 1 % _ 04
M V R E F _ D I M0
R 3 99
C5 0 1
1 K _ 1 % _ 04
0 . 1u _ 1 0 V _X 7 R _0 4
M V R E F _D Q_ D I M0 7
V T T _ ME M 9 , 3 7
1 . 5 V 3 , 9 , 1 9, 3 7
3 . 3 V S 3 , 9 . . 1 2 , 14 , 1 6 . . 2 4 , 26 . . 3 5
1 .5 V
C 473
C4 9 7
C4 9 4
C 493
C 5 00
C 4 96
C 4 78
C4 9 0
C 4 87
C4 7 6
0 . 2 2 u _1 0 V _ Y 5 V _ 0 4
0 . 2 2u _ 1 0V _Y 5 V _ 04
0. 1 u _ 10 V _ X 7 R _ 0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
0 . 0 1 u _5 0 V _ X 7R _ 04
0 . 0 1u _ 5 0V _X 7 R _ 0 4
0 . 0 1 u _5 0 V _ X 7R _ 04
0 . 0 1u _ 5 0V _X 7 R _ 0 4
DDR3 SO-DIMM_0 REV B - 9
B.Schematic Diagrams
M_ A _ A 0
M_ A _ A 1
M_ A _ A 2
M_ A _ A 3
M_ A _ A 4
M_ A _ A 5
M_ A _ A 6
M_ A _ A 7
M_ A _ A 8
M_ A _ A 9
M_ A _ A 1 0
M_ A _ A 1 1
M_ A _ A 1 2
M_ A _ A 1 3
M_ A _ A 1 4
M_ A _ A 1 5
Schematic Diagrams
DDR SO-DIMM_1 REV
SO-DIMM 1
REVERSE TYPE
H=4.0mm
J D I MM 1B
JD I MM 1 A
4 M _ B _ A [ 1 5: 0 ]
M_ B _ A 0
M_ B _ A 1
M_ B _ A 2
M_ B _ A 3
M_ B _ A 4
M_ B _ A 5
M_ B _ A 6
M_ B _ A 7
M_ B _ A 8
M_ B _ A 9
M_ B _ A 1 0
M_ B _ A 1 1
M_ B _ A 1 2
M_ B _ A 1 3
M_ B _ A 1 4
M_ B _ A 1 5
pin 1
B.Schematic Diagrams
pin 2
Sheet 9 of 55
DDR3 SO-DIMM_1
REV
4
4
4
4
R 23 9
S A 0 _ DIM 1
S A 1 _ DIM 1
8 , 1 3 , 20 , 3 5 S MB _C L K _ D D R 3
8 , 1 3, 2 0 , 3 5 S MB _ D A T A _ D D R 3
R 2 40
1 0 K _ 04
4 M_ B _ B S 0
4 M_ B _ B S 1
4 M_ B _ B S 2
4 M _ CS # 2
4 M _ CS # 3
M _C L K _ D D R 2
M_ C L K _ D D R #2
M _C L K _ D D R 3
M_ C L K _ D D R #3
4 M _ CK E 2
4 M _ CK E 3
4 M _B _ C A S #
4 M _B _ R A S #
4 M _ B_ W E#
10 9
10 8
79
11 4
12 1
10 1
10 3
10 2
10 4
73
74
11 5
11 0
11 3
19 7
20 1
20 2
20 0
11 6
12 0
4 M _ OD T2
4 M _ OD T3
4 M _B _D M[ 7 : 0 ]
1 0 K_ 0 4
98
97
96
95
92
91
90
86
89
85
10 7
84
83
11 9
80
78
3 .3 V S
4 M _B _ D QS [ 7 : 0 ]
4 M _ B _D QS #[ 7 : 0 ]
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
M_ B _ D M
0
1
2
3
4
5
6
7
11
28
46
63
13 6
15 3
17 0
18 7
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
S0
S1
S2
S3
S4
S5
S6
S7
12
29
47
64
13 7
15 4
17 1
18 8
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
S# 0
S# 1
S# 2
S# 3
S# 4
S# 5
S# 6
S# 7
10
27
45
62
13 5
15 2
16 9
18 6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1 0 /AP
A1 1
A1 2 /BC #
A1 3
A1 4
A1 5
BA 0
BA 1
BA 2
S0 #
S1 #
C K0
C K0 #
C K1
C K1 #
C KE0
C KE1
C AS#
R AS#
WE #
SA 0
SA 1
SC L
SD A
O DT 0
O DT 1
D
D
D
D
D
D
D
D
M0
M1
M2
M3
M4
M5
M6
M7
D
D
D
D
D
D
D
D
QS 0
QS 1
QS 2
QS 3
QS 4
QS 5
QS 6
QS 7
D
D
D
D
D
D
D
D
QS 0 #
QS 1 #
QS 2 #
QS 3 #
QS 4 #
QS 5 #
QS 6 #
QS 7 #
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
D Q1 0
D Q1 1
D Q1 2
D Q1 3
D Q1 4
D Q1 5
D Q1 6
D Q1 7
D Q1 8
D Q1 9
D Q2 0
D Q2 1
D Q2 2
D Q2 3
D Q2 4
D Q2 5
D Q2 6
D Q2 7
D Q2 8
D Q2 9
D Q3 0
D Q3 1
D Q3 2
D Q3 3
D Q3 4
D Q3 5
D Q3 6
D Q3 7
D Q3 8
D Q3 9
D Q4 0
D Q4 1
D Q4 2
D Q4 3
D Q4 4
D Q4 5
D Q4 6
D Q4 7
D Q4 8
D Q4 9
D Q5 0
D Q5 1
D Q5 2
D Q5 3
D Q5 4
D Q5 5
D Q5 6
D Q5 7
D Q5 8
D Q5 9
D Q6 0
D Q6 1
D Q6 2
D Q6 3
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
1 29
1 31
1 41
1 43
1 30
1 32
1 40
1 42
1 47
1 49
1 57
1 59
1 46
1 48
1 58
1 60
1 63
1 65
1 75
1 77
1 64
1 66
1 74
1 76
1 81
1 83
1 91
1 93
1 80
1 82
1 92
1 94
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q [ 6 3 : 0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
4
1 . 5V
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
3 .3 VS
2 0 mil s
C 3 06
C3 0 5
2 . 2 u _ 6. 3 V _ Y 5V _ 0 6
0 . 1u _ 1 0 V _X 7 R _ 0 4
199
77
122
125
198
30
3 , 8 T S # _D I MM 0 _1
3 , 8 D D R 3_ D R A M R S T #
C1 5 1
C1 5 3
4
R 18 5
M V R E F _ D Q_ D I M1
MV R E F _ D I M1
* 2. 2 u _ 6 . 3V _Y 5 V _0 6
0 . 1 u _1 0 V _ X 7R _ 04
C 23 7
1
126
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1 0
D1 1
D1 2
D1 3
D1 4
D1 5
D1 6
D1 7
D1 8
VD DS PD
N C1
N C2
N CT E S T
EVEN T#
R ESET#
VR E F _ DQ
VR E F _ CA
* 0 _0 4
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
*2 . 2 u _6 . 3 V _ Y 5 V _ 0 6
S3 Pow e r Re duct ion w hit e pa pe r
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2
44
48
49
54
55
60
61
65
66
71
72
12 7
12 8
13 3
13 4
13 8
13 9
14 4
14 5
15 0
15 1
15 5
15 6
16 1
16 2
16 7
16 8
17 2
17 3
17 8
17 9
18 4
18 5
18 9
19 0
19 5
19 6
V TT _ ME M
VTT1
VTT2
G 1
G 2
20 3
20 4
GN D 1
GN D 2
T Y C O_ J P N _C D _ 2 0 13 2 8 7 _B 1
6-86-24204-007
TY C O _J P N _ C D _2 0 1 32 8 7 _ B 1
V T T_ M E M
6-86-24204-007
C3 0 1
C3 0 0
C 2 85
C 29 0
10 u _ 6. 3V _ X 5 R _ 0 6
1u _ 6 . 3V _Y 5 V _0 4
1 u _ 6. 3V _ Y 5V _0 4
1 u _ 6. 3 V _ Y 5V _ 0 4
CLOS E TO SO- DIM M _ 1
1 .5 V
R1 8 2
1 K _ 1% _ 0 4
M V R E F _D I M1
R1 8 8
C 23 2
1 K _1 % _ 0 4
0 . 1 u_ 1 0 V _ X7 R _0 4
1. 5 V
C1 8 1
+
22 0 u _4 V _ V _ A
C1 9 6
C2 0 3
C2 1 0
C2 1 9
C 2 26
C 2 29
C 23 0
C1 9 1
1 0 u_ 6 . 3 V _ X5 R _0 6
1 0u _ 6 . 3 V _X 5 R _ 0 6
10 u _ 6 . 3V _X 5 R _ 0 6
4. 7 u _ 6. 3V _ Y 5V _0 6
4 . 7 u _ 6. 3 V _ Y 5V _ 0 6
1 u _ 6. 3 V _ Y 5V _ 0 4
1 u _6 . 3 V _ Y 5 V _ 0 4
1 u _6 . 3 V _ Y 5 V _ 0 4
MV R E F _ D Q _ D I M 1 7
V T T_ M E M 8 , 3 7
1 . 5V 3, 8 , 1 9 , 3 7
3 . 3V S 3, 8, 1 0 . . 1 2 , 14 , 1 6 . . 2 4, 26 . . 3 5
1. 5 V
B - 10 DDR SO-DIMM_1 REV
C1 9 2
C 20 0
C 2 01
C 2 07
C 20 8
C 21 3
C2 1 4
C 2 20
C2 2 1
C 22 8
0. 2 2 u _ 10 V _ Y 5 V _ 0 4
0 . 2 2u _ 1 0 V _Y 5 V _ 04
0 . 1 u _ 10 V _ X 7 R _ 0 4
0 . 1 u _1 0 V _ X 7R _ 04
0 . 1 u _1 0 V _ X 7R _ 04
0 . 1 u_ 1 0 V _ X7 R _0 4
0 . 0 1u _ 5 0V _ X 7 R _ 0 4
0 . 0 1 u_ 5 0 V _ X7 R _0 4
0. 01 u _ 50 V _ X 7 R _ 0 4
0 . 0 1u _ 5 0 V _X 7 R _ 0 4
Schematic Diagrams
MXM 3.0 Master
MXM 3.0
MASTER
V I N _ M XM
P E X_ S T D _ S W # 1
2 2 P NL _ P W R_ E N
2 2 P N L _ B L _E N
22 L V D S _D D C _D A T
22 L V D S _D D C _C L K
12 M XM _ H D A R S T #
1 2 H D A _S D I N 1
R1 0
2 2 _0 4
Max: 0.5inch
26 , 3 2 S P D I F _O U T
P E G_ R X N 7
P E G_ R X P 7
C 43 7
C 43 6
0. 1u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _ X 7 R _ 0 4
Z 2 7 01
Z 2 7 02
P E G_ R X N 6
P E G_ R X P 6
C 43 5
C 43 4
0. 1u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _ X 7 R _ 0 4
Z 2 7 03
Z 2 7 04
P E G_ R X N 5
P E G_ R X P 5
C 43 3
C 43 2
0. 1u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _ X 7 R _ 0 4
Z 2 7 05
Z 2 7 06
P E G_ R X N 4
P E G_ R X P 4
C 43 1
C 43 0
0. 1u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _ X 7 R _ 0 4
Z 2 7 07
Z 2 7 08
P E G_ R X N 3
P E G_ R X P 3
C 42 9
C 42 8
0. 1u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _ X 7 R _ 0 4
Z 2 7 09
Z 2 7 10
P E G_ R X N 2
P E G_ R X P 2
C 42 7
C 42 6
0. 1u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _ X 7 R _ 0 4
Z 2 7 11
Z 2 7 12
P E G_ R X N 1
P E G_ R X P 1
C 42 5
C 42 4
0. 1u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _ X 7 R _ 0 4
Z 2 7 13
Z 2 7 14
0. 1u _ 1 0V _ X 7 R _ 0 4
0. 1u _ 1 0V _ X 7 R _ 0 4
Z 2 7 15
Z 2 7 16
P E G_ R X N 0
P E G_ R X P 0
C 42 3
C 42 2
w it hin 5 00 mil s
M X M1 _ S MD
CLOSE T O MXM PINE2
Q3 5
MT N 7 0 0 2Z H S 3
Q3 4
MT N 7 0 0 2Z H S 3
S
M X M1 _ S MC
R3 3 7
J _M X M2 B
G
* 10 u _ 25 V _ N P O _ 12
G
10 u _ 25 V _ N P O_ 1 2
1 3 C L K _ P C I E _M X M1 #
1 3 C LK _ P C I E _ MX M1
D
S
S M D _ T H E R M_ 2 2 3, 3 1
D
2 2 L V DS _ U CL K N
2 2 L V DS _ U CL K P
S M C _ T H E R M_ 2 2 3, 3 1
22 L V D S _U 2N
22 L V D S _U 2P
47 K _ 0 4
3 .3 V S
MX M 1_ P R S N T # 17 , 3 1
22 L V D S _U 1N
22 L V D S _U 1P
A L L _ S Y S _ P W R GD
22 L V D S _U 0N
22 L V D S _U 0P
V GA _P W R GD 1
R 33 6
1 0 K _ 04
2 4 H D MI _ C # 2
24 H D M I _C 2
3 .3 V S
A C / B A TL # 1 1, 3 1
T H _ OV E R T #1
T H_ A L E RT # 1
MX M 1_ S M D
MX M 1_ S M C
11 , 1 4 , 2 1, 2 2 , 2 4
2 4 H D MI _ C # 1
24 H D M I _C 1
R 33 5
R 33 4
2 . 2 K _ 04
2 . 2 K _ 04
3 .3 V S
R 33 9
R 33 8
4 . 7 K _ 04
4 . 7 K _ 04
3 .3 V S
2 4 H D MI _ C # 0
24 H D M I _C 0
2 4 H D MI _ C C L K #
2 4 H D MI _ C C L K
2 4 H D MI _ C _S D A
2 4 H D MI _ C _S C L
M XM _ B I T C L K 1 2
M XM _ S D O U T 1 2
M XM _ S Y N C 1 2
H D MI _ S 1 2 4
P E G_ T X N [ 0 . . 7 ]
P E G_ T XN [ 0 . . 7]
2
2 1 DV I_ D# 2
2 1 D V I _D 2
P E G_ T X P [ 0 . . 7]
P E G_ T XP [ 0 . . 7 ] 2
P E G_ R XN [ 0 . . 7]
P E G_ R X N [ 0 . . 7 ] 2
2 1 DV I_ D# 1
2 1 D V I _D 1
P E G_ R XP [ 0 . . 7 ]
P E G_ R X P [ 0 . . 7 ] 2
2 1 DV I_ D# 0
2 1 D V I _D 0
2 1 DV I_ CL K #
2 1 D V I _C LK
3. 3 V S
T H _O V E R T # 1
2 1 D V I _ D D C _D A T
2 1 D V I _ D D C _C LK
1
P E G_ T XN 7
P E G_ T XP 7
4
P E G_ T XN 5
P E G_ T XP 5
P E X_ R E F C L K #
P E X_ R E F C L K
G ND
R SVD
R SVD
R SVD
R SVD
R SVD
L V D S _ UCL K #
L V D S _ UCL K
G ND
L V D S _ U T X3 #
L V D S _ U T X3
G ND
L V D S _ U T X2 #
L V D S _ U T X2
G ND
L V D S _ U T X1 #
L V D S _ U T X1
G ND
L V D S _ U T X0 #
L V D S _ U T X0
G ND
D P _ C _ L 0#
D P _ C_ L 0
G ND
D P _ C _ L 1#
D P _ C_ L 1
G ND
D P _ C _ L 2#
D P _ C_ L 2
G ND
D P _ C _ L 3#
D P _ C_ L 3
G ND
D P _ C_ A UX #
D P _ C_ A UX
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
R SVD
G ND
D P _ A _ L0 #
D P _ A _ L0
G ND
D P _ A _ L1 #
D P _ A _ L1
G ND
D P _ A _ L2 #
D P _ A _ L2
G ND
D P _ A _ L3 #
D P _ A _ L3
G ND
D P _ A _ A UX #
D P _ A _ A UX
P R S NT _ L #
CL K _ RE Q #
P E X _R S T #
V GA _ D D C _ D A T
V GA _ D D C _ C LK
V GA _ V S Y N C
V G A _H S Y N C
GN D
V G A _R E D
V GA _ GR E E N
V GA _ B L U E
GN D
L V D S _ LC L K #
L V D S _L C LK
GN D
L V D S _ LT X 3 #
L V D S _L T X 3
GN D
L V D S _ LT X 2 #
L V D S _L T X 2
GN D
L V D S _ LT X 1 #
L V D S _L T X 1
GN D
L V D S _ LT X 0 #
L V D S _L T X 0
GN D
DP _ D_ L 0 #
D P _ D_ L 0
GN D
DP _ D_ L 1 #
D P _ D_ L 1
GN D
DP _ D_ L 2 #
D P _ D_ L 2
GN D
DP _ D_ L 3 #
D P _ D_ L 3
GN D
D P _ D _A U X #
DP _ D_ A U X
D P _ C _H P D
D P _ D _H P D
R SVD
R SVD
R SVD
GN D
D P _B _ L 0 #
DP _ B _ L 0
GN D
D P _B _ L 1 #
DP _ B _ L 1
GN D
D P _B _ L 2 #
DP _ B _ L 2
GN D
D P _B _ L 3 #
DP _ B _ L 3
GN D
D P _B _A U X #
DP _ B _ A U X
D P _ B _H P D
D P _ A _H P D
3 V3
3 V3
15 4
15 6
15 8
16 0
16 2
16 4
16 6
16 8
17 0
17 2
17 4
17 6
17 8
18 0
18 2
18 4
18 6
18 8
19 0
19 2
19 4
19 6
19 8
20 0
20 2
20 4
20 6
20 8
21 0
21 2
21 4
21 6
21 8
22 0
22 2
22 4
22 6
22 8
23 0
23 2
23 4
23 6
23 8
24 0
24 2
24 4
24 6
24 8
25 0
25 2
25 4
25 6
25 8
26 0
26 2
26 4
26 6
26 8
27 0
27 2
27 4
27 6
27 8
28 0
MX M1 _ C L K R E Q# 1 3
V GA _ V S Y N C 2 1
V GA _ H S Y N C 2 1
V GA _ R 21
V GA _ G 21
V GA _ B 2 1
L V D S _ L C L K N 22
L V DS _ L CL K P 2 2
L V D S _ L 2N
L V D S _ L 2P
22
22
L V D S _ L 1N
L V D S _ L 1P
22
22
L V D S _ L 0N
L V D S _ L 0P
22
22
H D MI _ D # 2 2 4
H D MI _ D 2 2 4
H D MI _ D # 1 2 4
H D MI _ D 1 2 4
H D MI _ D # 0 2 4
H D MI _ D 0 2 4
Sheet 10 of 55
MXM 3.0 Master
H D MI _ D C L K # 24
H D MI _ D C L K 2 4
HD
HD
HD
HD
MI _ D _ S D A 2 4
MI _ D _ S C L 24
MI _ C H P D 2 4
MI _ D H P D 2 4
D V I _ D #5 2 1
DV I_ D 5 2 1
D V I _ D #4 2 1
DV I_ D 4 2 1
D V I _ D #3 2 1
DV I_ D 3 2 1
DV I_ H P D 2 1
3 V R UN
MX M _T H _ O V E R T # 3 3
2
1 1 TH _ OV E R T# 2
P E G_ T XN 6
P E G_ T XP 6
1 53
1 55
1 57
1 59
1 61
1 63
1 65
1 67
1 69
1 71
1 73
1 75
1 77
1 79
1 81
1 83
1 85
1 87
1 89
1 91
1 93
1 95
1 97
1 99
2 01
2 03
2 05
2 07
2 09
2 11
2 13
2 15
2 17
2 19
2 21
2 23
2 25
2 27
2 29
2 31
2 33
2 35
2 37
2 39
2 41
2 43
2 45
2 47
2 49
2 51
2 53
2 55
2 57
2 59
2 61
2 63
2 65
2 67
2 69
2 71
2 73
2 75
2 77
2 79
2 81
MXM3 .0 MOD ULE BOARD CONN EC TOR
R5
*1 0 mi l _ 04
C 3
5
RA
1 1 , 16 P E G _ R S T #
5 VS
C4
3
Stuff
E 2 -1
E 2 -2
E 2 -3
E 2 -4
E 2 -5
E 2 -6
E 2 -7
E 2 -8
E 2 -9
E 2 -10
E 4 -1
E 4 -2
E 4 -3
E 4 -4
E 4 -5
E 4 -6
E 4 -7
E 4 -8
E 4 -9
E 4 -10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
10 0
10 2
10 4
10 6
10 8
11 0
11 2
11 4
11 6
11 8
12 0
12 2
12 4
13 4
13 6
13 8
14 0
14 2
14 4
14 6
14 8
15 0
15 2
S TE C H -B 3 5 P 1 0 1-0 1 1 21 -H
U3 6
74 A H C 1 G0 8 GW
? ?
3. 3 V S
P E G_ T XN 4
P E G_ T XP 4
5
High swing
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
P R S N T _R #
W A KE#
P W R _ GO OD
P W R_ E N
R SVD
R SVD
R SVD
R SVD
P W R _ LE V E L
T H _ OV E R T #
TH _ A LE R T #
T H_ P W M
GP I O 0
GP I O 1
GP I O 2
S MB _ D A T
S MB _ C LK
G ND
O EM
O EM
O EM
O EM
G ND
P E X _ TX 1 5 #
P E X _T X 1 5
G ND
P E X _ TX 1 4 #
P E X _T X 1 4
G ND
P E X _ TX 1 3 #
P E X _T X 1 3
G ND
P E X _ TX 1 2 #
P E X _T X 1 2
G ND
P E X _ TX 1 1 #
P E X _T X 1 1
G ND
P E X _ TX 1 0 #
P E X _T X 1 0
G ND
P E X _T X 9 #
P E X_ T X 9
G ND
P E X _T X 8 #
P E X_ T X 8
G ND
P E X _T X 7 #
P E X_ T X 7
G ND
P E X _T X 6 #
P E X_ T X 6
G ND
P E X _T X 5 #
P E X_ T X 5
G ND
P E X _T X 4 #
P E X_ T X 4
G ND
P E X _T X 3 #
P E X_ T X 3
G ND
G ND
P E X _T X 2 #
P E X_ T X 2
G ND
P E X _T X 1 #
P E X_ T X 1
G ND
P E X _T X 0 #
P E X_ T X 0
G ND
T H_ A L E RT # 1
1
P E G_ T XN 3
P E G_ T XP 3
4
MX M _T H _ A L E R T# 3 3
2
1 1 TH _ A LE R T # 2
P E G_ T XN 2
P E G_ T XP 2
3 V RU N
U3 5
*7 4 A H C 1G 0 8G W
P E G_ T XN 1
P E G_ T XP 1
C 41 8
C4 1 7
4 . 7 u_ 2 5 V _ X5 R _ 0 8
*4 . 7 u_ 2 5 V _X 5 R _ 0 8
V I N _ MX M
P E G_ T XN 0
P E G_ T XP 0
CL OSE T O MXM CONN.
C2 8
S T E C H -B 3 5P 1 0 1 -01 1 2 1-H
??
10 u _ 25 V _ N P O_ 1 2
3 . 3 V 2 , 3 , 12 . . 1 4 , 1 6, 1 7 , 1 9, 2 2 , 2 5 , 28 , 2 9 , 35 . . 3 9
3 . 3 V S 3 , 8 , 9 , 11 , 1 2 , 14 , 1 6 . . 2 4, 2 6 . . 3 5
5 V S 1 1 , 1 9. . 21 , 2 3 . . 27 , 3 2 . . 3 5
V I N _ MX M 1 1
3 V R U N 11
5 V R U N _1 1 1
C 16
* 10 u _ 25 V _ N P O _ 12
5 V R UN_ 1
V I N _ MX M
CLOSE TO M XM PIN E1
C1 3
C 31
C4 1 0
C 41 2
C4 1 1
C 10
C1
C 41 6
C 41 3
4 . 7u _ 2 5V _ X 5 R _ 0 8
4 . 7 u _2 5 V _ X5 R _0 8
4. 7u _ 2 5V _ X 5 R _ 0 8
0 . 1 u _5 0 V _ Y 5 V _ 06
0. 1u _ 5 0V _ Y 5V _ 0 6
0 . 1 u _5 0 V _ Y 5 V _ 06
0. 1u _ 50 V _ Y 5V _ 0 6
0 . 0 1u _ 5 0V _X 7 R _ 0 4
0 . 0 1u _ 5 0V _X 7 R _ 0 4
C 29
C3 0
4 . 7 u_ 2 5 V _ X5 R _ 0 8
*4 . 7 u_ 2 5 V _X 5 R _ 0 8
CL OSE T O MXM CONN.
MXM 3.0 Master B - 11
B.Schematic Diagrams
Unstuff
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
3
5 V R U N _1
RA
P W R_ S RC
P W R_ S RC
P W R_ S RC
P W R_ S RC
P W R_ S RC
P W R_ S RC
P W R_ S RC
P W R_ S RC
P W R_ S RC
P W R_ S RC
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
5V
5V
5V
5V
5V
G ND
G ND
G ND
G ND
P E X_ S T D _ S W #
V GA _ D I S A B LE #
P NL _ P W R_ E N
P N L _ B L_ E N
P N L _ B L_ P W M
H DM I_ CEC
D V I_ HP D
L V D S _ DD C_ DA T
L V D S _ DD C_ CL K
G ND
O EM
O EM
O EM
O EM
G ND
P E X_ R X1 5 #
P E X_ R X1 5
G ND
P E X_ R X1 4 #
P E X_ R X1 4
G ND
P E X_ R X1 3 #
P E X_ R X1 3
G ND
P E X_ R X1 2 #
P E X_ R X1 2
G ND
P E X_ R X1 1 #
P E X_ R X1 1
G ND
P E X_ R X1 0 #
P E X_ R X1 0
G ND
P E X_ R X9 #
P E X_ R X9
G ND
P E X_ R X8 #
P E X_ R X8
G ND
P E X_ R X7 #
P E X_ R X7
G ND
P E X_ R X6 #
P E X_ R X6
G ND
P E X_ R X5 #
P E X_ R X5
G ND
P E X_ R X4 #
P E X_ R X4
G ND
P E X_ R X3 #
P E X_ R X3
G ND
G ND
P E X_ R X2 #
P E X_ R X2
G ND
P E X_ R X1 #
P E X_ R X1
G ND
P E X_ R X0 #
P E X_ R X0
G ND
M X M 3.0 MOD U LE BO AR D CO NN E C TO R
PWR_SRC(10A)--7-20V
5VRUN(2.5A)--5V
3VRUN(1A)--3.3V
Low swing
V I N _ MX M
J _ MX M2 A
E 1- 1
E 1- 2
E 1- 3
E 1- 4
E 1- 5
E 1- 6
E 1- 7
E 1- 8
E 1- 9
E 1 -1 0
E 3- 1
E 3- 2
E 3- 3
E 3- 4
E 3- 5
E 3- 6
E 3- 7
E 3- 8
E 3- 9
E 3 -1 0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
133
135
137
139
141
143
145
147
149
151
Schematic Diagrams
MXM 3.0 Slave
Unstuff
High swing
15A
Stuff
RB
R1 2
*1 0 mi l _ 04
PE X _ ST D_ SW # 2
Sheet 11 of 55
MXM 3.0 Slave
P E G _R X N 1 5
P E G _R X P 15
C4 5 3
C4 5 2
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X 7R _0 4
P E G _R X N 1 4
P E G _R X P 14
C4 5 1
C4 5 0
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X 7R _0 4
P E G _R X N 1 3
P E G _R X P 13
C4 4 9
C4 4 8
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X 7R _0 4
P E G _R X N 1 2
P E G _R X P 12
C4 4 7
C4 4 6
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X 7R _0 4
P E G _R X N 1 1
P E G _R X P 11
C4 4 5
C4 4 4
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X 7R _0 4
P E G _R X N 1 0
P E G _R X P 10
C4 4 3
C4 4 2
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X 7R _0 4
P E G _R X N 9
P E G _R X P 9
C4 4 1
C4 4 0
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X 7R _0 4
P E G _R X N 8
P E G _R X P 8
C4 3 9
C4 3 8
0 . 1 u _1 0 V _ X 7R _0 4
0 . 1 u _1 0 V _ X 7R _0 4
w ithi n 50 0m ils
C 4 05
* 0. 01 u _ 50 V _ X 7R _ 04
2A
15A
V I N _ MX M
C4 1 9
C5
C2
C2 2
*1 0 u_ 1 0 V _ Y 5 V _ 08
*0 . 1 u _1 6 V _ Y 5 V _ 0 4
0 . 1 u_ 1 6 V _Y 5 V _0 4
0. 0 1 u _1 6 V _ X 7R _0 4
*1 0 u_ 1 0 V _Y 5 V _ 08
R3 2 7
8
7
6
5
3
2
1
1 00 K _ 0 4
*2 2 _ 0 4
10 0 K _ 0 4
Q 5
S I 48 3 5 B D Y
D
S
2 0K _ 0 4
R5 0 0
Q4 8
*MT N 70 0 2 Z H S 3
G
R3 2 6
R 49 9
D
C3 8
4 7K _ 0 4
Q 30
M T N 7 0 02 Z H S 3
G
5V
R3 4 2
3. 3 V S
5 VS
MX M 2_ P R S N T # 1 7, 3 1
R 32 5
1 00 K _ 0 4
V GA _P W R G D 2
A L L _ S Y S _ P W R GD
1 0, 1 4 , 2 1 , 22 , 2 4
MX M2 _ S MD
MX M 2_ S M D
MX M 2_ S M C
2 .2 K _ 0 4
2 .2 K _ 0 4
R 1
R 2
4 .7 K _ 0 4
4 .7 K _ 0 4
3. 3 V S
MX M2 _ S MC
Q 1
M TN 7 00 2 Z H S 3
S
A C / B A T L # 10 , 3 1
T H _ OV E R T # 2 1 0
T H_ A L E RT # 2 1 0
R 3 40
R 3 41
Q 2
M TN 7 00 2 Z H S 3
D
S
D
S MD _ TH E R M _ 1 2 , 1 3 , 3 1
1 0 , 1 6 P E G_ R S T#
13 M XM 2 _C L K R E Q #
1 3 C L K _P C I E _ MX M 2#
1 3 C L K _ P C I E _ M XM 2
S MC _ TH E R M _ 1 2 , 1 3 , 3 1
3. 3 V S
5V S
R 11
2 .5 A
0 _0 8
5A
R 7
P E G_ T X N [ 8 . . 1 5 ]
P E G_ T XN [ 8 . . 1 5]
P E G_ T X P [ 8 . . 15 ]
5 V R U N _1
C1 7
C1 8
C 15
C 35
0 . 1 u_ 1 6 V _Y 5 V _ 04
0. 1 u _ 16 V _ Y 5 V _ 0 4
0 . 0 1u _ 1 6 V _X 7 R _ 0 4
* 10 u _ 10 V _ Y 5V _ 0 8
2 .5 A
0 _0 8
5 V R U N _2
C 20
C2 7
C2 6
C 21
C 25
* 1 0u _ 1 0V _ Y 5V _0 8
0 . 1 u_ 1 6 V _Y 5 V _ 04
0. 1 u _ 16 V _ Y 5 V _ 0 4
0 . 0 1u _ 1 6 V _X 7 R _ 0 4
* 10 u _ 10 V _ Y 5V _ 0 8
2
P E G_ T XP [ 8. . 1 5 ] 2
P E G_ R XN [ 8 . . 1 5]
P E G_ R X N [ 8. . 15 ] 2
P E G_ R XP [ 8. . 1 5 ]
P E G_ R X P [ 8 . . 1 5 ] 2
P E G_ T XN 1 5
P E G_ T XP 1 5
3 V RU N
V I N _ MX M
P E G_ T XN 1 4
P E G_ T XP 1 4
P E G_ T XN 1 3
P E G_ T XP 1 3
C9
C1 4
C1 9
C 33
4 . 7 u_ 2 5 V _X 5 R _ 0 8
*4 . 7 u_ 2 5 V _X 5 R _ 0 8
10 u _ 25 V _ N P O_ 1 2
* 10 u _ 25 V _ N P O_ 1 2
P E G_ T XN 1 2
P E G_ T XP 1 2
CLOSE TO MXM CONN.
P E G_ T XN 1 1
P E G_ T XP 1 1
5 V RU N_ 2
CLOSE TO M XM PIN E1
V I N _ MX M
P E G_ T XN 1 0
P E G_ T XP 1 0
P E G_ T XN 9
P E G_ T XP 9
C2 4
C2 3
C4 0 7
C 4 08
4 . 7 u_ 2 5 V _X 5 R _ 0 8
*4 . 7 u_ 2 5 V _X 5 R _ 0 8
10 u _ 25 V _ N P O_ 1 2
* 10 u _ 25 V _ N P O_ 1 2
P E G_ T XN 8
P E G_ T XP 8
CLOSE TO MXM CONN.
CL OSE T O MXM PINE2
S TE C H -B 35 P 1 0 1- 01 1 2 1-H
? ?
J _M XM 1 B
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
261
263
265
267
269
271
273
275
277
279
281
P E X_ R E F C L K #
P E X_ R E F C L K
GN D
RS V D
RS V D
RS V D
RS V D
RS V D
LV D S _ U C LK #
LV D S _ U C LK
GN D
LV D S _ U T X 3#
LV D S _ U T X 3
GN D
LV D S _ U T X 2#
LV D S _ U T X 2
GN D
LV D S _ U T X 1#
LV D S _ U T X 1
GN D
LV D S _ U T X 0#
LV D S _ U T X 0
GN D
DP _ C_ L 0 #
DP _ C_ L 0
GN D
DP _ C_ L 1 #
DP _ C_ L 1
GN D
DP _ C_ L 2 #
DP _ C_ L 2
GN D
DP _ C_ L 3 #
DP _ C_ L 3
GN D
D P _ C _ A U X#
DP _ C_ A U X
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
RS V D
GN D
D P _ A _ L0 #
D P _ A _ L0
GN D
D P _ A _ L1 #
D P _ A _ L1
GN D
D P _ A _ L2 #
D P _ A _ L2
GN D
D P _ A _ L3 #
D P _ A _ L3
GN D
DP _ A _ A UX #
DP _ A _ A UX
P R S N T_ L #
S T E C H -B 3 5P 1 0 1 -0 11 2 1 -H
??
V I N _ M XM
B - 12 MXM 3.0 Slave
Q6
S I 4 8 35 B D Y
8
3
7
2
6
1
5
4
2A
V IN
3V R U N
R9
0 _0 6
S
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
_S R C
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
GN D
P R S N T_ R #
W AK E#
P W R _ GOO D
P W R_ E N
R SVD
R SVD
R SVD
R SVD
P W R _ LE V E L
T H _ OV E R T #
TH _A LE R T #
TH _ P W M
GP I O 0
GP I O 1
GP I O 2
S MB _ D A T
S MB _ C LK
GN D
O EM
O EM
O EM
O EM
GN D
P E X _ TX 1 5 #
P E X _T X 1 5
GN D
P E X _ TX 1 4 #
P E X _T X 1 4
GN D
P E X _ TX 1 3 #
P E X _T X 1 3
GN D
P E X _ TX 1 2 #
P E X _T X 1 2
GN D
P E X _ TX 1 1 #
P E X _T X 1 1
GN D
P E X _ TX 1 0 #
P E X _T X 1 0
GN D
P E X _T X 9 #
P E X_ T X 9
GN D
P E X _T X 8 #
P E X_ T X 8
GN D
P E X _T X 7 #
P E X_ T X 7
GN D
P E X _T X 6 #
P E X_ T X 6
GN D
P E X _T X 5 #
P E X_ T X 5
GN D
P E X _T X 4 #
P E X_ T X 4
GN D
P E X _T X 3 #
P E X_ T X 3
GN D
GN D
P E X _T X 2 #
P E X_ T X 2
GN D
P E X _T X 1 #
P E X_ T X 1
GN D
P E X _T X 0 #
P E X_ T X 0
GN D
3. 3V S
G
swing
5 V RU N_ 2
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
PW R
E 2- 1
E 2- 2
E 2- 3
E 2- 4
E 2- 5
E 2- 6
E 2- 7
E 2- 8
E 2- 9
E 2- 10
E 4- 1
E 4- 2
E 4- 3
E 4- 4
E 4- 5
E 4- 6
E 4- 7
E 4- 8
E 4- 9
E 4- 10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
10 0
10 2
10 4
10 6
10 8
11 0
11 2
11 4
11 6
11 8
12 0
12 2
12 4
13 4
13 6
13 8
14 0
14 2
14 4
14 6
14 8
15 0
15 2
G
B.Schematic Diagrams
RB
P W R _ SRC
P W R _ SRC
P W R _ SRC
P W R _ SRC
P W R _ SRC
P W R _ SRC
P W R _ SRC
P W R _ SRC
P W R _ SRC
P W R _ SRC
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
5V
5V
5V
5V
5V
G ND
G ND
G ND
G ND
P EX _ S T D_ S W #
V G A _ DIS A B L E #
P N L _P W R _ E N
P N L _B L _ E N
P N L _B L _ P W M
H D M I _C E C
D VI_ HPD
L V D S _D D C _ D A T
L V D S _D D C _ C L K
G ND
O EM
O EM
O EM
O EM
G ND
P EX _ RX1 5 #
P EX _ RX1 5
G ND
P EX _ RX1 4 #
P EX _ RX1 4
G ND
P EX _ RX1 3 #
P EX _ RX1 3
G ND
P EX _ RX1 2 #
P EX _ RX1 2
G ND
P EX _ RX1 1 #
P EX _ RX1 1
G ND
P EX _ RX1 0 #
P EX _ RX1 0
G ND
P EX _ RX9 #
P EX _ RX9
G ND
P EX _ RX8 #
P EX _ RX8
G ND
P EX _ RX7 #
P EX _ RX7
G ND
P EX _ RX6 #
P EX _ RX6
G ND
P EX _ RX5 #
P EX _ RX5
G ND
P EX _ RX4 #
P EX _ RX4
G ND
P EX _ RX3 #
P EX _ RX3
G ND
G ND
P EX _ RX2 #
P EX _ RX2
G ND
P EX _ RX1 #
P EX _ RX1
G ND
P EX _ RX0 #
P EX _ RX0
G ND
M XM 3 .0 MOD U LE B O AR D CO NN E C T OR
PWR_SRC(10A)--7-20V
5VRUN(2.5A)--5V
3VRUN(1A)--3.3V
Low
V I N _ MX M
J _ MX M 1A
E 1 -1
E 1 -2
E 1 -3
E 1 -4
E 1 -5
E 1 -6
E 1 -7
E 1 -8
E 1 -9
E 1- 10
E 3 -1
E 3 -2
E 3 -3
E 3 -4
E 3 -5
E 3 -6
E 3 -7
E 3 -8
E 3 -9
E 3- 10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
1 01
1 03
1 05
1 07
1 09
1 11
1 13
1 15
1 17
1 19
1 21
1 23
1 25
1 33
1 35
1 37
1 39
1 41
1 43
1 45
1 47
1 49
1 51
MXM 3.0 MODULE BOAR D CONNECTOR
V I N _ MX M
4
MXM 3.0
SLAVE
C 34
C4 1 5
C 4 14
C4 2 1
C4 2 0
C 11
C8
C 37
C 36
4 . 7 u _2 5 V _ X5 R _0 8
4 . 7u _ 2 5V _ X 5 R _ 0 8
4 . 7 u _2 5 V _ X 5R _ 08
0 . 1 u_ 5 0 V _Y 5 V _0 6
0. 1 u _ 50 V _ Y 5 V _ 0 6
0 . 1 u_ 5 0 V _ Y 5 V _ 06
0. 1u _ 5 0V _ Y 5V _ 0 6
0 . 0 1 u_ 5 0 V _ X7 R _ 0 4
0 . 0 1 u_ 5 0 V _ X7 R _0 4
3 . 3V S 3 , 8. . 1 0 , 1 2 , 14 , 1 6 . . 2 4, 2 6 . . 3 5
5 V 1 9, 2 5 , 3 6 . . 39
5 V S 1 0, 19 . . 2 1 , 23 . . 2 7 , 3 2. . 35
V I N 22 , 3 4 . . 4 0
V I N _M XM 1 0
3 VRU N 1 0
5 V RU N_ 1 1 0
CL K _ RE Q #
P E X_ RS T #
V GA _ D D C _D A T
V GA _ D D C _C L K
V GA _ V S Y N C
V G A _ HSY NC
G ND
V G A_ RE D
V GA _ G R E E N
V GA _ B L U E
G ND
LV D S _ L C L K #
L V D S _ LC L K
G ND
LV D S _ L TX 3 #
L V D S _ LT X 3
G ND
LV D S _ L TX 2 #
L V D S _ LT X 2
G ND
LV D S _ L TX 1 #
L V D S _ LT X 1
G ND
LV D S _ L TX 0 #
L V D S _ LT X 0
G ND
D P _ D _L 0 #
DP _ D_ L 0
G ND
D P _ D _L 1 #
DP _ D_ L 1
G ND
D P _ D _L 2 #
DP _ D_ L 2
G ND
D P _ D _L 3 #
DP _ D_ L 3
G ND
D P _D _ A U X #
D P _ D _A U X
D P _C _ H P D
D P _D _ H P D
RS V D
RS V D
RS V D
G ND
D P _ B _L 0 #
D P _B _ L 0
G ND
D P _ B _L 1 #
D P _B _ L 1
G ND
D P _ B _L 2 #
D P _B _ L 2
G ND
D P _ B _L 3 #
D P _B _ L 3
G ND
D P _ B _ A UX#
D P _B _A U X
D P _ B_ HP D
D P _ A_ HP D
3 V3
3 V3
1 54
1 56
1 58
1 60
1 62
1 64
1 66
1 68
1 70
1 72
1 74
1 76
1 78
1 80
1 82
1 84
1 86
1 88
1 90
1 92
1 94
1 96
1 98
2 00
2 02
2 04
2 06
2 08
2 10
2 12
2 14
2 16
2 18
2 20
2 22
2 24
2 26
2 28
2 30
2 32
2 34
2 36
2 38
2 40
2 42
2 44
2 46
2 48
2 50
2 52
2 54
2 56
2 58
2 60
2 62
2 64
2 66
2 68
2 70
2 72
2 74
2 76
2 78
2 80
3V R U N
Schematic Diagrams
PCH 1/8 RTC, HDA, SATA
IBEXPEAK - M (HDA,JTAG,SATA)
RTCVCC
20 mils
C204
C
CM200
S32
7681220_32.768KHz
C184
JOPEN1
*OPEN_10mil-1M
M
C211
RTC_X1
RTC_X2
1
R130
C183
1M
_04
1
u_6.3V_X5R_04
TPM CLEAR
JOPEN2
*OPEN_10mil-1M
M
R178
RTCVCC
330K_04
R191
R190
R189
R187
26 HDA_BITCLK
10 MXM
_BITCLK
2
6 HDA_SYNC
1
0 M
XM_SYNC
26 HDA_SPKR
RTC_RST#
C14
SRTC_
RST#
D17
SM_INTRUDER#
A16
A14
PCH_INTVRMEN
A30
33_0
4
33_0
4
33_0
4
33_0
4
D29
R198
R197
C30
33_0
4
33_0
4
G
30
26 HDA_SDIN0
NO REBOOT STRAP
P1
HDA_SPKR
26,27 HDA_
RST#
1
0 M
XM_HDARST#
10 HDA_SDIN1
SERIRQ
HDA_SPKR
F32
NO REBOOT STRAP:
HDA_SPKR High Enable
R181
R179
33_0
4
33_0
4
B29
R447
1K_04
H32
1
26 HDA_SDOUT
10 MXM
_SDOUT
J30
JOPEN3
*O
PEN_10mil-1M
M
iTPM ENABLE/DISABLE
2
3.3VS
*1K_04
D33
B33
C32
A32
LPC_AD0 22,31
LPC_AD1 22,31
LPC_AD2 22,31
LPC_AD3 22,31
C34
LPC_FRAME# 22,31
FWH4 / LFRAME#
SRTCRST#
I NTRUDER#
I NTVRMEN
LDRQ0#
L
DRQ
1# / GPIO23
SERI RQ
HDA_BCLK
A34
F34
AB9
AK7
SATA0RXN
AK6
SATA0RXP AK11
SATA0
TXN AK9
SATA0TXP
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2 E32
R116
RTCRST#
F30
3.3VS
10K_04
*1K_04
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
SERIRQ
SERIRQ 22,31
2
BH800.9G
R408
R148
RTCX
1
RTCX
2
PCH_JTAG
_TCK_BUF M3
SPI_SI
TPM FUNCTION:
SPI_SI High Enable
PCH_JTAG
_TMS
K3
PCH_JTAG
_TDI
K1
PCH_JTAG
_TDO
J2
PCH_JTAG
_RST#
J4
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO1
3
JTAG_TM
S
JTAG_TDO
JTAG_RST#
SATA_
RXN0 32
SATA_
RXP0 32
SATA_
TXN0 32
SATA_
TXP0 3
2
HDD 1/2
AH6
SATA1RXN AH5
SATA1RXP
AH9
SATA1
TXN
AH8
SATA1TXP
SATA_
RXN1 25
SATA_
RXP1 25
SATA_
TXN1 25
SATA_
TXP1 2
5
SATA ODD
AF11
SATA2RXN AF9
SATA2RXP
AF7
SATA2
TXN
AF6
SATA2TXP
SATA_
RXN2 32
SATA_
RXP2 32
SATA_
TXN2 32
SATA_
TXP2 3
2
HDD 2/2
AH3
SATA3RXN
AH1
SATA3RXP
AF3
SATA3
TXN AF1
SATA3TXP
SATA_
RXN3 32
SATA_
RXP3 32
SATA_
TXN3 32
SATA_
TXP3 3
2
eSATA
AD9
SATA4RXN
AD8
SATA4RXP AD6
SATA4
TXN AD5
SATA4TXP
SATA_
RXN4 32
SATA_
RXP4 32
SATA_
TXN4 32
SATA_
TXP4 3
2
Sheet 12 of 55
PCH 1/8
RTC, HDA, SATA
HDDx1
AD3
SATA5RXN AD1
SATA5RXP AB3
SATA5
TXN
AB1
SATA5TXP
JTAG_TCK
JTAG_TDI
Zd iff = 9 0O
SATAICO
MPO
SATAI COM
PI
AF16
AF15
SATAICOM
P
R437
37.4_1%_04
1.1VS_VTT
Zo = 5 0O
3.3V
20K_04
PCH_JTAG
_RST#
R154
10K_04
R136
200_1%_04
PCH_JTAG
_TMS
R150
100
_04
SPI_CS0# R117
R138
200_1%_04
PCH_JTAG
_TDO
R123
100
_04
R137
200_1%_04
PCH_JTAG
_TDI
R151
100
_04
PCH_JTAG
_TCK_BUF R149
0_04
BA2
SPI_CS0
#_R
AV3
SPI_CS1
#_R
AY3
AY1
SPI_SI
SPI_SO
4.7K_04
R118
33_04
SPI_SO_R
AV1
3.3VS
SPI_CL
K
R147
SPI_CS0#
SPI_CS1#
SPI_MO
SI
SPI_MISO
IBEXPEAK-M
SATALED#
SPI
SPI_SCLK
R153
SATA0GP/ GPIO21
SATA1GP/ GPIO19
T3
10K_04
3.3VS
SATA_LED# 33
Y9
O
DD_
DETECT# 25
V1
SATA_DET#
1
R406
10K_04
R127
10K_04
3.3VS
R120
3.3VS
0_04
C169
J_SBSPI1
U9
8
VDD
R145
SI
SO
R115
3.3K_
1%_04
SPI_WP#
3
WP#
CE#
SCK
R121
1
2
7
8
0.1u_16V_Y5V_0
4
3.3K_
1%_04
SPI_HOLD# 7
HOLD#
VSS
5
SPI_SI
2
SPI_SO
1
SPI_CS0#
6
SPI_SCLK
JSPI1
*OPEN_35mil
SPI_CS0#_R
*3.3K_1%_04
SPI_CS#
_CON
SPI_SO_
R
J_SBSPI1
1
3
5
7
2
4
6
8
SPI_SCLK
SPI_SI
*SPNZ-08
S3-B-C-0-P
4
RTCVCC 1
9
1
.1
VS_VTT 3,5,6,13,14,17..20,35,36
VDD3 28,31..34,39,40
3
.3
VS 3,8..11,14,16..24,26..35
3
.3
V 2,3,13,14,16,17
,1
9,22,25,28,29,35..39
MX
25L1605DM2I-12G
SPI SOCKET
ACA-SPI-004-T03
SPI_* = 1.5"~6.5"
16 M
PCH 1/8 RTC, HDA, SATA B - 13
B.Schematic Diagrams
1
2
B13
D13
LPC
Z o= 50 O
Z o= 50 O
R129
20K_1%_04
J_
RTC
U14A
10M_04
15p_50V_NPO_04
RTC
1
u_6.3V_X5R_04
C179
RTC CLEAR
IHDA
1K_04
*1
u_6.3V_X5R_04
398905 DG1.5:
spacing > 15 mil
R175
SATA
A
X3
D14
RB751V-40
R1
43
Zo= 5 0O
15p_50V_NPO_04
JTAG
RTC_VBAT_1
C218
1
1 0mils
1u_6.3V_Y5
V_0
4
R128
20K_1%_04
2
1
C
D15
RB751V-40
3
4
A
2
2 0mils
VDD3
Schematic Diagrams
PCH 2/8 PCIE, SMBUS, CLK
IBEXPEAK - M (PCI-E,SMBUS,CLK)
30
30
30
30
Sheet 13 of 55
PCH 2/8
PCIE, SMBUS, CLK
P C IE _ R XN5 _ CR
P C I E _ R X P 5 _C R
P C IE _ T X N5 _ CR
P C I E _ T X P 5 _C R
A U3 0
AT3 0
A U3 2
AV3 2
C2 4 4
C2 4 1
0 . 1 u _ 10 V _X 7 R _ 04
0 . 1 u _ 10 V _X 7 R _ 04
P C I E _ TX N 4 _ C
P C I E _ TX P 4_ C
BA3 2
BB3 2
B D3 2
BE3 2
C2 4 2
C2 4 5
0 . 1 u _ 10 V _X 7 R _ 04
0 . 1 u _ 10 V _X 7 R _ 04
P C I E _ TX N 5 _ C
P C I E _ TX P 5_ C
BF3 3
B H3 3
B G3 2
BJ 3 2
BA3 4
AW 3 4
B C3 4
B D3 4
28
28
28
28
P C IE _ R XN7 _ T V
P C I E _ R X P 7 _T V
P C IE _ T X N7 _ T V
P C I E _ T X P 7 _T V
C2 5 8
C2 5 9
20 P C I E _R X N 8 _ H D M I _ I N
2 0 P C I E _ R X P 8 _ H D MI _ I N
2 0 P C IE _ T X N8 _ H DM I_ IN
2 0 P C I E _ T X P 8 _ H D MI _ I N
2 0 C L K _ P C IE _ HD M I_ IN#
2 0 CL K _ P C IE _ H DM I_ IN
0 . 1 u _ 10 V _X 7 R _ 04
0 . 1 u _ 10 V _X 7 R _ 04
C2 5 3
C2 4 7
100MHz 2
0 . 1 u _ 10 V _X 7 R _ 04
0 . 1 u _ 10 V _X 7 R _ 04
P C I E _ TX N 7 _ C
P C I E _ TX P 7_ C
AT3 4
A U3 4
A U3 6
AV3 6
P C I E _ TX N 8 _ C
P C I E _ TX P 8_ C
B G3 4
BJ 3 4
B G3 6
BJ 3 6
1
3
4
R N1 9
0 _ 4 P 2 R_ 0 4
C L K _ P C H_ S R C0 _ N
C L K _ P C H_ S R C0 _ P
AK4 8
AK4 7
1
2
4
3
R N1 8
0 _ 4 P 2 R_ 0 4
C L K _ P C H_ S R C1 _ N
C L K _ P C H_ S R C1 _ P
A M4 3
A M4 5
P9
20 H D MI _ I N _ C L K R E Q #
2 8 C L K _ P C I E _ W LA N #
2 8 C L K _ P C IE _ W L A N
100MHz
100MHz
1
2
4
3
R N1 7
0 _ 4 P 2 R_ 0 4
C L K _ P C H_ S R C2 _ N
C L K _ P C H_ S R C2 _ P
A M4 7
A M4 8
N4
2 8 NE W C A RD _ CL K R E Q #
100MHz
2
1
3
4
R N1 4
0 _ 4 P 2 R_ 0 4
R1 9 2
* 0 _0 4
R1 6 1
* 0 _0 4
C L K _ P C H_ S R C4 _ N
C L K _ P C H_ S R C4 _ P
L A N _C L K R E Q#
2 9 LA N _ C L K R E Q#
3 0 C L K _ P CI E _ CR #
3 0 C L K _ P C IE _ CR
SM BD ATA
P
P
P
P
E R N3
ER P3
E T N3
ETP3
P E R N4
P ER P4
P E T N4
P ETP4
P
P
P
P
S M L 0 A L E R T# / GP I O6 0
E R N5
ER P5
E T N5
ETP5
100MHz 2
1
3
4
R N1 2
0 _ 4 P 2 R_ 0 4
A H4 2
A H4 1
A8
A M5 1
A M5 3
M9
C L K _ P C H_ S R C5 _ N
C L K _ P C H_ S R C5 _ P
AJ 5 0
AJ 5 2
P C I E C L K R Q5 #
H6
P E R N6
P ER P6
P E T N6
P ETP6
100MHz 21
3
4
AK5 3
AK5 1
R N1 5
* 4P 2 R X 3 3 _ 04 _ S H OR T
MX M 2_ C L K R E Q#
1 1 M X M2 _ C L K R E Q#
P1 3
E R N7
ER P7
E T N7
ETP7
P
P
P
P
E R N8
ER P8
E T N8
ETP8
Port
Port
Port
Port
Port
Port
Port
Port
B - 14 PCH 2/8 PCIE, SMBUS, CLK
0
1
2
3
4
5
6
7
S M L 1 A L E R T# / GP I O7 4
S M L 1D A T A / GP I O7 5
C L _C L K 1
CL _ D A T A 1
C L _ RS T 1 #
C L K O U T_ P E G_ A _ N
C L K OU T _ P E G _ A _ P
C L K O U T _ D MI _ N
C LK OU T _ D M I _ P
C LK OU T _ D P _ N / C L K OU T _ B C LK 1_ N
C L K O U T_ D P _ P / C L K O U T _ B C L K 1 _ P
C L K O UT _ PC IE 0 N
C L K O UT _ PC IE 0 P
P C I E C L K R Q0 # / GP I O 7 3
C L K O UT _ PC IE 1 N
C L K O UT _ PC IE 1 P
C L K O UT _ PC IE 2 N
C L K O UT _ PC IE 2 P
C L K O UT _ PC IE 3 N
C L K O UT _ PC IE 3 P
C L K I N _ D O T _ 96 N
C L K I N _ D OT _ 9 6 P
C L K I N _P C I L O OP B A C K
C L K O UT _ PC IE 4 N
C L K O UT _ PC IE 4 P
X T A L 2 5_ I N
XT A L 2 5 _ OU T
P C I E C L K R Q4 # / GP I O 2 6
X C L K _ R C OM P
C L K O UT _ PC IE 5 N
C L K O UT _ PC IE 5 P
P E G _B _C L K R Q# / G P I O 5 6
C L K IN _ B CL K _ N
CL K IN _ B C L K _ P
R E F C L K 14 I N
P C I E C L K R Q3 # / GP I O 2 5
C L K O UT _ PE G _ B _ N
C L K O UT _ PE G _ B _ P
C LK I N _ D MI _ N
C L KIN _ DM I_ P
C L KIN _ S A T A _ N / C K S S C D_ N
C L K I N _S A T A _ P / C K S S C D _ P
P C I E C L K R Q2 # / GP I O 2 0
I B E X P E A K -M
PCI-E x1
S ML 0 D A T A
B 9
P CH _ B T _ EN#
H 14
S MB _ C L K _ D D R 3
C 8
S MB _ D A T A _ D D R 3
S M B _ CL K _ D DR 3 8 ,9 ,2 0 ,3 5
P C H _ U P E K _ I N I T#
C 6
S ML 0 _ C L K
G 8
S ML 0 _ D A TA
S M L 0_ C L K 2 8
S M L 0_ D A T A 2 8
M 14
L P D _ S P I_ IN T R#
E 10
S ML 1 _ C L K
R4 1 7
G 12
S ML 1 _ D A TA
R4 2 5
0 _0 4
C L K O U T F LE X0 / GP I O6 4
S M D _T H E R M_ 1 2 , 1 1 , 3 1
CL _ C L K 1 2 8
T11
CL _ D A T A 1 2 8
T9
M X M1 _ C L K R E Q#
A D4 3
A D4 5
C L K _ P C H _ P E GA _ N
C L K _ P C H _ P E GA _ P
3
4
100MHz
RN 2 0
*4 P 2 R X3 3 _ 0 4 _ S H O R T
100MHz
1 0 K_ 0 4
S M L0 _ C L K
R4 2 6
2 .2 K _ 0 4
S M L0 _ D A T A
R4 2 2
2 .2 K _ 0 4
L P D_ S P I_ INT R #
R4 4 0
1 0 K_ 0 4
S M L1 _ C L K
R4 2 0
2 .2 K _ 0 4
S M L1 _ D A T A
R4 2 9
2 .2 K _ 0 4
P C IE CL K RQ 5 #
R3 9 7
1 0 K_ 0 4
MX M 1 _C L K R E Q #
R1 5 2
1 0 K_ 0 4
MX M 2 _C L K R E Q #
R4 3 2
1 0 K_ 0 4
C L K _ P C I E _ MX M 1 # 1 0
C L K _ P C I E _ MX M 1 1 0
C L K_ EXP_ N 3
C L K_ EXP_ P 3
P CH _ CL K _ D P _ N_ R
P CH _ CL K _ D P _ P _ R
A W24
B A2 4
100MHz
A P3
A P1
133MHz
F 18
E 18
96MHz
100MHz
14.318MHz
33MHz
A H5 1
A H5 3
X T A L 2 5 _ IN
X T A L 2 5 _ OU T
A F3 8
X C L K _ R C OM P
T45
2 .2 K _ 0 4
R4 4 5
MX M 1 _ C L K R E Q # 1 0
2
1
A N4
A N2
J42
2 .2 K _ 0 4
R1 5 9
P C H_ U P E K _ IN IT #
CL _ R S T # 1 2 8
H 1
P 41
R4 3 4
S M B_ DA T A _ D D R3
S M C _T H E R M_ 1 2 , 1 1 , 3 1
0 _0 4
T13
A H1 3
A H1 2
S M B_ CL K _ D DR 3
S M B _ D A T A _D D R 3 8 , 9 , 2 0 , 3 5
J14
A T1
A T3
1 0 K_ 0 4
P C H_ B T _ E N # 2 5
P E G _ A _ C L K R Q# / GP I O4 7
P
P
P
P
P C I E C L K R Q5 # / GP I O 4 4
11 C L K _ P C I E _ M XM 2 #
1 1 C L K _ P C I E _ M X M2
S M L0 C L K
S M L 1 C L K / GP I O5 8
P C I E C L K R Q1 # / GP I O 1 8
Onl y PC IECLK RQ [2 :1 ]# on PCH a re core w e l l
pow e re d. A ll ot he r PC IECLK RQ x # a re suspe nd
w e ll pow e re d.
29 C L K _ P C I E _ G LA N #
2 9 C LK _P C I E _G L A N
E R N2
ER P2
E T N2
ETP2
SM BC L K
U4
2 8 W L A N _ CL KR E Q #
2 8 C L K _ P C IE _ NE W _ CA RD #
28 C L K _ P C I E _ N E W _ C A R D
P
P
P
P
S M B A L E R T# / GP I O1 1
R1 6 2
CL K _ P CIE _ IC H # 2 0
CL K _ P CIE _ IC H 2 0
CL K _ B UF _ B C L K _ N 2 0
CL K _ B UF _ B C L K _ P 2 0
C L K _ B U F _ D OT 9 6 _ N 20
C L K _ B U F _ D OT 9 6 _ P 2 0
Checklist 1.6 ? ? ? ?
CL K _ S A T A # 2 0
CL K _ S A T A 2 0
C 276
CL K _ B UF _ R EF 1 4 2 0
R2 2 1
CL K _ P CI_ F B
16
*1 M _ 04
X4
*X 8 A 0 2 5 0 00 F G1 H _2 5 M H z
C 275
R 456
90 . 9 _ 1 % _ 0 4
0 _0 4
1
*0 _ 0 4
E R N1
ER P1
E T N1
ETP1
P C H_ B T _ E N #
2
*0 _ 0 4
R1 9 6
AW 3 0
BA3 0
B C3 0
B D3 0
P
P
P
P
SMBus
R1 9 3
2 9 P C I E _R X N 4 _ G L A N
2 9 P C I E _R X P 4 _ GL A N
2 9 P C IE _ T X N4 _ G L A N
2 9 P C I E _ T X P 4 _ GL A N
P C I E _ TX N 2 _ C
P C I E _ TX P 2_ C
0 . 1 u _ 10 V _X 7 R _ 04
0 . 1 u _ 10 V _X 7 R _ 04
B G3 0
BJ 3 0
BF2 9
B H2 9
Link
C2 4 6
C2 4 3
P C I E _ TX N 1 _ C
P C I E _ TX P 1_ C
PCI-E*
B.Schematic Diagrams
2 8 P C IE _ R X N2 _ N E W _ C A RD
2 8 P C IE _ R X P 2 _ NE W _ CA R D
2 8 P C IE _ T X N2 _ N E W _ C A RD
2 8 P C IE _ T X P 2 _ NE W _ CA R D
0 . 1 u _ 10 V _X 7 R _ 04
0 . 1 u _ 10 V _X 7 R _ 04
Co n tr ol l er
C2 4 0
C2 3 8
PEG
1 _ W L AN
1_ W LA N
1 _ W L AN
1_ W LA N
From CLK BUFFER
P C IE _ RX N
P C IE _ RX P
P C I E _ TX N
P C I E _ TX P
Clock Flex
28
28
28
28
3 .3 V
SMB us
Zo= 50 O
U1 4 B
*1 5 p _ 50 V _N P O _ 0 4
1 .1 V S _ V T T
90.9-O ? % pullup to +VccIO
(1.05V, S0 rail)
P 43
C L K O U T F LE X1 / GP I O6 5
C L K O U T F LE X2 / GP I O6 6
C L K O U T F LE X3 / GP I O6 7
T42
N 50
C L K _ DO C0 2 0
C L K _ DO C1 2 0
RSVD. for ICS9LVS3158
Usage
WLAN
NEW ARD
X
GLAN
CARD READER
X
TV
HDMI IN
5 V 1 1 , 1 9, 25 , 3 6 . . 3 9
3 . 3V S 3 , 8 . . 1 2 , 1 4 , 1 6 . . 2 4, 26 . . 3 5
1 . 1V S _ V T T 3 , 5 , 6 , 1 2 , 14 , 1 7 . . 2 0 , 3 5 , 3 6
3 . 3V 2 , 3 , 1 2 , 1 4, 1 6 , 1 7 , 1 9 , 2 2 , 2 5, 28 , 2 9 , 3 5 . . 3 9
Schematic Diagrams
PCH 3/8 DMI, PWRGD
A ub ur nd al e Gr ap hi cs Di sa bl e Gu id el in e
I n ad di ti on , FD I_ RX N_[ 7: 0] a nd F DI _R XP _[ 7: 0] c an b e le ft
f lo at in g on t he P CH .
F DI _T X[ 7: 0] a nd F DI _TX #[ 7: 0] c an b e le ft f lo at in g on t he
A ub ur nd al e
T he G FX _I MO N, F DI _F SYN C[ 0] , FD I_ FS YN C[ 1] , FD I_ LS YN C[ 0] ,
F DI _L SY NC [1 ], a nd
F DI _I NT s ig na ls s ho uld b e ti ed t o GN D (t hr ou gh 1 K ? %
r es is to rs ) in t he c omm on
m ot he rb oa rd d es ig n cas e. P le as e no t th at i f th es e si gn als
a re l ef t fl oa ti ng , the re a re n o
f un ct io na l im pa ct s but a s ma ll a mo un t of p ow er ( ~1 5 mW )
m ay be w as te d. V AX G_ SEN SE
a nd V SS AX G_ SE NS E on Au bu rn da le c an b e le ft a s no c on ne ct.
IBEXPEAK - M (DMI,FDI,GPIO)
U1 4 C
BE2 2
BF2 1
BD 2 0
BE1 8
2 D MI _ T XN 0
2 D MI _ T XN 1
2 D MI _ T XN 2
2 D MI _ T XN 3
1 .1 V S_ V T T
R1 8 4
4 9 . 9 _1 % _ 0 4
BH 2 5
D M I _ C O MP _ R
BF2 5
3 98 90 5 DG 1. 5:
4 m il w id th a nd p la ce
w it hi n 50 0 mi l of P CH
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
D M I 0T X N
D M I 1T X N
D M I 2T X N
D M I 3T X N
DM
DM
DM
DM
I_ RX N
I_ RX N
I_ RX N
I_ RX N
I_ RX N
I_ RX N
I_ RX N
I_ RX N
I 0T X P
I 1T X P
I 2T X P
I 3T X P
D M I _Z C O MP
XP
XP
XP
XP
XP
XP
XP
XP
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
F DI_ IN T
F DI_ F SY NC 0
F DI_ F SY NC 1
D M I _I R C OMP
F DI_ L SY NC 0
F DI_ L SY NC 1
BA1 8
B H1 7
B D1 6
B J 16
BA1 6
BE1 4
BA1 4
B C1 2
BB1 8
BF1 7
B C1 6
B G1 6
AW 1 6
B D1 4
BB1 4
B D1 2
B J 14
F D I _ I N T_ R
BF1 3
F D I _ F S Y N C 0 _R
B H1 3
F D I _ F S Y N C 1 _R
B J 12
F DI_ L S Y N C0 _ R
B G1 4
F DI_ L S Y N C1 _ R
J1 2
P CIE _ W A K E #
R1 7 7
* 1K _0 4
RN 7
4
3
2
1
5
6
7
8
Sheet 14 of 55
PCH 3/8
DMI, PWRGD
* 1K _ 8 P 4 R _ 0 4
FOR RESET SWITCH (? ? ? )
R4 1 5
3 .3 VS
3 .3 V
1 0 K _ 04
T6
SYS_ R ESET #
A L L _S Y S _ P W R GD
S Y S _ P W R OK
S Y S _ P W R OK
R 114
* 20 m i _l P _ 0 4
S B _P W R O K
S B _P W R O K
R 113
* 20 m i _l P _ 0 4
P M _ MP W R OK
M6
B1 7
S Y S _ P W R OK
P W RO K
12
11
K 5
P M_ MP W R O K
13
R1 6 5
7
3 ,3 5 DE L A Y _ P W RG D
1 0K _0 4
A U X P P W R OK _ R
A1 0
R1 1 0
1 0K _0 4
D 9
3 P M _D R A M_ P W R GD
3 1 R S MR S T#
SUS_PWR_DN_ACK is Active-high and
is driven low by the Intel ME when
it requires the PCH Suspend Well to
be powered.
3 1 S US _ P W R_ A CK
C 16
R1 7 3
1 0K _0 4
R1 2 5
0 _0 4
3 1 P W R _B TN #
3 .3 V
R4 1 8
1 0K _0 4
INTEL? ? ? ? EC
S US _ P W R _ A CK _ R
M1
P W R_ B T N#
P 5
A C_ P R E S E NT _ R
P 7
P M_ B A T L OW #
A 6
S W I#
3 1 S W I#
F14
ME P W R O K
LA N _ R S T #
D R A MP W R O K
RS M RS T #
S U S _ P W R _ A C K / GP I O 3 0
P W R B TN #
System Power Management
14
U 7D
7 4 LV C 0 8 P W
* 20 m i _l P _ 0 4
P C IE _ W A K E# 2 8 ,2 9
W AKE #
R1 2 6
R 111
C L K R U N # / GP I O 3 2
S U S _ S T A T # / GP I O 6 1
S U S C LK / GP I O 6 2
S L P _ S 5 # / GP I O 6 3
SL P_ S4 #
SL P_ S3 #
SL P_ M #
A C P R E S E N T / GP I O 3 1
T P2 3
B A T LO W # / G P I O7 2
P MS Y N C H
GP IO29 / S L P _ L A N
RI#
#
8 .2 K _ 0 4
3 .3 VS
P M _ CL KRU N# 2 2
Y1
3 .3 V
FO R TP M
P8
S 4 _ S T A T E # 22
F3
P CIE _ W A K E #
R 4 35
10 K _ 0 4
S W I#
R 4 38
10 K _ 0 4
S US_ P W R _ A CK_ R
R 1 35
10 K _ 0 4
P W R_ B T N #
R 4 14
*1 0 K _ 04
P M_ B A T L OW #
R 1 58
10 K _ 0 4
E4
H7
S U S C # 3 1 , 3 4, 3 7
P1 2
S U S B # 2 0, 28 , 3 1 , 3 4, 3 6
K8
N2
B J 10
F6
H _P M_ S Y N C 3
P M _S LP _ L A N #
R 4 00
*1 0 K _0 4
3 .3 V
A C _P R E S E N T _ R
The ACPRESENT pin is used by
EC to indicate to the Intel
ME the current power source
of the system.
3 .3 V
3. 3 V
14
C 15 9
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
3 8 1. 8V S _P W R G D
3 .3 V
U 7B
7 4 L V C0 8 P W
4
14
G
S
3, 3 6 1 . 1 V S _ V T T_ P W R G D
6
U7 C
7 4L V C 0 8P W
9
8
A L L _ S Y S _ P W R GD
10
A L L_ S Y S _ P W R GD
10 , 1 1 , 2 1, 22 , 2 4
37 D D R 1. 5V _ P W R G D
3 8 1 .5 VS _ PW RG D
36
7
1 . 1 V S _ V T T_ E N
R1 0 8
2 K_ 0 4
H _ V T T P W R GD
7
14
5
U 7A
7 4 LV C 0 8 P W
1
3
1 . 1 V S _ 1 . 5 V _P W R O K
R 1 05
2
3
3 . 3 V S 3 , 8 . . 1 2, 16 . . 2 4 , 2 6. . 35
3 . 3 V 2 , 3 , 12 , 1 3 , 1 6, 17 , 1 9 , 2 2, 2 5 , 2 8 , 29 , 3 5 . . 3 9
1 . 1 V S _ V T T 3, 5 , 6 , 1 2 , 1 3, 1 7 . . 2 0 , 35 , 3 6
1 K_ 0 4
7
3 1 ,4 0 AC_ IN #
I B E X P E A K -M
D
Q3 7
*M T N 7 0 02 Z H S 3
PCH 3/8 DMI, PWRGD B - 15
B.Schematic Diagrams
BD 2 2
BH 2 1
BC 2 0
BD 1 8
2 D MI _ T XP 0
2 D MI _ T XP 1
2 D MI _ T XP 2
2 D MI _ T XP 3
D M I 0R X P
D M I 1R X P
D M I 2R X P
D M I 3R X P
FDI
BD 2 4
BG 2 2
BA2 0
BG 2 0
2 D MI _ R XP 0
2 D MI _ R XP 1
2 D MI _ R XP 2
2 D MI _ R XP 3
FD
FD
FD
FD
FD
FD
FD
FD
D M I 0R X N
D M I 1R X N
D M I 2R X N
D M I 3R X N
DMI
BC 2 4
BJ 2 2
AW 2 0
BJ 2 0
2 D MI _ R XN 0
2 D MI _ R XN 1
2 D MI _ R XN 2
2 D MI _ R XN 3
Schematic Diagrams
PCH 4/8 LVDS, DDI, GND
IBEXPEAK - M (GND)
U 1 4I
IBEXPEAK - M (LVDS,DDI)
AB4 6
V4 8
Sheet 15 of 55
PCH 4/8
LVDS, DDI GND
AP3 9
AP4 1
A T4 3
A T4 2
AV5 3
AV5 1
BB4 7
BA5 2
AY4 8
AV4 7
BB4 8
BA5 0
AY4 9
AV4 8
AP4 8
AP4 7
AY5 3
A T4 9
A U5 2
A T5 3
AY5 1
A T4 8
A U5 0
A T5 1
AA5 2
AB5 3
A D5 3
V5 1
V5 3
Y5 3
Y5 1
R 46 0
1 K _ 1 % _0 4
DA C_ IR E F _ R
A D4 8
AB5 1
S D V O _T V C L K I N N
S DV O _ T V CL K IN P
L _ B K L T C TL
S DV O _ S T A L L N
S D V O_ S T A L L P
L _ D D C _C L K
L _ D D C _D A T A
S D V O_ I N T N
S D V O _I N T P
B J 46
B G4 6
B J 48
B G4 8
BF4 5
B H4 5
L _ C TR L _ C L K
L _ C TR L _ D A T A
L VD _ IBG
L VD _ VBG
S DV O _ CT R L CL K
S D V O _ C T R LD A T A
L VD _ VRE F H
L VD _ VRE F L
L V D S A _ C LK #
L V D S A _ C LK
L VD SA_ D ATA# 0
L VD SA_ D ATA# 1
L VD SA_ D ATA# 2
L VD SA_ D ATA# 3
L VD SA_ D ATA0
L VD SA_ D ATA1
L VD SA_ D ATA2
L VD SA_ D ATA3
L V D S B _ C LK #
L V D S B _ C LK
L VD
L VD
L VD
L VD
SB_ D
SB_ D
SB_ D
SB_ D
ATA# 0
ATA# 1
ATA# 2
ATA# 3
L VD SB_ D ATA0
L VD SB_ D ATA1
L VD SB_ D ATA2
L VD SB_ D ATA3
C RT _ BL U E
C RT _ G REE N
C RT _ R E D
D D
DD
D D
DD
D D
DD
D D
DD
PB_ 0 N
PB_ 0 P
PB_ 1 N
PB_ 1 P
PB_ 2 N
PB_ 2 P
PB_ 3 N
PB_ 3 P
D DP C _ CT R L CL K
D D P C _ C T R LD A T A
D DP C_ A U X N
D D P C _A U X P
D DP C _ HP D
D
D
D
D
D
D
D
D
DP C _ 0 N
D P C_ 0 P
DP C _ 1 N
D P C_ 1 P
DP C _ 2 N
D P C_ 2 P
DP C _ 3 N
D P C_ 3 P
D DP D _ CT R L CL K
D D P D _ C T R LD A T A
C RT _ D DC _ CL K
C RT _ D DC _ DAT A
C RT _ H S YN C
C RT _ VS Y N C
D A C _I R E F
C RT _ IR T N
DD P B _ A U X N
D D P B _A U X P
DD P B _ HP D
Digital Display Interface
AB4 8
Y4 5
L _ BKL TEN
L _ V D D_ E N
LVDS
Y4 8
CRT
B.Schematic Diagrams
U1 4 D
T4 8
T4 7
D DP D_ A U X N
D D P D _A U X P
D DP D _ HP D
D
D
D
D
D
D
D
D
DP D _ 0 N
D P D_ 0 P
DP D _ 1 N
D P D_ 1 P
DP D _ 2 N
D P D_ 2 P
DP D _ 3 N
D P D_ 3 P
I B E X P E A K -M
Connect to GND
External Graphics (PCH Integrated Graphics Disable)
T5 1
T5 3
B G4 4
B J 44
A U3 8
B D4 2
B C4 2
B J 42
B G4 2
BB4 0
BA4 0
AW 3 8
BA3 8
Y4 9
AB4 9
BE4 4
B D4 4
AV4 0
BE4 0
B D4 0
BF4 1
B H4 1
B D3 8
B C3 8
BB3 6
BA3 6
U5 0
U5 2
B C4 6
B D4 6
A T 38
B J 40
B G4 0
B J 38
B G3 8
BF3 7
B H3 7
BE3 6
B D3 6
AY 7
B1 1
B1 5
B1 9
B2 3
B3 1
B3 5
B3 9
B4 3
B4 7
B7
B G1 2
BB1 2
BB1 6
BB2 0
BB2 4
BB3 0
BB3 4
BB3 8
BB4 2
BB4 9
BB5
B C1 0
B C1 4
B C1 8
BC 2
B C2 2
B C3 2
B C3 6
B C4 0
B C4 4
B C5 2
BH 9
B D4 8
B D4 9
BD 5
BE1 2
BE1 6
BE2 0
BE2 4
BE3 0
BE3 4
BE3 8
BE4 2
BE4 6
BE4 8
BE5 0
BE6
BE8
BF 3
BF4 9
BF5 1
B G1 8
B G2 4
BG 4
B G5 0
B H1 1
B H1 5
B H1 9
B H2 3
B H3 1
B H3 5
B H3 9
B H4 3
B H4 7
BH 7
C1 2
C5 0
D5 1
E1 2
E1 6
E2 0
E2 4
E3 0
E3 4
E3 8
E4 2
E4 6
E4 8
E6
E8
F4 9
F5
G1 0
G1 4
G1 8
G 2
G2 2
G3 2
G3 6
G4 0
G4 4
G5 2
AF3 9
H1 6
H2 0
H3 0
H3 4
H3 8
H4 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U 1 4H
[ 1 59 ]
[ 1 60 ]
[ 1 61 ]
[ 1 62 ]
[ 1 63 ]
[ 1 64 ]
[ 1 65 ]
[ 1 66 ]
[ 1 67 ]
[ 1 68 ]
[ 1 69 ]
[ 1 70 ]
[ 1 71 ]
[ 1 72 ]
[ 1 73 ]
[ 1 74 ]
[ 1 75 ]
[ 1 76 ]
[ 1 77 ]
[ 1 78 ]
[ 1 79 ]
[ 1 80 ]
[ 1 81 ]
[ 1 82 ]
[ 1 83 ]
[ 1 84 ]
[ 1 85 ]
[ 1 86 ]
[ 1 87 ]
[ 1 88 ]
[ 1 89 ]
[ 1 90 ]
[ 1 91 ]
[ 1 92 ]
[ 1 93 ]
[ 1 94 ]
[ 1 95 ]
[ 1 96 ]
[ 1 97 ]
[ 1 98 ]
[ 1 99 ]
[ 2 00 ]
[ 2 01 ]
[ 2 02 ]
[ 2 03 ]
[ 2 04 ]
[ 2 05 ]
[ 2 06 ]
[ 2 07 ]
[ 2 08 ]
[ 2 09 ]
[ 2 10 ]
[ 2 11 ]
[ 2 12 ]
[ 2 13 ]
[ 2 14 ]
[ 2 15 ]
[ 2 16 ]
[ 2 17 ]
[ 2 18 ]
[ 2 19 ]
[ 2 20 ]
[ 2 21 ]
[ 2 22 ]
[ 2 23 ]
[ 2 24 ]
[ 2 25 ]
[ 2 26 ]
[ 2 27 ]
[ 2 28 ]
[ 2 29 ]
[ 2 30 ]
[ 2 31 ]
[ 2 32 ]
[ 2 33 ]
[ 2 34 ]
[ 2 35 ]
[ 2 36 ]
[ 2 37 ]
[ 2 38 ]
[ 2 39 ]
[ 2 40 ]
[ 2 41 ]
[ 2 42 ]
[ 2 43 ]
[ 2 44 ]
[ 2 45 ]
[ 2 46 ]
[ 2 47 ]
[ 2 48 ]
[ 2 49 ]
[ 2 50 ]
[ 2 51 ]
[ 2 52 ]
[ 2 53 ]
[ 2 54 ]
[ 2 55 ]
[ 2 56 ]
[ 2 57 ]
[ 2 58 ]
I B E X P E A K -M
B - 16 PCH 4/8 LVDS, DDI, GND
V SS[2 5 9 ]
V SS[2 6 0 ]
V SS[2 6 1 ]
V SS[2 6 2 ]
V SS[2 6 3 ]
V SS[2 6 4 ]
V SS[2 6 5 ]
V SS[2 6 6 ]
V SS[2 6 7 ]
V SS[2 6 8 ]
V SS[2 6 9 ]
V SS[2 7 0 ]
V SS[2 7 1 ]
V SS[2 7 2 ]
V SS[2 7 3 ]
V SS[2 7 4 ]
V SS[2 7 5 ]
V SS[2 7 6 ]
V SS[2 7 7 ]
V SS[2 7 8 ]
V SS[2 7 9 ]
V SS[2 8 0 ]
V SS[2 8 1 ]
V SS[2 8 2 ]
V SS[2 8 3 ]
V SS[2 8 4 ]
V SS[2 8 5 ]
V SS[2 8 6 ]
V SS[2 8 7 ]
V SS[2 8 8 ]
V SS[2 8 9 ]
V SS[2 9 0 ]
V SS[2 9 1 ]
V SS[2 9 2 ]
V SS[2 9 3 ]
V SS[2 9 4 ]
V SS[2 9 5 ]
V SS[2 9 6 ]
V SS[2 9 7 ]
V SS[2 9 8 ]
V SS[2 9 9 ]
V SS[3 0 0 ]
V SS[3 0 1 ]
V SS[3 0 2 ]
V SS[3 0 3 ]
V SS[3 0 4 ]
V SS[3 0 5 ]
V SS[3 0 6 ]
V SS[3 0 7 ]
V SS[3 0 8 ]
V SS[3 0 9 ]
V SS[3 1 0 ]
V SS[3 1 1 ]
V SS[3 1 2 ]
V SS[3 1 3 ]
V SS[3 1 4 ]
V SS[3 1 5 ]
V SS[3 1 6 ]
V SS[3 1 7 ]
V SS[3 1 8 ]
V SS[3 1 9 ]
V SS[3 2 0 ]
V SS[3 2 1 ]
V SS[3 2 2 ]
V SS[3 2 3 ]
V SS[3 2 4 ]
V SS[3 2 5 ]
V SS[3 2 6 ]
V SS[3 2 7 ]
V SS[3 2 8 ]
V SS[3 2 9 ]
V SS[3 3 0 ]
V SS[3 3 1 ]
V SS[3 3 2 ]
V SS[3 3 3 ]
V SS[3 3 4 ]
V SS[3 3 5 ]
V SS[3 3 6 ]
V SS[3 3 7 ]
V SS[3 3 8 ]
V SS[3 3 9 ]
V SS[3 4 0 ]
V SS[3 4 1 ]
V SS[3 4 2 ]
V SS[3 4 3 ]
V SS[3 4 4 ]
V SS[3 4 5 ]
V SS[3 4 6 ]
V SS[3 4 7 ]
V SS[3 4 8 ]
V SS[3 4 9 ]
V SS[3 5 0 ]
V SS[3 5 1 ]
V SS[3 5 2 ]
V SS[3 5 3 ]
V SS[3 5 4 ]
V SS[3 5 5 ]
V SS[3 5 6 ]
V SS[3 6 6 ]
H 49
H 5
J24
K1 1
K4 3
K4 7
K7
L14
L18
L2
L22
L32
L36
L40
L52
M 12
M 16
M 20
N 38
M 34
M 38
M 42
M 46
M 49
M5
M8
N 24
P1 1
AD 1 5
P2 2
P3 0
P3 2
P3 4
P4 2
P4 5
P4 7
R 2
R 52
T12
T41
T46
T49
T5
T8
U 30
U 31
U 32
U 34
P3 8
V1 1
P1 6
V1 9
V2 0
V2 2
V3 0
V3 1
V3 2
V3 4
V3 5
V3 8
V4 3
V4 5
V4 6
V4 7
V4 9
V5
V7
V8
W 2
W 52
Y 11
Y 12
Y 15
Y 19
Y 23
Y 28
Y 30
Y 31
Y 32
Y 38
Y 43
Y 46
P4 9
Y 5
Y 6
Y 8
P2 4
T43
AD 5 1
AT8
AD 4 7
Y 47
AT1 2
AM 6
AT1 3
AM 5
A K 45
A K 39
A V 14
AB1 6
AA1 9
AA2 0
AA2 2
A M1 9
AA2 4
AA2 6
AA2 8
AA3 0
AA3 1
AA3 2
AB1 1
AB1 5
AB2 3
AB3 0
AB3 1
AB3 2
AB3 9
AB4 3
AB4 7
AB5
AB8
AC 2
A C5 2
A D1 1
A D1 2
A D1 6
A D2 3
A D3 0
A D3 1
A D3 2
A D3 4
A U2 2
A D4 2
A D4 6
A D4 9
AD 7
AE2
AE4
AF1 2
Y1 3
A H4 9
AU 4
AF3 5
AP1 3
A N3 4
AF4 5
AF4 6
AF4 9
AF5
AF8
AG 2
A G5 2
A H1 1
A H1 5
A H1 6
A H2 4
A H3 2
AV1 8
A H4 3
A H4 7
AH 7
AJ 1 9
AJ 2
AJ 2 0
AJ 2 2
AJ 2 3
AJ 2 6
AJ 2 8
AJ 3 2
AJ 3 4
AT5
AJ 4
AK1 2
A M4 1
A N1 9
AK2 6
AK2 2
AK2 3
AK2 8
VS S [0 ]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
[1 ]
[2 ]
[3 ]
[4 ]
[5 ]
[6 ]
[7 ]
[8 ]
[9 ]
[ 1 0]
[ 1 1]
[ 1 2]
[ 1 3]
[ 1 4]
[ 1 5]
[ 1 6]
[ 1 7]
[ 1 8]
[ 1 9]
[ 2 0]
[ 2 1]
[ 2 2]
[ 2 3]
[ 2 4]
[ 2 5]
[ 2 6]
[ 2 7]
[ 2 8]
[ 2 9]
[ 3 0]
[ 3 1]
[ 3 2]
[ 3 3]
[ 3 4]
[ 3 5]
[ 3 6]
[ 3 7]
[ 3 8]
[ 3 9]
[ 4 0]
[ 4 1]
[ 4 2]
[ 4 3]
[ 4 4]
[ 4 5]
[ 4 6]
[ 4 7]
[ 4 8]
[ 4 9]
[ 5 0]
[ 5 1]
[ 5 2]
[ 5 3]
[ 5 4]
[ 5 5]
[ 5 6]
[ 5 7]
[ 5 8]
[ 5 9]
[ 6 0]
[ 6 1]
[ 6 2]
[ 6 3]
[ 6 4]
[ 6 5]
[ 6 6]
[ 6 7]
[ 6 8]
[ 6 9]
[ 7 0]
[ 7 1]
[ 7 2]
[ 7 3]
[ 7 4]
[ 7 5]
[ 7 6]
[ 7 7]
[ 7 8]
[ 7 9]
I B E X P E A K -M
V S S [8 0 ]
V S S [8 1 ]
V S S [8 2 ]
V S S [8 3 ]
V S S [8 4 ]
V S S [8 5 ]
V S S [8 6 ]
V S S [8 7 ]
V S S [8 8 ]
V S S [8 9 ]
V S S [9 0 ]
V S S [9 1 ]
V S S [9 2 ]
V S S [9 3 ]
V S S [9 4 ]
V S S [9 5 ]
V S S [9 6 ]
V S S [9 7 ]
V S S [9 8 ]
V S S [9 9 ]
VS S[1 0 0 ]
VS S[1 0 1 ]
VS S[1 0 2 ]
VS S[1 0 3 ]
VS S[1 0 4 ]
VS S[1 0 5 ]
VS S[1 0 6 ]
VS S[1 0 7 ]
VS S[1 0 8 ]
VS S[1 0 9 ]
VS S[1 1 0 ]
VS S[1 1 1 ]
VS S[1 1 2 ]
VS S[1 1 3 ]
VS S[1 1 4 ]
VS S[1 1 5 ]
VS S[1 1 6 ]
VS S[1 1 7 ]
VS S[1 1 8 ]
VS S[1 1 9 ]
VS S[1 2 0 ]
VS S[1 2 1 ]
VS S[1 2 2 ]
VS S[1 2 3 ]
VS S[1 2 4 ]
VS S[1 2 5 ]
VS S[1 2 6 ]
VS S[1 2 7 ]
VS S[1 2 8 ]
VS S[1 2 9 ]
VS S[1 3 0 ]
VS S[1 3 1 ]
VS S[1 3 2 ]
VS S[1 3 3 ]
VS S[1 3 4 ]
VS S[1 3 5 ]
VS S[1 3 6 ]
VS S[1 3 7 ]
VS S[1 3 8 ]
VS S[1 3 9 ]
VS S[1 4 0 ]
VS S[1 4 1 ]
VS S[1 4 2 ]
VS S[1 4 3 ]
VS S[1 4 4 ]
VS S[1 4 5 ]
VS S[1 4 6 ]
VS S[1 4 7 ]
VS S[1 4 8 ]
VS S[1 4 9 ]
VS S[1 5 0 ]
VS S[1 5 1 ]
VS S[1 5 2 ]
VS S[1 5 3 ]
VS S[1 5 4 ]
VS S[1 5 5 ]
VS S[1 5 6 ]
VS S[1 5 7 ]
VS S[1 5 8 ]
A K 30
A K 31
A K 32
A K 34
A K 35
A K 38
A K 43
A K 46
A K 49
AK 5
AK 8
AL 2
AL 5 2
AM 1 1
B B 44
AD 2 4
AM 2 0
AM 2 2
AM 2 4
AM 2 6
AM 2 8
B A 42
AM 3 0
AM 3 1
AM 3 2
AM 3 4
AM 3 5
AM 3 8
AM 3 9
AM 4 2
AU 2 0
AM 4 6
A V 22
AM 4 9
AM 7
A A 50
B B 10
AN 3 2
AN 5 0
AN 5 2
A P 12
A P 42
A P 46
A P 49
AP 5
AP 8
AR 2
AR 5 2
AT1 1
B A 12
AH 4 8
AT3 2
AT3 6
AT4 1
AT4 7
AT7
A V 12
A V 16
A V 20
A V 24
A V 30
A V 34
A V 38
A V 42
A V 46
A V 49
AV 5
AV 8
AW 1 4
AW 1 8
AW 2
BF 9
AW 3 2
AW 3 6
AW 4 0
AW 5 2
AY 1 1
AY 4 3
AY 4 7
Schematic Diagrams
PCH 5/8 PCI, USB, NVRAM
IBEXPEAK - M (PCI,USB,NVRAM)
DMI Termination Voltage
Bo ot B IO S L oc at io n
0
1
0
L PC
R es er ve d
P CI
1
1
S PI
*1 K _ 04
P C I _G N T # 0
R 4 62
*1 K _ 04
P C I _G N T # 1
Understand the RED FONT define
R 2 11
*1 K _ 04
P C I _G N T # 3
J50
G4 2
H4 7
G3 4
3 . 3V S
4
R N 11
3
8. 2 K _ 8 P 4 R _ 0 4 2
1
1
RN 9
2
8. 2 K _ 8 P 4 R _ 0 4 3
4
1
R N 13
2
8. 2 K _ 8 P 4 R _ 0 4 3
4
5
6
7
8
8
7
6
5
8
7
6
5
1
RN 8
2
8. 2 K _ 8 P 4 R _ 0 4 3
4
1
R N 10
2
8. 2 K _ 8 P 4 R _ 0 4 3
4
8
7
6
5
8
7
6
5
INT _ P IR
INT _ P IR
INT _ P IR
INT _ P IR
P C I _P E R R #
P C I _L O C K #
P C I _D E V S E L #
P C I _S E R R #
P C I _F R A M E #
I N T _ P I R QD #
P C I _I R D Y #
I N T _ P I R QE #
I N T _P I R Q H #
P C I _T R D Y #
P C I _R E Q# 1
P C I _R E Q# 2
E Q# 0
E Q# 1
E Q# 2
E Q# 3
F51
A4 6
B4 5
M5 3
P CI_ G NT # 0
P CI_ G NT # 1
P CI_ G NT # 3
F48
K4 5
F36
H5 3
I N T _ P I R QE #
I N T _ P I R QF #
I N T _ P I R QG#
I N T _ P I R QH #
B4 1
K5 3
A3 6
A4 8
P CI_ R
P CI_ R
P CI_ R
P CI_ R
P C I _ S T OP #
I N T _P I R QC #
I N T _P I R QG #
INT _ P IRQ A #
P C I _R E Q# 3
I N T _ P I R QF #
I N T _ P I R QB #
P C I _R E Q# 0
N V _R C O MP
NV _ W E # _ C K 0
NV _ W E # _ C K 1
T 0#
T 1# / G P I O 51
T 2# / G P I O 53
T 3# / G P I O 55
QE # /
QF # /
QG # /
QH # /
G
G
G
G
P I O2
P I O3
PIO 4
PIO 5
K6
PCI RST #
P C I_ S ERR #
P C I_ P ERR #
E4 4
E5 0
P C I_ IRD Y #
P C I _ D E V S E L#
P C I_ F RA M E #
A4 2
H4 4
F46
C4 6
P C I _ L OC K #
D4 9
P C I _ S T OP #
P C I_ T RDY #
D4 1
C4 8
S E R R#
P E R R#
IRD Y #
PAR
DE V S E L #
F R A ME #
2 2 , 3 3 P LT _ R S T#
US B RB IA S #
S T OP #
T RD Y#
1 3 C LK _P C I _ F B
3 1 P C LK _ K B C
R 21 0
R 20 9
2 2 _ 04
2 2 _ 04
C L K _ P C I _F B _R
C L K _ P C I _K B C _ R
2 2 P C LK _ T P M
R 21 7
* 2 2_ 0 4
C L K _ P C I _T P M _R
USB R BIA S
P ME #
D 5
P L T_ R S T #
U SBP0 N
U S B P 0P
U SBP1 N
U S B P 1P
U SBP2 N
U S B P 2P
U SBP3 N
U S B P 3P
U SBP4 N
U S B P 4P
U SBP5 N
U S B P 5P
U SBP6 N
U S B P 6P
U SBP7 N
U S B P 7P
U SBP8 N
U S B P 8P
U SBP9 N
U S B P 9P
US B P 1 0 N
U S B P 1 0P
US B P 1 1 N
U S B P 1 1P
US B P 1 2 N
U S B P 1 2P
US B P 1 3 N
U S B P 1 3P
P L OC K #
M7
PIN PLT_ RST# to Buf fer
NV_ R B#
N V _ W R #0 _ R E #
N V _ W R #1 _ R E #
RE Q 0 #
R E Q 1 # / GP I O 5 0
R E Q 2 # / GP I O 5 2
R E Q 3 # / GP I O 5 4
PIR
PIR
PIR
PIR
OC 0 # / GP I O 5 9
OC 1 # / GP I O 4 0
OC 2 # / GP I O 4 1
OC 3 # / GP I O 4 2
OC 4 # / GP I O 4 3
OC 5 # / G P I O 9
OC 6 # / GP I O 1 0
OC 7 # / GP I O 1 4
PL T RST #
N5 2
P5 3
P4 6
P5 1
P4 8
CL K O
CL K O
CL K O
CL K O
CL K O
NV _ CE
NV _ CE
NV _ CE
NV _ CE
[ 0] #
[ 1] #
[ 2] #
[ 3] #
AV9
B G8
NV _ DQ S [0 ]
NV _ DQ S [1 ]
AP7
AP6
AT 6
AT 9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ 8
BJ 6
B G6
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
NV _ DQ
BD3
AY6
NV _ A L E
NV _ CL E
[0 ]
[1 ]
[2 ]
[3 ]
[4 ]
[5 ]
[6 ]
[7 ]
[8 ]
[9 ]
[1 0 ]
[1 1 ]
[1 2 ]
[1 3 ]
[1 4 ]
[1 5 ]
N V _ C LE
I nt el r ec om me nds r ou ti ng
f ro m th e pa d of th e
N V_ RC OM P pi n usi ng t ha t
m ic ro st ri p
l ay er t o on e end o f a
3 2. 4 O ? % pr eci si on
r es is to r to g rou nd . Ro ut e
s ig na l us in g 50- O
s in gl e- en de d imp ed an ce
a nd 5 00 m il s (12 .7 m m)
m ax t ra ce l en gth . Av oi d
r ou ti ng n ex t
t o cl oc k pi ns or u nd er
s ti tc hi ng c ap aci to rs
NV _ A L E
*1 0 0 u _6 . 3 V _ B _ A
UT _ P CI0
UT _ P CI1
UT _ P CI2
UT _ P CI3
UT _ P CI4
I B E X P E A K -M
N V _ DQ [0 ]
N V _ DQ [1 ]
AY8
AY5
N V _ R E #_ W R # 0
N V _ R E #_ W R # 1
T P _ N V _D QS _0 #
N V _ DQ S[0 ]
AV1 1
BF 5
NV _ W E # _ CK 0
NV _ W E # _ CK 1
N V _ DQ [4 ]
N V _ DQ [5 ]
US B _ B IA S
3 2 . 4_ 1 % _ 04
USB _ PN 0
USB _ PP 0
USB _ PN 1
USB _ PP 1
USB _ PN 2
USB _ PP 2
USB _ PN 3
USB _ PP 3
32
32
32
32
25
25
25
25
USB _ PN 5
USB _ PP 5
USB _ PN 6
USB _ PP 6
USB _ PN 7
USB _ PP 7
USB _ PN 8
USB _ PP 8
28
28
28
28
28
28
25
25
T P _ N V _R F U _1
T P _ N V _R F U _2
US B PO RT 0
US B PO RT 1
US B PO RT 2
N V _ R E # _ W R #0
N V _ CE[1 ]#
N V _ CE[0 ]#
C ON 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NE W CA RD
CC D
T P _ N V _D QS _1 #
N V _ DQ S[1 ]
FI NG ER PR IN T
U S B _ P N 12 2 5
USB _ PP 1 2 2 5
BL UE TO OT H
V CC _ 4
V CC _ 5
V CC _ 6
CE _ 6 #
VSS_ 1 3
DQ 2
DQ 3
VSS_ 1 4
CK _ 0 #
CK_ 0 /W E _ 0 #
VSS_ 1 5
DQ 6
DQ 7
VSS_ 1 6
R /B #
W P#
VSS_ 1 7
CL E _ 1
AL E_ 1
VSS_ 1 8
W /R _ 1 /RE _ 1 #
CE _ 3 #
VSS_ 1 9
RF U _ 3
RF U _ 4
VSS_ 2 0
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
N V _ CE [2 ]#
N V _ D Q [ 2]
N V _ D Q [ 3]
T P _ N V _ C K _ 0#
N V _ W E # _C K 0
N V _ D Q [ 6]
N V _ D Q [ 7]
Sheet 16 of 55
PCH 5/8
PCI, USB, NVRAM
N V _ R_ B #
T P _ N V _ W P 0#
N V _ CL E
N V _ A LE
N V _ RE # _ W R# 1
N V _ CE [1 ]#
T P _ NV_ R F U_ 3
T P _ NV_ R F U_ 4
K EY
N V _ DQ [8 ]
N V _ DQ [9 ]
N V _ D Q [ 1 2]
N V _ D Q [ 1 3]
N V _ CE[3 ]#
27
28
29
30
31
32
33
34
35
36
37
38
39
22 . 6 _ 1% _ 0 4
VSS_ 9
DQ 8
DQ 9
VSS_ 1 0
DQ S_ 1 #
DQ S_ 1
VSS_ 1 1
D Q _ 12
D Q _ 13
VSS_ 1 2
CE_ 5 #
V C C Q_ 1
V C C Q_ 2
VSS_ 2 1
DQ 1 0
DQ 1 1
VSS_ 2 2
CK _ 1 #
CK_ 1 /W E _ 1 #
VSS_ 2 3
DQ 1 4
DQ 1 5
VSS_ 2 4
CE _ 7 #
V RE F
V CCQ _ 3
66
67
68
69
70
71
72
73
74
75
76
77
78
N V _ D Q [ 10 ]
N V _ D Q [ 11 ]
T P _ N V _ C K _ 1#
N V _ W E # _C K 1
N V _ D Q [ 14 ]
N V _ D Q [ 15 ]
N V _ CE [3 ]#
T P _ NV_ VR E F
*A C E S 5 1 77 1 -0 78 0 M- 00 2 (1 . 8 V )
6-86-26078-001
D2 5
N1 6
J1 6
F1 6
L1 6
E1 4
G1 6
F1 2
T1 5
V CC _ 1
V CC _ 2
V CC _ 3
CE_ 4 #
VSS_ 1
DQ 0
DQ 1
VSS_ 2
DQ S_ 0 #
DQ S_ 0
VSS_ 3
DQ 4
DQ 5
VSS_ 4
RF U _ 1
RF U _ 2
VSS_ 5
CL E _ 0
AL E_ 0
VSS_ 6
W / R _0 # / R E _0 #
CE_ 1 #
VSS_ 7
CE_ 0 #
CE_ 2 #
VSS_ 8
TV
U S B _ P N 10 3 2
USB _ PP 1 0 3 2
R 4 44
N V _ CL E
N V_ AL E
US B PO RT 3
WL AN
*1 K _ 0 4
C 55 2
NV _ R_ B #
R1 3 2
R 4 28
+
N V _ R C OM P
B2 5
V _ N V R A M_ V C C Q
3 . 3V S
AV7
Zo= 85O
*1 K _ 0 4
Da nb ur y Te ch no log y
Di sa bl ed w he n Low
En ab le d w he n Hig h
AU2
H1 8
J1 8
A1 8
C1 8
N2 0
P2 0
J2 0
L2 0
F2 0
G2 0
A2 0
C2 0
M2 2
N2 2
B2 1
D2 1
H2 2
J2 2
E2 2
F2 2
A2 2
C2 2
G2 4
H2 4
L2 4
M2 4
A2 4
C2 4
R 4 27
NV_ALE
N V _ CE[2 ]#
P I R QA #
P I R QB #
P I R QC #
P I R QD #
GN
GN
GN
GN
/ NV_ IO 0
/ NV_ IO 1
/ NV_ IO 2
/ NV_ IO 3
/ NV_ IO 4
/ NV_ IO 5
/ NV_ IO 6
/ NV_ IO 7
/ NV_ IO 8
/ NV_ IO 9
N V _I O 1 0
N V _I O 1 1
N V _I O 1 2
N V _I O 1 3
N V _I O 1 4
N V _I O 1 5
N V _A LE
N V _ C LE
C / B E 0#
C / B E 1#
C / B E 2#
C / B E 3#
G3 8
H5 1
B3 7
A4 4
QA #
QB #
QC #
QD #
N V _ DQ 0
N V _ DQ 1
N V _ DQ 2
N V _ DQ 3
N V _ DQ 4
N V _ DQ 5
N V _ DQ 6
N V _ DQ 7
N V _ DQ 8
N V _ DQ 9
N V _ D Q1 0 /
N V _ D Q1 1 /
N V _ D Q1 2 /
N V _ D Q1 3 /
N V _ D Q1 4 /
N V _ D Q1 5 /
AY9
BD1
AP1 5
BD8
3 .3 V S
R4 3 1
R4 3 9
R4 4 2
R4 3 0
R4 0 7
1 0 K _ 04
1 0 K _ 04
1 0 K _ 04
1 0 K _ 04
1 0 K _ 04
U S B _O C 0 1 # 2 5
U S B _O C 2 3 # 2 5
U S B _O C 5 # 2 8
3 . 3V
1. 8 V S
V _ N V RA M _ V CC Q
R 16 4
0_08
R 16 0
* 0_ 0 8
C2 0 6
*2 2 u_ 6 . 3 V _ X5 R _0 8
P C H _G P I O 9 3 7
P C H _G P I O 10 3 7
3 .3 V S
C1 7 0
*0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
5
3 .3 V S
C1 7 8
* 0 . 1u _ 1 6 V _Y 5 V _ 04
5
1 7 D G P U _ H OL D _ R S T #
1
4
U 10
* 74 A H C 1 G 08 G W
1
4
P L T _ RST #
2
1 . 8 V S 6 , 1 8, 3 8
3 . 3 V S 3 , 8 . . 12 , 1 4 , 1 7. . 24 , 2 6 . . 3 5
3 . 3 V 2 , 3, 1 2 . . 1 4 , 17 , 1 9 , 2 2, 25 , 2 8 , 2 9, 3 5 . . 3 9
V _ N V R A M _V C C Q 1 8
P E G_ R S T # 1 0 , 1 1
B U F _ P L T _R S T # 3, 20 , 2 8 . . 3 1
3
2
3
P L T_ R S T#
U 11
7 4 A H C 1G 0 8G W
Re v_ 3. 0
3 3 V G A _ RS T #
R1 5
0 _ 04
R5 1 9
*0 _ 0 4
PCH 5/8 PCI, USB, NVRAM B - 17
B.Schematic Diagrams
R 4 61
(N AN D)
N V _ DQ S0
N V _ DQ S1
NVRAM
PC I_ GN T# 1
0
0
1
NV _ C E # 0
NV _ C E # 1
NV _ C E # 2
NV _ C E # 3
PCI
PC I_ GN T#0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD1 0
AD1 1
AD1 2
AD1 3
AD1 4
AD1 5
AD1 6
AD1 7
AD1 8
AD1 9
AD2 0
AD2 1
AD2 2
AD2 3
AD2 4
AD2 5
AD2 6
AD2 7
AD2 8
AD2 9
AD3 0
AD3 1
USB
Boot BIOS Strap
Se t to V ss w he n L OW
Se t to V cc w he n H IG H
NV_CLE
U 14 E
H4 0
N3 4
C4 4
A3 8
C3 6
J34
A4 0
D4 5
E3 6
H4 8
E4 0
C4 0
M4 8
M4 5
F53
M4 0
M4 3
J36
K4 8
F40
C4 2
K4 6
M5 1
J52
K5 1
L34
F42
J40
G4 6
F44
M4 7
H3 6
Schematic Diagrams
PCH 6/8 GPIO, CPU
R1 3 9
3 .3 V S
B MB U S Y #
1 0 K_ 0 4
IBEXPEAK - M (GPIO,VSS_NCTF,RSVD)
BIOS RECOVERY
DISABLE----NO STUFF
(DEFAULT)
ENABLE-----STUFF
R4 0 9
3 .3 V S
1 0 K_ 0 4
B I OS _R E C
U1 4 F
R4 1 2
3 1 S C I#
D 37
J32
H O S T _A LE R T # 2
CRB/SV DETECT
NO STUFF [DETECT]
Sheet 17 of 55
PCH 6/8
GPIO, CPU
3 .3 V S
R1 3 4
* 1 0 K _ 04
LA N _ P H Y _ P W R _ C T R L
H O S T _A LE R T # 1
CR B _ S V _ DE T
R1 2 4
F38
2 2 S B _ B L ON
B I OS _ R E C
S RS _ E N
2 9 S B _ IS O L A T E B #
1 0 K _ 04
S V _ S E T _ UP
R 4 23
A B1 2
S B _ I S OL A T E B #
V1 3
S T P _P C I #
M 11
DG P U_ P W R_ E N #
AB 7
1 0 K _ 04
V 6
MX M1 _ P R S N T #
CR B _ S V _ DE T
R5 0 1
1 0 K_ 0 4
S 3 Pow e r Re duct ion w hi te pape r
D R A MR S T _C N T R L _P C H
1 K_ 0 4
DR A M RS T _ C NT RL _ P C H
3 DR A M RS T _ CN T RL _ P C H
V 3
P 3
R4 1 9
1 0 K_ 0 4
H O S T _A LE R T # 2
R4 2 1
1 0 K_ 0 4
S B _ I S OL A T E B #
R3 9 8
1 0 K_ 0 4
LA N _ P H Y _ P W R _ C T R L
1 1 , 3 1 MX M2 _ P R S N T#
M X M1 _ P R S N T #
R 411
GP I O 8
0 _ 04
C L K O U T _ P C I E 7N
CL K O UT _ P C IE 7 P
S A T A 5 GP
AA 4
P C H _ GP I O 5 7
F 8
* 0_ 0 4
A H4 5
A H4 6
A F 48
A F 47
C LK _P C I E _ T V # 2 8
C LK _P C I E _ T V 2 8
R 133
L A N _ P H Y _ P W R _ C T R L / GP I O1 2
A 20 G A T E
1 0 K_ 0 4
3 .3 VS
U 2
G A2 0 3 1
3 .3 VS
GP I O 1 5
S A T A 4 GP / GP I O1 6
C LK OU T _B C L K 0 _ N / C L K O U T _ P C I E 8N
T A C H 0 / GP I O1 7
S C L O C K / GP I O2 2
ME M _ L E D / GP I O 2 4
C L K O U T _ B C L K 0 _P / C L K O U T _ P C I E 8 P
PEC I
R C IN#
GP I O 2 7
P R OC P W R GD
A M3
BC L K_ CPU _ N 3
A M1
B G1 0
R 1 46
BC L K_ CPU _ P 3
R 5 10
0_ 0 4
1 0 K_ 0 4
H_ P E C I 3
T1
K B C _ RS T # 3 1
B E 10
B D1 0
T H R M TR I P #
H _C P U P W R GD
R1 6 9
56 _ 0 4
R1 6 8
56_04
S A T A C LK R E Q # / GP I O3 5
S A T A 2 GP / GP I O3 6
T P1
S A T A 3 GP / GP I O3 7
T P2
S L OA D / G P I O 38
T P3
S D A TA OU T0 / GP I O 3 9
T P4
P C I E C L K R Q6 # / G P I O4 5
T P5
P C I E C L K R Q7 # / G P I O4 6
T P6
S D A TA OU T1 / GP I O 4 8
T P7
S A T A 5 GP / GP I O4 9
T P8
GP I O 5 7
T P9
B A 22
A W22
B B 22
Connected to PCH (THRMTRIP#)
Routing guidelines available in
Calpella Design Guide.
NOTE: CRB uses a 54.9 O ? %
series resistor and 56-O pull-up.
A Y4 5
A Y4 6
A V 43
A V 45
A F 13
M 18
N 18
* 1 0 K _ 04
R4 0 4
1 0 K_ 0 4
P C H _ GP I O 5 7
3 . 3V S
R1 4 1
* 1 0 K _ 04
S A T A 5 GP
R4 5 0
1 0 K_ 0 4
S CI#
R1 9 4
1 0 K_ 0 4
S MI #
R1 5 5
1 0 K_ 0 4
MF G _ MO D E
R4 1 6
1 0 K_ 0 4
S T P _ P CI#
R1 5 6
1 0 K_ 0 4
DG P U_ P W R_ E N #
R1 9 5
1 0 K_ 0 4
C R _W A K E #
R1 4 0
1 0 K_ 0 4
D G P U _ H OL D _R S T #
R4 3 3
* 1 0 K _ 04
R4 1 0
* 1 0 K _ 04
DG P U_ P W RO K
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
VSS_ N
CT F _ 1
CT F _ 2
CT F _ 3
CT F _ 4
CT F _ 5
CT F _ 6
CT F _ 7
CT F _ 8
CT F _ 9
CT F _ 1 0
CT F _ 1 1
CT F _ 1 2
CT F _ 1 3
CT F _ 1 4
CT F _ 1 5
CT F _ 1 6
CT F _ 1 7
CT F _ 1 8
CT F _ 1 9
CT F _ 2 0
CT F _ 2 1
CT F _ 2 2
CT F _ 2 3
CT F _ 2 4
CT F _ 2 5
CT F _ 2 6
CT F _ 2 7
CT F _ 2 8
CT F _ 2 9
CT F _ 3 0
CT F _ 3 1
TP1 1
TP1 2
TP1 3
A J2 4
A K 41
A K 42
M 32
TP1 4
TP1 5
TP1 6
TP1 7
N 32
M 30
N 30
H 12
TP1 8
TP1 9
N C_ 1
N C_ 2
A A 23
A B 45
A B 38
A B 42
N C_ 3
N C_ 4
N C_ 5
I N I T 3_ 3 V #
TP2 4
I B E X P E A K -M
B - 18 PCH 6/8 GPIO, CPU
RSVD
R4 0 1
TP1 0
A 4
A4 9
A 5
A5 0
A5 2
A5 3
B 2
B 4
B5 2
B5 3
BE 1
B E5 3
BF 1
B F53
BH 1
BH 2
BH 5 2
BH 5 3
BJ 1
BJ 2
BJ 4
BJ 4 9
BJ 5
BJ 5 0
BJ 5 2
BJ 5 3
D 1
D 2
D 53
E 1
E5 3
3
1 .1 V S _ V T T
H _ T H R M TR I P # 3
S T P _ P C I # / GP I O 3 4
F 1
AB 6
H O S T _A LE R T # 1
R 1 57
T A C H 3 / GP I O7
A B1 3
H 3
2 7 S B _ MU T E #
S V _ S E T _ UP
R4 1 3
H 10
DG P U_ P W RO K
MF G _ MO D E
6
Y 7
T A C H 2 / GP I O6
GP I O 2 8
10 , 3 1 M XM 1 _ P R S N T #
3 .3 V
T7
AA 2
1 00 K _ 0 4
R 405
K 9
RESET MXM
1 6 D G P U _ H O LD _ R S T #
3 .3 V S
F10
C L K O U T _ P C I E 6N
CL K O UT _ P C IE 6 P
T A C H 1 / GP I O1
MISC
C R_ W A K E #
C
* R B 75 1 V -4 0
S CI#
A
D 19
3 0 S D _ CD #
B MB U S Y # / GP I O0
NCTF
B.Schematic Diagrams
3 1 S M I#
C 38
CPU
Y 3
S MI #
GPIO
B MB U S Y #
*0 _ 0 4
A B 41
T3 9
P 6
C 10
1. 1V S _V TT 3 , 5 , 6 , 1 2 . . 1 4 , 18 . . 2 0 , 3 5 , 3 6
3. 3V 2, 3, 1 2 . . 1 4 , 1 6 , 19 , 2 2 , 2 5 , 2 8, 29 , 3 5 . . 3 9
3. 3V S 3 , 8 . . 1 2, 1 4 , 1 6 , 1 8. . 24 , 2 6 . . 3 5
Schematic Diagrams
PCH 7/8 PWR
IBEXPEAK - M (POWER)
L26
AK2 4
40mA
*HCB100 5KF-121T20_ 04
BJ2 4
This pin can be left as no connect
in On-Die VR enabled mode
C227
*10u _6.3V_X5R_06
1. 1VS_VTT
3.06 2A
C234
C508
C528
C529
C5 30
10u_6 .3V_X5R_06
1u_6.3V_Y5V_04
1u_ 6.3V_Y5V_04
1u_6. 3V_Y5V_04
1u_6.3V_Y5V_0 4
AN2 0
AN2 2
AN2 3
AN2 4
AN2 6
AN2 8
BJ2 6
BJ2 8
AT2 6
AT2 8
AU2 6
AU2 8
AV2 6
AV2 8
AW2 6
AW2 8
BA2 6
BA2 8
BB2 6
BB2 8
BC2 6
BC2 8
BD2 6
BD2 8
BE2 6
BE2 8
BG2 6
BG2 8
BH2 7
AN3 0
AN3 1
1.1VS_VCCAPLL_FDI
L24
*HCB1608KF- 121T25_06
1.1VS_VTT
37mA
3. 3VS
AN3 5
1. 1VS_1.5VS_1. 8VS
AT2 2
BJ1 8
This pin can be left a s no connect
in On-Die VR enabled mode
C223
AM2 3
CRT
AE50
VCCADAC[2]
AE52
C544
C543
AF53
0.0 1u_16V_X7R_04
0.1u_ 16V_Y5V_04
VSSA_DAC[1]
VSSA_DAC[2]
VCCALVDS
VSSA_LVDS
LVDS
1.1VS_VCCAPLL_EXP
VCCIO[2 4]
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
VCCIO[2 5]
VCCIO[2 6]
VCCIO[2 7]
VCCIO[2 8]
VCCIO[2 9]
VCCIO[3 0]
VCCIO[3 1]
VCCIO[3 2]
VCCIO[3 3]
VCCIO[3 4]
VCCIO[3 5]
VCCIO[3 6]
VCCIO[3 7]
VCCIO[3 8]
VCCIO[3 9]
VCCIO[4 0]
VCCIO[4 1]
VCCIO[4 2]
VCCIO[4 3]
VCCIO[4 4]
VCCIO[4 5]
VCCIO[4 6]
VCCIO[4 7]
VCCIO[4 8]
VCCIO[4 9]
VCCIO[5 0]
VCCIO[5 1]
VCCIO[5 2]
VCCIO[5 3]
VCCIO[5 4]
VCCIO[5 5]
VCC3_3[ 1]
VCCVRM[ 1]
VCCFDI PLL
VCCIO[1 ]
3. 3VS
AF51
AH38
1m A
3.3VS_ VCCA_L VD
L46
*HCB1 005KF-121T2 0
3. 3VS
AH39
R454
AP43
AP45
AT46
AT45
0_04
1. 8VS_VCCTX_LVD
59m A
L48
*HCB10 05KF-121T20
1. 8VS
R459
VCCAPLLEXP
VCC3_3[2]
1.0 5V
69mA
VCCADAC[1]
VCC3_3[3]
VCC3_3[4]
AB34
3.3VS
0_04
AB35
AD35
C547
Sheet 18 of 55
PCH 7/8
PWR
0.1 u_16V_ Y5 V_04
VCCVRM[2]
VCCDMI[1]
VCCDMI[2]
AT24
AT16
196 mA
1.1VS_1.5VS_1.8VS
1.1VS_VCC_DMI
61m A
AU16
R436
0_ 04
1 .1VS_VTT
C505
1u_6 .3V_Y5V_04
1. 8V
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
AM8
AM9
AP11
AP9
V_NVRAM_ VCCQ
1 56mA
C507
0.1 u_16V_ Y5 V_04
3.3VS
8 5mA
C534
*10u _6.3V_X5R_06
IBEXPEAK-M
0.1u_16V_Y5V_04
1.1VS_FDI_VCCI O
1.1VS_VTT
R172
0 _04
Ibe x P eak po wer su pp ly ran ge
1.1VS_1 .5VS_1.8VS
1.5 VS
1.8 VS
Min
V olt age
Ma x
R1 80
*0_0 6
1.0 0V
1 .05 V
1. 10V
R1 83
0_06
1.4 3V
1 .5V
1. 58V
1.7 1V
1 .8V
1. 89V
3.1 4V
3 .3V
3. 47V
4.7 5V
5V
5. 25V
1.1VS_VTT 3 ,5,6,1 2..14, 17,19,2 0,35,36
1.1VS_1. 5VS_1.8VS 19
1.5VS 20,28, 38
1.8VS 6,16,3 8
3.3VS 3,8.. 12,14,1 6,17,19 ..24,2 6..35
V_NVRAM_VCCQ 16
PCH 7/8 PWR B - 19
B.Schematic Diagrams
1.1VS_ VTT
POWER
HVCMO S
1u_6.3V_Y5V_0 4
VCCCORE[ 1]
VCCCORE[ 2]
VCCCORE[ 3]
VCCCORE[ 4]
VCCCORE[ 5]
VCCCORE[ 6]
VCCCORE[ 7]
VCCCORE[ 8]
VCCCORE[ 9]
VCCCORE[ 10]
VCCCORE[ 11]
VCCCORE[ 12]
VCCCORE[ 13]
VCCCORE[ 14]
VCCCORE[ 15]
DMI
2.2u_6. 3V_X5 R_ 04
U1 4G
AB2 4
AB2 6
AB2 8
AD2 6
AD2 8
AF2 6
AF2 8
AF3 0
AF3 1
AH2 6
AH2 8
AH3 0
AH3 1
AJ3 0
AJ3 1
PCI E*
C5 42
FD I
NAND / SPI
1. 432A
C512
VCC CORE
1.1VS_VTT
Schematic Diagrams
PCH 8/8 PWR
V olt ag e Rai l Vo lta ge
V _CP U_ IO
1 .1/ 1. 05
V 5RE F
5
V 5RE F_ Su s
5
V cc3 _3
3 .3
V ccA DA C
3 .3
V ccA DP LL A
1 .05
V ccA DP LL B
1 .05
V ccC or e
1 .05
V ccD MI
1 .05
V ccD MI
1 .1
V ccI O
1 .05
V ccL AN
1 .05
V ccM E
1 .05
V ccM E3 _3
3 .3
V ccp NA ND
1 .8
V ccR TC
3 .3
V ccS us 3_ 3
3 .3
V ccS us HD A
3 .3
V ccV RM
1 .8/ 1. 5
V ccA LV DS
3 .3
V ccT X_ LV DS
1 .8
IBEXPEAK - M (POWER)
This pi n ca n be l ef t as no connec t in
O n- Die VR e nabl ed mode
1 .1 V S _ VT T
L 49
*H C B 1 0 05 K F -1 2 1 T2 0
1 . 1V S _V C C A _ C L K
C 27 7
C 2 82
* 10 u _6 . 3 V _ X 5R _0 6
* 0. 1u _ 16 V _ Y 5 V _ 0 4
A P 51
A P 53
A F 23
3 20 mA
1 . 1V S _V T T
P OW ER
U 1 4J
5 2m A
A F 24
1.05V
V C C A C LK [ 1]
VCC
VCC
VCC
VCC
V C C A C LK [ 2]
1.05V
V C CL A N[1 ]
V C CL A N[2 ]
C5 2 4
TP _P C H _ V C C D S W
Y 20
1 u_ 6 . 3 V _Y 5 V _0 4
C 50 9
A D 38
A F 43
1 u _ 6. 3 V _ Y 5 V _ 0 4
A F 41
A F 42
1. 84 9A
V 39
C 2 35
C2 3 6
C 5 25
V 41
22 u _6 . 3 V _ X 5R _0 8
22 u _ 6. 3 V _ X 5R _ 08
1 u _ 6. 3 V _ Y 5 V _ 0 4
V 42
Y 39
V CCR T CEX T
Y 41
C 5 03
Y 42
0 . 1 u _1 0 V _ X7 R _0 4
US B
V C C M E [ 2]
V C C M E [ 3]
V C C M E [ 4]
V C C M E [ 5]
V C C M E [ 6]
V C C M E [ 7]
V C C M E [ 8]
V C C M E [ 9]
V C C M E [ 10 ]
V C C M E [ 11 ]
V C C M E [ 12 ]
1. 1 V S _ V C C A _ A _ D P L
1 . 1 V S _ V TT
L47
H C B 1 0 05 K F -1 2 1T 2 0
V9
D C P R TC
1. 1 V S _ 1 . 5 V S _1 . 8 V S
C2 8 3
C 27 4
C2 6 3
2 2 u_ 6 . 3 V _X 5 R _ 0 8
2 2 u_ 6 . 3 V _ X5 R _ 0 8
1 u_ 6 . 3 V _ Y 5 V _0 4
R 23 4
68 mA
69 mA
* 0_ 0 4
L27
H C B 1 0 05 K F -1 2 1T 2 0
C2 6 7
C 28 8
C2 5 6
2 2 u_ 6 . 3 V _X 5 R _ 0 8
2 2 u_ 6 . 3 V _ X5 R _ 0 8
1 u_ 6 . 3 V _ Y 5 V _0 4
A U 24
B B 51
B B 53
B D 51
B D 53
1 . 1 V S _ V C C A _B _D P L
A H 23
A J 35
A H 35
1 . 1 V S _ V TT
1. 1V S _ V T T
C 53 9
C5 2 0
1 u _6 . 3 V _ Y 5 V _ 04
1 u_ 6 . 3 V _Y 5V _0 4
A F 34
1 .1 VS_ VT T
C 5 10
A H 34
1 u _ 6. 3 V _ Y 5 V _ 0 4
A F 32
V 12
C5 0 4
C5 2 6
0 . 1 u_ 1 6 V _Y 5 V _0 4
V C C V R M[ 3 ]
1.05V
V C C A D P LL A [ 1 ]
V C C A D P LL A [ 2 ]
C lo ck a nd Mi sc el la ne ou s
C 5 13
1.05V
V C C A D P LL B [ 1 ]
V C C A D P LL B [ 2 ]
V C C I O [ 21 ]
V C C I O [ 22 ]
V C C I O [ 23 ]
1.05V
V C C S U S 3 _3 [ 1 ]
V C C S U S 3 _3 [ 2 ]
V C C S U S 3 _3 [ 3 ]
V C C S U S 3 _3 [ 4 ]
V C C S U S 3 _3 [ 5 ]
V C C S U S 3 _3 [ 6 ]
V C C S U S 3 _3 [ 7 ]
V C C S U S 3 _3 [ 8 ]
V C C S U S 3 _3 [ 9 ]
V C C S U S 3 _ 3[ 1 0 ]
V C C S U S 3 _ 3[ 1 1 ]
V C C S U S 3 _ 3[ 1 2 ]
V C C S U S 3 _ 3[ 1 3 ]
V C C S U S 3 _ 3[ 1 4 ]
V C C S U S 3 _ 3[ 1 5 ]
V C C S U S 3 _ 3[ 1 6 ]
V C C S U S 3 _ 3[ 1 7 ]
V C C S U S 3 _ 3[ 1 8 ]
V C C S U S 3 _ 3[ 1 9 ]
V C C S U S 3 _ 3[ 2 0 ]
V C C S U S 3 _ 3[ 2 1 ]
V C C S U S 3 _ 3[ 2 2 ]
V C C S U S 3 _ 3[ 2 3 ]
V C C S U S 3 _ 3[ 2 4 ]
V C C S U S 3 _ 3[ 2 5 ]
V C C S U S 3 _ 3[ 2 6 ]
V C C S U S 3 _ 3[ 2 7 ]
V C C S U S 3 _ 3[ 2 8 ]
V C C I O[ 5 6 ]
V 5 R E F _S U S
0 . 1 u_ 1 6 V _Y 5 V _0 4 1. 1 V _ I N T _ V C C S U S
V C C 3 _3 [ 8 ]
V C C 3 _3 [ 9 ]
V C C 3 _ 3[ 1 0 ]
Y 22
V2 8
U 28
U 26
U 24
P2 8
P2 6
N 28
N 26
M 28
M 26
L28
L26
J28
J26
H 28
H 26
G 28
G 26
F28
F26
E2 8
E2 6
C 28
C 26
B2 7
A2 8
A2 6
163 mA
3 . 3V
C 51 8
0 . 1 u_ 1 6 V _Y 5 V _0 4
3. 3 V _ V C C P U S B
R4 4 3
V C C 3 _ 3[ 1 2 ]
V C C 3 _ 3[ 1 3 ]
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 .1 VS_ VT T
5 V _ P C H _V C C 5 R E F S U S
D1 6
U 23
C
A
R 44 6
R B 5 5 1 V -30 S 2
1 00 _ 0 4
U 19
0 . 1 u _1 6 V _ Y 5 V _ 04
U 20
V C C 3 _ 3[ 1 4 ]
F24
1 mA
5V
K4 9
1 mA
V C C5 RE F
1u _ 1 6V _ X 5 R _ 0 6
J38
V C C S A T A P LL [ 1 ]
1.05VV C C S A T A P LL [ 2 ]
D CPS S T
1.05V
D CPS U S
V 15
C 5 40
V 16
0 . 1 u _1 6 V _ Y 5 V _ 04
Y 16
V C C S U S 3_ 3 [ 3 1]
V C C S U S 3_ 3 [ 3 2]
V C C 3 _ 3[ 5 ]
V C C 3 _ 3[ 6 ]
V C C 3 _ 3[ 7 ]
C 5 35
4 . 7 u _6 . 3 V _ Y 5 V _ 06
0 . 1 u_ 1 6 V _Y 5 V _0 4
0 . 1 u _1 6 V _ Y 5 V _ 04
A U 18
2m A
RT C V CC
V C C I O[ 1 1 ]
V C C I O[ 1 2 ]
VC
VC
VC
VC
V _ C P U _ I O[ 2 ]
C I O[ 1 3 ]
C I O[ 1 4 ]
C I O[ 1 5 ]
C I O[ 1 6 ]
V C C I O[ 1 7 ]
V C C I O[ 1 8 ]
V C C I O[ 1 9 ]
V C C I O[ 2 0 ]
C PU
C 53 2
V C C I O[ 1 0 ]
A T 18
V _ C P U _ I O[ 1 ]
C 2 33
V C C V R M[ 4 ]
3 57m A
3. 3 V S
V C C R TC
C 2 02
I B E XP E A K -M
A R B 5 51 V -3 0 S 2
1 0 0 _0 4
3 .3 VS
5 VS
L38
C 52 7
M 36
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 u _1 6 V _ X5 R _0 6
3. 3 V S
P3 6
C 55 5
U 35
0 . 1 u_ 1 6 V _Y 5 V _0 4
A D 13
AK3
AK1
L 22
* H C B 10 0 5 K F -1 21 T 2 0
3 1mA
1. 1 V S _ V T T
C1 8 7
C 1 85
*1 u _6 . 3 V _ X 5R _0 4
*1 0u _ 6 . 3V _ X 5 R _ 0 6
VC
VC
VC
VC
1.05V
C ME [ 1 3 ]
C ME [ 1 4 ]
C ME [ 1 5 ]
C ME [ 1 6 ]
Thi s pin ca n be le ft a s no c onne ct in
On-D ie VR e na ble d mode
A H 22
AT2 0
1 . 1 V S _ 1 . 5V S _1 . 8 V S
A H 19
A D 20
AF2 2
1 . 1V S _ V T T
A D 19
AF2 0
AF1 9
A H 20
C 52 3
1 u _6 . 3 V _ Y 5 V _ 04
AB1 9
AB2 0
AB2 2
A D 22
AA3 4
Y 34
Y 35
AA3 5
P C H _ V C C _ 1_ 1 _ 20
R 45 3
*2 0 m li _ P _ 04
R TC V C C 12
1 . 1 V S _ 1. 5 V S _ 1 . 8V S 18
1 . 1 V S _ V TT 3 , 5 , 6, 1 2 . . 1 4 , 17 , 1 8 , 20 , 3 5 , 36
5 V 1 1, 25 , 3 6 . . 39
5 V S 1 0 , 11 , 2 0 , 21 , 2 3 . . 27 , 3 2 . . 35
1 . 5 V 3 , 8, 9 , 3 7
3 . 3 V 2 , 3, 1 2 . . 1 4, 1 6 , 1 7, 2 2 , 2 5, 2 8 , 2 9, 3 5 . . 3 9
3 . 3 V S 3 , 8. . 1 2 , 1 4, 1 6 . . 1 8 , 20 . . 2 4 , 26 . . 3 5
1 . 1 V S _V TT
3 . 3 V _ 1. 5 V _ V C C P A Z S U S
A 12
R TC
1m A
V C C S U S 3_ 3 [ 2 9]
C
R2 2 7
C 27 9
1. 1 V S _ V C C A P L L
V C C I O [ 4]
V C C S U S 3_ 3 [ 3 0]
3 .3 V
C2 3 1
V2 3
V C C I O [ 3]
SATA
C 5 19
3 .3 VS
V CCS US HD A
L30
6m A
C 5 37
0 . 1 u _1 6 V _ Y 5 V _ 04
1u _ 6. 3V _ Y 5 V _ 0 4
B - 20 PCH 8/8 PWR
*2 0m i l _P _ 0 4
C 51 7
N 36
V C C I O [ 2]
P CI /G PI O/L PC
P 18
U 22
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 u_ 6 . 3 V _Y 5 V _0 4
V C C 3 _ 3[ 1 1 ]
V C C I O[ 9 ]
C 20 9
1 .1 VS_ VT T
C5 1 4
VCC S S T
3 .3 V
1 . 1V S _V T T
V2 4
V2 6
Y 24
Y 26
D 20
V 5R E F
PC I/ GPI O/ LP C
A D 41
H DA
B.Schematic Diagrams
A D 39
1. 1 V S _ V T T
1.05V
V C C M E [ 1]
0 . 1 u_ 1 6 V _Y 5 V _0 4
Sheet 19 of 55
PCH 8/8
PWR
D CPS U S B Y P
I O[ 5 ]
I O[ 6 ]
I O[ 7 ]
I O[ 8 ]
S0 I cc max C ur ren t (A )
< 1 (m A)
< 1 (m A)
< 1 (m A)
0. 35 7
0. 06 9
0. 06 8
0. 06 9
1. 43 2
0. 05 8
0. 06 1
3. 06 2
0. 32 0
1. 84 9
0. 08 5
0. 15 6
2 (m A)
0. 16 3
6( mA )
0. 19 6
< 1 (m A)
0. 05 9
R 4 48
0 _0 4
R 4 49
*0 _ 04
3 .3 V
1 .5 V
Schematic Diagrams
CLK GEN, HDMI-In
CLOCK GENERATOR
C L K _ 3 . 3V _ 1 . 5 V
RSVD. for ICS9LVS3158
R 1 04
R 92
1 .5 VS
CL K _ V CC 1
U6
* 0_ 0 4
0 _ 04
1
5
17
24
29
C LK _ V C C 1
XO U T
3 3p _ 5 0V _ N P O_ 0 4
1
C1 3 5
C 13 4
3 3p _ 5 0V _ N P O_ 0 4
3 3 _ 04
27
28
XI N
R E F _ 0 / C P U _S E L
30
C LK _ S D A TA
C LK _ S C LK
31
32
33
8
9
12
21
26
2
1
3
4
D OT _ 9 6
D O T_ 9 6 #
3
4
C L K _B U F _ D O T9 6 _P
C L K _B U F _ D O T9 6 _N
X T A L_ O U T
X T A L_ I N
10
11
13
14
S R C _ 1/ S A T A
S R C _ 1 # / S A TA #
SRC _ 2
S R C_ 2 #
R E F _0 / C P U _ S E L
2
1
3
4
RN 4
0 _4 P 2 R _ 0 4
2
1
3
4
RN 5
0 _4 P 2 R _ 0 4
R1 0 7
SD A
SC L
G
2 . 2 K _0 4
1 0 u_ 6 . 3 V _X 5 R _ 0 6
C L K _P C I E _ I C H 13
C L K _P C I E _ I C H # 1 3
C P U _S T OP #
VSS
VSS_ 2 7
VSS_ SATA
VSS_ SR C
VSS_ C PU
VSS_ R EF
20
19
23
22
CP U _ 1
C PU_ 1 #
CP U _ 0
C PU_ 0 #
25
C K P W RG D/P D #
H C B 16 0 8 K F -1 21 T 25
C1 6 5
0. 1 u _ 10 V _ X 7R _0 4
0. 1 u _ 10 V _ X 7R _0 4
10 u _ 6. 3 V _ X 5R _ 06
D
8 , 9 , 1 3, 3 5 S MB _ D A TA _ D D R 3
S
C L K _V C C 1
1 .1 VS _ V T T
VDD_I/O can be
ranging from
1.05V to 3.3V
0.1uF near the every power pin
C LK _ 3 . 3 V _1 . 5 V
1
2
4
3
RN 3
*0 _ 4P 2 R _0 4
1
2
4
3
RN 1
0 _4 P 2 R _ 0 4
C LK _ D OC 1
C LK _ D OC 0
R E F _ 0 / C P U _S E L
C L K _B U F _ B C L K _ P 1 3
C L K _B U F _ B C L K _ N 1 3
3. 3 V S
* 10 p _5 0 V _ N P O _0 4
Sheet 20 of 55
CLK GEN, HDMI-In
EMI Capactior
CPU_SEL_During
1 0 K _0 4
C1 3 1
EMI
C L K _ P W R GD
D
*0 _ 04
L17
C1 5 8
CK_PEWGD Latch Pinl
1 . 1V S _V T T
CPU_0
CPU_1
0(default)
133MHz
133MHz
1(0.7V-1.5V)
100MHz
100MHz
PIN_30
C1 3 6
G
R8 0
* 4 . 7K _ 0 4
R8 1
1 0 K _ 04
R E F _ 0/ C P U _ S E L
*0 . 1 u _1 0 V _ X7 R _ 0 4
1 M _0 4
3 . 3V S
G
5V S
R9 9
C 1 64
C L K _S A TA 1 3
C L K _S A TA # 1 3
2 . 2K _ 0 4
16
CL K _ S CL K
R 78
C 16 3
0 . 1 u_ 1 0 V _X 7 R _ 0 4
13
13
R 82
2 . 2 K _0 4
C 13 2
0 . 1 u_ 1 0V _X 7 R _ 0 4
6
7
27M
27 M_ S S
3 5 CL K EN#
R 77
C1 4 9
0 . 1 u_ 1 0V _ X 7 R _ 0 4
CL K _ V CC 2
V S S _ D OT
S
D
C1 6 0
0 . 1u _ 1 0V _ X 7 R _ 04
0.1uF near the every power pin
RN 2
0 _4 P 2 R _ 0 4
R 83
8 , 9 , 1 3, 3 5 S MB _C LK _ D D R 3
C1 5 4
0 . 1u _ 1 0V _ X 7 R _ 04
15
18
V DD_ S R C_ I/O
V DD_ C P U_ I/O
Q1 8
MT N 7 0 02 Z H S 3
Q1 7
MT N 7 0 02 Z H S 3
S
C1 3 3
CL K _ V CC 2
D_ DO T
D_ 2 7
D_ S RC
D_ CP U
D_ RE F
S L G8 S P 5 8 5
SMBus
L1 6
H C B 1 6 08 K F -1 2 1T 2 5
3 . 3V S
CL K _ DO C0 1 3
CL K _ DO C1 1 3
CL K _ S DA T A
Q1 6
MT N 7 0 02 Z H S 3
R9 7
* 1 0_ 0 4
C L K _D OC 0
R 98
*1 0 _ 04
R9 5
* 1 0_ 0 4
C L K _D OC 1
R 94
*1 0 _ 04
R5 1 4
1 .5 VS
R5 1 3
5V S _ H D MI _ I N
0 _ 04
D4 0 C
* R B 7 5 1 V -40
RSVD. for ICS9LVS3158
0_ 0 6
U 45
5V S
4
5
A
3
1 4, 28 , 3 1, 3 4 , 3 6 S U S B #
V IN
V IN
V O UT
EN
G ND
1
3 . 3 V S _ H D MI _ I N
2
*G5 2 4 3A
R3 1 7
3 .3 VS
1 3 H D MI _ I N _ C L K R E Q#
R ev _3 .0
J _ HDM I_ IN
C 12 8 17 -1 1 9A 5 -L
5
4
3
2
1
H D M I _I N _ V C C
HDM I_ IN_ S DA
16
14
HDM I_ IN_ CL K #
12
HDM I_ IN_ CL K
10
8
HDM I_ IN_ D1 #
6
HDM I_ IN_ D1
4
2
H O T P L U G D E TE C T
+5 V
DD C/C E C G ND
S DA
SC L
RES ER VE D
CEC
TM D S C LO C K C L K S HIE L D
TM D S C LO C K +
TM D S D A T A 0S HIE L D0
T MD S D A T A 0 +
TM D S D A TA 1S H I E LD 1
TM D S D A TA 1+
TM D S D A T A 2S HIE L D2
T MD S D A T A 2 +
19
R 5 54
1K _0 4 H D MI _ I N _ H P D
6
7
8
9
10
1 0 K _ 04
1 3 C L K _ P C I E _ H D MI _ I N #
13 C LK _ P C I E _H D M I _I N
D 42
18
J _M I N I _ H D MI _ I N
2 3 T X _ HDM I_ CL K #
2 3 T X _ HDM I_ CL K
MINI-PCIE CARD for HDMI IN
H D MI _ I N _ C L K #
H D MI _ I N _ C L K
H D MI _ I N _C LK # 2 3
H D MI _ I N _C LK 23
15
H D MI _ I N _S C L
13
H D MI _ I N _C E C
H D MI _ I N _D 0# 2 3
H D MI _ I N _D 0 23
13 P C I E _R X N 8 _H D M I _I N
1 3 P C I E _ R XP 8 _ H D MI _ I N
D 43
11
9
H D MI _ I N _D 0#
7
H D MI _ I N _D 0
5
4
3
2
1
6
7
8
9
10
1 3 P C I E _ T X N 8 _H D M I _I N
1 3 P C I E _ T XP 8 _ H D MI _ I N
H D MI _ I N _D 1#
H D MI _ I N _D 1
H D MI _ I N _D 1# 2 3
H D MI _ I N _D 1 23
H D MI _ I N _D 2#
H D MI _ I N _D 2
2 3 T X_ H D MI _ D 2 #
2 3 T X_ H D MI _ D 2
H D MI _ I N _D 2# 2 3
H D MI _ I N _D 2 23
5
* MS E A 4 2 5 10 V 1 2 B 0
3
H D MI _ I N _D 2#
1
H D MI _ I N _D 2
D 44
1
H D M I _I N _ S C L
3
2
H D M I _I N _ S D A
W AKE#
B T_ D A TA
B T_ C H C L K
CL K RE Q #
GN D 0
R E F C LK R E F C LK +
GN D 1
3 .3 V_ 0
GN D 5
1 .5 V_ 0
U I M_ P W R
U I M_ D A TA
U I M _C LK
U I M_ R E S E T
U I M _V P P
2
4
6
8
10
12
14
16
3 . 3V S _H D M I _I N
1 . 5V S
H D M I _I N _V C C
T X_ H D MI _ S D A 2 3
T X_ H D MI _ S C L 2 3
H D MI _ I N _H P D
C 39 2
C5 7 9
1 u _6 . 3 V _ X5 R _ 0 4
0. 1u _ 16 V _ Y 5 V _ 0 4
KEY
H D MI _ I N _ D 0 #
H D MI _ I N _ D 0
* MS E A 4 2 5 10 V 1 2 B 0
17
1
3
5
7
9
11
13
15
H D MI _ I N _ S C L 2 3
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NC3
NC4
GN D 2
P E Tn 0
P E Tp 0
GN D 3
GN D 4
P ERn 0
P ERp 0
GN D 1 1
NC6
NC7
NC8
NC9
NC1 0
NC1 1
NC1 2
NC1 3
GN D 6
W _D I S A B L E #
PER SET #
3. 3 V A U X
GN D 7
1 .5 V_ 1
N C (S MB _C LK )
N C (S MB _ D A TA )
GN D 8
N C (U S B _ D -)
N C (U S B _D +)
GN D 9
N C (L E D _ W W A N #)
L E D _W LA N #
N C (L E D _ W P A N #)
1 .5 V_ 2
GN D 1 0
3 .3 V_ 1
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
B U F _P L T _R S T # 3, 1 6 , 28 . . 3 1
3 . 3V S _H D M I _I N
TX _ H D MI _ D 0 # 2 3
TX _ H D MI _ D 0 2 3
5 V S _ H D MI _ I N
TX _ H D MI _ D 1 # 2 3
TX _ H D MI _ D 1 2 3
1 . 5V S
3 . 3V S _H D M I _I N
C 39 8
C4 0 2
C3 9 4
1 u _ 6. 3 V _ X 5R _0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
*1 0 u _6 . 3 V _ X5 R _ 0 6
B E L LW E TH E R 8 0 00 3 -1 02 1
H = 4.0 mm
H D MI _ I N _ S D A 23
*T V N _ S T 23 _ 0 2_ A B 0
1 .5 VS
3. 3 V S _ H D MI _ I N
C 39 6
C 4 03
C4 0 0
C 58 7
C 39 3
C3 9 9
C 3 95
C 4 04
C3 9 7
C 4 01
1 u _ 6. 3 V _ X 5R _0 4
0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1u _ 1 6V _ Y 5V _ 0 4
* 10 u _ 6. 3 V _ X 5R _0 6
1 0 u _6 . 3 V _ X5 R _ 0 6
1 0u _ 6. 3V _ X 5R _ 06
1 u _ 6. 3 V _ X 5R _0 4
1 u _ 6. 3 V _ X 5R _0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 04
2 3 H D MI _ I N _ V C C
5V S _H D M I _I N
2, 3 , 1 2 . . 14 , 1 6 , 17 , 1 9, 22 , 2 5, 2 8 , 2 9, 3 5 . . 3 9 3. 3 V
1 8, 2 8 , 3 8 1 . 5 V S
3 , 8. . 1 2 , 1 4, 1 6 . . 1 9, 2 1 . . 2 4, 2 6 . . 3 5 3 . 3 V S
1 0 , 11 , 1 9 , 21 , 2 3 . . 27 , 3 2 . . 35 5 V S
3 , 5 , 6, 12 . . 1 4, 17 . . 1 9, 35 , 3 6 1. 1 V S _ V T T
CLK GEN, HDMI-In B - 21
B.Schematic Diagrams
R7 9
1 3 C L K _B U F _ R E F 1 4
2
6 -2 2-1 4R 31- 1B H
2
X1
X 8 A 01 4 3 1A F K 1H _1 4 . 3 18 1 8 MH z
VD
VD
VD
VD
VD
3 . 3V S
CLKGEN POWER
C LK _ V C C 1
Schematic Diagrams
CRT, DVI
DVI PORT
5 V S _ D V I _P W R
D 13
5 VS
R 34
1 K_ 0 4
L 11
F C M1 0 0 5K F -1 21 T 0 3
C9 8
R B 5 5 1 V -3 0 S 2
0. 1 u _ 1 6V _Y 5 V _ 04
J _D V I
Close to DVI connector
R3 2
C 77
5 V S _D V I _ P W R
*4 7 K _ 0 4
C
C7 2
R 54
4 . 3 K _ 1% _ 0 4
R 44
4 . 3 K _ 1% _ 0 4
D V I_ D# 2 _ R
D V I_ D2 _ R
D V I _D # 4
D V I_ D4
D V I _D # 1
D V I_ D1
C1 1 4
C1 0 4
C1 4 0
C1 3 7
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1u _ 1 0 V _ X7 R _0 4
D V I_ D# 4 _ R
D V I_ D4 _ R
D V I_ D# 1 _ R
D V I_ D1 _ R
4 70 p _ 5 0V _X 7 R _0 4
1 0 D V I _D # 3
10 D V I _ D 3
C1 2 0
C1 1 8
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1u _ 1 0 V _ X7 R _0 4
D V I_ D3 _ R
D V I_ D# 3 _ R
5 VS
1 0 D V I _D # 0
10 D V I _ D 0
C1 4 6
C1 4 4
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1u _ 1 0 V _ X7 R _0 4
D V I_ HP D_ R
D V I_ D# 0 _ R
D V I_ D0 _ R
C1 2 4
C1 2 6
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1u _ 1 0 V _ X7 R _0 4
D V I_ D# 5 _ R
D V I_ D5 _ R
C8 0
C8 4
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1u _ 1 0 V _ X7 R _0 4
D V I_ CL K _ R
D V I_ CL K # _ R
G
3. 3 V S
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1u _ 1 0 V _ X7 R _0 4
10
10
10
10
A
D 7
* BAV9 9
C1 3 0
C1 2 7
1 0 D V I _D # 2
10 D V I _ D 2
4 7 0p _ 5 0 V _ X7 R _ 04
AC
S
1 0 D V I _ D D C _D A T
D
Q 9
M T N 7 0 0 2Z H S 3
G
S
1 0 D V I _ D D C _C L K
5 V S _ DV I_ P W R
D
Q 11
M T N 7 0 02 Z H S 3
R 55
4 . 7 K _0 4
R 52
4 . 7 K _0 4
1 0 D V I _D # 5
10 D V I _ D 5
DD CD A T A
1 0 D V I_ CL K
1 0 DV I_ C L K #
DD CC L K
DV
DV
DV
DV
DV
DV
DV
I _R
I _G
I _B
I _H
I _V
I _D
I _D
ED
R EEN
LU E
S Y NC
SYN C
D CD A T
D C C LK
R2 9
R3 3
R5 1
R5 3
D
D
D
D
3 3 _ 04
3 3 _ 04
3 3 _ 04
3 3 _ 04
1
2
3
4
5
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
C1
C2
C3
C4
8
7
6
VI_ H
VI_ V
V I_ DD A T
V I_ DC L K
DVI
TM
TM
TM
TM
TM
TM
TM
TM
TM
TM
DS
DS
DS
DS
DS
DS
DS
DS
DS
DS
+ 5V P OW E R
DA T A 2 DA T A 2 +
2/ 4 S hi e l d
DA T A 4 DA T A 4 +
DA T A 1 DA T A 1 +
D A T A 1 / 3 S h i e dl
DA T A 3 DA T A 3 +
GN D (A N A L OG )
H O T P LU G D E T E C T
TM D S D A T A 0 TM D S D A T A 0 +
TM D S D A T A 0 / 5 S h i e dl
TM D S D A T A 5 TM D S D A T A 5 +
TM D S C L K S h i e dl
TM D S C L K +
TM D S C l k C ASE
C ASE
RE D
GR E E N
B L UE
H S Y NC
C ASE
V S Y NC
C ASE
DD C D a ta
GN D
D D C C kl
GN D
D SUB
14
M3
M4
M1
M2
C 5
C 6
QH 1 11 2 1 -D J T 0 -4 F
G
5 VS
10 V GA _ H S Y N C
D
Q 7
MT N 70 0 2 Z H S 3
S
10 V GA _ V S Y N C
H SYN C
Very close to DVI connector
V S Y NC
D
Q8
MT N 7 0 0 2 Z H S 3
D V I _ D #0 _ R
R 96
4 99 _ 1 % _0 4
R 36
1K _ 0 4
D V I _ D 0_ R
R 93
4 99 _ 1 % _0 4
R 31
1K _ 0 4
D V I _ D #1 _ R
R 85
4 99 _ 1 % _0 4
D V I _ D 1_ R
R 84
4 99 _ 1 % _0 4
D V I _ D #2 _ R
R 76
4 99 _ 1 % _0 4
D V I _ D 2_ R
R 75
4 99 _ 1 % _0 4
D V I _ C LK _R
R 38
4 99 _ 1 % _0 4
D V I _ C LK #_ R
R 42
4 99 _ 1 % _0 4
D V I _ D 3_ R
R 69
4 99 _ 1 % _0 4
D V I _ D #3 _ R
R 68
4 99 _ 1 % _0 4
D V I _ D #4 _ R
R 67
4 99 _ 1 % _0 4
D V I _ D 4_ R
R 61
4 99 _ 1 % _0 4
D V I _ D #5 _ R
R 73
4 99 _ 1 % _0 4
D V I _ D 5_ R
R 74
D V I_ HS Y NC
L 14
F C M1 0 05 K F -12 1 T 0 3
D V I_ DD CD A T
DV I_ D DA T
D DC CL K
L 15
F C M1 0 05 K F -12 1 T 0 3
D V I_ DD CC L K
DV I_ D CL K
AC
A
C
A
C
5 VS
D 3
* BAV9 9
A
A
AC
D4
*B A V 9 9
C
1 0p _ 5 0 V _ N P O _ 04
A C
1 0 p _ 50 V _ N P O_ 0 4
C
1 0 p _5 0 V _ N P O_ 0 4
5V S
C7 5
C
1 0p _ 5 0 V _ N P O _ 04
C 76
A C
AC
5 VS
C 90
D 12
* BAV9 9
DV I_ V
D DC DAT A
C9 5
D9
*B A V 99
DV I_ H
D V I_ V S Y NC
F C M1 0 05 K F -12 1 T 0 3
5 VS
A
L 10
F C M1 0 05 K F -12 1 T 0 3
D 8
* BAV9 9
AC
V S Y NC
L8
D6
*B A V 9 9
5 VS
A
A
C
A C
H SYN C
5V S
C
5 VS
5 V S _ DV I_ P W R
D2
*B A V 99
D V I_ RE D
F C M1 0 0 5 K F -1 2 1T 0 3
D V I_ RE D
L6
F C M1 0 0 5 K F -1 2 1T 0 3
D V I _ GR E E N
D V I_ B L UE
L5
1 0 VG A_ B
B - 22 CRT, DVI
L7
D V I _ GR E E N
1 0 V GA _ G
F C M1 0 0 5 K F -1 2 1T 0 3
1 0, 11 , 1 4 , 2 2 , 24 A LL _ S Y S _ P W R G D
D V I_ B L UE
R 28
R 25
R2 1
C6 9
C 61
C 55
C5 8
C 66
C7 1
1 5 0 _1 % _ 0 4
1 5 0 _ 1% _ 0 4
15 0 _ 1 %_ 0 4
1 0p _ 5 0 V _ N P O _0 4
1 0 p _5 0 V _ N P O_ 0 4
1 0 p _ 50 V _ N P O_ 0 4
1 0p _ 5 0 V _ N P O _ 04
1 0 p _5 0 V _ N P O_ 0 4
10 p _ 50 V _ N P O_ 0 4
R8 6
0_ 0 6
G
S
1 0 V GA _ R
4 99 _ 1 % _0 4
Q1 9
*MT N 7 00 2 Z H S 3
D
S
G
B.Schematic Diagrams
C
D V I _H P D _R
10 D V I _ H P D
Sheet 21 of 55
CRT, DVI
A
3 . 3 V S 3 , 8 . . 1 2, 14 , 1 6 . . 2 0 , 22 . . 2 4 , 2 6 . . 3 5
5 V S 1 0 , 1 1, 19 , 2 0 , 2 3. . 27 , 3 2 . . 3 5
3 . 3 V 2 , 3 , 12 . . 1 4 , 1 6 , 1 7, 1 9 , 2 2 , 2 5, 2 8 , 2 9 , 3 5. . 39
V D D 3 1 2 , 2 8, 3 1 . . 3 4 , 3 9, 4 0
Schematic Diagrams
Panel, Inverter, TPM
TPM 1.2
18.4" PANEL
U3 1
12 , 3 1
12 , 3 1
12 , 3 1
12 , 3 1
P L VDD
26
23
20
17
L PC_ AD0
L PC_ AD1
L PC_ AD2
L PC_ AD3
P CL K _ T P M
1 6 P CL K _ T P M
C8 5
C9 2
0. 1u _ 16 V _ Y 5 V _ 0 4
*1 0 u _1 0 V _ Y 5 V _ 08
R 24
R 26
J_ L C D
1 0 LV D S _ U 1 N
1 0 LV D S _ U 1 P
1 0 LV D S _ U 2 N
1 0 LV D S _ U 2 P
1 0 L V DS _ UC L K N
1 0 LV D S _ U C LK P
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
3 .3 V S
L V DS _ DD C_ CL K 1 0
L V DS _ DD C_ DA T 1 0
L V D S _ L 0N
L V D S _ L 0P
10
10
L V D S _ L 1N
L V D S _ L 1P
10
10
L V D S _ L 2N
L V D S _ L 2P
10
10
22
16
27
15
28
1 4 S 4 _ S TA TE #
TP M_ B A D D
9
TP M_ P P
7
1
3
12
8
L V D S _ L C L K N 10
L V DS _ L CL K P 1 0
0
1
2
3
L C LK
V D D1
V D D2
V D D3
10
19
24
3 .3 V S
C 37 7
C3 8 3
C3 7 5
C 3 73
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
*0 . 1 u _1 6 V _ Y 5 V _ 04
*0 . 1 u_ 1 6 V _Y 5 V _0 4
* 1 u_ 1 0V _0 6
TPM
L F R A ME #
L R ESET #
S ERIR Q
C L K RU N#
V SB
5
3 .3 V
C 38 2
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
L P C P D#
GP I O
GP I O2
T E S T B I/B A D D
XTAL I
6
2
13
X7
* C M2 0 0 S 32 7 6 81 2 2 0_ 3 2 . 76 8 K H z
4
1
3
2
P P
X TA LO
N C_ 1
N C_ 2
N C_ 3
T EST I
GN D _ 1
GN D _ 2
GN D _ 3
GN D _ 4
14
4
11
18
25
C3 8 1
C 38 0
*1 5p _ 5 0V _ N P O_ 0 4
* 15 p _ 50 V _ N P O _ 04
*S L B 9 63 5 T T
8 8 10 7 -3 00 0 1
Asserted before entering S3
LPC reset timing:
LPC_PD# inactive to LPC_RST# inactive 32~96us
HI
T PM_ PP
T PM_ BA DD
T P M_ P P
R 3 06
* 10 K _ 0 4
T P M_ B A D D
R 3 07
* 10 K _ 0 4
R 3 08
* 10 K _ 0 4
Sheet 22 of 55
Panel, Inverter,
TPM
3 .3 V S
: AC CE SS
L OW : NO RM AL
( De fa ul t )
HI
( De fa ul t )
: 4E / 4 F h
P C L K _T P M
L OW : 2E / 2 F h
VIN
INVERTER
L9
H C B 1 60 8 K F -1 2 1T 2 5
R2 9 8
*3 3 _0 4
C 37 6
*1 0p _ 5 0V _ N P O_ 0 4
40mil
C 65
C7 3
C 74
* 10 u _ 25 V _ N P O _ 12
*0 . 0 1 u_ 5 0 V _X 7 R _ 0 4
0 . 0 1u _ 5 0V _ X 7 R _ 0 4
B R I GH TN E S S
AC
J _ INV
I N V _ B L ON
R3 7
0_ 0 4
C7 9
0. 1 u _ 16 V _ Y 5 V _ 0 4
A
C
*B A V 9 9
PANEL POWER
3 1 B RIG HT NE S S
B R I GH TN E S S
6
87 2 1 3-0 6 0 0G
3 .3 V
3 .3 V S
JINV
1
1
2
3
4
5
6
D3 9
C5 8 6
U3
1
V IN
V IN
PL VD D
V OU T
EN
G ND
*0 . 1 u _1 6 V _ Y 5 V _ 04
3 . 3V
3 . 3V
2
G 52 4 3 A
C 62
4
3 1 B K L _E N
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
6
3. 3 V
5
1 0 P N L _B L _ E N
7
From EC
From MXM
U1 B
7 4L V C 0 8 P W
R3 0
3. 3 V S
U 1C
7 4 L V C0 8 P W
14
1 0 P NL _ P W R_ E N
3
14
P N L _P W R _ E N
14
4
5
9
*1 0 0 K _0 4
8
S Y S 15 V
1
2
3
R7 1
* 1 M_ 04
*1 M_ 0 4
3
D
D
D
G
S
*0 . 1 u_ 1 6 V _Y 5 V _0 4
3. 3 V
6
From Hall IC
5
1A
4
31 , 3 3 L I D _ S W #
R2 7
C
D5
1 0 , 1 1, 1 4 , 2 1, 2 4 A L L _S Y S _ P W R G D
10 0 K _ 04
A
R B 7 5 1V -4 0
U 1D
7 4 LV C 0 8P W
7
7
0. 1 u _ 16 V _ Y 5 V _ 0 4
I N V _ B L ON
2
12
11
13
P L VDD
7
R 70
D
C1 0 2
14
Q1 2
SYS1 5 V
C 1 15
U 1A
7 4 L V C0 8 P W
1
10
3 . 3V
D
*S I 3 4 5 6D V -T 1-E 3
Q 13
R6 3
C 1 13
R6 5
R6 4
10 0 K _ 04
0 . 1 u _1 6 V _ Y 5 V _ 04
*2 2 0_ 0 4
*2 20 _ 0 4
1 7 S B _ B L ON
C 1 22
*0 . 02 2 u _2 5 V _ X7 R _0 6
D
B
Q 15
* MT N 7 0 02 Z H S 3
G
E
Q1 4
* D T C 1 1 4E U A
S
P N L _P W R _ E N
*M TN 70 0 2 Z H S 3
S
C
G
2 , 3 , 1 2. . 1 4 , 1 6, 1 7 , 1 9, 2 5 , 2 8, 29 , 3 5. . 39 3 . 3 V
3 , 8 . . 1 2, 1 4 , 1 6. . 2 1 , 2 3, 2 4 , 2 6. . 3 5 3 . 3 V S
1 1, 3 4 . . 4 0 V I N
34 , 3 9 S Y S 1 5 V
Panel, Inverter, TPM B - 23
B.Schematic Diagrams
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
3. 3 V S
1 0 LV D S _ U 0 N
1 0 LV D S _ U 0 P
4 . 3 K _ 1% _ 0 4
4 . 3 K _ 1% _ 0 4
21
12 , 3 1 LP C _ F R A M E #
1 6 , 33 P L T _R S T #
1 2, 3 1 S E R I R Q
1 4 P M_ C LK R U N #
L AD
L AD
L AD
L AD
Schematic Diagrams
HDMI Repeater, Fan Control
NOTE:
H/W
S/W
HDMI IN
REPEATER
PCSCL
H
H
PCSDA
L
H
PC SC L
R 538
4 .7 K _ 0 4
PC SD A
R 539
* 4. 7 K _0 4
R 540
4 7 _ 04
3 . 3 V S _ C A T 6 35 1
FAN CONTROL
5 VS
U 39
1
2
3
4
3 . 3 V S _ C A T 6 35 1
3 1 C P U _F A N
FO N
VIN
V O UT
VSE T
G
G
G
G
8
7
6
5
ND
ND
ND
ND
G 9 90 P 1 1 U
C 5 46
C 5 45
0 . 1 u _ 16 V _ Y 5 V _ 0 4
* 10 u _ 1 0 V _ Y 5 V _ 0 8
3 . 3 V S _ C A T 6 35 1
400mA
C5 9 9
C6 0 1
C6 0 2
C6 0 3
10 u _ 6 . 3 V _ X 5R _ 0 6
0. 1u _ 1 6 V _ Y 5 V _ 0 4
0 . 1u _ 1 6 V _ Y 5 V _ 0 4
0 . 1u _ 1 6 V _ Y 5 V _ 0 4
H D MI _I N _ S D A R 5 5 2
H D MI _I N _ S C L R 5 5 3
R 530
31
32
33
34
35
36
37
38
39
40
41
2 0 H D MI _ I N _ C L K #
2 0 H D M I _I N _ C LK
2 0 H D M I _I N _ D 0#
2 0 H DM I_ IN_ D 0
2 0 H D M I _I N _ D 1#
2 0 H DM I_ IN_ D 1
VS S
R X CM
R X CP
VC C
R X 0M
R X 0P
VS S
R X 1M
R X 1P
VC C
PA D
5V S _ C P U F A N
J _ CP UF A N
* 0 _ 04
* 0 _ 04
R5 4 5
* 0 _ 04
T X_ H D M I _ S D A
T X_ H D M I _ S C L
T X_ H DM I_ SDA 2 0
T X_ H DM I_ SCL 2 0
R4 5 5
3 .3 V S
C
D3 7
S M C_ T H E RM _ 2 1 0 ,3 1
C A T 6 3 51
VS S
T XCM
TXC P
VCC
T X0 M
TX0 P
VS S
T X1 M
TX1 P
VCC
C 5 36
A
S C S 3 55 V
1 0 u _ 10 V _ Y 5 V _ 0 8
8 5 2 0 5-0 3 7 0 1
CPU FAN
VGA SLAVE FAN
5V S
20
19
18
17
16
15
14
13
12
11
1
2
3
4 . 7 K _ 04
3 1 CPU _ F AN SEN
30
29
28
27
26
25
24
23
22
21
PC SCL
RE X T
R XSC L
RX S DA
VCC
VS S
P C S CL
VCC
T X S DA
T X S CL
VSS
U4 8
Sheet 23 of 55
HDMI Repeater,
Fan Control
R5 4 3
R5 4 4
* 0 _0 4
* 0 _0 4
4 9 9 _1 % _ 0 4
3 . 3 V S _ C A T6 3 5 1
0_04
0_04
U1 7
1
2
3
4
3 1 V G A F A N 1 _ ON
T X _ H D MI _ C L K # 2 0
T X _ H D MI _ C L K 2 0
T X _ H D MI _ D 0 # 2 0
T X _ H D MI _ D 0 2 0
F
V
V
V
ON
IN
OU T
SET
G
G
G
G
C2 6 9
0 .1 u _ 1 6 V _ Y 5 V_ 0 4
*1 0 u_ 1 0 V _ Y 5V _0 8
5 VS_ VG AF AN 1
J_ V G A F A N 1
3 .3 VS
R 2 01
3 . 3 V S _C A T 6 3 5 1
C
D1 8
1
2
3
4 .7 K_ 0 4
C2 5 1
A
SC S3 5 5 V
10 u _ 1 0 V _ Y 5 V _ 0 8
85 2 0 5 -0 37 0 1
MXM1 FAN
1
2
3
4
5
6
7
8
9
10
VG A_ FAN 1 SEN
20 H D MI _ I N _ D 2 #
2 0 H D MI _I N _ D 2
T X _ H D MI _ D 2 # 2 0
T X _ H D MI _ D 2 2 0
3 . 3 V S _C A T 6 3 51
R 53 1
PC SD A
R5 4 6
* 0 _ 04
5 VS
VGA MASTER FAN
U4 0
1
2
3
4
S M D_ T H E RM _ 2 1 0 ,3 1
4 . 7K _0 4
3 1 V GA F A N 2_ O N
R 54 7
4 . 7K _0 4
R 548
* 4. 7 K _ 0 4
8
7
6
5
ND
ND
ND
ND
G9 9 0 P 1 1U
C 278
T X _ H D MI _ D 1 # 2 0
T X _ H D MI _ D 1 2 0
RX 2 M
R X2 P
VSS
V CC
I2 C EN
OE B
P CS DA
VS S
TX2 P
TX2 M
2 0 H DM I_ IN_ S D A
2 0 H D M I _I N _ S C L
3 . 3 V S _ C A T 6 35 1
F ON
VIN
V OU T
VSET
GN
GN
GN
GN
8
7
6
5
D
D
D
D
G9 9 0 P 1 1 U
C5 5 3
C5 5 4
0 . 1 u_ 1 6 V _ Y 5V _0 4
*1 0 u _ 10 V _Y 5 V _ 0 8
5 V S _ V G A F A N2
A
H D MI _ I N _ V C C
5 VS
C
R 54 9
D 45
A
*R B 7 5 1 V -4 0
C
D 46
*R B 7 5 1 V -4 0
5 VS
U 47
*4 7 K _ 0 4
8
7
6
5
H DM I_ IN_ S C L
H DM I_ IN_ S D A
R 55 0
R 55 1
VC C A0
WP
A1
SC K A2
SD A VSS
J _ V GA F A N 2
1
2
3
4
3. 3 V S
C
D 17
* A T 2 4 C 0 2 B N -S H - T
4 7K _0 4
4 7K _0 4
R1 9 9
6 -0 4- 02 40 2 -A92
1
2
3
4. 7 K _ 0 4
C5 3 3
A
SCS3 5 5 V
1 0 u_ 1 0 V _ Y 5 V _0 8
8 5 20 5 -0 3 7 01
MXM2 FAN
VG A_ FAN 2 SEN
3 .3 V S
3 .3 VS
R547 R548 U47,R549,D45,D46 R541,R542 R543,R544 R552,R553
V
V
V
V
X
W/O
? ?
W/O
? ?
V
X
X
X
V
V
R 20 0
5
X
1 0 0 K _ 04
VG A_ F AN 1 SEN
4
2
X
V
X
X
3 1 V GA S E N _S E L
Q 20
M T N7 0 0 2 Z HS 3
G
4
S
2
Vin
O ut
3
5
1A
2
3 V S _ C A T6 3 5 1
U 20
1
4
4
GN D
R 532
VG A_ F AN 2 SEN
2
R2 1 4
7 4 A H C 1 G 0 8 GW
* 1 21 _ 1 % _ 0 4
* 1 0u _ 6 . 3 V _ X 5 R _ 0 6
1 00 K _ 0 4
Z0 103
C 60 5
C 60 6
1 0 u _6 . 3 V _ X 5 R _ 0 6
1 0 u _6 . 3 V _ X 5 R _ 0 6
R 535
* 2 00 _ 1 % _ 0 4
Rev_3.0
B - 24 HDMI Repeater, Fan Control
7 4 A H C 1 G 32 G W
3 .3 VS
* C M 1 1 17
Gn d / A d j
3
C 604
U 19
1
3 .3 VS
U 46
3 .3 VS
7 4 A H C 1 G 0 8 GW
5
X
3
V
L52
H C B 1 6 0 8 K F -1 2 1 T 25
5V S
U 16
1
D
EEPROM,
repeater
EEPROM,
repeater
H D M I _ I N _V C C 2 0
5 VS_ H DM I_ IN 2 0
3 . 3 V S 3, 8. . 12 , 1 4 , 1 6 . . 2 2 , 2 4, 2 6 . . 3 5
5 V S 10 , 1 1 , 1 9 . . 2 1 , 2 4. . 2 7, 3 2 . . 3 5
3 . 3 V 2 , 3 , 1 2 . . 1 4 , 1 6 , 17 , 1 9 , 2 2 , 2 5 , 2 8, 29 , 3 5 . . 3 9
V D D 3 12 , 2 8 , 3 1 . . 3 4 , 3 9, 40
3
NOTE:
W/EEPROM
1
B.Schematic Diagrams
H D MI _I N _ S C L R 5 4 1
H D MI _I N _ S D A R 5 4 2
VG A_ FAN SEN
31
Schematic Diagrams
HDMI Switch
HDMI SWITCH
3. 3 V S _ H D M I
0 . 1 u_ 1 6 V _Y 5 V _ 04
H D MI _ S 1
H D MI _ S 2
H D MI _ E Q
10 H D M I _S 1
32
33
34
17
18
H DM I_ CL K
H D MI _ C LK #
H DM I_ 1
H D M I _# 1
23
24
H DM I_ 2
H D M I _# 2
26
27
29
30
31
H DM I_ S CL
H DM I_ S DA
H D MI _ H P D
49
3. 3V S _H D M I 1
PORT1
S1
S2
EQ
Y 4 (P )
Z 4 (N )
C4 7
R 43
0 . 1u _ 1 6 V _Y 5 V _ 04
4 . 0 2 K _1 % _ 0 4
(P )A 1 2
(N )B 1 2
(P )A 1 1
(N )B 1 1
S CL 1
S DA 1
H P D1
H D M I _ C C LK _C
H D M I _ C C LK #_ C
45
44
H DM I_ C0 _ C
H D M I _ C # 0 _C
42
41
H DM I_ C1 _ C
H D M I _ C # 1 _C
39
38
H DM I_ C2 _ C
H D M I _ C # 2 _C
37
36
35
H DM I_ C_ S C L
H DM I_ C_ S D A
HDMI_EQ
Y 2 (P )
Z 2 (N )
(P )A 2 4
(N )B 2 4
Y 1 (P )
Z 1 (N )
S CL _ S INK
S DA _ S IN K
H P D _S I N K
HDMI
(P )A 2 3
(N )B 2 3
PORT2
(P )A 2 2
(N )B 2 2
(P )A 2 1
(N )B 2 1
VDD
V S A DJ
S CL 2
S DA 2
H P D2
H DM I_ DCL K 1 0
H DM I_ DCL K # 1 0
60
59
H DM I_ D0 1 0
H D M I _ D # 0 10
57
56
H DM I_ D1 1 0
H D M I _ D # 1 10
52
51
50
HDMI 1.3 compliant cable
H
10m 28 AWG HDMI cable
HDMI_S1 HDMI_S2
H
PORT1
L
H
PORT2
Chipset
R56
R57
D10, D11, D42
TMDS251
Stuff
x
Stuff
Stuff
x
N10 (N9 Core)
H DM I_ D_ S C L
H DM I_ D_ S D A
TMDS261
H DM I_ D_ S CL 1 0
H D M I _ D _ S D A 10
H DM I_ DHP D 1 0
x
R6 2
3 .3 V S
HDMI OUT
4. 7 K _ 0 4
H DM I_ S DA
R 46
4. 7 K _ 0 4
5 VS
C
D 41
A
R B 7 5 1V -4 0
19
18
16
14
H D MI _ C LK #
H DM I_ CL K
12
10
8
H D M I _# 1
H DM I_ 1
6
+5 V
17
SC L
RE S E R V E D
C EC
TM D S C L OC K C LK S H I E L D
TM D S C L OC K +
T M D S D A T A 0S HIE L D 0
TM D S D A T A 0 +
TM D S D A T A 1 S H I E LD 1
TM D S D A T A 1 +
2
T M D S D A T A 2S HIE L D 2
TM D S D A T A 2 +
15
H D MI _ S C L
H DM I_ S CL
13
11
9
7
H D M I _ #0
H DM I_ 0
5
3
1
H D M I _ #2
H DM I_ 2
C4 1
C4 5
0. 1 u _ 1 0V _ X 7 R _ 0 4
0. 1 u _ 1 0V _ X 7 R _ 0 4
H D MI _ C C L K 1 0
H D MI _ C C L K # 10
H D MI _C 2 _C
H D MI _C # 2_ C
C7 8
C8 1
0. 1 u _ 1 0V _ X 7 R _ 0 4
0. 1 u _ 1 0V _ X 7 R _ 0 4
H D MI _ C 2 1 0
H D MI _ C # 2 1 0
H D MI _C 1 _C
H D MI _C # 1_ C
C5 9
C6 3
0. 1 u _ 1 0V _ X 7 R _ 0 4
0. 1 u _ 1 0V _ X 7 R _ 0 4
H D MI _C 0 _C
H D MI _C # 0_ C
C5 1
C5 6
0. 1 u _ 1 0V _ X 7 R _ 0 4
0. 1 u _ 1 0V _ X 7 R _ 0 4
R2 0
R1 9
R2 3
R2 2
R3 9
R3 5
R1 6
R1 4
DDC /CE C G ND
S DA
4
Stuff
* 0_ 0 6
D 11
A
C
R B 5 51 V -3 0 S 2
D 10
A
C
R B 5 51 V -3 0 S 2
A
C
R1 3
D 1
3 . 3 V S _ H D MI
*0 _ 06
R B 7 51 V -4 0
3 . 3 V S _ H D MI 1
49 9 _ 1%
49 9 _ 1%
49 9 _ 1%
49 9 _ 1%
49 9 _ 1%
49 9 _ 1%
49 9 _ 1%
49 9 _ 1%
_04
_04
_04
_04
_04
_04
_04
_04
G
A L L_ S Y S _ P W R G D
3. 3V S _H D M I
R 57
*2 . 2 K _ 0 4
R 56
4 . 7 K _0 4
H D MI _ C 1 1 0
H D MI _ C # 1 1 0
H D MI _ E Q
Re v_ 3. 0
H D MI _ C 0 1 0
H D MI _ C # 0 1 0
3. 3V S _H D M I
R 47
4 .7 K _ 0 4
H D MI _ S 1
R 48
4 .7 K _ 0 4
H D MI _ S 2
R 17
2 .2 K _ 0 4
H D MI _ D _S C L
R 18
2 .2 K _ 0 4
H D MI _ D _S D A
R 50
2 .2 K _ 0 4
H D MI _ C _S C L
R 49
2 .2 K _ 0 4
H D MI _ C _S D A
10 , 1 1 , 14 , 2 1 , 2 2
Q1 0
MT N 70 0 2 Z H S 3
3 . 3 V S 3 , 8 . . 1 2, 14 , 1 6 . . 2 3, 2 6 . . 3 5
5 V S 1 0 , 1 1 , 19 . . 2 1 , 2 3, 2 5 . . 2 7 , 32 . . 3 5
G ND 1
GN D 2
G ND 3
GN D 4
H D MI _ S D A
Sheet 24 of 55
HDMI Switch
x
G ND1
GN D 2
G ND 3
GN D 4
H DM I_ S DA
H DM I_ HP D
H OT P L U G D E T E C T
H D MI _C C L K _ C
H D MI _C C L K # _ C
D
*2 2 u _6 . 3 V _ X 5R _ 08
S
C5 3 8
R62, R13
5 VS
J_ H D M I
C 1 2 80 7 -1 19 A 5 -L
2 2 u _6 . 3 V _ X 5R _ 08
HDMI_DHPD
Re v_ 3. 0
5 VS
C 53 1
HDMI_CHPD
T MD S 2 51
3 .3 V S
R 45
HDMI_HPD
H DM I_ D2 1 0
H D M I _ D # 2 10
Re v _3. 0
H DM I_ S CL
HDMI_SCL
HDMI_SDA
HDMI_C_SCL
HDMI_C_SDA
HDMI_D_SCL
HDMI_D_SDA
HDMI PORT
H
N10 Later
H DM I_ C_ S CL 1 0
H D M I _ C _ S D A 10
H DM I_ CHP D 1 0
63
62
54
53
L
VGA CARD TYPE
Y 3 (P )
Z 3 (N )
NC
N C
NC
N C
NC
N C
NC
N C
NC
N C
NC
16
HDMI
(P )A 1 3
(N )B 1 3
48
47
HDMI Switch B - 25
B.Schematic Diagrams
20
21
H DM I_ 0
H D M I _# 0
(P )A 1 4
(N )B 1 4
G ND
GN D
G ND
GN D
GN D
G ND
GN D
C4 9
0 . 1 u _1 6 V _ Y 5 V _ 0 4
3
9
15
22
28
43
58
C 88
0 . 1 u _ 16 V _ Y 5 V _ 0 4
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
1
2
4
5
7
8
10
11
13
14
64
C 68
TMDS Input equalization selector (control pin)
U2
6
12
19
25
40
46
55
61
Schematic Diagrams
ODD, CCD, BT, USB2.0
SATA ODD
CCD
R8
*2 8 mi l _N P _0 6
J_ OD D
C 56 5
C 56 7
0 . 0 1u _ 1 6V _ X 7R _ 04
0 . 0 1u _ 1 6V _ X 7R _ 04
S A T A _ RX N1 _ C
S A T A _ R X P 1 _C
C 56 8
C 57 2
0 . 0 1u _ 1 6V _ X 7R _ 04
0 . 0 1u _ 1 6V _ X 7R _ 04
R2 6 1
Q4
MT P 34 0 3 N 3
S
D
C 32
S A TA _ R X N 1 1 2
S A TA _ R X P 1 1 2
C 12
5 V _ C C D _1
C 7
C6
1 0 0 K _0 4
0 . 1 u_ 1 6 V _Y 5V _0 4
10 u _1 0 V _ Y 5 V _0 8
R 4
5 VS
1 0 0 K _0 4
1 .6 A
OD D _ D E T E C T # 12
R 3
0 . 1 u _1 6 V _Y 5 V _0 4
1 0 u_ 1 0 V _Y 5V _ 0 8
TO SB GPIO
* 0 _0 4
5 V _ CC D
5V
S A TA _ T XP 1 1 2
S A TA _ T XN 1 12
J_ C C D
R 6
C3 3 9
C3 4 3
C 34 6
C 34 8
C3 4 7
0 . 1 u_ 1 6 V _Y 5V _0 4
*0 . 1 u _1 6 V _ Y 5 V _0 4
1 u_ 1 0V _ 0 6
1 0 u _1 0 V _Y 5 V _0 8
1 0 u_ 1 0V _ Y 5V _ 0 8
*1 0 u_ 1 0 V _Y 5V _ 0 8
3 3 0K _ 0 4
C 1 8 59 4 -11 3 0 5-L
P I N GN D 1 ~ 2 = G N D
Q3
MT N 7 0 0 2Z H S 3
G
S
3 1 CC D_ E N
1
2
3
4
5
1 6 US B _ P N8
1 6 US B _ P P 8
33 C C D _ D E T #
D
C 33 8
8 5 20 5 -05 0 0 1
FROM H8 def HI
Sheet 25 of 55
ODD, CCD, BT,
USB2.0
USB 2.0
BLUETOOTH
5V
3. 3 V
C2 6 8
U2 1
R 23 0
2
3
1 0u _ 1 0V _ Y 5 V _ 0 8
V IN
V IN
1 0 K _0 4
5
4
R2 3 6
16 U S B _O C 0 1 #
V O UT
V O UT
V O UT
F L G#
E N#
*0 _0 4
GN D
6
7
8
C3 1 7
C3 1 9
1
0 . 1u _ 1 6V _ Y 5 V _ 0 4
10 u _ 10 V _ Y 5 V _ 08
V C C U S B _ 01
3 . 3V _ B T
3 .3 V
R T 9 7 15 B GS
50m il
R2 4 5
50 mi l
0_ 0 6
U 24
C3 2 2
4
5
V IN
V IN
1 0u _ 10 V _ Y 5 V _ 08
BT_ EN
3
EN
V O UT
G ND
1
2
*G5 2 4 3A
5V
3 . 3V
C 1 68
U8
R 10 0
10 u _1 0 V _ Y 5 V _ 08
2
3
1 0 K _0 4
5
4
R 5 02
1 6 U S B _ OC 23 #
* 0_ 0 4
V IN
V IN
V OU T
V OU T
V OU T
FLG #
EN #
G ND
6
7
8
C 1 56
C 15 2
1
0. 1 u _1 6 V _ Y 5 V _0 4
1 0 u_ 1 0 V _Y 5V _ 0 8
V C CUS B _ 2 3
C 3 18
C 3 11
C 3 07
10 u _ 10 V _ Y 5 V _ 08
* 0 . 1u _ 16 V _ Y 5 V _ 04
0. 1 u _1 6 V _ Y 5 V _ 04
J _B T
C188? ? ? ? ? ? ? :
R T 97 1 5 B GS
220u_6.3V_6.3*6_B
PN:APL 3510B- -6-02- 03510-92 0
6-09-22712-390
PN:RT 9715B- -6- 02-09715- 920
1 6 U S B _ P N1 2
16 U S B _P P 1 2
33 B T _ D E T #
1 3 P C H _ B T _E N #
3 . 3V
CE 220UF M (6.3V) SMD
6SVPC220MV 6.6*6.6*5.9 OS-CON
6 - 1 1- 1 07 1 1 -8 B 1
15M OHM ? ?
C 1 61
L 19
H C B 1 6 0 8K F -1 2 1T 2 5
PO RT 0
1 6 US B _ P N2
1 6 US B _ P P 2
L P3
1
4
1 6 US B _ P P 3
1
3
4
60 mil
V CC US B 0 _ C
L P2
1
4
2
L 18
*H C B 16 0 8 K F -12 1 T 25
*W C M2 0 12 F 2 S -1 61 T 03 -S H OR T
1 6 US B _ P N3
J_ U S B
0 . 1 u_ 1 6V _Y 5V _ 0 4
60 mil
V CC US B 0 _ C
3
PO RT 1
V C C U S B _2 3
5
2
6
3
7
*W C M2 0 12 F 2 S -1 61 T 03 -S H OR T
31 B T _E N
FROM H8 def HI
C 16 2
1 0 0 u_ 6 . 3V _ B _ A
V C C U S B _2 3
2
C 1 67
C 16 6
1 0 u _1 0 V _Y 5 V _0 8
0 . 1 u_ 1 6V _Y 5V _ 0 4
8
V C C0
GN D
9
D A T A 0D A T A 0+
GN D
10
G ND 0
V C C1
GN D
11
D A T A 1D A T A 1+
12
GN D
G ND 1
C 1 07 B 4 -1 08 0 3- L
1 1 , 1 9, 3 6 . . 3 9 5 V
10 , 1 1 , 19 . . 2 1, 23 , 2 4, 2 6 , 2 7, 3 2 . . 35 5 V S
2, 3 , 1 2. . 14 , 1 6, 1 7 , 1 9, 2 2 , 28 , 2 9 , 35 . . 3 9 3. 3 V
3 2 V CC US B _ 0 1
B - 26 ODD, CCD, BT, USB2.0
R 2 29
*0 _ 0 4
R 2 46
1 0 0K _ 0 4
D
footprint: SCAR250
BT_ EN
J_BT1
1
6
2
3
4
5
1
6
8 7 2 13 -0 60 0 G
Q2 2
MT N 70 0 2Z H S 3
G
S
Ma in :
6 -0 2-7 53 48- 92 0
Se co nd: 6 -0 2-0 19 22- 92 0
+
B.Schematic Diagrams
P1
P2
P3
P4
P5
P6
S A T A _ TX P 1 _ C
S A T A _ TX N 1 _ C
G
S1
S2
S3
S4
S5
S6
S7
Schematic Diagrams
Codec, Subwoofer, DMIC
Vo =V ref *( R2 +R1 )/ R2
Vr ef =1. 21 5V
L32
3 .3 VS
R 40
0 _ 04
3 .3 V S
3 .3 V S _ DM IC
3 . 3V S _ A U D
L 33
DIGITAL
MIC
R4 1
C8 2
*1 5 . 8 K _ 1% _ 0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
H C B 10 0 5 K F -1 21 T 2 0
40mil
C 33 1
C 3 35
C3 3 7
C 30 4
C3 1 3
C3 1 0
* 0 . 1u _ 1 6V _ Y 5V _ 0 4
1 0 u_ 1 0 V _Y 5 V _0 8
0 . 1 u _1 6 V _ Y 5 V _ 04
0. 1 u _ 16 V _ Y 5 V _ 0 4
0 . 1 u_ 1 6 V _Y 5 V _0 4
*0 . 1 u _1 6 V _ Y 5 V _ 04
10 u _ 10 V _ Y 5 V _ 0 8
R3
R1
R 5 24
R2 5 7
* 8. 2 K _ 1 %_ 0 4
R5 2 5
0_04
0_04
D MI C _C LK
D MI C _D A T A
C 58 9
2
3
*C _0 4
C3 3 6
* 22 p _5 0 V _ N P O _0 4
25
38
1
9
4
7
A U DG
R2
C3 2 8
2. 2 u _ 16 V _ X 5R _ 06
A V DD1
A V D D2
R 51 5
R 51 6
*C _0 4
D V DD1
DV D D2
C 58 8
D VSS1
DVS S2
J _ DM IC
V OU T
4
A D J( N C ) GN D
GP I O0 / D M I C -C LK
GP I O1 / D M I C -D A TA
2 2 _0 4
Max: 0.5inch
47
3 3 EAPD
1 0 , 32 S P D I F _ OU T
VR EF
C 34 0
1 u _ 10 V _ 0 6
B EEP
R2 6 4
1 u _ 10 V _ 0 6
4 7K _ 0 4
R2 6 5
C3 3 3
C3 3 2
1 u _1 0 V _ 06
12
S ENS E_ A
S ENS E_ B
13
34
37
29
16
17
18
19
20
32 M I C 1 -L
3 2 MI C 1-R
R2 5 3
R2 5 4
DIGITAL
port A
S U R R -O U T -L
S U R R -OU T-R
S P D IF I/E AP D
MI C 2 -V R E F O
LI N E 2 -V R E F O
S P D IF O
port D
P CB E EP
4 . 7K _0 4
* 1 00 p _ 50 V _ N P O _ 04
A U DG
M I C 1 -L
M I C 1 -R
M I C 1 -V R E F O-L
MI C 1 -V R E F O-R
1 K_ 0 4
1 K_ 0 4
C 32 4
C 32 0
4. 7 u _ 6. 3 V _ Y 5 V _ 0 6
4. 7 u _ 6. 3 V _ Y 5 V _ 0 6
21
22
F R ON T-O U T -L
F R O N T -OU T-R
port ELLI INNEE 22-R-L
S e n se A
S e n se B
P I N 37 -V R E F O
L I N E 1 -V R E F O
MI C 2 -L
MI C 2 -R
port G
ANALOG
C E N TE R
LFE
port HSS II DD EE-R-L
port F
N.C .
C D -L
C D -GN D
C D -R
J DR E F
port CLLI INNEE 11-R-L
A VSS1
AVSS2
C 34 4
48
S D A TA -O U T
B I T -C L K
S D A TA -I N
SYN C
R E S E T#
port B
MI C 1 -L
MI C 1 -R
A L C 8 8 8 -V C 2 -GR
R 5 27
R 5 26
0_ 0 4
* 0 _0 4
A UDG
V o=0 .8 *( 1+R 3/ R4 )
28
32
MI C 1-V R E F O-L
MI C 1-V R E F O-R
39
41
H P _ OU T_ L
H P _ OU T_ R
30
31
MI C 2-V R E F
AUD G
R 24 7
R 25 1
A UD G
? ? APL5 317 -1 2BI -TRG
A UDG
*2 0m i l _P _ 0 4
*2 0m i l _P _ 0 4
35
36
R 3=8 .2 K, R4 =1 .6 K,
V o=4 .9 0V
H P -L 3 2
H P -R 32
R2 57 ,
R2 63
NO TE :
F R ON T_ L 2 7
F R ON T_ R 27
14
15
45
46
5 VS
1 u _1 0 V _ 0 6
1 K _1 % _ 04
27
43
44
R 2 56
1 0 K _ 04
3
C 33 0
R2 6 3
V R E F _ C OD E C C 3 0 2
1 0 u _1 0 V _ Y 5 V _ 08
1
2
A ME 8 8 0 4
( AP L 53 1 7 )
R4
AM E8 80 4
A U DG
Re v_ 3. 0
R 52 4,
R 52 5
V
P AC KA GE
X
VIN 1
GND 2
EN 3
6 VOUT
5 ADJ
4 PG
V
VIN 1
GND 2
SHDN# 3
5 VOUT
4 SET
A U D I O_ C E N 2 7
L E F _ OU T
S I D E -L
S I D E -R
AP L5 31 7
S IDE - L 2 7
S IDE - R 2 7
X
33
R 24 8
40
C3 1 4
C3 1 2
23
24
2 0 K _1 % _ 04
R 2 58
R 2 59
7 5 _1 % _ 04
7 5 _1 % _ 04
L I N E -I N _ L 32
L I N E -I N _ R 3 2
G ND
HP -L
HP -R
A U DG
Sheet 26 of 55
Codec, Subwoofer,
DMIC
A UD G
4 . 7 u_ 6 . 3 V _ Y 5 V _ 06
4 . 7 u_ 6 . 3 V _ Y 5 V _ 06
26
42
Re v _3. 0
R 26 2
5
6
8
10
11
EN
3* R/ L? ?
La yout note :
He a dphone ? ? ? ? > 1 0mi ls
? ? phone ja ck ? ?
? ?? ?? ??
R/ L? ? ? ? GND? ? ? ? 3 *? ?
G ND
SUBWOOFER
La yo ut N ot e:
Ve ry c los e to CO DE C
2W
? ? ? ?
MI C 1-V R E F O-L
MI C 1-V R E F O-R
R 24 4
R 24 3
2 . 2 K _ 04
4ohm
REAR R/L
The cut-off frequency Fcut
Fcut = 1 / (2 * Pi * (CA)
* (RA))
Fcut(-3db)=485.4Hz
485.4 Hz Low Pass Filter
C3 0 8
8 2 00 p _ 50 V _ X 7R _ 06
Z 2 22 0
C3 0 9
6 8 0p _ 5 0V _ X 7 R _ 0 4
6 8 0p _ 5 0V _ X 7 R _ 0 4
L E F _ OU T
L1
F C M 10 0 5 K F -1 21 T 03
L2
F C M 10 0 5 K F -1 21 T 03
L3
F C M 10 0 5 K F -1 21 T 03
L4
F C M 10 0 5 K F -1 21 T 03
5 VS
C3 2 7
0 . 2 2u _ 1 0V _ Y 5V _ 0 4
R2 5 0
2 0 K _0 4
R 2 52
1 0 K _ 1% _ 0 4
R 2 55
2 0 K _ 1% _ 0 4
R 2 60
3 9 . 2 K _1 % _ 04
2 0 K _0 4
4
3
1 u _1 0 V _ 06
2
S E N S E _A
0. 2 2 u _1 0 V _ Y 5 V _ 04
A U DG
C3 1 5
Re v _3. 0
2 7 SPK_ EN
1
ININ+
BYPASS
SD#
T P A 6 21 1 A 1 D G N R
T HE R NA L _ P A D
C3 2 6
V O+
VO -
S U B W OO F E R + _ C
5
L30
H C B 1 0 05 K F -1 2 1T 2 0
J _S I D E S U B
5 V S _ S UB W
V DD
GN D
27 S I D E _ R O +
2 7 S I D E _R O-
S U B W OO F E R -_ C
8
6
7
9
A UD G
R2 4 9
32 H P _S E N S E
8 5 2 04 -0 2 00 1
8 2 00 p _ 50 V _ X 7R _ 06
U2 5
3 2 MI C _S E N S E
J _ S IDE L
F C M 10 0 5 K F -1 21 T 03
C 29 7
A UD G
3 2 L I N E _S E N S E
F C M 10 0 5 K F -1 21 T 03
L 12
1
2
MI C 1-R
C 29 8
L 13
2 7 S I D E _L O +
2 7 S I D E _ L O-
2 . 2 K _0 4
MI C 1-L
C3 2 3
C 31 6
S U B W OO F E R +
S U B W OO F E R -
0 . 1u _ 1 6V _ Y 5V _ 0 4
1 0 u_ 1 0 V _Y 5 V _0 8
1
2
3
4
8 52 0 5 -04 0 0 1
A U DG
A UD G
SUBWOOFER
L ay ou t No te :
U 43 p in 1 ~ pin 1 1 and p in 47 a nd pi n 48
a re D igi ta l sig na ls .
Re v_ 3. 0
T he o the rs a re An al og si gn als .
*2 0 m li _ P _ 04
R5 2 8
*2 0 m li _ P _ 04
L34
H C B 16 0 8 K F -1 21 T 25
L ay ou t No te :
( 1) MI C1- L ( U13 .2 1)
( 3) LI NE- L (U 13. 23 )
R5 2 9
( 2) MI C1- R
(U 13 .2 2)
( 4) LI NE- R (U 13. 24 )
? ? ? ? ? ?
A UDG , ? ? ? ?
+ 5V S & + VI N pla ne .
? ? ?
A U DG
S U B W O OF E R +_ C
R2 4 1
* 20 m i _l P _ 0 4
S U B W OO F E R +
S U B W O OF E R -_C
R2 4 2
* 20 m i _l P _ 0 4
S U B W OO F E R 3. 3 V S 3 , 8 . . 1 2, 1 4 , 1 6. . 24 , 2 7 . . 35
5V S 10 , 1 1 , 19 . . 2 1 , 23 . . 2 5 , 2 7, 3 2 . . 3 5
La yout not e:
G ND a nd AUD G spa ce is
6 0mi ls ~ 10 0mi ls
Codec, Subwoofer, DMIC B - 27
B.Schematic Diagrams
1 2 HD A _ S DO UT
1 2 H D A _B I T C LK
1 2 H DA _ S D IN0
1 2 HD A _ SY N C
12 , 2 7 H D A _R S T #
V IN
P G( S E T )
5
*1 . 6 K _ 1% _ 0 4
8 5 2 04 -0 4 00 1
1 2 HD A _ SP K R
6
3 K _1 % _ 04
U 26
3 1 K B C_ B E E P
U2 7
Re v_ 3. 0
C 3 34
3 . 3V S _D MI C
1
2
3
4
* H C B 1 0 0 5K F -12 1 T 20
5 VS_ AU D
40mil
Schematic Diagrams
Audio AMP
FRONT R/L
2W
4ohm
5 VS
R ev _3 .0
? ? ? ? ?
R E A R _L
L5 1
H C B 10 0 5 K F -1 21 T 2 0
5V S _ A M P
R E A R _R
C 56 3
C 5 64
C5 6 6
0 . 1 u_ 1 6 V _ Y 5 V _0 4
1 u _ 10 V _ 0 6
10 u _ 10 V _ Y 5 V _ 0 8
U 42
AUD G
2 6 F R O N T _R
AUD G
R 4 76
R 4 78
7. 5 K _ 1 % _0 4
7. 5 K _ 1 % _0 4
C 5 62
C 5 71
0 . 47 u _1 6 V _ Y 5 V _ 06
0 . 47 u _1 6 V _ Y 5 V _ 06
5
9
R 4 74
R 4 80
7. 5 K _ 1 % _0 4
7. 5 K _ 1 % _0 4
C 5 61
C 5 69
0 . 47 u _1 6 V _ Y 5 V _ 06
0 . 47 u _1 6 V _ Y 5 V _ 06
17
7
Re v_ 3. 0
R 4 67
R 4 68
5 VS
1 0 0K _0 4
* 10 0 K _ 04
R 4 69
R 4 73
SD #
2
3
* 10 0 K _ 04
1 0 0K _0 4
P VDD
P VDD
V DD
R INR IN+
19
SPK_ EN
GA I N 0
GA I N 1
A UD G
G A IN0
G A IN1
LO U T +
L O UT RO UT +
RO UT G ND
G ND
G ND
BYP ASS
G ND
E X P OS E D P A D
NC
1
11
13
20
21
6
15
16
4
S P K O U T L +_ C
Sheet 27 of 55
Audio AMP
S P K O U T L -_C
18
S P K O UT R+ _ C
14
S P K O U T R -_ C
R 47 5
*2 0m i l _P _ 0 4
S P K OU TL +
S P K O U T L -_C
R 47 9
*2 0m i l _P _ 0 4
S P K OU TL -
S P K O UT R+ _ C
R 47 2
*2 0m i l _P _ 0 4
S P K OU TR +
S P K O U T R -_ C
R 47 7
*2 0m i l _P _ 0 4
S P K OU TR -
L 38
F C M1 0 0 5K F - 12 1 T0 3
10
12
AU DG
S P K O U T L +_ C
A UDG
8
T P A 6 0 17 A 2 P W P R
S P K OU T L+
S P K OU T L-
C 57 0
C 5 94
1 0 u _1 0 V _ Y 5 V _ 08
* 0 . 47 u _ 10 V _ Y 5 V _ 0 4
Re v _3. 0A U D G
AU DG
S P K OU T L+ _ R
S P K OU T L-_ R
L 39
F C M1 0 0 5K F - 12 1 T0 3
C 3 87
C 38 6
*1 80 p _ 50 V _ N P O _ 04
* 18 0 p _5 0 V _ N P O _0 4
J _F R C E N S P K
1
2
3
4
5
6
14
3 .3 V S
U 2 3C
74 L V C 0 8 P W
L 40
C E N TE R _ S P K +
C E N TE R _ S P K -
F C M 10 0 5 K F -1 21 T 0 3
L 41
F C M 10 0 5 K F -1 21 T 0 3
8 5 2 04 -0 6 00 1
9
1 7 S B _ MU TE #
8
10
3 . 3V S
R2 2 5
12
3
2
3 .3 VS
R 2 35
14
3 1 KB C_ M UT E#
1 2, 2 6 H D A _ R S T #
10 0 K _ 04
1 0 M_ 0 4
U2 3 B
7 4L V C 08 P W
11
5
7
4ohm
CENTER
C 3 85
C 38 4
*1 80 p _ 50 V _ N P O _ 04
* 18 0 p _5 0 V _ N P O _0 4
Fcut(-3db)=1809.4Hz
2000Hz Low Pass Filter
L5 0
H C B 10 0 5 K F -12 1 T 20
5 V S _ RE A R
*1 8 00 p _5 0 V _ X7 R _0 6
*1 8 00 p _5 0 V _ X7 R _0 6
4ohm
1.5W
? ? ? ?
5V S
R ev _3 .0
C 5 97
C 5 98
S P K OU T R + _ R
S P K OU T R -_ R
L 37
F C M1 0 0 5K F - 12 1 T0 3
Q2 1
MT N 70 0 2 Z H S 3
Fcut(-3db)=1965Hz
2000Hz High Pass Filter
R E A R_ R
R E A R_ L
26
G
S
H P_ EN
1.5W
SPK_ EN
7
6
? ? ? ?
SPK_ EN
13
4
32 H P _P L U G
REAR R/L
L 36
F C M1 0 0 5K F - 12 1 T0 3
S P K OU T R +
S P K OU T R -
U 23 D
7 4 LV C 0 8P W
14
7
3 .3 V S
U2 3 A
7 4L V C 08 P W
D
14
3 .3 VS
1
7
C5 4 9
C5 4 8
C5 6 0
0. 1 u _ 16 V _ Y 5 V _ 0 4
1 u_ 1 0 V _0 6
10 u _ 10 V _ Y 5 V _ 0 8
Fcut(-3db)=1012.3Hz
1000Hz High Pass Filter
C 28 0
22 0 0p _ 5 0V _ X 7 R _ 0 6
C 29 4
22 0 0p _ 5 0V _ X 7 R _ 0 6
5V S
U 41
2 6 S I D E -R
A U DG
R 52 0
R 52 1
0_04
0_04
C5 5 9
C5 5 7
1 8 00 p _ 50 V _ X 7R _ 06
1 8 00 p _ 50 V _ X 7R _ 06
Z 2 3 12
R 52 2
R 52 3
0_04
0_04
C5 5 0
C5 5 8
1 8 00 p _ 50 V _ X 7R _ 06
1 8 00 p _ 50 V _ X 7R _ 06
Z 2 3 13
5
9
17
7
SPK_ EN 1 9
AUDG
5V S
AUDG
R 4 65
R 4 71
* 10 0 K _ 04
1 0 0K _ 0 4
R 4 70
R 4 64
* 10 0 K _ 04
1 0 0K _ 0 4
GA I N 0
GA I N 1
2
3
1
11
13
20
21
L INL IN+
RIN RIN +
SD#
GA I N 0
GA I N 1
P VDD
P VDD
VDD
LO U T +
6
15
16
4
S I D E _ LO + _C
8
S I D E _ LO -_ C
C2 9 5
0 . 0 2 2u _ 50 V _ Y 5 V _ 0 6
R2 2 4
8. 2 K _ 0 4
R2 3 8
8. 2 K _ 0 4
0 . 0 2 2u _ 50 V _ Y 5 V _ 0 6
18
S I D E _ R O +_ C
A U DG
A U DG
C2 8 9
1 u _1 0 V _ 06
R OU T GN D
GN D
GN D
BYPAS S
GN D
E X P OS E D P A D
NC
14
*2 0 m li _ P _ 04
R4 6 6
*2 0 m li _ P _ 04
S I D E _R O+ _ C
R4 5 8
*2 0 m li _ P _ 04
S I D E _R O-_ C
R4 5 7
*2 0 m li _ P _ 04
S D#
V O+
V OVD D
GN D
5
C E N T E R _S P K +_ C
8
C E N T E R _S P K -_C
6
C2 9 3
C 28 7
0. 1 u _ 16 V _ Y 5 V _ 0 4
1 0 u _1 0 V _ Y 5 V _ 08
S I D E _ R O -_C
A U DG
12
C5 5 6
0. 4 7 u _1 6 V _ Y 5 V _ 06
S I D E _ L O+ 2 6
S I D E _ L O-
26
S I D E _ R O+ 2 6
S I D E _ R O- 2 6
C E N T E R _S P K + _ C
R2 2 3
* 20 m i _l P _ 0 4
C E N TE R _ S P K +
C E N T E R _S P K - _C
R2 3 7
* 20 m i _l P _ 0 4
C E N TE R _ S P K -
L28
H C B 1 0 05 K F -1 2 1 T2 0
5 VS_ C EN
7
Z 2 31 7
Re v_ 3. 0
R4 6 3
1
BYPA SS
T P A 6 2 11 A 1 D G N R
A U DG
S I D E _L O -_C
SPK_ EN
ININ+
A U DG
10
T P A 6 0 17 A 2 P W P R
S I D E _L O +_ C
U 22
4
3
2
Re v_3 .0
L OU T RO UT +
A UDG
B - 28 Audio AMP
C2 8 1
2 6 A UDIO _ CE N
T H E R N A L_ P A D
A U DG
9
26 S I D E -L
Thermal Pad
B.Schematic Diagrams
A UD G
L INL IN+
Thermal Pad
2 6 F R ON T_ L
3 . 3 V S 3 , 8. . 1 2 , 1 4, 1 6 . . 2 4, 26 , 2 8. . 35
5 V S 1 0 , 11 , 1 9 . . 21 , 2 3 . . 26 , 3 2 . . 35
Schematic Diagrams
New Card, Mini Card
NEW CARD
3 .3 V
3. 3 V
5
C3 5 8
B U F _ P L T _R S T #
*0 . 1 u _1 6 V _ Y 5 V _ 04
U2 9
7 4A H C 1 G 08 G W
1
4
N C _ R S T#
3 . 3V S
3. 3V
3 . 3V _ N E W
A UX IN
2
12
J _N E W
3. 3 V O U T
1. 5 V I N
1. 5 V O U T
3 . 3V S _ N E W
3
R 50 3
1 6 US B _ O C5 #
6
20
1
*1 0 K _0 4
*0 _ 0 4
S Y S R S T#
S HD N#
S TB Y #
19
P E RS T #
C PPE#
CP US B #
OC #
R C LK E N
1 0 K _ 04
4
5
13
14
8
18
C 3 72
C3 6 9
0 . 1 u _1 6 V _ Y 5 V _ 04
C3 6 1
0. 1 u _ 16 V _ Y 5 V _ 0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
16
N C_ CP P E #
N C_ CP U S B #
P C IE _ W A K E #
14 , 2 9 P C I E _ W A K E #
1 3 NE W C A RD _ CL K RE Q #
3. 3 V S
1 3 C L K _P C I E _ N E W _ C A R D
1 3 C L K _P C I E _ N E W _ C A R D #
R 27 3
* 1 0K _ 0 4
CP P E #
CP US B #
W AKE#
CL K RE Q #
1 0K _0 4
19
18
R E F C LK +
R E F C LK RE S E RV E D
P E Rp 0 RE S E RV E D
P E Rn 0
P E Tp 0
G ND
P E Tn 0
G ND
G ND
G ND
US B _ D+
G ND
US B _ DG ND
G ND
S MB _ D A T A
G ND
S MB _ C L K
22
21
25
24
3
2
1 6 U S B _P P 5
1 6 U S B _P N 5
3 .3 V
8
7
1 3 S ML 0_ D A TA
1 3 S ML 0 _C LK
3. 3 V
+1 . 5 V
+1 . 5 V
17
4
11
16
1 3 P C I E _ R X P 2 _N E W _ C A R D
1 3 P C IE _ RX N2 _ NE W _ C A RD
1 3 P C I E _T X P 2 _N E W _ C A R D
1 3 P C I E _T X N 2 _ N E W _ C A R D
R 3 03
ENE P2 231 NF_E2 pin 1,8 ,9,1 0,2 0
has int erna lly pu lled hig h
(11 0~ 33 0K Ohm)
3 . 3V S
+3 . 3 V
+3 . 3 V
9
10
10
9
P 2 23 1 N L E 2
1 .5 V S
+3 . 3 V A U X
14
15
48 mil
GN D
NC
P E RS T #
12
1 .5 V S _ NE W
11
7
NC
NC
NC
NC
13
5
6
Sheet 28 of 55
New Card,
Mini Card
1
20
23
26
27
28
29
30
S A N T A -1 3 08 2 0 -1
P I N G N D 1~ 4 = GN D
C 3 64
C3 7 4
0 . 1 u _1 6 V _ Y 5 V _ 04
C3 7 9
0 . 1 u_ 1 6 V _Y 5 V _0 4
54 ? ? : 6 -21-G 3A50-126-S
34 ? ? : 6 -21-G 3A50-126-S1
0 . 1u _ 1 6V _ Y 5V _ 0 4
MINI-PCIE CARD (WLAN + 80 PORT)
MINI-PCIE CARD For TV
J _ MI N I _W LA N
P CIE _ W A K E #
R9 1
3 .3 V S
1 3 W L A N _ C LK R E Q#
10 K _ 0 4
1 3 C L K _ P C I E _W L A N #
13 C LK _P C I E _ W LA N
1
3
5
7
9
11
13
15
W AKE#
B T _ DA T A
B T _ CHC L K
C L K R E Q#
GN D 0
RE F CL K RE F CL K +
GN D 1
J _ MI N I _T V
3 . 3 V _0
G ND5
1 . 5 V _0
U I M _P W R
U I M_ D A T A
U I M_ C L K
U I M_ R E S E T
U I M_ V P P
2
4
6
8
10
12
14
16
3 . 3V
1 . 5V S
R 4 24
3. 3 V
* 1 0K _ 0 4
17 C LK _P C I E _ TV #
1 7 CL K _ P CIE _ T V
1
3
5
7
9
11
13
15
W AKE#
B T _D A T A
B T _C H C LK
C L K R E Q#
GN D 0
REF C L KREF C L K+
GN D 1
KEY
31 8 0 P OR T_ D E T#
3 1 3 IN 1
1 3 P C I E _R XN 1 _W L A N
1 3 P C I E _R XP 1_ W L A N
13 P C I E _ TX N 1 _ W L A N
13 P C I E _ TX P 1 _ W LA N
3 3 W L A N _ D E T#
3 .3 V
1 3 C L _C LK 1
1 3 C L _D A TA 1
1 3 C L _R S T# 1
V D D3
R
R
R
R
90
89
88
87
*
*
*
*
10 m
10 m
10 m
10 m
i l_ 0 4
i l_ 0 4
i l_ 0 4
i l_ 0 4
M
M
M
N
INI_ CL K 1
INI_ DA T A 1
INI_ RS T # 1
MI N I _0 1
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NC 3
NC 4
GN D 2
PET n 0
PET p 0
GN D 3
GN D 4
P E R n0
P E R p0
GN D 1 1
NC 6
NC 7
NC 8
NC 9
NC 1 0
NC 1 1
NC 1 2
NC 1 3
3 . 3V _0
GN D 5
1 . 5V _0
U I M _P W R
U I M_ D A T A
U I M_ C L K
UIM _ RE S E T
U I M_ V P P
2
4
6
8
10
12
14
16
3. 3V S
1. 5V S
KEY
G ND6
W _ D I S A B LE #
P E R S E T#
3 .3 V A UX
G ND7
1 . 5 V _1
N C ( S MB _ C L K )
N C (S MB _ D A T A )
G ND8
N C (U S B _ D -)
N C (U S B _ D + )
G ND9
N C (LE D _ W W A N # )
L E D_ W L A N#
N C (LE D _ W P A N # )
1 . 5 V _2
G N D 10
3 . 3 V _1
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
B U F _ P L T_ R S T#
W L AN_ EN
31
3 . 3V
1 3 P C I E _ R X N 7_ T V
13 P C I E _ R X P 7 _T V
13 P C I E _ TX N 7_ T V
1 3 P C I E _T X P 7 _T V
U S B_ PN7 1 6
U S B _ P P 7 16
8 0 CL K 3 1
1 . 5V S
3 . 3V
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NC 3
NC 4
GN D 2
PETn 0
PETp 0
GN D 3
GN D 4
P E Rn 0
P E Rp 0
GN D 1 1
NC 6
NC 7
NC 8
NC 9
N C 10
N C 11
N C 12
N C 13
GN D 6
W _ DIS A B L E #
P E R S E T#
3 .3 VAUX
GN D 7
1 . 5V _1
N C (S M B _ C L K )
N C (S M B _ D A T A )
GN D 8
N C (U S B _ D -)
N C (U S B _ D + )
GN D 9
N C (L E D _W W A N # )
L E D_ W L A N#
N C ( LE D _ W P A N # )
1 . 5V _2
G N D 10
3 . 3V _1
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
B U F _ P LT _ R S T #
3 .3 VS
1. 5V S
U S B _ P N6 1 6
U SB_ PP6 1 6
1. 5 V S
3. 3 V S
3 . 3V S
For WLAN Device
B E L L W E T H E R 8 00 0 3 -10 2 1
C5 5 1
C 19 8
C 1 95
B E L L W E T H E R 80 0 0 3-1 0 2 1
H = 4mm
0 . 1u _ 1 6V _ Y 5V _ 0 4
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 0 u _1 0 V _ Y 5 V _ 08
H = 4mm
3 .3 V
1 .5 V S
C1 4 2
C1 4 1
C 4 81
C 48 4
C 4 80
C 48 3
C4 8 2
1 u _6 . 3 V _ X5 R _0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
0. 1 u _ 16 V _ Y 5 V _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 04
1 u _ 6. 3 V _ X 5R _ 04
0 . 1 u_ 1 6 V _Y 5 V _0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
1 2 , 3 1. . 3 4 , 3 9, 4 0 V D D 3
1 8 , 2 0, 3 8 1 . 5 V S
2 , 3 , 1 2. . 1 4 , 1 6, 1 7 , 1 9, 2 2 , 2 5, 2 9 , 3 5. . 3 9 3 . 3 V
3 , 8 . . 1 2, 1 4 , 1 6. . 2 4 , 2 6, 2 7 , 2 9. . 3 5 3 . 3 V S
New Card, Mini Card B - 29
B.Schematic Diagrams
R3 0 5
3 .3 V
1 4 , 2 0, 3 1 , 3 4, 3 6 S U S B #
R 3 04
3. 3 V I N
* 10 0 K _ 04
36 mil
48 mil
15
B U F _P L T _ R S T #
3 , 1 6 , 20 , 2 9 . . 3 1 B U F _ P L T_ R S T#
3 .3 V
A U XO U T
R 29 3
*1 0 0K _0 4
N C _ P E R S T#
U3 0
17
R2 9 2
3
1 . 5V S
2
Schematic Diagrams
LAN-RTL8111DL, RJ45
RTL8111DL
L21
3 . 3V
100MHz/100
S W F 2 52 0 C F -4 R 7 M-M
>60mils
40 m il
C 1 76
C 18 0
C 1 97
C1 8 2
0 . 1 u _ 16 V _ Y 5V _0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
0 . 1 u _ 16 V _ Y 5V _ 0 4
0. 1 u _ 1 6V _ Y 5 V _0 4
? ? ? INDUCTOR
(600mA)
1A
E VDD 1 2
40 mi l
R1 3 1
3 . 6 K _ 1% _ 0 4
C1 7 1
C1 8 9
22 u _ 6 . 3V _X 5 R _ 0 8
0 . 1 u _ 16 V _ Y 5V _ 0 4
C 2 24
C 22 5
1 u _ 1 6V _ X 5 R _ 0 6
1 u _ 16 V _ X 5 R _ 0 6
FOR RTL PIN19
must be within
200mil (to pin 48)
FOR RTL PIN1,29,37,40
D V D D1 2
must be within 200mil
60 mi l
C 1 93
C1 9 0
C1 9 9
C2 1 2
C 17 7
0 . 1 u _ 16 V _ Y 5V _0 4
0. 1 u _ 1 6V _Y 5 V _ 04
0 . 1u _ 1 6 V _ Y 5 V _ 0 4
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
FOR RTL PIN10,13,30,36,39
LA N _ V D D 3
D 38
A
A S D 7 5 1V
C
S B _ I S O LA TE B # 17
Support D3 E
D V DD 1 2
L A N_ V D D3
D V D D1 2
X T A L1
R S TB
R 16 7
1K _ 0 4
R 16 6
15 K _ 0 4
R 17 1
*1 0 mi l _ 04
3 .3 V S
B U F _ P L T_ R S T # 3 , 1 6 , 2 0 , 28 , 3 0 , 3 1
P C IE _ W A KE # 1 4 ,2 8
X2
2
1
L A N_ C L K RE Q # 1 3
X T A L2
C 17 5
C 17 4
2 2 p _5 0 V _ N P O_ 0 4
2 2 p_ 5 0 V _ N P O _ 04
L A N _V D D 3
DV D D1 2
L A N _V D D 3
L AN_ VD D3
>40MILS
3 .3 V
36
35
34
33
32
31
30
29
28
27
26
25
X 8 A 0 25 0 0 0 F G1 H _2 5 MH z
L A N _V D D 3
R 17 4
D V D D 12 _ 3
LE D 1 / E E S K
L E D 2/ E E D I
L E D3 /E E D O
E E CS
GN D _ 3
D V D D 1 2 _2
VD D3 3 _ 1
I S OL A T E B
PER ST B
L A NW A K E B
C L K RE Q B
Sheet 29 of 55
LAN-RTL8111DL,
RJ45
M A2 /EESK
MA 1/ EEDI
M A0 /EED O
EEC S
I S OL A T E B
R 1 19
0 _0 4
R 1 22
2 . 49 K _ 1 % _ 04
XT AL 1
XT AL 2
E NS W RE G
R SET
37
38
39
40
41
42
43
44
45
46
47
48
V D D 3 3_ 2
L ED0
A V D D 1 2 _2
A V D D 3 3 _2
CKT A L 1
CKT A L 2
E NS W RE G
V D D S R _1
V D D S R _2
RSE T
GN D _ 4
S RO UT 1 2
PCI-E LAN
4. 7 K _ 0 4
R5 0 4
N C/S M DA T A
N C/S M CL K
E GN D
HSO N
H S OP
E V DD 1 2
RE F CL K _ N
R E F C LK _ P
H S IN
HS IP
G ND _ 2
DVD D1 2 _ 1
RTL8111DL-GR
24
23
22
21
20
19
18
17
16
15
14
13
0 _ 04
L A N _ DS M # 3 1
Support D3 E
PCIE _R XN2 _ GL AN _C
PCIE _R XP2 _G L AN_ C
C 2 16
C 2 15
0 . 1 u _1 0 V _ X 7R _ 0 4
0 . 1 u _1 0 V _ X 7R _ 0 4
LAN_D SM #
DO S
W IN
? ? ??
H
H
H
?? ? ??
H
L
H
P C I E _ R X N 4 _ GL A N 13
P C I E _ R X P 4 _ GL A N 1 3
0 . 1 u _1 6 V _ Y 5 V _ 0 4
60 m il
MX 1 +
AV D D3 3 _ 1
MD I P 0
M D IN0
FB1 2
M D IP 1
M DIN 1
G ND _ 1
M DIP 2
MD I N 2
AV D D1 2 _ 1
M DIP 3
M D IN3
C 18 6
2 2 u _ 6. 3 V _ X 5 R _ 0 8
1
2
3
4
5
6
7
8
9
10
11
12
C 1 72
MX 1 -
U1 3
MX 2 +
MD I O2 +
M D I O2 -
M D I O3 +
M DIO 3 D VDD 1 2
M DIO 1 +
M D I O1 DVD D1 2
M DIO 0 +
MD I O 0-
L 45
* W C M 2 01 2 F 2 S -1 6 1T 0 3
4
3
MX 2 -
MX 3 +
1
2
L 43
* W C M 2 01 2 F 2 S -1 6 1T 0 3
4
3
1
2
L 44
* W C M 2 01 2 F 2 S -1 6 1T 0 3
4
3
L MX 1 -
L M X1 +
L M X1 L M X2 +
L M X2 -
1
2
3
6
L M X3 +
L M X3 L M X4 +
L M X4 -
4
5
7
8
DA
DA
DB
DB
+
+
-
DC
DC
DD
DD
+
+
-
s hi e l d
s hi e l d
GN D 1
GN D 2
L MX 2 +
L MX 2 -
C 10 0 Y 8 -1 0 8 05 -L
L MX 3 +
L 23
MX 3 MD
MD
MD
MD
IO
IO
IO
IO
0+
01+
1-
MD I O 2+
MD I O 2MD I O 3+
MD I O 3Z 2 1 01
Z 2 1 02
Z 2 1 03
Z 2 1 04
12
11
9
8
6
5
3
2
10
7
4
1
TD
TD
TD
TD
44+
33+
M X4 M X 4+
M X3 M X 3+
TD
TD
TD
TD
22+
11+
M X2 M X 2+
M X1 M X 1+
TC
TC
TC
TC
T4
T3
T2
T1
MC
MC
MC
MC
T4
T3
T2
T1
13
14
16
17
MX 1 +
MX 1 MX 2 +
MX 2 -
19
20
22
23
MX 3 +
MX 3 MX 4 +
MX 4 -
15
18
21
24
Z 2 10 5
Z 2 10 6
Z 2 10 7
Z 2 10 8
MX 4 +
MX 4 -
1
C1 8 8
C 1 94
C 20 5
C2 1 7
0. 0 1 u _ 16 V _ X 7 R _ 0 4
0 . 0 1 u_ 1 6 V _ X 7R _ 04
0 . 0 1u _ 1 6 V _ X7 R _0 4
0 . 01 u _ 1 6V _X 7 R _ 0 4
1
R 17 6
R1 7 0
R 16 3
R1 4 4
7 5 _ 1% _ 0 4
75 _ 1 % _0 4
7 5 _1 % _ 0 4
75 _ 1 % _0 4
Z 21 0 9
C2 2 2
10 0 0 p _2 K V _ X 7 R _ 1 2 _H 1 2 5
2
L 42
* W C M 2 01 2 F 2 S -1 6 1T 0 3
4
3
L F E 9 21 9 C -R
B - 30 LAN-RTL8111DL, RJ45
L MX 1 +
J _ R J -4 5
D V D D 12
R T L 8 1 11 D L- GR
CLOSE TO T RANSFORM ER
S3
EV DD 1 2
C LK _P C I E _ GL A N # 1 3
C L K _ P C I E _G L A N 1 3
P C I E _ T X N 4 _ GL A N 1 3
P C I E _ T XP 4 _ G LA N 1 3
C T RL 1 2 A
L A N_ V D D3
B.Schematic Diagrams
L25
H C B 1 00 5 K F -1 2 1 T2 0
>60mils
C T R L 1 2A
L A N _V D D 3
L20
H C B 1 6 08 K F - 12 1 T 2 5
2
L MX 3 -
Layout note:
L MX 4 +
L MX 4 -
Place under the common
choke body and same as
PHY layout requirment
V D D 3 1 2 , 28 , 3 1 . . 3 4 , 39 , 4 0
3 . 3 V S 3 , 8 . . 1 2, 1 4 , 1 6 . . 2 4, 2 6 . . 2 8 , 3 0. . 35
3 . 3 V 2 , 3, 12 . . 1 4 , 1 6 , 17 , 1 9 , 2 2, 25 , 2 8 , 3 5. . 39
Schematic Diagrams
Card Reader, IEEE1394
7 in 1 SOCKET
JMB380
Layout Note:
Close to JMB380
Zdi ff = 1 10 O
C 2 66
2 2 0 p_ 5 0 V _N P O_ 0 4
R 2 18
4 . 9 9 K _ 1% _ 0 4
R 2 19
5 6 _ 04
1 39 4 _ XI
J _C A R D -N O R
S D_ CD #
S DW P #
S D/M S _ D1
S D/M S _ D0
1 7 S D_ C D#
C2 9 1
2 0 p _5 0 V _ N P O _ 04
R 22 8
X5
F S X- 8L _ 24 . 5 7 6 MH z
V C C_ CA R D
2
1 M_ 0 4
1 39 4 _ XO
R 2 15
5 6 _ 04
C2 9 2
2 0 p _5 0 V _ N P O _ 04
Z 2 6 14
S D/M S _ D2
3 .3 V S _ CA RD
5 6 _ 04
MS _ I N S #
S D/M S _ D3
S D C MD / MS B S
S D/M S CL K
3 .3 V S
13 9 4 _T P B I A S 0
R 20 8
R 2 20
0 _ 06
5 6 _ 04
C 2 73
S D C MD / MS B S
S D/M S CL K
S D/M S _ D1
S D/M S _ D0
S D/M S _ D3
C2 6 2
C2 6 0
C 34 5
C 3 29
0. 1 u _ 16 V _ Y 5 V _ 0 4
10 u _ 10 V _ Y 5 V _ 0 8
0 . 1 u_ 1 6 V _Y 5 V _ 04
S D/M S _ D2
0. 1 u _ 16 V _ Y 5 V _ 0 4
0 . 3 3 u_ 1 6 V _ Y 5 V _ 06
CD_ S D
W P_ SD
D A T 1 _S D
D A T 0 _S D
W P GN D _ S D
VSS_ SD
V S S _ MS
B S _ MS
CL K_ SD
D A T 1 _M S
S D I O / D A T 0 _M S
V D D _S D
D A T 2 _M S
VSS_ SD
I N S _ MS
D A T 3 _M S
C MD _ S D
S C L K _ MS
V C C _M S
C D / D A T 3 _S D
V S S _ MS
D A T 2 _S D
G
G
G
G
ND
ND
ND
ND
P2 3
P2 4
P2 5
P2 6
MS D 0 19 -C 0-1 0 A 3
1 2K _ 0 4
Z 2 6 01
2 2_ 0 4
S D / MS _ D 3
S D / MS _ D 2
S D / MS _ D 1
0. 1 u _ 16 V _ Y 5 V _ 0 4 S D / MS _ D 0
C 2 86
DV 1 8
TX I N
TX O U T
MD I O7
MD I O6
MD I O5
MD I O4
DV 3 3
MD I O3
MD I O2
MD I O1
MD I O0
*1 0 p _5 0 V _ N P O _0 4
T CP S
MD I O 1 3
MD I O 1 4
C R _ LE D N
D V3 3
R E G_ C T R L
D V1 8
CR1 _ P CT L N
C R 1 _C D 0 N
C R 1 _C D 1 N
S E E C LK
SEED AT
GN D _ M
JMB380
QFN-48
24
23
22
21
20
19
18
17
16
15
14
13
49
TC PS
M D I O 13
M D I O 14
Z261 1
R 20 3
1 0 K _0 4
3. 3 V S _ C A R D
40 mil
D V 1. 8 V
S D _ CD#
M S _ INS #
Z261 2
Z261 3
V C C _C A R D
>30 mil
C 2 48
C 24 9
0 . 1 u _1 6 V _ Y 5 V _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 04
C2 5 0
0 . 1 u_ 1 6V _Y 5 V _0 4
IEEE1394
Note:
Close to CON.
J MB 3 8 0-Q GA Z 0 B
3 , 1 6 , 2 0, 2 8 , 2 9, 3 1 B U F _P L T _ R S T #
L P1
* 1 60 _ OH M_ # 94 4 C M -0 05 1
J _ 13 9 4
Z 2 60 5
Z2606
Z 2 60 2
Z2603
Z 2 60 4
1
2
3
4
5
6
7
8
9
10
11
12
3 .3 V S _ CA R D
R2 3 3
37
38
39
40
41
42
43
44
45
46
47
48
TR EXT
T P B IA S _ 1
T P A 1P
TPA1 N
T P B 1P
TPB1 N
T A V 33
M DIO 8
M D I O9
M D I O 10
M D I O1 1
M D I O 12
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 3 94 _ X I
1 3 94 _ X O
M DIO 7
SD W P#
S D / MS C LK _R
S D C M D / MS B S
S D / MS C LK
C3 2 5
XR STN
XTEST
A P CL K N
A P CL K P
A P V DD
A P GN D
A P RE X T
A P RX P
A P RX N
APV1 8
APT XN
APTXP
U1 8
M D I O 12
36
35
34
33
32
31
30
29
28
27
26
25
12 mil
C2 8 4
S D/M S CL K
Z2607
Z 2 60 8
Z2609
Z 2 61 0
R2 2 6
DV 1 .8 V
C 25 2
C 25 4
13 C LK _P C I E _ C R #
1 3 C L K _P C I E _ C R
D V 1 .8 V
C 26 1
C 26 4
C 2 72
C2 7 0
C2 7 1
12 mil
10 u _1 0 V _ Y 5 V _ 0 8
0 . 1u _ 1 6V _Y 5V _0 4
1 00 0 p _5 0 V _ X7 R _0 4
R 21 6
Sheet 30 of 55
Card Reader,
IEEE1394
0. 1 u _ 10 V _ X 7R _ 04
0. 1 u _ 10 V _ X 7R _ 04
0. 1 u _ 10 V _ X 7R _ 04
0. 1 u _ 10 V _ X 7R _ 04
P C I E _ R X P 5 _C R 1 3
P C I E _ R X N 5 _ C R 13
P C I E _ T XN 5 _C R 1 3
P C I E _ T XP 5 _ C R 1 3
GN D 1
GN D 2
DV 1 .8 V
GN D
GN D
TPA+
TP A TPB+
TP B -
4
3
2
1
5
6
7
8
4
3
2
1
1 39 4 _ TP
1 39 4 _ TP
1 39 4 _ TP
1 39 4 _ TP
A 0+
A 0B 0+
B 0-
C2 5 7
C 1 3 1 43 -1 0 40 5 -L
0 . 1u _ 1 6V _ Y 5V _0 4
8 . 2 K _ 04
V C C _C A R D
3 .3 V S _ CA R D
R2 0 6
4 . 7K _0 4
S D_ CD #
R2 0 7
4 . 7K _0 4
MS _ I N S #
R2 3 1
1 0K _0 4
R 23 2
1 0 K _0 4
S DW P #
R 20 4
1 0 K _0 4
MD I O1 3
R 20 2
2 0 0K _ 0 4
MD I O1 2
R 20 5
2 0 0K _ 0 4
MD I O1 4
3 . 3 V S 3 , 8. . 12 , 1 4 , 16 . . 2 4 , 2 6. . 2 9 , 3 1. . 3 5
MD I O7
Card Reader, IEEE1394 B - 31
B.Schematic Diagrams
>30 mil
13 9 4 _T P B 0 13 9 4 _T P B 0 +
13 9 4 _T P A 0 13 9 4 _T P A 0 +
R 2 22
P1
P2
P3
P4
P5
P6
P7
P8
P9
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
P1 6
P1 7
P1 8
P1 9
P2 0
P2 1
P2 2
1
Note:
Close to JMB380
Schematic Diagrams
KBC ITE IT8512-J
MODEL_ID
VD D3
K B C _ A V DD
L 35
H C B 1 00 5 K F -1 2 1T 2 0
EVT/DVT 3.3V
PVT
V D D3
0V
C 3 60
C3 5 9
C 35 3
C3 6 8
C3 5 7
C3 5 2
C3 5 1
1 0 u _1 0 V _ Y 5 V _ 08
0 . 1u _ 1 6V _ Y 5V _ 0 4
0 . 1 u_ 1 6 V _ Y 5 V _ 04
0. 1 u _ 16 V _ Y 5 V _ 0 4
0 . 1u _ 1 6V _Y 5V _0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
0. 1u _ 16 V _ Y 5V _ 0 4
3 .3 V S
K B C _ A GN D
C 36 6
R2 7 5
*1 0 K _ 04
R2 8 1
1 0K _0 4
0. 1 u _ 16 V _ Y 5V _ 0 4
M OD E L_ I D
V D D3
R2 9 7
Sheet 31 of 55
KBC ITE IT8512-J
1 00 K _ 0 4
P C LK _ K B C
K B C _ W RE S E T #
1 7 GA 2 0
1 4 , 40 A C _ I N #
3 2 L E D_ A C IN#
2 T H E R M_ A L E R T #
1 7 S MI #
1 7 S CI#
23
15
4 0 B A T 1 _D E T
1 0, 1 7 M XM 1_ P R S N T #
1 1, 1 7 M XM 2_ P R S N T #
2 C P U _ TH E R M
Bat te ry, T ou ch Key
CPU, MXM2
M XM 1, HDMI Re pe ate r
3 3 ,4 0 S M C_ B A T 1
3 3 ,4 0 S M D_ B A T 1
2 , 1 1 , 1 3 S M C _ T H E R M_ 1
2 , 1 1 , 1 3 S M D _ T H E R M_ 1
1 0 , 2 3 S M C _ T H E R M_ 2
1 0 , 2 3 S M D _ T H E R M_ 2
R5 1 1
14
126
4
16
20
76
77
78
79
80
81
2 3 C P U _F A N
2 3 V GA F A N 1_ O N
2 3 V GA F A N 2_ O N
3 3 E C _L E D _B L
3 3 E C _L E D _T S
33 E C _ LE D _ F R
ADCp ort
M ust pu ll up
ex te rnal r e sis tors
B A T1 _ D E T
B A T1 _ V OL T _ R
C H G _ C U R S E N _R
T O TA L_ C U R _ R
M OD E L_ I D
S
S
S
S
S
S
MC _ B A T 1
MD _ B A T 1
MC _ T H E R M_ 1
MD _ T H E R M_ 1
MC _ T H E R M_ 2
MD _ T H E R M_ 2
66
67
68
69
70
71
72
73
110
111
115
116
117
118
* 0 _0 4
22 B R I GH TN E S S
26 K B C _ B E E P
3 3 L E D _ S C R OL L #
3 3 LE D _ N U M#
33 L E D _C A P #
3 2 L E D _ B A T _ C H G#
32 L E D _B A T _ F U L L #
3 2 LE D _ P W R #
2 8 8 0 CL K
28 3 I N 1
2 8 8 0P O R T _ D E T #
23 V G A S E N _ S E L
32 T P _ C L K
32 T P _ D A T A
8 0C L K
3 IN1
8 0P OR T _ D E T #
1 4 P W R_ B T N#
85
86
87
88
89
90
125
3 3 S E N S OR _ I N T#
3 4 P W R_ S W #
2 2 , 33 L I D _ S W #
24
25
28
29
30
31
32
34
18
21
33
3
VBAT
K S I0 /S T B #
K S I1 /A F D #
K S I2 /INIT #
K S I 3 / S LI N #
K S I4
K S I5
K S I6
K S I7
LPC K/B MATRIX
W R S T#
K S O 0/ P D 0
K S O 1/ P D 1
K S O 2/ P D 2
K S O 3/ P D 3
K S O 4/ P D 4
K S O 5/ P D 5
K S O 6/ P D 6
K S O 7/ P D 7
K S O8 / A C K #
K S O 9 /B US Y
K S O 1 0/ P E
K S O1 1 / E R R #
K S O1 2 / S LC T
K S O1 3
K S O1 4
K S O1 5
GA 2 0 / GP B 5
K B R S T# / G P B 6 ( P U )
P W U R E Q #/ G P C 7 ( P U )
L 80 L L A T/ GP E 7 ( P U )
E C S C I # / GP D 3 ( P U )
E C S MI # / GP D 4 ( P U )
DAC
DA C
DA C
DA C
DA C
DA C
DA C
0 / GP J 0
1 / GP J 1
2 / GP J 2
3 / GP J 3
4 / GP J 4
5 / GP J 5
I T8 51 2E
( P D )K S O1 6 / GP C 3
( P D )K S O1 7 / GP C 5
ADC
A DC
A DC
A DC
A DC
A DC
A DC
A DC
A DC
0 / GP I 0
1 / GP I 1
2 / GP I 2
3 / GP I 3
4 / GP I 4
5 / GP I 5
6 / GP I 6
7 / GP I 7
L K 0/
A T 0/
L K 1/
A T 1/
L K 2/
A T 2/
GP B 3
GP B 4
GP C 1
GP C 2
GP F 6 ( P U )
GP F 7 ( P U )
0/ G
1/ G
2/ G
3/ G
4/ G
5/ G
6/ G
7/ G
K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
K B -S O0
K B -S O1
K B -S O2
K B -S O3
K B -S O4
K B -S O5
K B -S O6
K B -S O7
K B -S O8
K B -S O9
K B -S O1 0
K B -S O1 1
K B -S O1 2
K B -S O1 3
K B -S O1 4
K B -S O1 5
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
K B -S O
(
(
(
(
(
(
(
PA0 (
PA1 (
PA2 (
PA3 (
PA4 (
PA5 (
PA6 (
PA7 (
PU
PU
PU
PU
PU
PU
PU
PU
)
)
)
)
)
)
)
)
P S 2 C L K 0 / GP F
P S 2 D A T 0 / GP F
P S 2 C L K 1 / GP F
P S 2 D A T 1 / GP F
P S 2 C L K 2 / GP F
P S 2 D A T 2 / GP F
0(
1(
2(
3(
4(
5(
PU
PU
PU
PU
PU
PU
PD
PD
PD
PD
PD
PD
PD
)I D 0 / GP H
)I D 1 / GP H
)I D 2 / GP H
)I D 3 / GP H
)I D 4 / GP H
)I D 5 / GP H
)I D 6 / GP H
0
1
2
3
4
5
6
( P D )I D 7 / GP G 1
1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24
MP ? ? ?
J _ 8 0D B G
( P D )E G A D / G P E 1
( P D )E GC S # / G P E 2
( P D )E GC L K / G P E 3
PS/2
WAKE UP
)
)
)
)
)
)
( P D )W U I 5 / G P E 5
( P D )L P C P D # / W U I 6 / G P E 6
PWM/COUNTER
( P D )T A C H 0 / GP D 6
( P D )T A C H 1 / GP D 7
WAKE UP
( P D )T MR I 0/ W U I 2 / GP C 4
( P D )T MR I 1/ W U I 3 / GP C 6
CIR
R I 1 # / W U I 0/ G P D 0 ( P U )
R I 2 # / W U I 1/ G P D 1 ( P U )
( P D )C R X / GP C 0
( P D )C TX / G P B 2
GP INTERRUPT
1 00
1 01
1 02
1 03
1 04
1 05
1 06
LPC/WAKE UP
V D D3
V DD 3
2
1
10
9
0 . 1 u_ 1 6V _Y 5 V _0 4
R 3 11
AVSS
R2 7 7
*2 0m i l _N P _ 04
1 K _ 04
8
VD D
? ? ?
Z 20 0 6
3
Z 20 0 7
7
C K 3 2K E
CK 3 2 K
K
K
K
K
B C_ S P I_ S I_ R
B C _ S P I _ S O_ R
B C_ S P I_ CE # _ R
B C_ S P I_ S CL K _ R
W P#
H OL D #
4
VSS
R3 0 2
R3 1 0
R3 0 9
R2 9 9
C
C
C
C
4 . 7 K _0 4
S U S _ P W R _A C K 1 4
W LA N _ E N 2 8
K B C _ MU TE # 2 7
D D _ O N _ LA TC H 3 4
S U S B # 1 4 , 20 , 2 8 , 34 , 3 6
S U S C # 1 4 , 3 4, 3 7
D D_ O N 3 4
37 8
39 1
39 0
37 1
47 _ 0 4
15 _ 1 %_ 0 4
15 _ 1 %_ 0 4
47 _ 0 4
*3 3 p_ 5 0 V _N
*3 3 p_ 5 0 V _N
*3 3 p_ 5 0 V _N
*3 3 p_ 5 0 V _N
P O_ 0 4
P O_ 0 4
P O_ 0 4
P O_ 0 4
K B C_ S P I_ S I
K B C_ S P I_ S O
K B C_ S P I_ C E #
K B C _ S P I _ S C LK
K B C_ S P I_ S I
K B C_ S P I_ S O
K B C_ S P I_ C E #
K B C _ S P I _ S C LK
E N 2 5P 05 - 5 0 GC P
K B C _A C / B A T L #
82
83
84
E GA D 33
E GC S # 3 3
E GC L K 3 3
4 0 B A T _V OL T
35
17
R S MR S T # 14
K B C_ RS T # 1 7
40 C H G _C U R S E N
4 0 T O TA L _ C U R
47
48
C
D 31
A
C IR_ IN
S CS 3 5 5 V
R2 9 1
10 K _ 0 4
V D D3
P C LK _ K B C
R 29 5
* 10 _ 0 4
P C L K _ K B C _R
C3 6 7
*1 0 p _5 0 V _ N P O _ 04
B A T _ V OL T
R 28 0
1 0 0_ 0 4
B A T 1 _V O L T_ R
C3 5 6
1 u _1 0 V _ 06
C H G_ C U R S E N
R 27 9
1 0 0_ 0 4
C H G_ C U R S E N _ R
C3 5 5
1 u _1 0 V _ 06
T OT A L _ C U R
R 27 8
1 0 0_ 0 4
T OT A L _C U R _R
C3 5 4
1 u _1 0 V _ 06
C P U _ F A N S E N 23
V GA _ F A N S E N 2 3
1 20
1 24
1 19
1 23
5
2
1
6
S I
SO
C E#
S CK
C CD _ EN 2 5
93
94
95
96
97
98
99
1 07
SPI_SI_R = 0.1"~0.5"
K B C _S P I _S C L K
V C OR E _O N 3 5
L A N _ D S M # 29
V D D3
C IR_ IN
S W I # 14
C HG _ EN 4 0
2
1 28
R2 9 4
75
VSS
VSS
VSS
VSS
VSS
VSS
1
27
49
91
11 3
122
C 36 5
J_80DBG
V DD 3
80 C L K
80 P O R T _ D E T #
U 32
19
CLOCK
I T 8 51 2 E -J
C 3 70
S P I_ V DD
( P D )L 80 H LA T / G P E 0
VSS
R X D / GP B 0 ( P U )
T XD / GP B 1( P U )
1
3
5
7
9
S P U F Z -1 0 S 3 -V B -0 -B
K B C _S P I _C E #
K B C _S P I _S I
K B C _S P I _S O
( P D )R I N G #/ P W R F A I L # / L P C R S T# / G P B 7
UART
2
4
6
8
10
3I N 1
85 2 0 1-2 4 0 51
56
57
1 12
2 5 B T_ E N
2 2 B K L_ E N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3 2 C I R _R X
EXT GPIO
GI N T / GP D 5( P U )
108
109
4
5
6
8
11
12
14
15
R 3 01
GPIO
PWM
PW M
PW M
PW M
PW M
PW M
PW M
PW M
PW M
K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7
R 3 00
*2 0m i l _N P _ 04
F L F R A ME # / GP G 2
F L A D0 /S C E #
F L A D 1/ S I
F L A D2 /S O
F L A D 3 / GP G 6
F L CL K /S C K
( P D )F L R S T# / W U I 7 / TM / GP G 0
SMBUS
S MC
S MD
S MC
S MD
S MC
S MD
58
59
60
61
62
63
64
65
FLASH
P W R S W / GP E 4( P U )
L ID_ S W #
J _ KB1
A V CC
L A D0
L A D1
L A D2
L A D3
L P C C LK
L F RA M E #
S E R IRQ
L P C R S T# / W U I 4 / GP D 2( P U )
24
J_KB1
74
26
50
92
114
12 1
127
VSTBY
VSTB Y
VSTBY
VSTB Y
VSTBY
VSTB Y
VC C
10
9
8
7
13
6
5
22
12
B.Schematic Diagrams
U 28
1 2 , 2 2 L P C _A D 0
1 2 , 2 2 L P C _A D 1
1 2 , 2 2 L P C _A D 2
1 2 , 2 2 L P C _A D 3
1 6 P C L K _K B C
1 2 , 22 L P C _ F R A ME #
1 2 ,2 2 S E RIR Q
3 , 1 6 , 20 , 2 8 . . 3 0 B U F _ P L T_ R S T#
1 0M _0 4
X6
C M 20 0 S 3 2 76 8 1 22 0 _ 32 . 7 6 8K H z
1
2
C3 6 2
K B C _ A C / B A T L# C
D 27
A
R B 75 1 V -4 0
C
A
R B 75 1 V -4 0
4 0 A C_ IN
D 26
A C / B A T L# 1 0 , 11
4
3
C3 6 3
0 . 1 u_ 1 6 V _Y 5 V _ 04
1 2 p _5 0 V _ N P O _0 4
12 p _ 50 V _ N P O_ 04
K B C _ A GN D
3, 8 . . 1 2 , 14 , 1 6 . . 2 4, 2 6 . . 3 0, 3 2 . . 3 5 3. 3 V S
1 2 , 2 8, 3 2 . . 3 4, 39 , 4 0 V D D 3
B - 32 KBC ITE IT8512-J
C
AC
A
D 29
B A V 9 9 RE CT IF IE R
C
S MD _ B A T 1
AC
A
D 30
B A V 9 9 RE CT IF IE R
C
B A T1 _ D E T
AC
A
D 28
B A V 9 9 RE CT IF IE R
C
B A T_ V O LT
AC
A
D 25
B A V 9 9 RE CT IF IE R
C
C H G _C U R S E N
AC
A
D 24
B A V 9 9 RE CT IF IE R
C
T O TA L _ C U R
AC
A
D 23
B A V 9 9 RE CT IF IE R
S MC _ B A T 1
1
11
VD D3
S MC _ B A T 1
S MD _ B A T 1
R 28 6
R 28 5
4 . 7 K _0 4
4 . 7 K _0 4
S MC _ TH E R M _ 1
S MD _ TH E R M _ 1
R 28 7
R 28 9
*4 . 7 K _ 0 4
*4 . 7 K _ 0 4
S MC _ TH E R M _ 2
S MD _ TH E R M _ 2
R 28 8
R 29 0
4 . 7 K _0 4
4 . 7 K _0 4
B A T 1 _D E T
R 28 4
1 0 K _0 4
L ID_ S W #
R 29 6
1 0 0K _ 0 4
AD C PORT
Schematic Diagrams
MB to Small B’d Connector A
AUDIO B'd
GAME KEY B'd
Click B'd
J_ A U D I O
16 U S B _P P 0
16 U S B _P N 0
V CC US B_ 0 1
2 6 H P -R
2 7 H P _ P LU G
2 6 LI N E -I N _R
2 6 L I N E -I N _ L
10 , 2 6 S P D I F _ O U T
S A T A _ RX N3 1 2
S AT A _ RX P3 1 2
S A T A _ TX N 3 1 2
S A T A _ TX P 3 1 2
3 .3 V S
H P -L 2 6
MI C 1 -R 2 6
MI C 1 -L 26
L INE _ S E N S E 2 6
MI C _ S E N S E 2 6
H P _S E N S E 2 6
A UD G
H= 1. 8
3 . 3 V S _ JG A ME K E Y
J _ GA M E K E Y
1
2
3
4
5
6
7
8
9
10
11
12
H =1 .8
3 . 3V S
F5
*5 6m i l _0 8
5 V S _J T P
1
2
3
4
5
6
7
8
9
10
J_GAMEKEY
GA M
GA M
GA M
GA M
GA M
GA M
GA M
GA M
E# 1
E# 2
E# 3
E# 4
E# 5
E# 6
E# 7
E# 8
33
33
33
33
33
33
33
33
1
12
1
2
3
4
5
6
7
8
9
10
T P _ DA T A
T P _ CL K
T P_ DAT A 3 1
T P_ CL K 3 1
L ED_ ACI N# 3 1
L ED_ PW R # 3 1
L E D _ B A T _ C H G # 31
L ED_ BA T _ F UL L # 3 1
F6
*5 6 mi l _ 08
85 2 0 1-1 0 0 51
6- 20- 94 A2 0-1 12
8 7 1 51 -1 2 07 G
V D D 3 _J T P
T P _ DA T A
T P _ CL K
PWR BUTTON B'd
Finger Printer B'd
3. 3 V S
J_ F P
1
2
3
4
J _ P W R B TN
1
2
3
3 .3 V S _ F P
L 29
H C B 1 0 0 5K F -12 1 T 20
R 4 87
R 4 86
H= 1.8
* 10 K _ 0 4
* 10 K _ 0 4
V D D3
5V S
Sheet 32 of 55
MB to Small B‘d
Connector A
CIR BOARD
3 .3 VS
VDD 5
J _C I R
U S B _ P N 10 1 6
U S B _ P P 1 0 16
1
2
3
C 30 3
0 . 1 u_ 1 6 V _Y 5 V _0 4
C I R _R X 31
8 5 2 04 -0 3 00 1
8 52 0 1- 04 0 51
8 5 2 04 -0 3 00 1
5 VS
F7
*5 6 mi l _ 08
J _ TP
1
M _B T N # 3 4
4
J_FP
HDDx1 B'd
HDDx2 B'd
J _ HDD 2
12 S A T A _ T XP 0
12 S A T A _ T XN 0
1 2 S A TA _R XN 0
1 2 S A TA _R XP 0
J_ H D D 1
1 2 S A T A _ TX P 4
1 2 S A T A _ TX N 4
5 VS
2
4
6
8
10
1
3
5
7
9
S P N A F -1 0 -B -1-C
S A T A _ RX N4 1 2
S A T A _ RX P 4 1 2
3 .3 V S
5 VS
3. 3 V S
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
S A TA _ T X P 2 1 2
S A TA _ T X N 2 1 2
S A TA _ R XN 2 1 2
S A TA _ R XP 2 1 2
3 .3 V S
5 VS
S Q P OF Z -2 0 S 2 -B -1 -K
3 , 8 . . 12 , 1 4 , 1 6. . 2 4 , 2 6. . 3 1 , 3 3. . 3 5 3 . 3 V S
10 , 1 1 , 19 . . 2 1 , 23 . . 2 7 , 33 . . 3 5 5 V S
1 2 , 2 8, 3 1 , 3 3, 3 4 , 3 9, 4 0 V D D 3
3 4, 3 9 V D D 5
2 5 V C C U S B _ 01
MB to Small B’d Connector A B - 33
B.Schematic Diagrams
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
88 1 0 7-3 0 0 01
16 U S B _P P 1
16 U S B _P N 1
Schematic Diagrams
MB to Small B’d Connector B
FRONT LED B'd
J _ FL ED
Front LED control
J _ T LE D
1
2
3
4
5
6
7
8
9
10
11
12
5 VS_ FT
6
5
4
3
2
1
8 52 0 4 -06 0 0 1
F LE D _ R
F LE D _ G
F LE D _ B
TOUCH SENSOR B'd
TOUCH PAD LED B'd
J _ S ENS O R
5 V S _ TL E D
5 V S _ J S E NS O R
C L E D _R
C L E D _G
C L E D _B
F8
* 5 6m i _l 0 8
5 VS_ 1
30 mils
5 VS
C 38 8
H =1 .8
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
F LE D _ R
F LE D _ G
F LE D _ B
F ON
V IN
V OU T
V SET
8
7
6
5
GN D
GN D
GN D
GN D
1 2 S A TA _ L E D #
3 1 L E D _N U M #
3 1 L E D_ CA P #
3 1 LE D _ S C R O L L#
3 1 EG AD
31 E G C S #
31 E G C L K
31 , 4 0 S MD _B A T1
31 , 4 0 S MC _B A T1
2 2 , 3 1 LI D _S W #
V DD3 _ J S E NS O R
*G 99 0 P 1 1U
30 mils
5 VS_ FT
8 52 0 4 -12 0 0 1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
U3 3
1
2
3
4
E C _ LE D _ F R 3 1
C 38 9
10 mils
2
4
6
8
10
12
14
16
18
20
22
24
26
28
5 VS_ BL
H= 1.8
S E N S OR _I N T # 3 1
C O LO R _ R
C O LO R _ G
C O LO R _ B
B T _R
B T _G
B T _B
CC D_ R
CC D_ G
CC D_ B
5 V S _ JT S
F2
*5 6m i l _0 8
5V S _ J S E N S OR
3 .3 V S
F1
*5 6m i l _0 8
3. 3 V S _ J S E N S O R
F3
*5 6m i l _0 8
V D D3
V D D 3_ J S E N S O R
Touch sensor LED control
3. 3V S _ J S E N S OR
V D D 3 _J S E N S OR
RA
RB
RC
Sheet 33 of 55
MB to Small B‘d
Connector B
Fr on t L ED
CT RL
Fro nt L ED +
T/P L ED CT RL
Unstuff
Stuff
Unstuff
Unstuff
Unstuff
Stuff
5 V S _ J S E N S OR
3 . 3 V S _ JS E N S O R
U5
5V S _ B L
1
2
3
4
30 mils
5 VS
N O CTR L
Stuff
Stuff
Unstuff
5 VS_ 1
5 VS_ FT
R 31 2
0 _0 6
R 31 4
0 _0 6
R 31 3
*0 _ 0 6
RA
RB
RC
5 VS_ F T
C 59 0
C 5 91
C5 9 2
C5 9 3
C 1 50
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
* 0 . 1u _ 1 6V _ Y 5V _ 0 4
*0 . 1 u_ 1 6V _Y 5V _0 4
*0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u _1 6 V _ Y 5 V _ 0 4
5 VS_ T L ED
F ON
V IN
V OU T
VSET
GN
GN
GN
GN
D
D
D
D
8
7
6
5
G9 9 0 P 1 1U
30 mils
E C _L E D _T S 3 1
5 V S _ J TS
C 1 39
0 . 1 u _1 6 V _ Y 5 V _ 0 4
Back LED control
F9
*5 6 m il _ 08
5 VS_ 3
5V S _ 2
F4
S MD 08 0 5 P 10 0 T F _1 A
U 34
1
2
3
4
30 mils
5 VS
C4 0 9
H= 1. 8
Logo LED control
*0 . 1 u_ 1 6V _Y 5V _0 4
F ON
VIN
V OU T
VSET
GN D
GN D
GN D
GN D
8
7
6
5
U 4
1
2
3
4
30 mils
5 VS
H =1. 8
C1 1 9
*0 . 1 u _1 6 V _ Y 5 V _ 04
* G9 9 0P 1 1 U
FO N
V IN
V O UT
VSET
G ND
G ND
G ND
G ND
8
7
6
5
ITE8301E
* G9 9 0P 11 U
U 15
30 mils
30 mils
E C _ LE D _ B L
5V S _B L
E C _L E D _B L 3 1
E C_ L E D_ B L
5V S _J C LE D
C4 0 6
C1 2 5
*0 . 1 u_ 1 6V _Y 5V _0 4
*0 . 1 u _1 6 V _ Y 5 V _ 04
3 1 E GA D
3 1 E G CS#
3 1 E G CL K
RE
R3 2 1
5 VS_ 3
E S E L0
8 3 01 R S T#
C LE D _ R
C LE D _ G
C LE D _ B
B L E D _R
B L E D _G
B L E D _B
F L E D _R
F L E D _G
F L E D _B
L L E D_ R
L L E D_ G
L L E D_ B
C OL OR _R
C OL OR _G
C OL OR _B
RD
0_ 0 6
B ac k LED
C TR L
RE Unstuff
5 VS_ BL
R7 2
5V S _2
0_06
L ogo L ED
C TRL
N O C TR L
Stuff
RD Unstuff
5 V S _ JC LE D
NO C TRL
Stuff
BACK R side LED
2 6 EAPD
A
R
G
B
R3 2 0
3 00 _ 1% _ 0 4
D2
R3 1 9
4 64 _ 1% _ 0 4
D3
R3 1 8
1 00 _ 1% _ 0 4
BACK L LED B'd
Q 31
M TN 7 00 2 Z H S 3
D 32
R Y -S P 1 1 7 U R D GN B 4
D1
Z2904
R3 2 8
3 00 _ 1% _ 0 4
Z2913
D2
Z2905
R3 2 9
4 64 _ 1% _ 0 4
Z2914
D3
Z2906
R3 3 0
1 00 _ 1% _ 0 4
Z2915
6
5
4
3
2
1
A
GA M E # 1 3 2
GA M E # 2 3 2
GA M E # 3 3 2
GA M E # 4 3 2
GA M E # 5 3 2
GA M E # 6 3 2
GA M E # 7 3 2
GA M E # 8 3 2
W L A N_ DE T # 2 8
B T _D E T # 2 5
CC D_ DE T # 2 5
MX M_ T H _ OV E R T # 10
MX M_ T H _ A L E R T # 1 0
V GA _ R S T# 1 6
P L T_ R S T# 1 6 , 22
CCD _ DE T #
Re v _3. 0
BT _ R
BT _ G
BT _ B
CC D_ R
CC D_ G
CC D_ B
Rev _3 .0
V DD3
C2 3 9
C 2 55
0. 1 u _ 16 V _ Y 5 V _ 0 4
5 VS_ BL
0 . 1 u _1 6 V _ Y 5 V _ 04
V D D3
B LE D _ R
B LE D _ G
B LE D _ B
R 21 3
4 . 7 K _ 04
Q 32
M TN 7 00 2 Z H S 3
8 3 0 1R S T #
3 00 _ 1% _ 0 4
R3 2 3
4 64 _ 1% _ 0 4
D3
Z2909
R3 2 4
1 00 _ 1% _ 0 4
B L ED_ G
S
R3 2 2
Z2908
R3 3 1
3 00 _ 1% _ 0 4
Z2911
R3 3 2
4 64 _ 1% _ 0 4
D3
Z2912
R3 3 3
1 00 _ 1% _ 0 4
B - 34 MB to Small B’d Connector B
LOGO LED B'd
0 . 1 u_ 1 6 V _Y 5 V _0 4
J _ CL E D
Q 33
M TN 7 00 2 Z H S 3
G
D2
R2 1 2
4. 7 K _ 0 4
ESEL 0
R2 7 6
10 K _ 0 4
CC D_ DE T #
C 26 5
G
D2
D 35
R Y -S P 1 1 7 U R D GN B 4
Z2910
D1
R
G
B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
I T 8 3 01 E
8 7 21 2 -0 6G 0
D
R
G
B
V D D3
VSTBY
G P I O3 7
G P I O3 6
G P I O3 5
G P I O3 4
G P I O3 3
G P I O3 2
G P I O3 1
G P I O3 0
G P I O2 9
G P I O2 8
G P I O2 7
G P I O2 6
G P I O2 5
G P I O2 4
G P I O2 3
G P I O2 2
G P I O2 1
G P I O2 0
G P I O1 9
G P I O1 8
G P I O1 7
G P I O1 6
VSTBY
V D D3
D 33
R Y -S P 1 1 7 U R D GN B 4
D1
Z2907
A
VSS
GP I O_ D A T A
CY CL E _ S T A RT
GP I O_ C L K
CH IP _ S E L 1
CH IP _ S E L 0
R E S E T#
GP I O0
GP I O1
GP I O2
GP I O3
GP I O4
GP I O5
GP I O6
GP I O7
GP I O8
GP I O9
GP I O1 0
GP I O1 1
GP I O1 2
GP I O1 3
GP I O1 4
GP I O1 5
VSS
J _ B LE D L
D
R
G
B
B L ED_ R
S
G
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D
D 34
R Y -S P 1 1 7 U R D GN B 4
D1
5 VS_ BL
S
B.Schematic Diagrams
8 72 1 6 -28 1 6 -06
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
B L ED_ B
6
5
4
3
2
1
8 5 20 4 -0 60 0 1
5 VS _ J CL ED
LL E D _R
LL E D _G
LL E D _B
3 , 8 . . 1 2, 1 4 , 1 6. . 2 4 , 2 6. . 3 2 , 3 4, 3 5 3 . 3 V S
1 0 , 11 , 1 9 . . 21 , 2 3 . . 27 , 3 2 , 34 , 3 5 5 V S
1 2 , 2 8, 3 1 , 3 2, 3 4 , 3 9, 4 0 V D D 3
Schematic Diagrams
Power System
POWER SW
Q4 2
I R F 7 8 3 2Z TR P B F
8
7
3
6
2
5
1
7 0?
S Y S 15 V
V DD 5
1 0. 5 A
16 A ma x .
5 VS
1 0 .5 A
R4 8 2
4
S Y S 15 V
C 5 76
C5 7 4
R4 8 3
0 . 1 u _ 16 V _ Y 5 V _ 0 4
1 0 u_ 1 0 V _Y 5 V _0 8
10 0 K _ 04
1M _ 04
5 VS_ EN
R2 8 2
D
S U S B 3 7 , 38
1 M_ 0 4
C5 7 7
Q 38
M TN 7 00 2 Z H S 3
S
1
14 , 2 0 , 28 , 3 1 , 3 6 S U S B #
1 00 0 p _5 0 V _ X 7R _ 04
S
D
G
Q2 9
M T N 7 0 02 Z H S 3
G
PJ 7
*O P E N -1m m
R 2 83
ON
ON
S Y S 1 5V
Q3 9
I R F 8 7 0 7P B F
8
7
3
6
2
5
1
V DD 3
5 .5 A
VA
(1)
V D D3
R4 8 1
R4 8 4
1 0 u_ 1 0 V _Y 5 V _0 8
10 0 K _ 04
*2 2 0_ 0 4
C5 7 8
Q 40
M TN 7 00 2 Z H S 3
G
2 20 0 p _5 0 V _ X 7R _ 04
A
C
D
Z 3 0 02
1 0 K _0 4
(6)
3 1 PW R_ SW #
D 21
S C S 3 55 V
Q 41
* MT N 7 0 0 2Z H S 3
G
S
G
R 27 1
To KB C
Sheet 34 of 55
Power System
S
Q2 5
M TP 3 4 0 3N 3
S
D
C5 7 3
0 . 1 u _ 16 V _ Y 5 V _ 0 4
3 .3 V S _ E N
D 22
S C S 3 55 V
A
C
R 26 9
C 5 75
1M _ 04
(8)
D
(2)
VIN 1
3. 3 V S
5 . 5A
4
R4 8 5
V IN
70 ? 9 .1 A ma x .
1 0 0K _ 0 4
P W R _S W #
R 27 0
2 0 K _ 04
D
Z3 0 01
G
S3 Pow e r Re ducti on w hite pa pe r
C
M _B TN
MM _ B TN
G
G
S
E
0 . 1 u _1 6 V _ Y 5 V _ 0 4
B
C 3 49
Q2 3
DT A1 1 4 EUA
C3 5 0
R 26 8
0. 1 u _ 16 V _ Y 5V _ 0 4
1 0 0 K _0 4
Q 26
M T N 7 00 2 Z H S 3
1.5VS_CPU
1
D
R 26 7
1 0 0K _ 0 4
S
VIN
D
S
Q2 4
MT N 70 0 2 Z H S 3
ON
(7)
D D _ ON _L A T C H
Q 28
M T N 7 0 02 Z H S 3
2
D D _ ON _ LA T C H 3 1
R2 7 4
1 00 K _ 0 4
M B TN #
S Y S 15 V
M_ B T N #
R2 6 6
1 0K _0 4
V D DQ
R 51 7
R5 0 5
* 0_ 0 4
V IN1
V IN
7
VIN
M _ B TN #
8
1 .5 V S _ CP UE N
V IN 1
D D _ ON _L A T C H
D D _ ON _ LA T C H
3
M_ B T N #
PW R _ SW #
M TN 7 00 2 Z H S 3
5
1 0 u_ 1 0 V _Y 5 V _0 8
R 50 6
C5 8 5
*2 2 0 0P _ 5 0 V _ 04
GN D
D
I N S T A N T -O N
C5 8 4
0 . 1 u _ 16 V _ Y 5 V _ 0 4
G
P W R_ S W #
4
C 5 83
2 2 0_ 0 4
Q 50
6
1 .5 V S _ CP U
6A
D
Co-l ay out SO P-8
P28 08
VA
2
1M _ 04
Q4 9
I R F 8 7 0 7P B F
8
7
3
6
2
5
1
S
U4 4
1
VA
6A
4
(3)
*P 2 8 0 8
Q 51
M TN 7 00 2 Z H S 3
S
G
SYS1 5 V
S Y S 15 V
R 2 72
R5 1 8
1 M _0 4
1 M_ 0 4
D
1
From KB C
P J6
*OP E N -1 m m
Q 27
M T N 7 0 02 Z H S 3
14 , 3 1 , 3 7 S U S C #
Q5 2
M T N 7 0 02 Z H S 3
G
S
G
2
3 1 D D _O N
S US C
ON
D D _ ON # 39
D
ON
S
3 2 M_ B T N #
ON
TU RN O N
5V, 3V
ON
TUR N O N
CPU V DDQ
40 V A
11 , 2 2 , 3 5. . 4 0 V I N
3 9 V IN 1
2 2, 3 9 S Y S 15 V
3 2 ,3 9 V DD 5
1 2 , 28 , 3 1 . . 3 3, 3 9 , 4 0 V D D 3
3 , 8 , 9, 1 9 , 3 7 1. 5 V
3 7 V DD Q
1 0 , 11 , 1 9 . . 2 1, 2 3 . . 2 7 , 32 , 3 3 , 35 5 V S
3, 8. . 1 2 , 1 4, 16 . . 2 4 , 26 . . 3 3 , 3 5 3. 3 V S
3 ,6 1 .5 V S _ CP U
Power System B - 35
B.Schematic Diagrams
TURN ON
5 VS/3 VS/1 .8 VS/1 .5 VS/ VTT_ MEM
Z3 0 03
2
* 1 00 K _ 0 4
Schematic Diagrams
Power VCore
P C1 7 4
* 1n _5 0 V_ 0 4
V IN
P R 1 95
39 . 2 K _1 %_ 0 4
S G ND2
Rev _3.0
4. 7 u_ 2 5V _ X 5R _0 8
P C 13 9
P C1 3 0
*15 u _2 5V _ 6 . 3* 4. 4 _C
4. 7 u _2 5V _ X 5R _0 8
4 . 7u _ 25 V _X 5 R _ 08
P C1 3 3
0. 1 u _5 0V _ Y 5 V_ 0 6
4 . 7u _ 25 V _X 5 R _ 08
P C 1 31
D
S
S
C S _P H 1
A
V IN
G
HDR 2
22 0 pF _ 50 V _ 06
DEL PC187
P R 19 2
1 0 _0 6
P L 13
0. 3 6 U H _ 10 *1 0 *3. 5
LX 2
26A
3 H _ P R O C H OT #
S G ND2
10 _0 4
0. 2 2 u_ 50 V _ 08
BST2
P Q6 2
I R F H 7 9 32
G
G
P Q6 3
I R F H 79 32
22 u _6 . 3V _ X 5R _ 0 8
P C 12 4
22 u _6 . 3V _ X 5R _ 0 8
P C 12 1
22 u _6 . 3V _ X 5R _ 0 8
P C 12 0
22 u _6 . 3V _ X 5R _ 0 8
P C 11 9
22 u _6 . 3V _ X 5R _ 0 8
P C 47
22 u _6 . 3V _ X 5R _ 0 8
P C 46
22 u _6 . 3V _ X 5R _ 0 8
P C 19 3
22 u _6 . 3V _ X 5R _ 0 8
P C 19 5
22 u _6 . 3V _ X 5R _ 0 8
P C 1 96
A
S
F M5 82 2
PC 19 7
22 u _6 . 3V _ X 5R _ 0 8
P C 12 2
22 0 pF _ 50 V _ 06
1
T TS N S
P L 14
*0 . 36 U H _ 1 2. 9 *1 4* 3. 8
P C 12 3
P D 21
S
G
S
7 . 3 2K _ 1% _ 04
P R 1 96
5. 1 _ 06
C
P Q6 1
MT N 7 00 2 Z H S 3
P R 19 8
P R 1 99
2 . 2_ 06
D
PR 19 7
D
P C 1 94
D
5 VS
3
VCC2
10 0 0U _2 V _1 2 *12
CSRE F
CSPH1,2
????? ?
5 VS
?? ???
VCC1
GN D
2
P R 13 8
G
4 . 7u _ 25 V _X 5 R _ 08
? ? ? ? ? ? ? switching? ? ? ? ? ?
P Q60
*I R F H 7 9 23
4. 7 u _2 5V _ X 5 R _0 8
CS_ P H2
P Q5 9
I R F H 79 23
D
PC1 8 5
4 .7 u _2 5 V_ X 5 R _ 08
5 VS
csref? ? SWITCHING
,? CARE? ? ~~10 mil
1 0 0_ 1 %_ 04
C
D
S
1 0 _0 6
P C 1 80
CS_ P H1
P R 19 1
1K _ 06
P C4 5
1
P R 18 8
F M 58 2 2
4 . 7 u_ 25 V _ X5 R _ 0 8
V RT T
T TS N S
A GN D
A GN D
P D2 0
C S _P H 2
P R 19 4
1 . 6 K_ 1 %_ 0 4
10
T TS N S 1 1
12
49
P R 19 0
1K _ 06
BST1
P C 13 5
P C 1 86
1 50 p_ 5 0V _ 06
P R 18 9
2. 2 _0 6
36
35
34
33
32
31
30
29
28
27
26
25
P C 1 27
P R 1 93
4. 3 2K _ 1 %_ 04
P C 1 84
1 2p _5 0 V _N P O _0 4
BST 1
DRVH 1
SW 1
SW FB1
P VCC
DRVL 1
P G ND
DRVL 2
SW FB2
SW 2
DRVH 2
BST 2
P R 1 85
5. 1 _ 06
P Q5 8
I R F H 79 32
0 . 1 u_ 50 V _ Y 5V _ 06
P C 18 3
0 . 1 U _1 0 V _X 7R _0 4
RS P
S GN D 2
P C 18 2
1 5 0p _5 0 V _0 6
EN
P W RG D
I MO N
CL KE N#
F B RT N
FB
C O MP
T RDE T #
V A RF R
P Q5 7
I R F H 79 32
G
G
V C OR E
26A
P L1 2
* 0. 3 6 U H _ 12 . 9* 14 *3 . 8
D
P R 1 81
PR1 8 2
P R 18 3
P R 18 4
V R _ ON 1
2
3
4
5
6
7
TR D E T # 8
9
5 VS
P C 1 79
5V S
ADP32 12
SW F B3
PW M 3
OD 3 #
I LI M
C S C O MP
C SS U M
C S REF
LL I N E
RA M P
RT
R PM
IRE F
3K _ 1 %_ 04
5 I MO N
2 0 C LK E N #
PC 18 1
10 00 p _5 0V _ X 7R _ 0 4
RS N
Sheet 35 of 55
Power VCore
PU 9
VCC
PH 1
PH0
DP RS L P
PS I#
VID6
VID 5
VID4
VID3
VID2
VID 1
VID0
3 K _ 1% _0 4
3 , 1 4 D E L A Y _ P W R GD
VCORE
P L1 1
0. 3 6U H _ 10 *1 0* 3. 5
24
23
22
21
20
19
18
17
16
15
14
13
P R 1 87
G
LX 1
37
38
39
40
41
42
43
44
45
46
47
48
P R 18 6
1u _1 6 V _X 5R _0 6
R T3
P C 19 8
1 0 0K _ N T C _ 06 _B
0. 0 1u _ 25 V _X 7 R _ 06
P R 1 42
0 _0 4
S GN D 2
2
R SP
V CC_ S E NS E 5
1 . 1 V S _V T T
???? ?
5 P M_ D P R S L P V R
P R 15 5
0 _0 4
P R 20 0
0 _0 4
P C 1 50
P R 1 50
0 _0 4
*1 00 0 P_ 5 0V _ 04
5 PS I#
R SN
V S S_ S E N S E 5
8
7
6
5
8
7
6
5
5 VS
P R 20 1
P RN4
*1 K _ 8P 4 R _ 04
H_ V ID0
H_ V ID1
H_ V ID2
H_ V ID3
H_ V ID4
H_ V ID5
H_ V ID6
V S 1. 8
1. 1 V S _V T T
* R _ 04
1 K_ 0 4
1 K _0 4
1 K _ 04
*1K _ 0 4
*1 K _0 4
1 K _0 4
* 1K _ 04
P R1 3 1
6 49 _ 1% _0 4
3. 3 V
PR 16 1
PR N 3
0 _ 8P 4 R _ 04
1
8
2
7
3
6
4
5
1
8
2
7
3
6
4
5
1 00 _1 % _0 4
V VID0
V VID1
V VID2
V VID3
V VID4
V VID5
V VID6
P R1 2 0
3 .3 V S
PR N 1
0 _ 8P 4 R _ 04
10 K _0 4
10 0 K_ 0 4
P C 1 42
*0 . 1u _ 50 V _Y 5V _ 06
*1 0K _ 0 4
*1 0 K _0 4
3 .3 V
P R 1 28
P R1 2 4
S
2
V IDIN0
V IDIN1
V IDIN2
V IDIN3
V IDIN4
V IDIN5
V IDIN6
V IDIN7
10
11
12
3
GP I O0
GP I O1
GP I O2
GP I O3
GN D
V IDO
V IDO
V IDO
V IDO
V IDO
V IDO
V IDO
V IDO
U T0
U T1
U T2
U T3
U T4
U T5
U T6
U T7
S DA
S CL
R S TO U T#
S L OT OC C #
A S EL
24
23
22
21
20
19
26
2
13
14
15
17
28
* I T8 2 68 R
1 . 5V _ C T R L1
1 . 5V _ C T R L0
1 . 5V _ C T R L1 3 7
1 . 5V _ C T R L0 3 7
31 V C OR E _ON
S GN D 2
P J1 1
P Q44
MT N 70 0 2Z H S 3
G
4 0 mi l
1
3 VSB
VBAT
16
B - 36 Power VCore
D
4
5
6
7
8
9
25
27
? ? switching
P R 16 4
0 _0 4
0 . 1u _1 0 V _X 7R _0 4
S
1
18
H_ V ID0
H_ V ID1
H_ V ID2
H_ V ID3
H_ V ID4
H_ V ID5
H_ V ID6
1
P J 12
*O P E N -40 m li
P C 1 73
P Q4 5
MT N 7 00 2 ZH S 3
G
P U8
2
_V I D 0
_V I D 1
_V I D 2
_V I D 3
_V I D 4
_V I D 5
_V I D 6
P R 1 52
P R1 4 4
P R 14 0
P R 13 5
P R 1 32
P R 1 29
P R1 2 5
H
H
H
H
H
H
H
*1 K _0 4
*1 K _ 04
* 1K _ 04
1K _ 04
1K _ 0 4
*1 K _0 4
1 K _0 4
5
5
5
5
5
5
5
V R _O N
P R 11 8
D
T RDE T #
P R 20 3
PR N 2
*1K _ 8 P4 R _ 0 4
1
2
3
4
1
2
3
4
P R 2 02
*R _0 4
5 . 1 K _1 %_ 0 4
P R 1 53
P R1 4 5
P R 14 1
P R 13 6
P R 1 33
P R 1 30
P R1 2 6
B.Schematic Diagrams
Re v_3. 0
+
H DR1
S
P R 18 0
1. 9 1K _ 1 %_ 04
G
S GN D 2
P C 13 6
3 . 3V S
P Q 56
* I R F H 7 92 3
S
3 . 3V S
S GN D 2
C S C OM P
CS S UM
CS R E F
C S C OM P
6 80 K _1 % _0 4
1 62 K _ 1% _0 6
4 7 . 5K _ 1% _ 04
80 . 6K _ 1 %_ 04
2
P C 17 7
47 0p _ 50 V _X 7 R _ 04
P Q 55
I R FH 79 2 3
10 0 0p _5 0 V _X 7R _0 4
S
P R 1 79
7 3. 2 K _1 %_ 0 4
1 K _ 04
P C 17 6
D
P C 1 78
15 0 0P _ 50 V _ 04
0. 2 2 u_ 5 0V _ 08
1
P R 1 78
RT 2
1 00 K _N TC _0 6_ B
? ? input
cap
1 6 0K _ 1% _0 4
4 . 7U _2 5V _ 0 8
P R 1 77
D
V IN
RT1 close to first phase
inductor
P C1 2 9
P C 1 75
1 U _6 . 3 V _X 5R _0 4
3 00 K _1 % _0 6
3 00 K _1 % _0 6
P C1 3 4
P R 17 4
* 47 K _0 4
? ? ? ? 0603
P R 1 75
P R 1 76
P C 1 28
Rev _3.0
CS _ P H1
CS _ P H2
P C 1 32
S G ND2
Rev_ 3.0
S MB _ D A T A _D D R 3 8, 9 , 13 , 2 0
S MB _ C L K _D D R 3 8, 9 , 13 , 2 0
P R 13 9
P R 14 3
*1 0K _ 04
*1 0K _ 04
ADDRESS
0: 7:h 37
1: 7'h4 E
3 . 3V
3. 3 V 2, 3 , 1 2. . 1 4, 1 6 , 17 , 19 , 2 2, 2 5, 2 8 , 29 , 36 . . 39
V C OR E 5
1. 1 V S _V T T 3, 5 , 6, 1 2 . 1 4 , 17 . . 20 , 3 6
3. 3 V S 3, 8 . . 1 2, 1 4, 1 6 . 2 4 , 26 . . 34
5V S 1 0, 1 1 , 19 . . 21 , 2 3. . 2 7, 3 2 . 3 4
V I N 1 1, 2 2, 3 4, 3 6 . . 40
Schematic Diagrams
Power 1.1V_VTT, Screw Hole
5V
CO NT ROL 1 .1 VS _V TT
5V
3 . 3V
P R 94
3 .3 V
H_VT TVID1
V IN
A
H_VTTVID1 = LOW, 1.1V
H_VTTVID1 = HIGH,
1.05V
1 0 K _0 4
PD 2
5 . 1 _ 06
P Q2 6
I R F 7 8 3 2Z T R P B F
P Q 27
I R F 78 3 2 Z TR P B F
P C 1 13
P C 11 2
P C 10 7
0 . 1 u_ 1 6 V _Y 5 V _0 4
Sheet 36 of 55
Power 1.1V_VTT,
Screw Hole
D
28 . 7 K _ 1% _ 0 6
0. 1u _ 50 V _ Y 5 V _ 06
0 . 1 u _5 0 V _ Y 5V _0 6
P C1 1 1
A
P C 1 10
R3B
P R8 3
P C 1 08
0 . 1 u _1 6 V _ Y 5 V _0 4
F M5 8 2 2
1u _ 1 0V _ 0 6
1 .1 V S _ V T T
2
*OP E N -1 2 mm
P C B F o o t p rin t = J U MP -12 M M
+
4
P C1 0 1
P J9
1
0 . 1 u_ 1 6 V _ Y 5V _ 0 4
P D1 1
4
4
17
1.1VS_VTT
V TT 1 . 1 V S
23A
0 . 1 u _1 6 V _ Y 5V _0 4
C
3
0 . 1 u_ 5 0 V _Y 5V _ 0 6
P C 2 4 P C 2 5 P C 23
15 u _2 5 V _ 6 . 3* 4. 4 _ C
22 0 u_ 4 V _ D 2 _ D
P R 1 01
5
6
7
8
15
16
GN D
PAD
PL 3
0 . 56 U H _ 10 * 10 *4 . 1
2
2
3
1
8
RT N
D0
D L
P R 84
1 0 0K _ 0 4
P Q2 4
PC1 0 4
G
D
2
S
MT N 7 0 0 2Z H S 3
0. 1 u _ 16 V _ Y 5 V _ 0 4
PJ 8
P Q 23
M TN 7 00 2 Z H S 3
P C9 7
P C 10 0
R
1
P R8 6
2 0 p_ 5 0 V _N P O_ 0 4
3 . 2 4 K _ 1% _ 0 4
47 0 p _5 0 V _ X7 R _0 4
R 3A
PR 8 1
1 7 . 4 K _1 % _ 04
* OP E N -4 0m i l
S
1
G
14
V CC
FB
1 . 1 V S _ V T T_ E N _R
1 0K _0 4
DH
I LI M
BST
VO UT
P Q 25
* I R F 7 4 13 Z P B F
1
2 2 0 0p _ 50 V _ X 7 R _ 0 6
P R 93
PG D
P C 1 02
0 . 1 u_ 1 0 V _X 7 R _ 0 4
ON
5V
9
G1
13
10
F B
P C9 8
0 . 1 u_ 5 0V _Y 5V _0 6
5
2 0K _ 0 4
D1
P R 87
6
3, 1 4 1 . 1V S _V T T _ P W R G D
11
LX
PQ 2 9
I R F 7 41 3 Z P B F
+
R
2
P R8 2
8 . 2 K _ 1 %_ 0 4
PR 8 8
0 _ 04
PR 8 9
* 0_ 0 4
14
H _ O2
1.05VS=0.75(1+(R1/R2))
1.1VS=0.75(1+(R1/R2)+(R1/(R3A+R3B)))
S U S B # 1 4 , 20 , 2 8 , 31 , 3 4
Re v_ 3.0
? ? ? /? ?
H _ O1
1. 1 V S _ V T T _E N
H _ D -M3
*6 -34 -M 56 A S -0 1 1 -1
PTH?
H2
C 1 11 D 11 1 N
H1
C 1 1 1 D 1 11 N
H 3
C 11 1 D 1 1 1N
H4
C 1 11 D 11 1 N
H_ NE W 1
H_ T 1
* 6 -36 -1 2 18 1 -2 0E -1
H _N E W 2
H _T 2
*6 -3 6-1 2 1 81 -2 0 E -1
H _ C -B 1
H _ C -B 2
H _ C -B 3
H _C -B 4
H_ E 3
H _ E2
H _E 1
H_ E4
? ? J_MINI_HDMI_IN
For 34 NEW CARD
? ?
? ?
TO P
H _C 1
6 -3 4 -D 9 0T 0 -0 10 -1
H _ C5
6-3 4 -D 9 0 T0 -0 1 0- 1
H _F 1
6 -34 -M 72 S S -0 1 0-1
H _ D -M 1
6 -3 4-M 5 6A S -0 1 1 -1
H _ D -M 2
6 -3 4 -M5 6 A S -01 1 -1
H _ G -H 2
6-3 4 -D 9 0 T0 -0 1 0- 1
H _A 4
6 -34 -D 90 T 0- 01 0 -1
H_ C 3
H_ C4
6 -3 4-D 9 0T 0 -0 10 -1 6 -34 -D 90 T 0 -01 0 -1
BO T
H_ NE W 4
H_ C2
6-3 4 -D 9 0 T 0-0 1 0 -1
H _ B -C 1
6 -3 4- M5 9E S -01 0
6 -34 -M 56 A S -0 1 1-1
H _ B -C 2
6 -3 4 -M5 9 E S -0 10
H _B - C 3
6- 34 -M5 9 E S -0 1 0
H _ B -C 4
6 -3 4-M 59 E S -0 1 0
P C B F o o t pri n t = H 7 _ 0D 3_ 7
NON PTH?
2
3
4
5
1
H _A 1 1
9
8
7
6
2
3
4
5
1
H _ A7
9
8
7
6
2
3
4
5
1
? ? ?
H_ A 9
9
8
7
6
2
3
4
5
1
H_ A 1 2
9
8
7
6
2
3
4
5
1
H _A 6
9
8
7
6
2
3
4
5
M7
C -M A R K
M8
C -MA R K
1
S5
S M D 8 0 X8 0
S2
S M D 8 0X 8 0
S3
S MD 80 X 8 0
S 4
S M D 8 0X 8 0
1
M5
C -M A R K
2
3
4
5
1
M6
C -MA R K
H _ A 10
9
8
7
6
1
M2
C -M A R K
1
1
M1
C -MA R K
1
M3
C -MA R K
2
3
4
5
H_ A 3
9
8
7
6
2
3
4
5
1
H_ A 8
9
8
7
6
2
3
4
5
1
9
8
7
6
6-38-M52N0-010
? ? ? ? ?
M4
C -M A R K
H _A 2
9
8
7
6
1
1
H_ A 1
9
8
7
6
1
1
1
H_ A 5
2
3
4
5
5 V T T 1. 1 V S
3, 5 , 6 , 1 2. . 1 4 , 1 7. . 20 , 3 5 1. 1 V S _ V T T
2, 3, 1 2 . . 1 4, 1 6 , 1 7, 1 9 , 2 2, 2 5 , 2 8, 2 9 , 3 5, 3 7 . . 3 9 3. 3 V
11 , 1 9 , 25 , 3 7 . . 3 9 5 V
1 1, 2 2 , 3 4, 3 5 , 3 7. . 4 0 V I N
Power 1.1V_VTT, Screw Hole B - 37
B.Schematic Diagrams
Re v_ 3. 0
EN
7
12
G0
1 0 0K _0 4
1 0 K _0 4
P U7
S C 4 75 A
2
3
1
P C 10 5
1 . 1V S _V T T _ E N _ R
PR 9 0
3 .3 V
4
2
3
1
4
Re v_3 .0
PR 9 1
4 . 7 u_ 2 5 V _X 5 R _0 8
5
6
7
8
S
5V
5
6
7
8
P R 96
1 0 0K _ 0 4
P C 2 0 P C 2 1 P C 2 2 P C 19
*1 u _6 . 3 V _ X 5R _0 4
M TN 70 0 2 Z H S 3
5
6
7
8
C
G
PQ 3 1
2 N3 9 0 4
E
B
4. 7 u _ 25 V _ X 5 R _ 0 8
PC1 0 6
P Q 32
10 K _ 0 4
4 . 7u _ 2 5V _ X 5 R _ 0 8
1 00 K _ 0 4
*1 0 0 K _0 4
P R9 7
5 H _V T T V I D 1
2
3
1
P R 98
+ 1.1V
F M 05 4 0- N
C
L
PR 9 5
5 . 62 K _ 1 %_ 0 4
4 . 7 u _2 5 V _ X 5R _ 08
P R1 0 5
+ 1.05V
D
H
Schematic Diagrams
Power 1.5V/0.75VS
5V
3 .3 V
A
V IN
Vout = 1.5V ( 1 + Ra / Rb )
PR 2 6
P R2 8
1 . 5 M_ 0 4
1 0_ 0 6
P R 27
* 10 0 p _ 50 V _ N P O _ 04
Ra
P R2 3
P C 43
2 K _ 1 % _0 4
1 u _1 0 V _ 06
Z3 801
3
Z3 802
2
S C 4 8 6_ P I N 6
Z3 804
6
8
Z3 805
9
V D D QS
P R2 1
F M 0 54 0 -N
PG D
1 0 0 K _ 04
7
D D R 1 . 5 V _P W R G D 1 4
V IN
PC 4 0
1 u _ 10 V _ 0 6
T ON
Z 38 1 3
Z3 807
P C 35
VTT_MEM
1 u_ 1 0 V _ 06
P C3 8
P R1 6
*1 5 mi l _ sh o rt
PJ 3
2
1
D L
1 00 0 p _5 0 V _ X 7R _0 4
Z3 809 14
15
1.5A
12
13
*O P E N _ 2 m m
P C B F oo t p ri n t = J U MP -2 MM
P R 13
P C2 6
PC 2 7
PC2 8
*2 0 K _ 1 %_ 0 6
*1 0 u_ 6 . 3 V _X 5 R _ 0 6
1 0 u_ 6 . 3 V _ X5 R _0 6
1 0u _ 6 . 3V _X 5 R _ 0 6
1
11
1.5V
1
2
3
1 u_ 1 0 V _ 06
*0 . 0 6 8u _ 5 0V _0 6
P R 1 71
2 2 _ 04
IL IM
LX
4
V TT _ ME M
V CC A
P C 41
VSSA
I R F 74 1 3 Z P B F
* 32 m i _l s h ort
V T TS
21 Z 3 8 16
P R1 5
19 Z 3 8 18
PQ 3 3
VSSA
VTT
VTT
PL 4
2 . 5 U H _6 . 8 *7 . 3 *3 . 5
1
2
3 K _1 % _ 06
22 Z 3 8 17
4
V DD P 1
20
5V
P Q 34
4
I R F 7 8 32 Z T R P B F
E N/P S V
V T TE N
PD 1 2
1 u _ 10 V _ 0 6
P G ND 2
P G ND 1
P G ND 1
P G ND 2
13A
P J1 0
1
2
P C 1 14
+
+
25
18
16
17
*2 2 0u _ 4 V _ D 2 _ D
PR 1 7
PC3 1
P C2 9
*1 5 m li _ sh o rt
VSSA
S C4 8 6
D
VDD Q
2
PC 4 2
PC 4 4
* 10 u _ 6. 3 V _ X 5 R _ 0 6
1 u _ 25 V _ X 7R _ 08
G
PQ 5 2
M TN 7 00 2 Z H S 3
S
S US B
Very Close to SC486(PU7)
P R2 5
4 7K _0 4
1. 5 V E N
5V
D
5V
S C 48 6 _ P I N 6
PC3 7
P Q6
Z38 19
1
PQ 5
MT N 7 0 0 2Z H S 3
P R3 1
PR 3 0
*3 7 . 4K _1 % _ 04
* 49 . 9 K _ 1 %_ 0 4
P J4
*O P E N -4 0 m li
P R1 7 2
P R 17 3
*1 0 K _ 04
*1 0 K _ 0 4
D
MT N 7 0 02 Z H S 3
2
G
S
1 4, 31 , 3 4 S U S C #
0 . 1u _ 1 6V _Y 5V _0 4
G
S
1 00 K _ 0 4
D
P R2 4
10 0 K _ 04
V TT E N
S
P Q5 3
* 0_ 0 4
* 0_ 0 4
P R 11 3
P R 11 2
* 0_ 0 4
* 0_ 0 4
PQ 7
G
G
*M T N 7 00 2 Z H S 3
G
MT N 7 0 0 2Z H S 3
* MT N 7 0 0 2Z H S 3
D
PC 3 2
0 . 1 u _1 6 V _ Y 5 V _ 0 4
VS SA
P Q5 4
S
SU SB
P R 11 0
P R 10 9
S
D
3 5 1 . 5V _C T R L 1
1 6 P C H _G P I O1 0
P Q4
3 5 1 . 5V _C T R L 0
1 6 P C H _ GP I O 9
G
*M T N 7 0 02 Z H S 3
1 .5 V_CTRL1
1
1
0
0
B - 38 Power 1.5V/0.75VS
D
*M TN 7 00 2 Z H S 3
D
*1 0 0 K _ 04
S3 Pow er Re duc tion whi te pa per
34 , 3 8 S U S B
P Q8
G
P R 17 0
S
5
P R1 4
S
5V
3 1 . 5 S _C P U _ P W R GD
1. 5_ CTRL0 Volt a ge
1
0
1
0
1.5 V
1. 56 05 V
1. 58 05 V
1. 64 05 V
1 .5 V
* OP E N _ 6m m
P C B F o o t p r ni t = J U M P -6 MM
F M5 8 22
I R F 7 8 32 Z T R P B F
PC 3 0
V DD P 2
V DD P 2
VDD Q
P C1 1 8
A
P C3 6
5
0 . 1 u _1 0 V _ X 7R _0 4
Z 3 8 15
4
23 Z 3 8 14
P Q3 5
C
Z 3 8 08
4 . 7 u _2 5 V _ X 5R _ 08
PC 3 4
5
6
7
8
P R1 9
D H
Z3 806 10
4 . 7 u _2 5 V _ X5 R _0 8
*1 5 u_ 2 5 V _6 . 3 *4 . 4 _ C
* 32 m i _l s h ort
P C3 3
*0 . 1 u_ 1 6 V _ 04
P C 1 15
5
6
7
8
* 1 0K _ 1 % _ 04
24 Z 3 8 12
1
2
3
Rb
P R2 9
1 0_ 0 6
B ST
C O MP
5
6
7
8
Sheet 37 of 55
Power 1.5V/0.75VS
10 _ 0 4
P R2 0
FB
RE F
1
2
3
P R1 8
P C 1 16
5 60 u _ 2. 5 V _ 6 . 6 *6 . 6 *5 . 9
B.Schematic Diagrams
P C1 1 7
+
P R2 2
0 . 1u _ 1 6V _Y 5 V _ 0 4
PC 3 9
1 0 _0 6
PD 3
C
P U3
0 . 01 u _ 16 V _ X 7 R _ 0 4
VD DQ
V DDQ 3 4
1 . 5 V 3 , 8 , 9 , 19
3 . 3 V 2 , 3 , 1 2. . 1 4 , 1 6 , 17 , 1 9 , 22 , 2 5 , 2 8, 2 9 , 3 5, 36 , 3 8 , 39
5 V 1 1 , 1 9, 25 , 3 6 , 38 , 3 9
V I N 1 1 , 22 , 3 4 . . 3 6, 3 8 . . 4 0
V TT _ ME M 8 , 9
Schematic Diagrams
Power 1.8VS/1.5VS
5V
A
VIN
PD1
10K_04
EN1.8VS
10K_1%_04
FM0540-N
PC96
15
PGD
PR2
PC3
0_04
20p_50V_NPO_04
Ra
PC1
GND
RTN
DL
PAD
PL2
2.5UH_6.5*6. 9*3
1
2
1.8VS
VS1.8
+ PC95
1.8VS
PJ2
3A
1
PC4
2
*OPEN-2mm
PCB Footprint = JUMP- 2MM
560u_2.5V_6.6*6.6*5.9
0.1u_16V_Y5V_04
PQ22B
AO4932
3
4
17
5
6
N.C
N.C
VCC 3
7
8
FB
1
2
*15u_25V_6.3*4.4_C
PC10
PR6
Sheet 38 of 55
Power 1.8VS/1.5VS
1u_6. 3V_Y5V_04
14K_1%_04
PR4
Rb
0.01u_50V_X7R_04
10K_1%_04
Vout = 0.75V ( 1 + Ra / Rb )
? ? ? PIN6?
5V
VS1. 8
1.5VS
PC12
2A
3. 3V
PU2
10K_04
1.5VS_PWRGD
14 1.5VS_PWRGD
PR11
PR8
10K_04
EN1.5VS
5V
5
9
7
VIN
VIN
POK
8
EN
D
1
PQ2
MTN7002ZHS3
G
S
34,37 SUSB
PC15
1u_10V_06
VCNTL
VOUT
VOUT
GND
VFB
6
0.1u_16V_Y5V_04
10u_6.3V_X5R_06
PR9
0.015u_10V_X7R_04
(15nF~48nF)
2
*OPEN-2mm
PCBFootprint = JUMP-2MM
Ra 1K_1%_04
PC14
OZ 803 3
PC5
1
3
1u_6.3V_Y5V_04
PC9
PJ1
4
2
1. 5VS
VS1.5
1.5 A
PC6
PC7
PC13
*10u_6. 3V_X5R_06
10u_6.3V_X5R_06
0. 1u_16V_Y5V_04
PR10
Rb
1.15K_1%_04
Vout = 0.8V ( 1 + Ra / Rb )
VIN 11, 22, 34..37,39,40
1.5VS 18,20,28
1.8VS 6,16,18
3.3V 2,3,12..14,16,17,19,22, 25, 28,29,35..37,39
5V 11, 19, 25,36,37,39
Power 1.8VS/1.5VS B - 39
B.Schematic Diagrams
9
0.1u_25V_X7R_06
LX
BST
10 VOUT
PC8
5
6
11
5V
EN
PU1
SC412A
PC94
4
10K_04
DH 16
12
PR1
N.C
0.1u_16V_Y5V_04
13
MTN7002ZHS3
8
N.C 14
S
PC2
I LIM
G
34, 37 SUSB
1.8VS_PWRGD
14 1.8VS_PWRGD
PQ1
+
4.7u_25V_X5R_08
PQ22A
AO4932
7
D
C
PR5
1
2
PR3
5V
Schematic Diagrams
Power 3.3V/5V
V IN1
P R3 7
P C5 4
2 . 2 u _ 6 . 3V _Y 5 V _ 0 6
10_06
A
Z 3 50 4
P C1 6 2
1 00 0 p _ 50 V _ X 7 R _ 0 4
P C 75
0. 0 1 u _ 5 0V _X 7 R _0 4
Z 35 1 3
LG A T E 1
P R 16 5
C
A
P D6
A
1 0 _0 6
4 2 2K _1 % _ 0 6
S G ND 4
C
S Y S 1 0V
F M 05 4 0 -N
P D 1 0 F M0 5 4 0- N
C
6- 13 - 42 23 1- 28 B
PR 1 6 7
SY S5 V
F M0 5 4 0- N
P D 17
INT V C C2
Z 3 50 5
P C9 0
22 0 0 p _5 0 V _ X 7 R _ 0 4
Z 3 50 6
P C 76
0. 0 1 u _ 5 0V _X 7 R _0 4
Z 35 1 4
PC 8 9
5
4
N C
0 . 1 u _ 50 V _ Y 5 V _0 6
IN T V C C2
1 1 3 K _ 1 %_ 0 4
P D8
F M0 5 4 0- N
C
S Y S 1 5V
P C8 2
22 0 0 p _5 0 V _ X 7 R _ 0 4
1 5 u _ 2 5V _6 . 3 * 4. 4 _ C
V DD 5
PQ 4 6
I R F 7 4 1 3Z P B F
4
PL 1 0
2 . 5 U H _ 10 * 1 0* 5
1
2
L G ATE1
4
SY S5 V
Z 3 5 11
PR 6 3
6. 8K _1 % _ 0 4
Z 3 5 12
PR 5 8
*1 0 0 K _ 04
P R1 6 8
3 0p _ 5 0 V _ N P O _ 0 4
9 1K _1 % _ 0 6
P C5 5
P R3 9
PC 7 3
1u _ 1 0 V _ 06
1 u _1 0 V _ 0 6
*3 0 p _5 0 V _ N P O_ 0 4
1 0K _1 % _ 0 4
2
*O P E N -5 m m
Ra
P C1 6 3
1
4
P Q5 0
I R F 7 8 32 Z T R P B F
P C6 6
PJ 1 4
11A
C
5
6
7
8
1 0 Z 35 1 0
P D1 8
F M5 8 2 2
P C1 7 2
A
PR 5 7
F M0 5 4 0- N
5
6
7
8
Z 35 0 9
A
P D7
P C1 6 8
+
1
2
3
Z 35 0 8
C
A
1
2
3
P G ND
DL
PC 6 9
1u _ 2 5 V _ X 7R _ 0 8
8
9
1
2
3
15
V DD P
* 0 . 1 u_ 2 5 V _ X 7 R _ 0 6
PR1 6 9
LX
7
11
P C6 7
I LI M
DH
R PSV
PR 4 0
BST
E N/P S V
13 7 K _ 1 % _ 04
PC 6 1
1 0 K_ 0 4
Sheet 39 of 55
Power 3.3V/5V
P C 71
1 u _ 10 V _ 0 6
16
V L DO
SC418
A GN D
Z 35 0 7
6
V IN
V IN
R T ON
13
17
1 0 00 p _ 5 0V _X 7R _ 0 4
P Q 49
* I R F 78 3 2 Z T R P B F
+ P C 17 1
2 2 0u _ 6 . 3 V _ 6 . 3 *6 _ B
Rb
+ PC 1 6 4
*1 5 0 u _ 6. 3 V _ V _ C
0 . 1u _ 1 6 V _ Y 5 V _ 0 4
PR 5 2
S GN D 4
S GN D 4
S G ND 4
S GN D 4
SY S5 V
1 0 0 K _ 04
S G N D4
Vout = 0.5V ( 1 + Ra / Rb )
IN T V C C2
A
P R1 6 6
*2 8 m li _ N P _ 06
V IN
PD 9
Re v _3 .0
PR 6 8
* 2 8m i l _ N P _ 0 6
S GN D 4
F M 05 4 0 -N
DH
N.C
16
15
14
V OU T
0 . 0 1 u _5 0 V _ X 7 R _ 0 4
2 . 9 4 K _ 1% _ 0 4
GN D
RT N
N .C
D L
N .C
3
Z 3 5 21
4
Z 3 5 22
1
PAD
S Y S 3V
P L9
2 . 5 U H _ 6 . 8 *7 . 3 *3 . 5
2
8A
P J1 3
1
V D D3
2
*O P E N -5 m m
P D 19
4
17
P C1 6 9
+
4
F M5 8 2 2
*1 5 0 u_ 6 . 3 V _ V _ C
P C1 6 7
+
2 2 0 u _ 6. 3 V _ 6 . 3 *6 _ B
P C1 6 5
PC 9 1
0 . 1u _ 1 6 V _ Y 5 V _ 0 4
5
PC 7 8
6
Rb
PR 6 4
Z 3 5 20
VC C
F B
7
PC 7 9
Z 3 5 19
2
A
9
BS T
0 . 1 u _5 0 V _ Y 5V _0 6
0 . 1 u _ 50 V _ Y 5 V _ 06
1
5
6
7
8
10
Z3517
P GD
LX
1
2
3
Z3516
E N
N .C
13
SY S5 V
12
11
10 0 K _ 0 4
IL IM
Z3515
P R6 6
P Q4 7
IRF 7 4 1 3 Z P B F
4
PC 9 2
C
Z 3 52 5
Z 3 5 18
PU 6
S C 4 12 A
5
6
7
8
* 20 m i l _N P _ 0 4
P C1 6 6
+
* 1 5u _ 2 5 V _ 6 . 3* 4 . 4 _C
1
2
3
PR 7 0
1 0 . 2 K _ 1% _ 0 6
P C 1 70
5
6
7
8
PR 6 5
3 0 p _ 5 0V _ N P O _0 4
6 . 8 K _ 1 % _0 4
1
2
3
P C7 7
1 0 K_ 0 4
P R7 7
C
PR 6 9
Ra
8
1 u _1 0 V _ 0 6
P Q4 8
I R F 78 3 2 Z T R P B F
0 . 0 1 u _5 0 V _ X 7 R _ 0 4
P Q5 1
*I R F 7 8 32 Z T R P B F
Vout = 0.75V ( 1 + Ra / Rb )
V DD 5
3A
S YS1 5 V
5V
3A
P R3 2
3A
P Q9
IRF 8 7 0 7 P BF
8
7
3
6
2
5
1
1M _ 0 4
4
1 M _0 4
V D D3
PQ 1 9
M TN 7 0 02 Z H S 3
G
1 0 0 0 p_ 5 0 V _ X 7R _ 0 4
D
Z 35 2 4
D
Z 3 5 23
PC 9 3
3 .3 V
3A
4
PR 7 9
PQ 1 3
I R F 8 7 07 P B F
8
7
3
6
2
5
1
P C5 1
P Q2 0
MT N 70 0 2 Z H S 3
G
22 0 0 p _5 0 V _ X 7 R _ 0 4
S
SY S1 5 V
S
B.Schematic Diagrams
18
14
19
Z 3 50 1
P G OO D
Z3503
V O UT
V DD A
1
2
3
E NL
12
S G ND 4
Z3502
20
F BL
21
S G ND 4
FB
2 0 K _ 1 % _0 4
PU4
PAD
1 0 K _ 04
75 K _ 0 4
5
6
7
8
PR 4 1
PC5 3
1 u _ 25 V _ X 7 R _ 08
PR4 2
P R 53
D D_ O N# 3 4
B - 40 Power 3.3V/5V
V IN1 3 4
S Y S 1 5 V 2 2 ,3 4
V D D 3 1 2, 2 8 , 3 1 . . 3 4 , 4 0
V D D 5 3 2, 3 4
S Y S 5 V 40
V I N 1 1 , 2 2 , 3 4 . . 3 8, 4 0
3 . 3 V 2, 3 , 1 2 . . 1 4 , 1 6 , 17 , 1 9 , 2 2 , 2 5, 28 , 2 9 , 3 5 . . 3 8
5 V 11 , 1 9 , 2 5 , 3 6. . 38
Schematic Diagrams
Power Charger, DC-In
VA
J _ AC
VA+ +
1
2
3
4
P R8 5
B AT
0 _ 20
VB
J _ BATT
PC 1 8
2 MJ -3 4 3 2-0 0 6
P C1 6
0 . 1 u _5 0 V _ Y 5 V _ 0 6
P C1 7
0 . 1 u _ 50 V _ Y 5V _0 6
P C 10 3
0. 1 u _ 5 0V _Y 5 V _ 06
PC 9 9
4 . 7 u_ 2 5 V _ X5 R _0 8
1
2
3
4
5
6
7
8
P R 1 02
4 . 7 u _2 5 V _ X 5R _ 08
P R3 6
P R3 8
P R3 5
3 1 , 3 3 S MC _B A T 1
3 1 , 3 3 S MD _B A T 1
31 B A T1 _ D E T
1 0 K_ 0 6
1 0_ 0 4
1 0_ 0 4
1 00 _ 0 4
Z 36 3 2
Z 36 3 3
Z 36 3 4
PC5 0
P C 49
PC 4 8
PC 6 5
3 0p _ 5 0V _N P O _0 4
3 0p _ 5 0 V _ N P O _0 4
3 0 p_ 5 0 V _ N P O _ 04
0 . 1 u _5 0 V _ Y 5 V _ 0 6
P C5 8
EMI
0. 1 u _ 5 0V _ Y 5 V _0 6
G ND 1
GN D
G ND 2
GN D
C 1 4 4G 4 -10 8 0 1 -L
Charg e Cu rre nt 3.0A
P R6 2
0_04
Charg e Vo ltag e 1 6.8V
Z 36 2 7
4
VA
VI N
4
R ev _3 .0
P Q 14 A
A O4 9 3 2
2
1
P R9 2
0 . 0 1_ 1 % _ 32
7
1
2
3
PL 1
10 U H _ 6 . 8 *7 . 3 *3 . 5
1
2
P Q 14 B
A O4 9 3 2
P Q1 0
P 2 00 3 E V G
5
6
7
8
To ta l Po we r 200W
BAT
E
PQ 1 2
D TA 11 4 E U A
C
Re v_ 3. 0
Z 3 62 6
0_04
4
PC 8 6
4
10 0 0 p_ 5 0 V _ X 7R _ 04
Z 3 60 1
PC 7 4
6 . 0 4 K _ 1% _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
+
G
Sheet 40 of 55
Power Charger,
DC-In
SY S5 V
S
+
10 _ 0 6
3
PR 5 0
B A T _ V O LT 3 1
PR 6 1
P Q1 7
M T N 7 0 0 2Z H S 3
P C7 0
* 15 u _ 25 V _ 6 X 4 . 5
P C6 0
1 5 u _2 5 V _ 6 . 3 *4 . 4 _C
5
6
8
P R7 3
Z 36 2 2
Z 3 62 5
P C8 0
0 . 1u _ 5 0 V _ Y 5V _0 6
1 0 K _ 1% _ 0 4
PC 8 1
+
P C 52
P R 1 00
0 . 1 u _ 50 V _ Y 5 V _ 0 6
PQ 2 8
P 2 00 3 E V G
8
7
3
6
2
5
1
1 5 u_ 2 5 V _ 6. 3* 4 . 4_ C
4
PR 9 9
1 3 0K _1 % _ 0 4
P R 60
3 0 K _1 % _ 0 4
Z 3 6 29
Z 3 6 38
PR 4 8
0 . 0 2 _1 % _ 3 2
D
V A
4
P R1 2
0 . 0 1_ 1 % _ 32
PQ 3
P 2 00 3 E V G
8
7
3
6
2
5
1
P Q1 1
P 2 00 3 E V G
5
6
7
8
PC 6 8
0 . 1 u_ 5 0 V _ Y 5 V _ 0 6
V DD 3
V DD 3
P R 34
P R 33
0 _0 4
0 _0 4
1
2
3
4
5
6
7
8
Z 3 60 8
P R8 0
1 0K _ 0 4
1 M_ 0 4
Z3630
B
G
P C8 3
V IN
C TL1
GN D
V RE F
R T
CS
AD J 3
B ATT
S GN D
24
23
22
21
20
19
18
17
33
P C8 5
0 . 1 u _5 0 V _ Y 5 V _ 0 6
A C _ I N # 14 , 3 1
S G ND 5
CT L 1
Z3624
Z3635
Z3636
Z3637
P R7 2
0 _0 4
PR 5 9
SY S5 V
4 9 . 9 K _ 1% _ 0 4
PC 8 7
P R7 5
P C8 8
SYS5 V
PR 4 3
1K _1 % _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
P R6 7
1 0 K _ 1% _ 0 4
Z3615
3 9 . 2 K _ 1 %_ 0 4
PR 7 6
0 . 1 u _ 16 V _ Y 5V _0 4
1 0 0 K _0 4
Z 3 61 6
PR 5 6
P R7 4
PC 8 4
S GN D 5
S G ND 5
S G ND 5
CT L 1
1 K _ 1 % _0 4
10 0 K _ 0 4
1
D
PR 5 5
S GN D 5
G
2 2 K _ 1 %_ 0 4
PQ 1 6
M TN 7 0 02 Z H S 3
PJ 5
31 C H G _ E N
G
P Q1 5
MT N 7 0 0 2Z H S 3
2
P R4 4
22 K _ 1 % _ 04
S
Z 36 3 1
S
P C 64
1 00 0 p _ 50 V _ X 7 R _ 0 4
Z3639
Z 3 6 14
0. 0 1 u _ 16 V _ X 7 R _ 0 4
S GN D 5
Z 3 61 3
1 0 K _ 1 % _0 4
Z 36 2 8
10 0 0 p_ 5 0 V _ X 7R _ 04
PC 6 3
*C _5 0 V _ 0 4
Z 3 6 11
Z 36 1 2
P C5 9
Z 3 6 10
P R4 5
P Q2 1
MT N 70 0 2 Z H S 3
E
S
TRERMAL PAD
V A
31
D
A C_ IN
C
A
UD Z 1 6 B
32
31
30
29
28
27
26
25
VC C
-I N C 1
+ IN C1
A C IN
A C OK
-I N E 3
AD J 1
C OM P 1
M B 3 9 A 13 2
P C 62
1 0 0 p _5 0 V _ N P O_ 0 4
Z3609
P R7 8
D
10 K _ 1 % _0 4
C
* 0 . 1u _ 1 6 V _ Y 5 V _ 0 4
S G ND 5
3 . 8 3 K _ 1 %_ 0 4
VA
C TL2
CB
O U T -1
LX
VB
O U T -2
P GN D
C EL L S
PC 5 7
Z 36 1 7
Z 3 6 18
Z 36 1 9
Z3620
Z 3 62 1
V A
Z 3 60 2
Z 3 60 3
Z 3 60 4
Z 3 60 5
Z 3 60 6
Z 3 60 7
P R4 7
0_04
P D5
PU 5
P R4 6
PR 5 4
PQ 1 8
D TC 1 14 E U A
*0 . 1 u _ 50 V _ Y 5 V _ 0 6
1 0 0K _0 4
PC 5 6
P R 10 4
*0 . 1 u _ 50 V _ Y 5 V _ 0 6
C
P C7 2
1 u _ 25 V _ X 7 R _ 0 8
-I N E 1
OU T C 1
O UT C 2
+ INC 2
-I N C 2
AD J 2
CO M P 2
C OM P 3
2 0 0K _0 4
PD 4
F M 0 54 0 -N
A
9
10
11
12
13
14
15
16
P R 10 3
* OP E N -1 m m
S GN D 5
3 1 TO T A L _C U R
3 1 C H G_ C U R S E N
0.5V/1A
PR 4 9
0 _0 4
0.5V/1A
PR 5 1
0 _0 4
P R7 1
0 _ 06
S GN D 5
34
1 1 , 2 2, 3 4 . . 3 9
12 , 2 8 , 3 1 . . 3 4, 3 9
39
2 , 3 , 1 2. . 1 4 , 1 6 , 1 7, 1 9 , 2 2 , 25 , 2 8 , 2 9 , 35 . . 3 9
VA
V IN
V D D3
SY S5 V
3 .3 V
Power Charger, DC-In B - 41
B.Schematic Diagrams
1
2
3
B
PQ 3 0
P 2 00 3 E V G
8
7
3
6
2
5
1
Schematic Diagrams
Single HDD Board
SINGAL SATA HDD
IR10
IR12
IU1
W/
Re-drive
W/O Re-drive
IR11
IR13
IRN1
IRN2
0.01U
V
X
IR1
IR7
X
0 ohm
IC12
IC14
IR6
D1
0
CH 0 & CH 1 -> 0 d B
1
0
CH 0 -> 5 d B CH 1 -> 0 d B
0
1
CH 0 -> 0 d B CH 1 -> 5 d B
1
1
CH 0 -> 5 d B CH 1 -> 5 d B
V
V
V
Function
D0
0
IC13
X
X
IJ _MB
I 5VS
ISATA_R XN 0
ISATA_R XP0
1
3
5
7
9
I3 .3 VS
D02-1
I3 .3 VS
SPNZ- 10 S2B- 01 5- 1
Note:
D02-1
6
10
16
20
2
4
6
8
10
Closed TO IU1
IR 11
IR 12
I SATA_R XN 0
I SATA_R XP0
IH _J 1
9
8
7
6
1
2
3
4
5
TY PE-J
1
IR 13
I3 .3 VS
I _G ND
I_ GN D
4
5
RX_0 P
RX_0 N
TX_0 P
TX_ 0N
HOST
D EV IC E
TX_1 N
TX_1 P
R X_ 1N
RX_1 P
0. 01 U_ 16 V_X7R _0 4
9
8
7
6
TY PE-J
I _G ND
1
2
D1
D0
IH _J 2
2
3
4
5
0. 01 U_ 16 V_X7R _0 4
0. 01 U_ 16 V_X7R _0 4
IZ0 3
IZ0 4
IR 6
IR 7
4. 7K_ 04
4. 7K_ 04
IR 8
IR 9
*4. 7K_ 04
*4. 7K_ 04
I R1
4 .7 K_04
D02-1
15
14
I SATA_ TXP0_ R
I SATA_ TXN0 _R
IR N1
1
2
12
11
I SATA_ RXN0 _R
I SATA_ RXP0_ R
IR N2
1
2
*0_ 4P2 R_ 04
4
3
IZ0 1
IZ0 2
*0_ 4P2 R_ 04
4
3
IZ0 3
IZ0 4
G ND
G ND
G ND
G ND
G ND
I SATA_TXP0
I SATA_TXN 0
0. 01 U_ 16 V_X7R _0 4
IZ0 1
IZ0 2
I U1
SN 75 LVC P41 2
7
EN
3
13
17
18
19
IR 10
VD D
VD D
VD D
VD D
I_ GN D
T- PAD
I_ GN D
21
Sheet 41 of 55
Single HDD Board
8
9
B.Schematic Diagrams
I SATA_TXP0
I SATA_TXN 0
Layout note:
Close to IJ_SATA
I _G ND
I_ GN D
Layout Note:
I J_ SATA
Layout note:
S1
S2
S3
S4
S5
S6
S7
ISATA_TXP0 _C
ISATA_TXN 0_ C
IC 11
IC 10
0. 01 u_1 6V_ X7 R_ 04
0. 01 u_1 6V_ X7 R_ 04
I SATA_ TXP0_ R
I SATA_ TXN0 _R
ISATA_R XN 0_ C
ISATA_R XP0 _C
IC 9
IC 8
0. 01 u_1 6V_ X7 R_ 04
0. 01 u_1 6V_ X7 R_ 04
I SATA_ RXN0 _R
I SATA_ RXP0_ R
If IU1 need to mount.
The IR10 and IR11 and IR12 and IR13
must change to 0.01U_16V_X7R_04
Closed TO IU1
I3 .3 VS
I C1 2
IC 13
IC 14
0 .0 1u _1 6V_ X7 R_ 04
0. 1u _1 6V_ Y5 V_0 4
1u _6 .3 V_X5R _0 4
I 3. 3VS
1.5A
P1
P2
P3
P4
P5
P6
P7
P8
P9
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
I _G ND
IC 6
I C4
*0. 1u _1 6V_ Y5V_ 04
*1 0u _1 0V_ Y5 V_0 8
1.0A
I _G ND
IC 3
IC 7
I C1
I C2
IC 5
0. 1u _1 6V_ Y5 V_0 4
*0. 1u _1 6V_Y 5V_ 04
1 0u _1 0V_ Y5 V_0 8
1 0u _1 0V_ Y5 V_0 8
22 u_ 6. 3V_ X5 R_ 08
AC ES-9 190 7- 02 20 A-H 01
P IN GN D1 ~2 =I_GN D
I_ GN D
B - 42 Single HDD Board
I_ GN D
6-77-X810J-D02: w/o Re-driver
6-77-X810J-D02-1: with Re-driver
I5 VS
I_ GN D
I_ GN D
I _GN D
+
IC 15
10 0u _6 .3 V_B_ A
Schematic Diagrams
Dual HDD Board
DUAL SATA HDD
HU2
H J _M B
1
3
5
7
9
11
13
15
17
19
X
W/O Re-drive
HRN2
HRN4
HR2 HR14
HR16
HRN1
HRN3
HR1 HR11
HR12
0.01U
HR21
HR25
X
V
HC28
HC30
V
H5 V S
P O S A -2 0 R -B -02 4
H_ G ND
V
0.01U
X
V
V
D0
0
1
0
D1
0
0
1
0 ohm
V
X
X
X
0 ohm
V
X
X
1
1
CH0 -> 5 dB CH1 -> 0 dB
CH0 -> 0 dB CH1 -> 5 dB
CH0 -> 5 dB CH1 -> 5 dB
H 3. 3V S
RX _ 1 N
R X_ 1 P
0 . 01 U _ 16 V _ X 7 R _ 0 4
21
8
9
H 3 . 3V S
HR 1 4
HR 1 6
4 .7 K _ 0 4
4 .7 K _ 0 4
HR 1 7
HR 1 8
* 4. 7K _ 0 4
* 4. 7K _ 0 4
H S A T A _ TX P 5 _ R
H S A T A _ TX N 5_ R
H RN 2
1
2
* 0 _4 P 2 R _0 4
4
3
H Z 01
H Z 02
12
11
HS A T A _ RX N5 _ R
HS A T A _ RX P 5 _ R
H RN 4
1
2
* 0 _4 P 2 R _0 4
4
3
H Z 03
H Z 04
H S A T A _ T XP 4
H S A T A _ TX N 4
H R2 2
H R2 4
H S AT A _ RXN 4
H S AT A _ RXP 4
H R2 6
6
10
16
20
1
2
0. 0 1 U _ 1 6 V _ X 7R _ 04
0. 0 1 U _ 1 6 V _ X 7R _ 04
H Z 07
H Z 08
V DD
VD D
V DD
VD D
15
14
0. 0 1 U _ 1 6 V _ X 7R _ 04
H Z 05
H Z 06
R X _0 P
R X _0 N
TX_ 0 P
T X _0 N
HOST
4
5
D02 -1
H3 .3 VS
Close to HJ_SATA1
H_ G ND
H _G N D
H R1 1
H R1 2
4. 7K _ 0 4
4. 7K _ 0 4
H R1 3
H R1 5
*4 . 7 K _ 0 4
*4 . 7 K _ 0 4
R X _1 N
RX _ 1 P
Sheet 42 of 55
Dual HDD Board
D02 -1
H S A TA _T X P 4 _ R
H S A TA _T X N 4 _ R
HR N1
1
2
* 0_ 4 P 2 R _ 0 4
4
3
HZ 0 5
HZ 0 6
12
11
H S A TA _R X N 4 _ R
H S A TA _R X P 4 _R
HR N3
1
2
* 0_ 4 P 2 R _ 0 4
4
3
HZ 0 7
HZ 0 8
Layout note:
Close to HJ_SATA2
H _ GN D
H _ GN D
Layout Note:
Layout Note:
Closed to HU2
Closed to HU1
Layout note:
Layout note:
H 3. 3V S
If HU2 need to use.
The HR19 and HR21 and HR23 and HR25
must change to 0.01U_16V_X7R_04
HC 2 8
HC 2 9
HC 3 0
0 . 0 1u _ 1 6 V _X 7 R _0 4
0 . 1u _ 1 6 V _Y 5 V _ 04
1 u_ 6 . 3 V _ X 5R _ 04
H_ G ND
H _ GN D
H3 .3 VS
If HU1 need to mount .
The HR20 and HR22 and HR24 and HR26
must change to 0.01U_16V_X7R_04
H_ G ND
H C2 5
H C2 6
H C2 7
0 . 0 1 u _1 6 V _ X 7 R _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
1 u _ 6 . 3V _X 5 R _ 0 4
H _ GN D
HJ _ S A T A 2
S1
S2
S3
S4
S5
S6
S7
H J _S A TA 1
S1
S2
S3
S4
S5
S6
S7
4 .7 K_ 0 4
15
14
DEVICE
T X_ 1 N
T X_ 1 P
0. 0 1 U _ 1 6 V _ X 7R _ 04
? ? SN75LVCP412RTJ? ?
Layout note:
H U1
S N 7 5L V C P 4 1 2
7
EN
G ND
GN D
G ND
GN D
G ND
DEVICE
T X_ 1 N
T X_ 1 P
H R2 0
D1
D 0
6
10
16
20
VD D
V DD
VD D
V DD
T X_ 0 P
TX _ 0 N
HOST
Closed TO HU1
D0 2-1
H R1
D0 2- 1
Note:
4 . 7 K _ 04
GN D
G ND
GN D
G ND
GN D
RX_ 0 P
RX_ 0 N
T -P A D
4
5
HU 2
S N7 5 L V CP 4 1 2
7
EN
3
13
17
18
19
1
2
D 1
D0
H R2 5
0 . 01 U _ 16 V _ X 7 R _ 0 4
0 . 01 U _ 16 V _ X 7 R _ 0 4
H Z03
H Z04
HC26
CH0 & CH1 -> 0 dB
H R2
D02 -1
Closed TO HU2
H R2 1
H R2 3
HC25
HC27
D 02 -1
Note:
H S A T A _ R XN 5
H S A T A _ R XP 5
HR22
HR26
Function
D0 2- 1
HSA T A_ T X P5
HS A T A _ T X N5
HR20
HR24
H S A T A _ T X P 4 _C
HS A T A _ T X N4 _ C
H C1 8
H C1 9
0 . 0 1u _ 1 6 V _X 7 R _0 4
0 . 0 1u _ 1 6 V _X 7 R _0 4
H S A T A _ T X P 4_ R
H S A T A _ T X N4 _ R
H S A T A _ R XN 4 _ C
H S A T A _ R XP 4_ C
H C2 0
H C2 1
0 . 0 1u _ 1 6 V _X 7 R _0 4
0 . 0 1u _ 1 6 V _X 7 R _0 4
H S A T A _ R X N 4 _R
H S A T A _ RX P 4 _ R
H _G N D
H _ GN D
H3 .3 VS
H S A T A _ T XP 5 _ C
H S A T A _ T XN 5 _C
HC 8
HC 7
0. 0 1 u _ 16 V _ X 7 R _ 0 4
0. 0 1 u _ 16 V _ X 7 R _ 0 4
H S A T A _T X P 5 _ R
H S A T A _T X N 5_ R
H S A T A _ R X N 5_ C
H SA T A _ RXP 5 _ C
HC 6
HC 5
0. 0 1 u _ 16 V _ X 7 R _ 0 4
0. 0 1 u _ 16 V _ X 7 R _ 0 4
H S A T A _R X N 5 _ R
H S A T A _R X P 5 _R
H3 .3 V S
1.5A
P1
P2
P3
P4
P5
P6
P7
P8
P9
P 10
P 11
P 12
P 13
P 14
P 15
HC 1
HC 1 0
*0 . 1 u _1 6 V _ Y 5 V _ 0 4
*1 0 u _1 0 V _ Y 5 V _ 0 8
H5 V S
H _ GN D
1.0A
H _ GN D
1.5A
P1
P2
P3
P4
P5
P6
P7
P8
P9
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
H C2 3
HC 1 6
* 0. 1 u _ 1 6V _ Y 5 V _0 4
*1 0 u _1 0 V _ Y 5 V _ 0 8
H 5V S
H_ G ND
H _ GN D
1.0A
H H _J 1
H C1 3
H C2 4
H C1 7
H C 22
H C1 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 0 4
0 . 1 u _ 16 V _ Y 5V _0 4
1u _ 1 0 V _0 6
1 0 u_ 1 0 V _ Y 5 V _ 0 8
+
H C9
1 0 0 u_ 6 . 3 V _ B _ A
S A T -2 2 V C 0G
2
3
4
5
1
H H _J 2
9
8
7
6
2
3
4
5
T Y P E -J
1
9
8
7
6
TY P E -J
P I N GN D1 ~ 2 = H _ G ND
HC 4
HC 2
HC 1 2
H C3
H C 11
0. 1 u _ 1 6V _Y 5 V _ 04
0 . 1u _ 1 6 V _ Y 5 V _ 0 4
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
1 u _1 0 V _ 0 6
10 u _ 1 0V _ Y 5 V _0 8
+
HC 1 5
H_ G ND
H _G N D
H_ G ND
H_ G ND
H _G N D
1 00 u _ 6. 3V _ B _ A
S A T -2 2V C 0 G
P IN GN D1 ~ 2 = H _ G ND
H_ G ND
H _ GN D
6-77-X810K-D02: w/o Re-driver
6-77-X810K-D02-1: with Re-driver
Dual HDD Board B - 43
B.Schematic Diagrams
H3 .3 V S
0 . 01 U _ 16 V _ X 7 R _ 0 4
H Z01
H Z02
HU1
H3 .3 V S
H _G N D
H R1 9
HC29
T -P A D
H5 V S
H S A T A _ RX N 4
H S A T A _ RX P 4
V
Re-drive
3
13
17
18
19
H3 .3 VS
W/
21
H S A T A _ RX N 5
H S A T A _ RX P 5
HR19
HR23
H S A T A _ T XP 4
H S A T A _ T XN 4
2
4
6
8
10
12
14
16
18
20
8
9
H S A T A _ T XP 5
H S A T A _ T XN 5
Schematic Diagrams
Audio Board
AUDIO BOARD
USB + eSATA
A 3 .3 V S
L ay ou t n ot e:
6
10
16
20
Closed TO AU1
AC 7
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
AZ 2 5
A e S A T A _ TX N _ C
AC 5
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
AZ 2 7
2
R X _1 N
RX _ 1 P
A e S A T A _ RX N_ C
A e SA T A _ RX P_ C
AC 6
AC 8
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
AZ 2 9
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4
AZ 3 1
2
A R9
A R1 0
4. 7K _ 0 4
4. 7K _ 0 4
A R1 4
A R1 5
*4 . 7 K _0 4
*4 . 7 K _0 4
A _G N D
A _ GN D
AZ2 6
4
AZ2 8
A LP 2
1
A J _ C OM B O
eSATA
3
A+
A-
AZ3 0
4
13
14
AZ3 2
BB+
*W C M2 0 1 2F 2 S -1 6 1 T0 3
AL 4
A V CC US B1
H C B 1 60 8 K F -1 21 T 2 5
L ay ou t no te :
A U S B _P N 6
Close to AJ_COMBO
A U S B _P P 6
9
A V C C U S B 1 _C
GN D 2
12
60 mil
POR T 2
A 3 . 3V S
1
10
11
12
11
3
13
17
18
19
AC2 4
0. 0 1 u_ 1 6 V _ X7 R _ 0 4
A LP 1
3
A _ A UD G
I C 1 -L
P _S E N S E
P -R
P _P L U G
P -L
8 8 10 7 -3 00 0 1
A _ GN D
A e S A T A _ TX P _ C
*W C M2 0 1 2F 2 S -1 6 1 T0 3
GN D
GN D
GN D
GN D
G ND
A e S A T A _R X N
A e S A T A _R X P
DEVICE
T X _ 1N
T X _ 1P
4. 7 K _ 0 4
15
14
TX _ 0 P
T X _0 N
HOST
T -P A D
AC2 3
0. 0 1 u_ 1 6 V _ X7 R _ 0 4
A U S B _P P 9
A U S B _P N 9
AM
AH
AH
AH
AH
4
5
A U1
S N 7 5L V C P 41 2
7
EN
R X _0 P
R X _0 N
D1
D 0
A S P DIF O
A LI N E _ S E N S E
A LI N E -I N _R
A LI N E -I N _L
A MI C _S E N S E
A MI C 1-R
A U S B _P P 6
A U S B _P N 6
GN D 3
15
1
A LP 3
GN D 4
2
4
3
USB
1
W C M2 0 12 F 2 S -1 61 T 0 3
AC 9
V CC 0
A C 11
G1
2
Sheet 43 of 55
Audio Board
A C 28
*0 . 1u _ 1 6V _ Y 5V _ 0 4
A C 29
*0 . 1u _ 1 6V _ Y 5V _ 0 4
A C 30
*0 . 1u _ 1 6V _ Y 5V _ 0 4
A C 31
D0
0
1
0
1
*0 . 1u _ 1 6V _ Y 5V _ 0 4
A _ GN D
A _ A U DG
D1
0
0
1
1
3
DA T A0 +
Place under the common
bead body and same as
USB trace requirment
Function
CH 0 & C H1 -> 0 d B
A _ GN D
*H C B 1 6 08 K F -1 2 1 T2 5
A U S B _P N 9
A U S B _P P 9
A C2 5
AC 2 6
A C2 7
0. 0 1 u _1 6 V _ X7 R _ 0 4
0 . 1 u _1 6 V _ Y 5 V _ 04
1u _ 6. 3V _ X 5 R _ 04
A LP 4
A _G N D
A _ GN D
3
G ND 4
C -1 9 0 95 0 7 -1
A _ GN D
A C 12
0 . 1 u_ 1 6V _Y 5V _0 4
A _G N D
PHONE JACK
A _ GN D
TV ANTENNA
SPDIF Digital
Re v 3.0
A C3 2
4. 7u _ 10 V _ X 5R _ 08
S PDIF OUT
A R 12
7 5_ 0 4
Headpho ne
A C 34
A C 18
A S PDIF O
+
* 10 0 u _6 . 3 V _ B _A
A C3 3
4. 7u _ 10 V _ X 5R _ 08
A_ A UD G
7 5_ 0 4
A R 13
A C 35
AC 1 3
A L5
0 . 0 1 u_ 1 6 V _X 7 R _ 0 4 F C M 10 0 5 K F -1 21 T 03
AZ1 9
5 A J_ H P
4
3
R
A HP _ S E N S E
A Z 14
1 0 0p _ 5 0V _ N P O_ 0 4
A H P -L
G4
GN D 1
A _ GN D
A C 10
+
1 0 0u _ 6 . 3V _B _ A
A _ GN D
A H P -R
DA T A1 +
2
4
G ND 3
DA T A1 -
8
1
W C M2 0 12 F 2 S -1 61 T 0 3
La yout not e:
A_ GND a nd A_AU DG spa c e is
6 0mi ls ~ 10 0mi ls
G3
7
60 mil
PO RT 3
A 3 .3 V S
CH 0 - > 5 dB CH 1 -> 5 dB
V CC 1
6
A V C C U S B 1 _C
G ND 2
GN D 0
5
AL 3
A V CC US B1
G2
4
A _ GN D
CH 0 - > 5 dB CH 1 -> 0 dB
CH 0 - > 0 dB CH 1 -> 5 dB
G ND 1
DA T A0 -
1 0 u_ 1 0 V _Y 5 V _0 8 0 . 1 u_ 1 6V _Y 5V _0 4
Lay ou t no te :
A _ GN D
A HP _ P L UG
A Z 15
6
2
1
AR 7
AR 8
AR 6
A C1 4
2 20 _ 0 4
1 80 p _ 50 V _ N P O _0 4
6
2
1
L
1 M _0 4
1 M_ 0 4
2 S J -S 35 1 -S 3 0
1 0 0p _ 5 0V _ N P O_ 0 4
* 10 0 u _6 . 3 V _ B _A
AR 5
*6 8 m li _ P _1 2
5 A J _ S P DIF
4
3
R
A Z 02
A J _ ANT 1
1
2
3
4
L
Re v 3 .0
2S J -S 3 5 1-S 30
A C 19
+
B.Schematic Diagrams
A 3 .3 V S
1
2
AC2 2
0. 0 1 u_ 1 6 V _ X7 R _ 0 4
8
9
A eS A TA _ T X N
A eS A TA _ T X P
A e S A T A _T X P
A e S A T A _T X N
A V CC US B 1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
21
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
VD D
V DD
VD D
V DD
AC2 1
0. 0 1 u_ 1 6 V _ X7 R _ 0 4
A J _ MB 1
A eS A TA _ R XP
A eS A TA _ R XN
Place under the common
bead body and same as
USB trace requirment
AR1 1
N ote :
A _ GN D
Re v 3 .0
A T V _ GN D
A _ GN D
A J _ ANT 2
1
2
3
A T V _D A T
F R -00 5 D
A _ GN D
2 02 7 9 -00 1 E -0 1
A _G N D
A_ A UD G
A _ AUD G
A H _ I4
MIC IN
A M I C 1 -R
AL 1 1
F C M1 00 5 K F -1 2 1T 0 3
A MI C _S E N S E
AZ1 6
A M I C 1 -L
AL 1 0
F C M1 00 5 K F -1 2 1T 0 3
AZ1 8
5 A J _ MI C
4
3
R
LINE IN
A L I N E -I N _ R
AL 8
F C M 10 0 5 K F -12 1 T 03
A L INE _ S E NS E
A Z 11
A L I N E -I N _ L
AL 9
F C M 10 0 5 K F -12 1 T 03
A Z 13
5 A J _L I N E
4
3
R
2
3
4
5
A C1 7
L
2 S J-S 35 1 -S 3 0
1 0 0p _ 5 0V _ N P O_ 0 4
A _ AUD G
Re v 3. 0
A C 16
A C1 5
1 00 p _ 50 V _ N P O_ 04
10 0 p _5 0 V _ N P O _0 4
1
A _A U D G
A _ A U DG
R ev 3 .0
A H_ I2
9
8
7
6
2
3
4
5
TY P E -I
A _ GN D
L
2 S J -S 3 5 1-S 3 0
A_ A UD G
A _ A UD G
B - 44 Audio Board
2
3
4
5
A C 20
1 0 0 p_ 5 0 V _N P O_ 0 4
A _ A U DG
6
2
1
A H_ I5
9
8
7
6
T Y P E -I
A _ GN D
6
2
1
1
A H _ O1 A H _O 2
T Y P E -O T Y P E -O
1
A H _I 1
9
8
7
6
2
3
4
5
T Y P E -I
A _ G ND
1
A H_ I3
9
8
7
6
2
3
4
5
T Y P E -I
A _G N D
1
9
8
7
6
T Y P E -I
A _ GN D
A _ GN D
Schematic Diagrams
Power Button Board
POWER BUTTON B'D
Sheet 44 of 55
Power Button
Board
B R2
B 3. 3VS
22 0_0 4
BM_BTN #
1
3
2
4
BM_ BTN #
5
6
88266- 03 00 1
BGN D
BS W 1
TJ G -53 3-S -T/ R
B Z01
1
2
3
A
B C1
0.1u_1 6V _Y 5V _04
BD 1
R Y -S P150DN B 84
BGN D
C
B J _MB
BG N D
BH _L1
2
3
4
5
1
TY PE -L
B G ND
Power Button Board B - 45
B.Schematic Diagrams
B3.3 V S
Schematic Diagrams
Click & FP Board
CLICK BOARD
CC 1
0 . 1 U _ 1 6V _ Y 5V _ 0 4
1
3
C 5 VS
C GN D
C J _T P
C T P B U T T ON _L
1
3
CSW 2
TJ G- 53 3 -S -V -T / R
2
4
1
3
2
4
C D2
R Y -S P 1 5 5 U H Y U Y G4
1
3
2
4
C GN D
3
1
CZ 0 8
CD 1
Y
SG
RIGHT
KEY
4
3
CZ 0 7
R Y -S P 1 5 5U H Y U Y G 4
4
2
1
C T P B U T T ON _R
C Z 06
3
CSW1~2
5
6
C T P B U TT O N _ R
C L E D _B A T_ C H G#
CL E D_ A C IN#
C L E D _B A T_ F U LL #
CL E D_ P W R #
BAT CHARGER LED
C GN D
POWER ON LED
Note
FINGER PRINTER
W it hou t EE PRO M
CC 2
0. 1 U _ 2 5 V _X 7 R _ 0 6
T CS 4B
St uff
CR 7
22 0 _ 06
C GR I D 0 / S E N S E _F
Un stu ff
D0 3A-2
C E S D _ R I N G_ F
C MO S I _ F
W it h EEP RO M
T CS 4B
1
2
CR9
T CS4 B
T CS 4EA
P ull H ig h
T CS 4E A
U nst uf f
T CS 4C
P ull L ow
T CS 4C
U nst uf f
CC 5
C Q1
*N D S 3 52 A P _ N L
G
3 3p _ 5 0V _ N P O_ 06
S
T CS4 C/ 4E A 2 20 _0 6
TC S4 B
T CS4 B
C R1 3
U ns tuf f
D
*0 . 02 2 U _ 1 6 V _X 7 R _ 0 4
TC S4 B
C R1 4
* 15 _ 06
CV D D_ F
T CS 4B
C A V D D _F
C D A TA 2 _ F
C R6
0 _0 4
C D A TA 1 _ F
C R8
0 _0 4
C D A TA 0 _ F
C R1 0
0 _0 4
C GP I O1 _F
C R1 1
0 _0 4
C MI S O/ MO D E 3 _ F
C R1 2
1 0K _ 0 4
C GP I O0 / I N T _ F
C C2 4
0 . 1U _ 16 V _ Y 5 V _ 0 4
C GN D
3 30K _0 4
C GN D
TC S4 C/4 EA 0 _04
St uff
T CS 4B
T CS 4C /4E A Un stu ff
CV DD _ F
CR1 6
4 7K_ 04
TC S4 C/4 EA 0 _04
T CS4 C/ 4EA 3 3P _50 V_ 03
C GN D
5 . 6 _0 6
CC6
*1 0 K _ 04
R C L A M P 0 50 2 B
1 00 _0 6
33 0 K _ 06
C G_ F E T _ F
1 0K _ 0 4
C R2 8
C U1
10mil
T CS 4C /4E A 5. 6_0 6
C3 .3 VS _ F
CVDD _ F
C R2 7
U nst uf f
3
T CS 4C /4E A Un stu ff
Un stu ff
T CS 4B
Un stu ff
T CS 4C /4E A 0. 1U_ 16 V_ Y5V _0 4
C V D D _F
T CS 4C /4E A 33 0K_ 04
E
*3 3_ 0 6
B
CV D D1 _ F
CV D D_ F
C Q2
* B T B 11 9 8 N 3
C U2
1
CG ND
C
B.Schematic Diagrams
22 0 _0 4
CU S B _ P N7 _ F
C U S B _ P P 7 _F
85 2 01 -0 4 05 1
C Z 05
C GN D
C GN D
6 -20 -9 4A 20- 11 2
T CS 4B
2 2 0 _0 4
C TP _ D A TA
C TP _ C LK
8 7 15 1 -1 20 7 G
Sheet 45 of 55
Click & FP Board
2 20 _ 04
1
2
3
4
CR2
2
C GN D
CV D D3
8 52 0 1 -10 0 5 1
22 0 _ 04
C R3
4
C GN D
1
_A C I N #
_P W R #
_B A T_ C H G#
_B A T_ F U L L #
CR 5
Y
SG
CL E D
CL E D
CL E D
CL E D
C3 .3 V S _ F
CJ _ F P 1
C T P B U TT O N _ L
CR4
C5 V S
1
2
3
4
5
6
7
8
9
10
11
12
CT P _ DAT A
CT P _ CL K
CV D D3
2
1
2
3
4
5
6
7
8
9
10
CV D D3
CSW 1
TJ G- 53 3 -S -V -T / R
2
4
5
6
C J _M B
1
2
3
4
5
6
7
8
9
10
LED
LIFT
KEY
2
A#
VC C
*3 3 0 K _0 4
* 0. 1 U _1 0 V _ X7 R _0 4
CN RE S E T _ F
8
C R1 7
CL R#
Cx
GN D
Q
1 u _1 0 V _ 06
TC S4 B
7
6
CG ND
CC 1 3
4
CC 3
CC 4
1 u_ 1 0 V _0 6
0. 1 U _1 0 V _ X7 R _0 4
5
C R 20
CG ND
? ? ? ? ?
,? ? 0 .1 uF ~1u F
C G_ F E T _ F
*S N 7 4L V C 1G 1 23 D C T
TC S4B
0 . 1 U _ 10 V _ X 7R _ 04
U ns tuf f
? ? ?
* 1 0K _ 0 4
4 7K _0 4
C C1 0
TC S4 C/ 4EA 1 U_ 6.3 V_ 04
C P D _ R E G_ F
* 2. 2 U _6 . 3 V _ 06
CV D D_ F
CG ND
C R1 5
C C1 1
3 3 0 K _0 4
B
Rx /Cx
3
C V D D _F
CR 1 8
C C9
1U _1 0V _06
TC S4 B
TC S4C /4 EA 2. 2U _1 6V_ X5 R_ 06
C R2 2
C GP I O 0/ I N T _F
* 0 _0 4
C US B _ P P 7 _ R_ F C R2 3
C R2 1
1 . 5 K _0 4
C U S B _ P P 7 _F
2 7 . 4_ 1 % _0 4
C C1 5
0 _0 4
4 7 p _5 0 V _ N P O _0 4
C GN D
TC S4 C/ 4EA U ns tuf f
C GN D
C C8
0 . 1 U _ 1 0V _ X 7 R _ 0 4
C C7
1 u _1 0 V _ 06
CU S B _ P N7 _ R_ F
C GN D
CD
CD
CG
CU
CU
1
3
5
7
9
11
13
15
17
19
21
23
U X OU T_ F
R I D 0/ S E N S E _ F
CS_ F
I S O/ M OD E 3_ F
P I O1 _ F
A T A 0_ F
A T A 1_ F
P I O0 / I N T_ F
S B_ PN7 _ R_ F
S B _ P P 7 _R _F
2
4
6
8
10
12
14
16
18
20
22
24
C GN D
C
C
C
C
C
C
C
C
CA V D D_ F
CV D D_ F
CV D D1 _ F
MO S I _ F
P D _ R E G_ F
N R E S E T _F
DA T A 2 _ F
E S D _ R I N G _F
MC LK _F
XIN_ F
X OU T _ F
C C1 8
2 . 2 u _1 6 V _ X5 R _ 0 6
C GN D
1
T Y P E -K
TY P E -K
B - 46 Click & FP Board
C GN D
2 2p _ 50 V _ N P O_ 04
C GN D
T CS 4B
33 P_5 0V _0 4
C H _ O2
C GN D
CH_ O 1
C C1 6
CC1 7
2 . 2 u _1 6 V _ X5 R _ 0 6
2. 2 u _ 16 V _ X 5R _0 6
1
C GN D
TCS 4C /4 EA 1M _0 4
CU 3
CM
CM
CM
CM
I S O/ M OD E 3_ F
OS I _ F
CS_ F
CL K _ F
5
2
1
6
S
Q
CS#
S CK
V DD
S tu ff
T CS4 C
S ee n ote
4
VSS
8
CC 1 9
W P#
T CS4 B
D0 3A- 2
CV D D_ F
Un st uff
T Y P E -K
C GN D
C GN D
18 p _ 50 V _ N P O _0 4
1U _10 V_ 06
CH _ K3
CG ND
C GN D
CC2 2
TCS 4B
2
3
4
5
T Y P E -K
CG ND
10 0K_ 04
T CS 4C /4E A Un stu ff
CG ND
C GN D
47 p _5 0 V _ N P O _0 4
C C 20
18 p _ 50 V _ N P O _ 04
T CS 4B
1
CC2 3
*1 0 0 K _0 4
T CS 4C /4E A 22 P_5 0V _0 4
C H_ K 2
1
CR 2 6
1 M _0 4
1 0 K _ 06
CG ND
2
3
4
5
CG ND
T CS 4B
T CS 4C /4E A 10 K_0 6
CH_ K 4
2
3
4
5
C US B _ P N7 _ F
C M U X OU T_ F
4
CX 1
1 2 MH z -H S X 5 3 1S
CV DD _ F
C H _K 1
2
3
4
5
1
3
C C 21
*C ON 24 A
C GN D
2
CXO UT _ F
CR2 4
C C1 2
2 7 . 4 _1 % _0 4
C GN D
CJ _ F P 3
CM
CG
CM
CM
CG
C R2 5
C X I N _F
H OL D #
3
*0 . 1 U _ 1 0V _X 7 R _ 0 4
7
*M 95 1 2 8W M N 6 T P
T CS4 EA S ee n ote
C GN D
C GN D
6-77-M9802-D03A: w/o FP
6-77-M9802-D03A-1: with FP
6-77-M9802-D03A-2: with FP,
w/o EEPROM
Schematic Diagrams
Game Key Board
GAME KEY BOARD
GSW 2
TJ G- 53 3- S-T/R
GG AME# 1
0. 1u _1 6V_ Y5 V_0 4
G R2
GR 5
GR 4
2 20 _0 4
2 20 _0 4
22 0_ 04
22 0_ 04
G _G ND
A
A
A
A
H T- 15 0N B-D T
H T- 15 0N B-D T
HT-1 50 NB- DT
HT-1 50 NB- DT
0. 1u _1 6V_ Y5 V_0 4
G _G ND
GSW 4
TJ G- 53 3- S-T/R
GG AME# 3
G _G ND
1
3
G _G ND
G 3. 3VS
G R1
G R8
GR 7
GR 6
2 20 _0 4
2 20 _0 4
22 0_ 04
22 0_ 04
G _G ND
G H_ O3
TYPE- O
G H_ O4
TYPE-T3
G H_ O7
TYPE- T2
G H_ O8
TYPE- T2
G H_ O9
TYPE-T2
G _G ND
G _G ND
G _G ND
GH _O 5
TY PE-T3
GH _O 10
TY PE-T2
2
4
0. 1u _1 6V_ Y5 V_0 4
G _G ND
GH _K1
G 3. 3VS
2
3
4
5
GJ _MB
G H_ O6
TYPE- T1
1
3
GC 7
G _G ND
C
C
C
HT-1 50 NB- DT
GSW 8
TJ G- 53 3- S-T/R
GG AME# 8
5
6
A
A
A
A
GD 5
HT-1 50 NB- DT
C
GD 8
H T- 15 0N B-D T
G H_ O2
TYPE- O
G _G ND
2
4
0. 1u _1 6V_ Y5 V_0 4
G D7
H T- 15 0N B-D T
G _G ND
1
3
GC 4
G D1
2
4
0. 1u _1 6V_ Y5 V_0 4
GSW 3
TJ G- 53 3- S-T/R
GG AME# 4
1
3
GC 8
0. 1u _1 6V_ Y5 V_0 4
G H_ O1
TYPE- O
Sheet 46 of 55
Game Key Board
GSW 7
TJ G- 53 3- S-T/R
GG AME# 7
2
4
5
6
G 3. 3VS
G_ GN D
2
4
GC 6
0. 1u _1 6V_ Y5 V_0 4
GC 3
G_ GN D
1
3
C
G _G ND
G3 .3 VS
GSW 6
TJ G- 53 3- S-T/R
GG AME# 6
5
6
GC 2
C
GD 4
C
GD 6
C
G D2
G3 .3 VS
G _G ND
2
4
1
2
3
4
5
6
7
8
9
10
11
12
GH _K5
2
3
4
5
1
TY PE-K
GH _K3
2
3
4
5
1
TY PE-K
GH _K6
2
3
4
5
1
TY PE-K
GH _K4
2
3
4
5
1
TY PE-K
GH _K2
2
3
4
5
1
TY PE-K
1
TY PE-K
GJ _M B
GG AME# 1
GG AME# 2
GG AME# 3
GG AME# 4
GG AME# 5
GG AME# 6
GG AME# 7
GG AME# 8
87 15 1- 12 07 G
1
G _G ND
G _G ND
G _G ND
G _G ND
G _G ND
G _G ND
12
6- 20 -9 4A 20 -1 12
G_ GN D
Game Key Board B - 47
B.Schematic Diagrams
1
3
G D3
G_ GN D
0. 1u _1 6V_ Y5 V_0 4
GSW 1
TJ G- 53 3- S-T/R
GG AME# 2
5
6
GC 5
5
6
GC 1
G R3
G_ GN D
2
4
G 3. 3VS
5
6
G 3. 3VS
1
3
5
6
G3 .3 VS
GSW 5
TJ G- 53 3- S-T/R
GG AME# 5
2
4
5
6
G3 .3 VS
1
3
Schematic Diagrams
Front R Side LED Board
Sheet 47 of 55
Front R Side LED
Board
X5VS
XJ _MB1
1
2
3
4
5
6
85204-06001
XR
XG
XB
X5VS
XD1
LTW - 008R GB- L
2
40mil
XGND
4
6
G
R
B
1
XZ 02
XR2
68. 1_1%_06
XZ05
3
XZ 03
XR1
221_1%_06
XZ06
5
XZ 04
XR6
100_1%_06
XZ07
20mil
20 mil
20 mil
XD2
LTW - 008R GB- L
68. 1_1%_06
XR4
221_1%_06
6
B
5
XR3
100_1%_06
D
XH_O1
TYPE- O
B - 48 Front R Side LED Board
XR
XH _P1
TY PE-P
XH _P2
TY PE- P
XG ND
XG N D
XB
G
XQ4
MTN7002ZH S3
G
S
G
XQ 3
MTN 7002ZHS3
S
XG
XQ2
MTN 7002ZH S3
D
XR5
3
D
G
R
1
4
2
S
B.Schematic Diagrams
FRONT R SIDE LED B'd
XGN D
XGND
XG ND
Schematic Diagrams
Front L Side LED Board
FRONT L SIDE LED B'd
Sheet 48 of 55
Front L Side LED
Board
Y5 VS
1
2
3
4
5
6
YR
YG
YB
YD 1
LTW-0 08 RG B-L
40mil
8 52 04 -06 00 1
2
G
1
Y Z02 YR 1
6 8. 1_1 %_0 6
Y Z08
20mil
4
R
3
Y Z03 YR 2
2 21 _1%_ 06
Y Z09
20mil
B
5
Y Z04 YR 3
1 00 _1%_ 06
Y Z10
20mil
Y GN D
6
YD 2
LTW-0 08 RG B-L
Y Z05 YR 4
6 8. 1_1 %_0 6
3
Y Z06 YR 5
2 21 _1%_ 06
6
B
5
Y Z07 YR 6
1 00 _1%_ 06
YH _P2
TY PE-P
YG ND
Y H_ P1
TYPE- P
Y Q3
MTN7 00 2ZH S3
YR
YB
G
S
G
YQ 1
MTN7 002 ZHS3
S
G
YQ2
MTN 70 02 ZH S3
S
YG
D
1
R
D
G
4
D
2
Y GN D
YG ND
YG ND
YH _O 2
TY PE-O
Y GN D
Front L Side LED Board B - 49
B.Schematic Diagrams
Y 5VS
Y J_MB1
Schematic Diagrams
CIR Board
B.Schematic Diagrams
CIR BOARD
Sheet 49 of 55
CIR Board
KH _O1
KH _O2
KH _O3
KV DD 5
K J_MB
1
2
3
KC IR _R X
KGN D
KVD D 5
KGN D
88 266-030 01
KGN D
KR 1
KU 1
IR M- V0 38/ TR 1-P
KVD D 5_C I R
100 _04
V
KC 1
0.1u_1 6V_ Y 5V_04
KC 2
*4. 7 u_10 V_X5R _06
G
KC 3
10 u_10 V_Y 5V _08
K GND
O
V
GND 2
G
GND 1
GN D 2
GN D 1
O
KGN D
KGN D
KC I R _R X
B - 50 CIR Board
Schematic Diagrams
Finger Board
FU 1
E XT_R I N G 2
CRID O
RIN G
M U XOU T
AV D D
P AD _VD D 1B
MI S O
DV D D
GP IO 1
A GN D
D A TA 0
D A TA 1
GP IO 0
M C LK
U SB _D N
U S B _D P
MOS I
P D _R E G
N R ES E T
D GN D
D A TA 2
E XT_R I N G 1
PV D D
XTA LI N
P GN D
XTA LOU T
FE S D _R IN G
B1
FG R I D 0/ S E N S E
C1
D1
F GN D
FM U XOU T
E1
F1
F AV D D
FM C S
G1
H1
F TC _V D D
FM I SO /M OD E 3
J1
A2
F DV DD1
FG PI O 1
B2
F J1
F GN D
F GN D
C2
FD AT A0
D2
FD AT A1
E2
FG PI O 0/ IN T
F2
FM C LK
G2
FU SB _P N 7_R
F GN D
F MU XO U T
F GR I D 0/S E N S E
F MC S
F MI S O/ MOD E3
F GP I O1
F D A TA 0
F D A TA 1
F GP I O0/ I N T
F U S B_ PN 7_R
F U S B_ PP 7_R
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
F MO SI
F P D _R EG
F N R ES E T
F D A TA 2
F E S D _R I N G
F MC LK
F XI N
F XO U T
F AV D D
F TC _V D D
F DV DD1
Sheet 50 of 55
Finger Board
F GN D
S P D Z -24 -B -017/ 032-1-R
H2
FU SB _P P 7_R
J2
FM OS I
A3
FP D _ R E G
B3
FN R E SE T
FJ1
1
C3
D3
FD AT A2
E3
FE S D _R IN G
F3
G3
23
23
1
F GN D
2
24
BOTTON VI EW
24
2
TOP VIEW
F TC _V D D
FX IN
H3
J3
FX OU T
F GN D
TC S 4E A
Change
Footprint
Finger Board B - 51
B.Schematic Diagrams
M CS
A1
Schematic Diagrams
V1.0 Power on SEQ Diagram
X8100 EVT POWER ON SEQUEN CE V1.0
M_BTN#
DD_ON
5V
3.3V
1.744 ms
1.1 28ms
rise=1.14 8ms
73 .6ms(t 02) 0 ~2 00 ms ,P AS S
SUS_PWR_ACK
B.Schematic Diagrams
; PC9 3=1500p
rise=1.020ms
73.6ms(t0 3) > 10 ms ,P AS S
RSMRST#
0ms( t05 ) 0~ 20 0m s, PA SS
AC_PRESENT_R
7 2ms
212ms
140ms
PWR_BTN#
98 ms
Sheet 51 of 55
V1.0 Power on SEQ
Diagram
SUSC#
1.5V
1. 76 ms
r is e= 24 8u s
3. 15 ms
DDR1.5V_PWRGD
50 us (t 09 )
SUSB#
5VS
3.3VS
>3 0u s, PA SS
ri se =1 .2 7m s
2 .3 88 ms
1 .6 49 ms
4 16 us
r is e= 75 6u s
ri se =3 18 us
1.8VS
1 .1 7m s
ri se =5 69 us
1.5VS
VTT_MEM
1.1VS_VTT
1.5VS_PWRGD
1.8VS_PWRGD
1.1VS_VTT_EN
3 78 us
2. 59 ms
r is e= 17 2u s
r is e= 48 8u s
1 .5 4m s
6 40 us
2 .0 8m s
2. 76 2m s
1.1VS_VTT_PWRGD
2 .7 62 ms
ALL_SYS_PWRGD
VCORE_ON
3 92 us
VCORE
3 70 ms (t 16 ) > 99 ms ,P AS S
1 .0 9V
79 0m V
ri se =3 56 us
80 4u s
CLKEN#
4 .9 ms (t 20 )
3~ 20 ms ,P AS S
DELAY_PWRGD
5 .7 ms
PM_MPWROK
5 .7 ms
SB_PWROK
5 .7 ms
SYS_PWROK
4 4m s( t2 3) > 1m s, PA SS
PM_DRAM_PWRGD
7 2m s( t2 6) > 1m s, PA SS
H_CPUPWRGD
7 4m s
BUF PLT RST#
B - 52 V1.0 Power on SEQ Diagram
B io s: 1 .0 0. E1
E C: 1 .0 0. E1 b-T ES T
T es t da te : 200 9/ 7/ 21
Schematic Diagrams
V1.0 Power_SEQ S3
X8100 V1.0 POWER
SEQUENCE S3 AND WAKE-UP
SUSB#
MEPWROK
32us(Te)
>0ms,PASS
118ms
3.3VS
1.520ms
1.1VS
4.144ms(Tj)
>5us,PASS
SYS_PWROK
2.016ms
Sheet 52 of 55
V1.0 Power_SEQ
S3
3.984ms(Ti) >40ns,PASS
114.8ms
VCORE_ON
4.4ms(Th) <100ns,FAIL
6ms
VCORE
590us(t17) <3ms,PASS
110ms(t16)
>99ms,PASS
ALL_SYS_PWRGD
116ms(t21) >5ms,PASS
VCCPWRGOOD
SUS_STATE#
400us
1.64ms(t28) >1ms,PASS
PLTRST#
60us(Tn) >30us,PASS
400us(Tm)
0.01~10ms,PASS
S3 Sleep SEQ
140us(t29)
1.78ms(t32)
S3 Wakeup
>60us,PASS
>1ms,PASS
SEQ
Bios: 1.00.E1
EC: 1.00.E1b-TEST
Test date: 2009/7/21
V1.0 Power_SEQ S3 B - 53
B.Schematic Diagrams
470us(Tc) >40ns,PASS
Schematic Diagrams
V1.0 Power_SEQ S4
X8100 V1.0 POWER
SEQUENCE S4 AND WAKE-UP
B.Schematic Diagrams
SUSB #
3.3V S
310us(Tc)>40ns,PASS
1.1V S
30us(Td)>40ns,PASS
1.49ms
4.02ms(Tj)
>5us,PASS
Sheet 53 of 55
V1.0 Power_SEQ
S4
MEPWR OK
2.588ms
30us(Te)
>0ms,PASS
379ms
V core_ ON
Vcore
760us
6.4ms
S YS_PW ROK
30us(Ti) >40ns,PASS
880us(Th)
<100ns,FAIL
SUSC#
D RAMPW ROK
limit to 0 ms(Tk)>-100ns,PASS
VC CPWRG OOD
S US_ST ATE#
384us(Tm)
>210us,PASS
PLTRS T#
1.596ms
48us(Tn) >30us,PASS
1.736ms
S4 Sleep SEQ
S4 Wakeup
SEQ
Bios: 1.00.E1
EC: 1.00.E1b-TEST
Test date: 2009/7/21
B - 54 V1.0 Power_SEQ S4
Schematic Diagrams
Power Block Diagram
5V S
V DD 5
3 .3 V
DD _O N#
SYST EM VR
5V
V DD 3
DD _O N
VD D 3
VD D 5
V IN
S YS TE M V R
VDD 3
2
1. 8V S
VI N
S LP _S 4
S WITC H ES
D D_ ON
BA TT ER Y
PA C K
1
1. 5V S
V IN
1. 1V S _V TT
V IN
VT T_ ME M
1 .5 V
1. 5V S _C P U
S US C#
DD _ ON
SU SB
PW R_SW #
Sta rtup
C ircuit
S US B#
PW R _BTN #
ITE 85 12
R SMR ST#
B utton
3
IB EX PE AK
17
A L L_ S Y S_ PW R G D
11
1 .5 V
B UF_ PLT_R ST#
SL P_ S 3 # (S US B# )
V COR E_ O N
10
99ms DELAY
CP U
Sheet 54 of 55
Power Block
Diagram
R STIN #
PLT_ RS T#
4
SL P_ S 4 # (S US C# )
H _ CPU PW RGD
PRO C PW RGD
SB _ PW RO K
V C CPW R GOO D_0
16
NC
SY S _PW ROK
14
V C CPW R GOO D_1
V D DPW R GO OD
PM_ PW RO K
DR A MPW RO K
S M_DR A MPW ROK
15
13
1 .8 VS
1 .8V S _ PW RG D
C PU COR E V R
7
CLK _PW RGD
1.8 VS VR
1 .5 VS
S LG8 SP5 85
1 .5V S _ PW RG D
8
1.5 VS VR
5
1 .5 V
1. 1 V S_V TT_ PW R GD
DD R1 . 5 V _ PW RG D
VCO RE
DEL A Y _ PW R GD
CLKEN#
V C ORE_O N
12
9
6
DDR V R
V TT _M E M
1 .1 VS
1 .1V S_ VTT VR
Power Block Diagram B - 55
B.Schematic Diagrams
AC
AD A PT ER
3. 3V S
SL P_ S3
SW IT C HE S
1 .8 VS
Schematic Diagrams
V2.0 Power_SEQ S3
X8100 V1.0 POWER
SEQUENCE S3 AND WAKE-UP
B.Schematic Diagrams
SUSB#
MEPWROK
62 us( Te)
> 0ms ,PA SS
219 ms
3.3VS
Sheet 55 of 55
V2.0 Power_SEQ
S3
3 6us (Tc )
>40 ns, PAS S
1 .41 0ms
1.1VS
2.5 58m s(T j)
>5us ,PA SS
SYS_PWROK
3. 092 ms
2. 758m s(T i) >4 0ns ,PA SS
216 .4m s
VCORE_ON
7.0 96m s(T h) <10 0ns ,FA IL
7 ms
VCORE
976 us( t17 )
<3m s,P ASS
216 ms( t21 )
>5m s,P ASS
20 9ms (t1 6)
>9 9ms ,PA SS
ALL_SYS_PWRGD
VCCPWRGOOD
SUS_STATE#
424 us
1 .59m s(t 28) > 1ms ,PA SS
PLTRST#
60u s(T n) >3 0us ,PA SS
364u s(T m)
0 .01 ~10 ms, PAS S
S3 Sleep SEQ
B - 56 V2.0 Power_SEQ S3
156 us( t29 )
> 60u s,P ASS
1.7 44m s(t 32) > 1ms ,PA SS
S3 Wakeup
SEQ