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System tasks UM-149
ModelSim Verilog system tasks
The following system tasks are specific to ModelSim. They are not included in the IEEE
Std 1364 nor are they likely supported in other simulators. Their use may limit the
portability of your code.
$coverage_save(<filename>, [<instancepath>], [<xml_output>])
The $coverage_save() system task saves Code Coverage information to a file during a
batch run that typically would terminate via the $finish call. If you don’t specify
<instancepath>, ModelSim saves all coverage data in the current design to the specified
file. If you do specify <instancepath>, ModelSim saves data on that instance, and all
instances below it (recursively), to the specified file.
If set to 1, the [<xml_output>] argument specifies that the output be saved in XML
format.
See Chapter 12 - Code Coverage for more information on Code Coverage.
$init_signal_driver
The $init_signal_driver() system task drives the value of a VHDL signal or Verilog net
onto an existing VHDL signal or Verilog net. This allows you to drive signals or nets at
any level of the design hierarchy from within a Verilog module (e.g., a testbench). See
$init_signal_driver (UM-534) in Chapter 16 - Signal Spy for complete details.
$init_signal_spy
The $init_signal_spy() system task mirrors the value of a VHDL signal or Verilog
register/net onto an existing Verilog register or VHDL signal. This system task allows
you to reference signals, registers, or nets at any level of hierarchy from within a Verilog
module (e.g., a testbench). See $init_signal_spy (UM-537) in Chapter 16 - Signal Spy for
complete details.
$signal_force
The $signal_force() system task forces the value specified onto an existing VHDL signal
or Verilog register or net. This allows you to force signals, registers, or nets at any level
of the design hierarchy from within a Verilog module (e.g., a testbench). A $signal_force
works the same as the force command (CR-176) with the exception that you cannot issue
a repeating force. See $signal_force (UM-539) in Chapter 16 - Signal Spy for complete
details.
$signal_release
The $signal_release() system task releases a value that had previously been forced onto
an existing VHDL signal or Verilog register or net. A $signal_release works the same as
the noforce command (CR-204). See $signal_release (UM-541) in Chapter 16 - Signal Spy.
$sdf_done
This task is a "cleanup" function that removes internal buffers, called MIPDs, that have
a delay value of zero. These MIPDs are inserted in response to the -v2k_int_delay
argument to the vsim command (CR-357). In general the simulator will automatically
remove all zero delay MIPDs. However, if you have $sdf_annotate() calls in your design
that are not getting executed, the zero-delay MIPDs are not removed. Adding the
$sdf_done task after your last $sdf_annotate() will remove any zero-delay MIPDs that
have been created.
ModelSim SE User’s Manual