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E
Timer 2 Mode/Control Register 8-5
InService Register
E bit (Enable RCU) 6-2
description
EN bit (Enable Bit)
Master mode 7-22
Slave mode 7-32
Timer 0 Mode/Control Register 8-3
Timer 1 Mode/Control Register 8-3
Instruction exceptions 7-3
Timer 2 Mode/Control Register 8-5
INT bit (Interrupt Bit)
EN bit (Enable PowerSave Mode) 4-7
Timer 0 Mode/Control Register 8-3
Enable RCU Register
Timer 1 Mode/Control Register 8-3
description 6-2
Timer 2 Mode/Control Register 8-5
Endofinterrupt processing 7-11
INT0 Control Register
EndofInterrupt Register
description
description
Master mode 7-13
Master mode 7-27
INT0 signal (Maskable Interrupt Request 0)
EOI 7-11
definition 3-5
EX bit (Pin Selector) 5-11
INT1 Control Register
EXT bit (External Clock Bit)
description
Timer 0 Mode/Control Register 8-4
Master mode 7-13
Timer 1 Mode/Control Register 8-4
INT1 signal (Maskable Interrupt Request 1)
External interrupt acknowledge bus cycles table 7-7
definition 3-5
INT2 Control Register
description
F
Master mode 7-15
F2-F0 field (Clock Divisor Select) 4-7
INT2 signal (Maskable Interrupt Request 2)
FER bit (Framing Error) 10-4
definition 3-5
Figure
INT3 Control Register
external interrupt acknowledge bus cycles 7-7
description
Fully nested mode interrupt controller connections
7-9
Fully nested mode 7-9
Fully nested mode interrupt controller connections 7-9
Master mode 7-15
INT3 signal (Maskable Interrupt Request 3)
definition 3-6
INT4 Control Register
description
H
HLDA signal (Bus Hold Acknowledge)
definition 3-4
HOLD signal (Bus Hold Request)
definition 3-4
I
Master mode 7-16
INT4 signal (Maskable Interrupt Request 4)
definition 3-6
INTA0 signal (Interrupt Acknowledge 0)
definition 3-5
INTA1 signal (Interrupt Acknowledge 1)
definition 3-6
Interrupt acknowledge 7-7
I4-I0 field (Interrupt InService) 7-22
Interrupt conditions and sequence 7-4
I4-I0 field (Interrupt Mask) 7-24
Interrupt control unit 7-1
I4-I0 field (Interrupt Requests) 7-21
Interrupt controller registers
IF (the interrupt enable flag) 7-2
master mode 7-12
INH bit (Inhibit Bit)
slave mode 7-28
I-4
Timer 0 Mode/Control Register 8-3
Interrupt controller reset conditions 7-8
Timer 1 Mode/Control Register 8-3
Interrupt enable flag (IF) 7-2
Index