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Download SPEAr320 address map and registers
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SPEAr320 Color liquid crystal display controller (CLCD) Table 311. PHERIPHID2 register bit assignments Bit Name Reset value Description [31:08] - - Reserved, read as zero [07:04] Revision 4’h0 These bits read back as 0x0 [03:00] Designer1 4’h4 These bits read back as 0x4 Table 312. PHERIPHID3 register bit assignments 17.2.14 Bit Name Reset value Description [31:08] - - Reserved, read as zero [07:00] Configuration 8’h0 These bits read back as 0x00 PCELLIDID0-3 registers The PCELLIDID0-3 Registers are four 8 bit registers, that span address locations 0xFF00xFFC. The registers can conceptually be treated as a 32 bit register. The register is used as a standard cross-peripheral identification system. The PCELLIDID0 Registers are hard-coded and the fields in the register determine the reset value. Table 313. PCCELLIDIDO register bit assignments Bit Name Reset Value Description [31:08] - - Reserved, read as zero [07:00] PCELLIDID0 8’h0D These bits read back as 0x0D Table 314: PCELLIDID1 register bit assignments Bit Name Reset Value Description [31:08] - - Reserved, read as zero 8’hF0 These bits read as 0xF0 [07:00] PCELLIDID1 Table 315. PCELLIDID2 register bit assignments Bit Name Reset Value Description [31:08] - - Reserved, read as zero [07:00] PCELLIDID2 8’h05 These bits read back as 0x05 Doc ID 022180 Rev 1 283/533
