Download Silicon Power 2 x 2GB DDR3 1600MHz DIMM
Transcript
DDR3 UDIMM w/o ECC Product Specification Features • DDR3 functionality and operations supported as defined in the component data sheet • 240pin, unbuffered dual in-line memory module (UDIMM) • Fast data transfer rates: PC3-8500, PC3-10600, PC3-12800 • Single or Dual rank • 1GB(128 Meg x 64), 2GB (256 Meg x 64), 4GB (512Meg x 64) • V DD = V DDQ = 1.5V ±0.075V • V DDSPD = 3.0V to 3.6V • Reset pin for improved system stability • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) • Fly-by topology • Terminated control, command, and address bus • Adjustable data-output drive strength • Serial presence-detect (SPD) EEPROM • Gold edge contacts • Pb-free 1 Rev. 14 Dec. 2011 DDR3 UDIMM w/o ECC Product Specification Module Specification Bandwidth Data Rate Timing (tCL-tRCD-tRP) PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-12800 DDR3-1600 9-9-9 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-12800 DDR3-1600 11-11-11 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-12800 DDR3-1600 11-11-11 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 SP004GBLTU160S21(2) PC3-12800 DDR3-1600 9-9-9 SP004GBLTU106V21(2) PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 SP004GBLTU160V21(2) PC3-12800 DDR3-1600 11-11-11 SP006GBLTU106S31(2) PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 SP006GBLTU160S31(2) PC3-12800 DDR3-1600 9-9-9 SP006GBLTU106V31(2) PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 SP006GBLTU160V31(2) PC3-12800 DDR3-1600 11-11-11 SP008GBLTU106V21(2) PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 PC3-12800 DDR3-1600 11-11-11 PC3-8500 DDR3-1066 7-7-7 PC3-10600 DDR3-1333 9-9-9 Part Number SP001GBLTU106S01(2) SP001GBLTU133S01(2) SP002GBLTU106S01(2) SP002GBLTU133S01(2) SP002GBLTU160S01(2) SP002GBLTU106V01(2) SP002GBLTU133V01(2) SP002GBLTU160V01(2) SP004GBLTU133V01(2) SP004GBLTU133V01(2) SP004GBLTU160V01(2) SP002GBLTU106S21(2) SP002GBLTU133S21(2) SP003GBLTU106S31(2) SP003GBLTU133S31(2) Module Density & Configuration 1GB (128Mx64) 128Mx8 1Rank 2GB (256Mx64) 128Mx8 2Ranks 2GB (256Mx64) 256Mx8 1Rank 4GB (512Mx64) 256Mx8 2Ranks 1GB x 2 Kit Package 1GB x 3 Kit Package SP004GBLTU106S21(2) SP004GBLTU133S21(2) SP004GBLTU133V21(2) SP006GBLTU133S31(2) SP006GBLTU133V31(2) SP008GBLTU133V21(2) 2GB x 2 Kit Package 2GB x 2 Kit Package 2GB x 3 Kit Package 2GB x 3 Kit Package 4GB x 2 Kit Package SP008GBLTU133V21(2) SP012GBLTU106V31(2) SP012GBLTU133V31(2) 4GB x 3 Kit Package Note: 1. This document supports all LTU Series DDR3 240Pin UDIMM products. 2. Some item was being EOL in this list, Please contact with our sales Dep. 3. All part numbers end with a double-digit code is for customize use only. Example: SP001GBLTU133S02-XX 2 Rev. 14 Dec. 2011 DDR3 UDIMM w/o ECC Product Specification Pin Assignments 240-Pin UDIMM Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VREFDQ VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS NC NC VSS NC NC VSS NC NC VSS NC NC CKE0 VDD BA2 NC VDD A11 A7 VDD A5 A4 VDD Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Symbol A2 VDD CK1 CK1# VDD VDD VREFCA NC VDD A10 BA0 VDD WE# CAS# VDD S1# ODT1 VDD NC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 240-Pin UDIMM Back Pin 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 Vss DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 3 Symbol VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DM3 NC VSS DQ30 DQ31 VSS NC NC VSS NC NC VSS NC NC VSS NC RESET# CKE1 VDD NC NC/A14 VDD A12 A9 VDD A8 A6 VDD A3 Pin 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Symbol A1 VDD VDD CK0 CK0# VDD NC A0 VDD BA1 VDD RAS# S0# VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 Pin 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT Rev. 14 Dec. 2011 DDR3 UDIMM w/o ECC Product Specification Pin Description Symbol Type A0–A14 Input BA0–BA2 Input Description Address inputs: Provide the row address for ACTIVE commands and the column address and auto precharge bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. The address inputs also provide the opcode during mode register command set. A0–A13 (128Mx8) A0–A14 (256Mx8). Bank address inputs: BA0, BA1 define to which device bank an ACTIVE, READ, WRITE, orPRECHARGE command is being applied. BA0, BA1 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates CKE0, CKE1 Input clocking circuitry on the DDR3 SDRAM. Data input mask: DM is an input mask signal for write data. Input data is masked when DM issampled HIGH, along with that input data, during a write access. DM is sampled on both DM0–DM7 Input edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS7pins. On-die termination: ODT (registered HIGH) enables termination resistance internal to the ODT0 DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS# Input ODT1 and DM. The ODT input will be ignored if disabled via the LOAD MODE command. RAS#, CAS#, Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being Input WE# entered. Reset: RESET# is an active LOW CMOS input referenced to V SS . The RESET# input Input RESET# is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 ×V DD and DC (LVCMOS) receiver LOW ≤ 0.2 ×V DD . Chip select: S# enables (registered LOW) and disables (registered HIGH) the command S0#, S1# Input decoder. Presence-detect address inputs: These pins are used to configure the SPD EEPROM SA[2:0] Input address range. Serial clock for presence-detect: SCL is used to synchronize the presence-detect data SCL Input transfer to and from the module. DQ0–DQ63 I/O Data input/output: Bidirectional data bus. DQS0–DQS7 Data strobe: Output with read data, input with write data for source synchronous operation. I/O DQS0#–DQS7# Edge-aligned with read data, center-aligned with write data. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and SDA I/O data into and out of the SPD EEPROM on the module. Power supply: 1.5V ±0.075V. The component V DD and V DDQ are connected to the module V DD Supply V DD . V DDSPD Supply Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V. V REFCA Supply Reference voltage: Control, command, and address (V DD /2). V REFDQ Supply Reference voltage: DQ, DM (V DD /2). V SS Supply Ground. V TT Supply Termination voltage: Used for control, command, and address (V DD /2). NC – No connect: These pins are not connected on the module. NU – Not used: These pins are not used in specific module configuration/operations. CK0, CK0#, CK1, CK1# Input 4 Rev. 14 Dec. 2011 DDR3 UDIMM w/o ECC Product Specification Simplified Mechanical Drawing(x8 1Rank) Note: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note: 2. The dimensional diagram is for reference only. 5 Rev. 14 Dec. 2011 DDR3 UDIMM w/o ECC Product Specification Simplified Mechanical Drawing(x8 2Ranks) Note: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note: 2. The dimensional diagram is for reference only. 6 Rev. 14 Dec. 2011