Download Transcend 512MB DDR266 ECC Unbuffer Memory
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184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 Description Placement The TS64MLD72V6F5 is a 64M x 72bits Double Data Rate SDRAM high-density for DDR266. The TS64MLD72V6F5 consists of 18pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP-II 400mil packages and a 2048 bits serial EEPROM on a 184-pin printed circuit board. The TS64MLD72V6F5 is a Dual In-Line Memory Module and is intended for mounting into 184-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible A on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. B Features • Power supply: VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V • Max clock Freq: 133MHZ. • Double-data-rate architecture; two data transfers per C D clock cycle • Differential clock inputs(CK and /CK) • DLL aligns DQ and DQS transition with CK transition • Auto and Self Refresh 7.8us refresh interval. • Data I/O transactions on both edge of data strobe. • Edge aligned data output, center aligned data input. • Serial Presence Detect (SPD) with serial EEPROM. • SSTL-2 compatible inputs and outputs. • MRS cycle with address key programs. I H G F E PCB : 09- 0920 CAS Latency (Access from column address) : 2.5 Burst Length (2,4,8 ) Data Sequence (Sequential & Interleave) Transcend Information Inc. 1 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 Dimensions Pin Identification Symbol Inches Function Side Millimeters A 133.35±0.20 5.250±0.008 B 72.39 2.850 DQ0~DQ63, C 6.35 0.250000 CB0~CB7 Data Input / Output. D 2.20 0.0870 DQS0~DQS8 Data strobe input/output E 31.75±0.20 1.250±0.00800 CK0, /CK0, F 19.80 0.779 CK1, /CK1 G 4.00 0.157 H 12.00 0.472 I 1.27±0.10 0.050±0.004 A0~A12,BA0,BA1 Address input Clock Input. CK2, /CK2 (Refer Placement) CKE0,CKE1 Clock Enable Input. /CS0,/CS1 Chip Select Input. /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DM0~DM8 Data-in Mask VDD +2.5 Voltage power supply VDDQ +2.5 Voltage Power Supply for DQS VREF Power Supply for Reference VDDSPD +2.5 Voltage Serial EEPROM Power Supply Transcend Information Inc. 2 SA0~SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add/Data input/output VSS Ground NC No Connection 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 Pinouts: Pin Pin Pin No Name No 01 VREF 47 02 DQ0 48 03 VSS 49 04 DQ1 50 05 DQS0 51 06 DQ2 52 07 VDD 53 08 DQ3 54 09 NC 55 10 NC 56 11 VSS 57 12 DQ8 58 13 DQ9 59 14 DQS1 60 15 VDDQ 61 16 *CK1 62 17 */CK1 63 18 VSS 64 19 DQ10 65 20 DQ11 66 21 CKE0 67 22 VDDQ 68 23 DQ16 69 24 DQ17 70 25 DQS2 71 26 VSS 72 27 A9 73 28 DQ18 74 29 A7 75 30 VDDQ 76 31 DQ19 77 32 A5 78 33 DQ24 79 34 VSS 80 35 DQ25 81 36 DQS3 82 37 A4 83 38 VDD 84 39 DQ26 85 40 DQ27 86 41 A2 87 42 VSS 88 43 A1 89 44 *CB0 90 45 *CB1 91 46 VDD 92 * Please refer Block Diagram Transcend Information Inc. Pin Name *DQS8 A0 *CB2 VSS *CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS */CK2 *CK2 VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 3 Pin Name VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 *CKE1 VDDQ NC DQ20 *A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CK0 /CK0 Pin No 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin Name VSS DM8 A10 *CB6 VDDQ *CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDDQ /CS0 */CS1 DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 Block Diagram A0~A12, BA0,BA1 DQ0~DQ7 A0~A12, BA0,BA1 DQ0~DQ7 A0~A12, BA0,BA1 DQ0~DQ7 A0~A12, BA0,BA1 DQ0~DQ7 A0~A12, BA0,BA1 /RAS /RAS 32Mx8 /RAS 32Mx8 /RAS 32Mx8 /RAS 32Mx8 /RAS /CAS /CAS /CAS /CAS CKE DM8 DQS8 /CS CKE DM2 DQS2 /RAS /CAS /WE /CS CKE 32Mx8 DDR SDRAM DM4 DQS4 /CS CKE DM6 DQS6 DM5 DQS5 /RAS /CAS /WE /CS CKE CK,/CK A0~A12, BA0,BA1 DQ0~DQ7 32Mx8 DDR SDRAM DQS 32Mx8 DDR SDRAM CKE DM8 DQS8 DM /WE CK,/CK CK,/CK /CAS DQS /CS CKE /RAS 32Mx8 DDR SDRAM DM /WE A0~A12, BA0,BA1 DQ0~DQ7 DQS CKE DM /CS /RAS /CAS DM 32Mx8 DDR SDRAM DQS /WE CK,/CK /RAS /CAS A0~A12, BA0,BA1 DQ0~DQ7 /WE /CS 32Mx8 DDR SDRAM CB0~ CB7 DM3 DQS3 CK1,/CK1 CK0,/CK0 CK2,/CK2 A0~A12, BA0,BA1 DQ0~DQ7 /RAS /CAS DQS CK,/CK 32Mx8 DDR SDRAM A0~A12, BA0,BA1 DM /WE DM7 DQ0~DQ7 /CAS CK,/CK CK,/CK A0~A12, BA0,BA1 DQ0~DQ7 DQS DM DM DQS CK,/CK DQS CKE CK,/CK CKE DM1 DQS1 DM0 DQS0 /WE /CS DM DQS /WE /CS 32Mx8 DDR SDRAM A0~A12, BA0,BA1 DQ0~DQ7 /RAS 32Mx8 DDR SDRAM /RAS /CAS DQS7 CK,/CK /RAS /CAS A0~A12, BA0,BA1 DQ0~DQ7 DM6 DQS6 DQS /CS CKE CKE CK,/CK 32Mx8 DDR SDRAM DM CKE1 /WE /CS A0~A12, BA0,BA1 DQ0~DQ7 DQS CK,/CK /WE /CS1 CKE 32Mx8 DDR SDRAM DM A0~A12, BA0,BA1 DQ0~DQ7 /RAS /RAS /CAS DM5 DQS5 DQS4 /CAS /WE /CS DM CK,/CK DM4 A0~A12, BA0,BA1 DQ0~DQ7 32Mx8 DDR SDRAM DQS CKE DM /CS /RAS /CAS DM /WE 32Mx8 DDR SDRAM DQS /RAS /CAS A0~A12, BA0,BA1 DQ0~DQ7 CKE CB0~ CB7 DM3 DQS3 CK1,/CK1 CK0,/CK0 CK2,/CK2 A0~A12, BA0,BA1 DQ0~DQ7 /WE /CS 32Mx8 DDR SDRAM DM DQS CK,/CK /CS DQS /WE CK,/CK DDR SDRAM DM DQS DM2 DQS2 DM1 DQS1 DM0 DQS0 CKE CK,/CK CKE /CS DM CKE /CS DDR SDRAM /WE CK,/CK CKE0 /WE DM /CS DDR SDRAM DQS /WE DQS CK,/CK /CAS /WE /CS0 DM /CAS DDR SDRAM DQ0~DQ7 A0~A12, BA0,BA1 DQ0~DQ63 DM7 DQS7 Serial EEPROM SCL SCL A0 SDA A1 SDA A2 SA0 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Transcend Information Inc. 4 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply to Vss VDD, VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55~+150 °C Power dissipation PD 27 W Short circuit current IOS 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85°C/85%, Static Stress °C-% Temperature Cycling Test TC 0°C ~ 125°C Cycling °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) Parameter Symbol Min Max Unit Note Supply voltage VDD 2.3 2.7 V I/O Supply voltage VDDQ 2.3 2.7 V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V 4 Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and /CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and /CK inputs VID(DC) 0.3 VDDQ+0.6 V 3 Input crossing point voltage, CK and /CK inputs VIX(DC) 1.15 1.35 V 5 Input leakage current II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current (Normal strength driver) IOH -16.8 mA VOUT= VTT + 0.84V Output Low Current (Normal strength driver) IOL 16.8 mA VOUT= VTT – 0.84V Output High Current (Half strength driver) IOH -9 mA VOUT= VTT + 0.45V Output High Current (Half strength driver) IOL 9 mA VOUT= VTT - 0.45V Note: 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled. TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of <=3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. Transcend Information Inc. 5 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, VDD=2.7V TA = 10°C) Parameter Symbol Max. Unit Note Operating current - One bank Active-Precharge; tRC=tRCmin; DQ, DM and DQS inputs changing twice per clock cycle; IDD0 1610 mA Address and control inputs changing once per clock cycle Operating current - One bank operation; One bank open, Burst=4; Reads IDD1 1940 mA - Refer to the following page for detailed test condition. Percharge power-down standby current; All banks idle; power –down mode; IDD2P 505 mA CKE = <VIL(max); VIN = VREF for DQ,DQS and DM Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); Address and other control inputs changing once per clock IDD2F 900 mA cycle; VIN = VREF for DQ,DQS and DM Active power - down standby current; one bank active; power-down mode; IDD3P 810 mA CKE<= VIL (max); VIN = VREF for DQ, DQS and DM Active standby current; CS# >= VIH(min); CKE>=VIH(min); One bank active; active - precharge; tRC=tRASmax; IDD3N 1170 mA DQ, DQS and DM inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating current - burst read; Burst length = 2; reads; continuous burst; IDD4R 2565 mA One bank active; address and control inputs changing once per clock cycle; 50% of data changing at every burst; lout = 0 mA Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; IDD4W 3240 mA DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst Auto refresh current; tRC = tRFC(min), IDD5 2565 mA 10*tCK for DDR266at 133Mhz; distributed refresh Self refresh current; CKE <= 0.2V; External clock should be on; IDD6 54 mA Operating current - Four bank operation; IDD7 4140 mA Four bank interleaving with BL=4 -Refer to the following page for detailed test condition 1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ Note: loading capacitor. Transcend Information Inc. 6 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) V 3 VREF - 0.31 V 3 Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V 1 Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 V 2 Note Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS (VDD=2.5, VDDQ=2.5, TA=0 to 70°C) Parameter Input reference voltage for Clock Input signal maximum peak swing Input Levels (VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.5*VDDQ 1.5 VREF+0.31/VREF-0.31 VREF VTT See Load Circuit Unit V V V V V Note Max 87 53 53 34 8 8 8 Unit pF pF pF pF pF pF pF VTT=0.5*VDDQ RT=50ohm Output ZO=50ohm VREF =0.5*VDDQ CLOAD=30pF Output Load circuit Input/Output CAPACITANCE (VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz) Parameter Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE) Input capacitance (CKE0, CKE1) Input capacitance (/CS0, /CS1) Input capacitance (CK0~CK2) Input capacitance (DM0~DM8) Data and DQS input/output capacitance (DQ0~DQ63) Data input/output capacitance (CB0~CB7) Transcend Information Inc. Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 7 Min 69 44 44 27 6 6 6 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 AC Timing Parameters & Specifications (These AC characteristics were tested on the Component) Parameter Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row active to Row active delay Row active to Row active delay Write recovery time Last data in to Read command Col. Address to Col. Address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK /CK Output data access time from CK /CK Data strobe edge to output data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control input setup time Address and Control input hold time Data-out high-impedance time from CK, /CK Data-out low-impedance time from CK, /CK Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Clock half period Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tDSS tDSH tDQSH tDQSL tDSC tIS tIH tHZ tLZ tMRD tDS tDH tDIPW tPDEX tXSNR tXSRD tREF tHP Min 65 75 45 20 20 15 15 1 1 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 -0.75 -0.75 15 0.5 0.5 1.75 7.5 75 200 7.8 tCLmin or tCHmin Max 120K 0.55 0.55 0.75 0.75 0.5 1.1 0.6 1.25 1.1 0.75 0.75 Unit ns ns ns ns ns ns ns tCK tCK ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns tCK us ns Note 2 1 Data hold skew factor tQHS 0.75 ns DQS write postamble time tWPST 0.4 0.6 tCK 3 Note: 1. Maximum burst refresh of 8 2. The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The Maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. Transcend Information Inc. 8 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 SIMPLIFIED TRUTH TABLE COMMAND Extended Register Mode Register Set Register Mode Register Set Auto Refresh Refresh Self Refresh Entry Exit Bank Active & Row Addr. (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) CKEn-1 CKEn /CS /RAS /CAS /WE H X L L L L OP CODE 1,2 X L L L L OP CODE 1,2 L L L H X H H H L L H H H H X X X X L L H H V X L H L H V L H H H Column Address Auto Precharge Enable Column Address Auto Precharge Enable Burst Stop Precharge All Banks Entry X X H X H L Active Power Down Exit Entry L H H L Precharge Power Down Mode L H L H L H L H X X X L V V V X X X X H X X X L H H H H X X X L V V V No Operation Command L 7. 8. 9. Column (A0~A9) V Column Address H (A0~A9) X V L X H 4 4 4 4, 6 7 X 5 X H X H H X X X X X 8 9 X L 5. 6. 3 3 Address H L L H 4. H L 3 3 X Exit DM 1. 2. 3. L Note Row Address L H H Bank Selection A0~A9,A11, A12 L Auto Precharge Disable Write & A10/AP X Auto Precharge Disable Read & Note: BA0,1 H H H 9 OP Code: Operand Code. A0 ~ A12 & BA0 ~ BA1: Program keys. (@EMRS/MRS) EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. Auto refresh functions are same as the CBR refresh of DRAM. The automatic precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. BA0 ~ BA1: Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. During burst write with auto precharge, new read/write command cannot be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. Burst stop command is valid at every burst length. DM sampled at the rising and falling edges of the DQS and Data-in is masked at the both edges (Write DM latency is 0). This combination is not defined for any function, which means "No Operation (NOP)" in DDR SDRAM. Transcend Information Inc. 9 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 Serial Presence Detect Specification Serial Presence Detect Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function Described # of Bytes Written into Serial Memory Total # of Bytes of S.P.D Memory Fundamental Memory Type # of Row Addresses on this Assembly # of Column Addresses on this Assembly # of Module Rows on this Assembly Data Width of this Assembly Data Width of this Assembly VDDQ and Interface Standard of this Assembly DDR SDRAM Cycle Time at CAS Latency=2.5 DDR SDRAM Access Time from Clock at CL=2.5 DIMM configuration type (non-parity, Parity, ECC) Refresh Rate Type Primary DDR SDRAM Width Error Checking DDR SDRAM Width Min Clock Delay for Back to Back Random Column Address Burst Lengths Supported # of banks on each DDR SDRAM device CAS Latency supported CS Latency WE Latency 21 DDR SDRAM Module Attributes 22 DDR SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 DDR SDRAM Cycle Time CL=2.0 DDR SDRAM Access from Clock CL=2.0 DDR SDRAM Cycle Time CL=1.5 DDR SDRAM Access from Clock CL=1.5 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Activate delay (tRRD) Minimum RAS to CAS Delay (tRCD) Minimum active to Precharge time (tRAS) Module ROW density Command/Address Input Setup Time Command/Address Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information SPD Data Revision Code Checksum for Bytes 0-62 Transcend Information Inc. 10 Standard Specification 128bytes 256bytes DDR SDRAM 13 10 2 bank 72bits 0 SSTL 2.5V 7.5ns .0.75ns ECC 7.8us/Self Refresh X8 X8 tCCD=1CLK Vendor Part 80 08 07 0D 0A 02 48 00 04 75 75 02 82 08 08 01 2,4,8 4 bank 2, 2.5 0 CLK 1 CLK Registered address & control inputs and on-card DLL +/-0.2V voltage tolerance 10ns .0.75ns 20ns 15ns 20ns 45ns 256MB 0.9ns 0.9ns 0.5ns 0.5ns - 0E 04 0C 01 02 20 00 A0 75 00 00 50 3C 50 2D 40 90 90 50 50 00 00 D2 184PIN DDR266 Unbuffered DIMM 512MB With 32Mx8 CL2.5 TS64MLD72V6F5 64-71 Manufacturers JEDEC ID 72 Manufacturing Location Transcend T 7F, 4F 54 54 53 36 34 4D 4C 73-90 Manufacturers Part Number TS64MLD72V6F5 44 37 32 56 36 46 35 20 20 20 20 20 91-92 93-94 95-98 99-127 128~255 Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data Unused Storage Locations Transcend Information Inc. By Manufacturer By Manufacturer Undefined 11 Variable Variable -