Download LG Electronics 55LA643V-ZB Flat Panel Television User Manual

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Transcript

Internal Use Only
North/Latin America
Europe/Africa
Asia/Oceania
http://aic.lgservice.com
http://eic.lgservice.com
http://biz.lgservice.com
LED TV
SERVICE MANUAL
CHASSIS : LD34N
MODEL: 55LA965V/W/9
55LA965V/W/9-ZA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL67733213 (1307-REV00)
Printed in Korea
CONTENTS
CONTENTS . ............................................................................................. 2
SAFETY PRECAUTIONS ......................................................................... 3
SERVICING PRECAUTIONS..................................................................... 4
SPECIFICATION........................................................................................ 6
ADJUSTMENT INSTRUCTION............................................................... 13
EXPLODED VIEW .................................................................................. 23
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-2-
LGE Internal Use Only
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by
in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-3-
LGE Internal Use Only
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the
SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the
following servicing precautions and any of the safety precautions
on page 3 of this publication, always follow the safety precautions. Remember: Safety First.
General Servicing Precautions
1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board
module or any other receiver assembly.
b. Disconnecting or reconnecting any receiver electrical plug
or other electrical connection.
c. Connecting a test substitute in parallel with an electrolytic
capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an explosion hazard.
2. Test high voltage only by measuring it with an appropriate
high voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".
3. Do not spray chemicals on or near this receiver or any of its
assemblies.
4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication
of contacts in not required.
5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.
6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks
are correctly installed.
7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.
8. Use with this receiver only the test fixtures specified in this
service manual.
CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.
Electrostatically Sensitive (ES) Devices
Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors
and semiconductor “chip” components. The following techniques
should be used to help reduce the incidence of component damage caused by static by static electricity.
1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder
ES devices.
4. Use only an anti-static type solder removal device. Some solder removal devices not classified as “anti-static” can generate
electrical charges sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate
electrical charges sufficient to damage ES devices.
6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or
comparable conductive material).
7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will
be installed.
CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the
brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity sufficient to damage an ES device.)
General Soldering Guidelines
1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within
the range or 500 °F to 600 °F.
2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.
3. Keep the soldering iron tip clean and well tinned.
4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.
5. Use the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.
(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suctiontype solder removal device or with solder braid.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
(500 °F to 600 °F)
b. First, hold the soldering iron tip and solder the strand
against the component lead until the solder melts.
c. Quickly move the soldering iron tip to the junction of the
component lead and the printed circuit foil, and hold it there
only until the solder flows onto and around both the component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
d. Closely inspect the solder area and remove any excess or
splashed solder with a small wire-bristle brush.
-4-
LGE Internal Use Only
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.
Removal
1. Desolder and straighten each IC lead in one operation by
gently prying up on the lead with the soldering iron tip as the
solder melts.
2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing
the IC.
Replacement
1. Carefully insert the replacement IC in the circuit board.
2. Carefully bend each IC lead against the circuit foil pad and
solder it.
3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).
"Small-Signal" Discrete Transistor
Removal/Replacement
1. Remove the defective transistor by clipping its leads as close
as possible to the component body.
2. Bend into a "U" shape the end of each of three leads remaining on the circuit board.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.
Power Output, Transistor Device
Removal/Replacement
1. Heat and remove all solder from around the transistor leads.
2. Remove the heat sink mounting screw (if so equipped).
3. Carefully remove the transistor from the heat sink of the circuit
board.
4. Insert new transistor in the circuit board.
5. Solder each transistor lead, and clip off excess lead.
6. Replace heat sink.
Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever this condition is encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC connections).
1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).
2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.
4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the
good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.
At Other Connections
Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.
1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly connected to the affected copper pattern.
3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-5-
LGE Internal Use Only
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This specification is applied to the LED TV used LD34N
chassis.
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
- Wireless : Wireless HD Specification (Option)
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 20 minutes prior to
the adjustment.
4. Model General Specification
No.
Item
Specification
Remarks
DTV & Analog (Total 37 countries)
DTV (MPEG2/4, DVB-T) : 30 countries
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece,
Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania,
Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Beralus
DTV (MPEG2/4, DVB-T2) : 8 countries
UK(Ireland), Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan, Russia
1
Market
DTV (MPEG2/4, DVB-C) : 37 countries
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece,
Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania,
Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, BeEU(PAL Market-36Countries)/CIS ralus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan
+ Morocoo(Africa)
DTV (MPEG2/4, DVB-S/S2) : 30 countries
Germany, Netherland, Switzerland, Hungary, Austria, Slovenia, Bulgaria, France, Spain, Italy, Belgium, Russia, Luxemburg, Greece,
Czech, Croatia, Turkey, Moroco, Ireland, Latvia, Estonia, Lithuania,
Poland, Portugal, Romania, Albania, Bosnia, Serbia, Slovakia, Beralus, UK, Sweden, Denmark, Finland, Norway, Ukraine, Kazakhstan
Supported satellite : 29 satellites
ABS1 75.0E/ AMOS 4.0W/ ASIASATS 105.5E/ ASTRA1LHMKR
19.2E/ ASTRA2ABD 28.2E/ ASTRA3AB 23.5E/ ASTRA4A 4.8E/
ATLANTICBIRD2 8.0W/ ATLANTICBIRD3 5.0W/ BADR 26.0E/ EUROBIRD3 33.0E/ EUROBIRD9A 9.0E/ EUTELSATW2A 10.E/ EUTELSATW3A 7.0E/ EUTELSATW4W7 36.0E/ EUTELSESAT 16.0E/
EXPRESSAM1 40.0E/ EXPRESAM3 140.0E/ EXPRESSAM33
96.5E/ HELLASAT2 39.0E/ HISPASAT1CDE 30.0W/ HOTBIRD
13.0E/ INTELSAT10&7 68.5E/ INTELSAT15 85.2E/ INTELSAT904
60.0E/ NILESAT 7.0W/ THOR 0.8W/ TURKSAT 42.0E/ YAMAL201
90.0E
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-6-
LGE Internal Use Only
No.
2
3
Item
Broadcasting system
Program coverage
Specification
Remarks
1) PAL-BG/DK/I/I’
2) SECAM L/L’, DK, BG, I
3) DVB-T/T2, C, S/S2
1 ) Digital TV
- VHF, UHF
- C-Band, Ku-Band
2) Analogue TV
-VHF : E2 to E12
-UHF : E21 to E69
-CATV : S1 to S20
-HYPER : S21 to S47
► DVB-T
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
4
Receiving system
► DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
Analog : Upper Heterodyne
Digital : COFDM, QAM
► DVB-C
- Symbolrate : 4.0Msymbols/s to 7.2 Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM
► DVB-S/S2
- symbolrate :
DVB-S2 (8PSK / QPSK) : 2 ~ 45 Msymbol/s
DVB-S (QPSK) : 2 ~ 45 Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
5
Input Voltage
AC 100 ~ 240 V, 50/60 Hz
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-7-
LGE Internal Use Only
5. External input format
5.1. 2D Mode
(1) Component input(Y, CB/PB, CR/PR)
No.
Resolution
H-freq(kHz)
V-freq(Hz)
1.
720×480
15.73
60.00
SDTV, DVD 480i
2.
720×480
15.63
59.94
SDTV, DVD 480i
3.
720×480
31.47
59.94
480p
4.
720×480
31.50
60.00
480p
5.
720×576
15.625
50.00
SDTV 576i
6.
720×576
31.25
50.00
SDTV 576p
7.
1280×720
45.00
50.00
HDTV 720p
8.
1280×720
44.96
59.94
HDTV 720p
9.
1280×720
45.00
60.00
HDTV 720p
10.
1920×1080
31.25
50.00
HDTV 1080i
11.
1920×1080
33.75
60.00
HDTV 1080i
12.
1920×1080
33.72
59.94
HDTV 1080i
13.
1920×1080
56.250
50
HDTV 1080p
14.
1920×1080
67.5
60
HDTV 1080p
(2) HDMI Input (PC/DTV)
No.
HDMI-PC
1
2
3
4
5
6
7
8
9
10
11
12
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
640*350
720*400
640*480
800*600
1024*768
1152*864
1280*1024
1360*768
1920*1080
3840*2160
3840*2160
3840*2160
31.468
31.469
31.469
37.879
48.363
54.348
63.981
47.712
67.5
67.5
56.25
54.0
70.09
70.08
59.94
60.31
60.00
60.053
60.020
60.015
60.00
30.00
25.00
24.00
25.17
28.32
25.17
40.00
65.00
80
108
85.5
148.5
297.00
297.00
297.00
EGA
DOS
VESA(VGA)
VESA(SVGA)
VESA(XGA)
VESA
VESA(SXGA)
VESA(WXGA)
WUXGA(Reduced Blanking)
UD
UD
UD
720*480
31.47
60
27.027
SDTV 480P
2
720*480
31.47
59.94
27.00
SDTV 480P
3
1280*720
45.00
60.00
74.25
HDTV 720P
4
5
1280*720
1920*1080
44.96
33.75
59.94
60.00
74.176
74.25
HDTV 720P
HDTV 1080I
6
1920*1080
33.72
59.94
74.176
HDTV 1080I
7
1920*1080
67.500
60
148.50
HDTV 1080P
8
9
10
11
12
1920*1080
1920*1080
1920*1080
1920*1080
1920*1080
67.432
27.000
26.97
33.75
33.71
59.939
24.000
23.976
30.000
29.97
148.352
74.25
74.176
74.25
74.176
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
HDTV 1080P
13
3840*2160
67.5
30.00
297.00
UDTV 2160P
14
3840*2160
56.25
25.00
297.00
UDTV 2160P
15
3840*2160
54.0
24.00
297.00
UDTV 2160P
DDC
Х
O
O
O
O
O
O
O
O
HDMI-DTV
1
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-8-
LGE Internal Use Only
5.2. 3D Mode
(1) RF Input(3D supported mode manually)
No.
Resolution
Proposed
1
HD - DTV
1080I
720P
SD - DTV
576P
576I
2
3
3D input proposed mode
2D to 3D
Side by Side(Half)
Top & Bottom
SD - ATV(CVBS/SCART)
(2) RF Input(3D supported mode automatically)
No.
Signal
1
Frame Compatible
3D input proposed mode
Side by Side(Half),
Top & Bottom
(3) HDMI 1.3 (3D supported mode manually)
No
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
1
720*480
31.5
60
27.03
SDTV 480P
2
720*576
31.25
50
27
SDTV 576P
3
1280*720
45.00
60.00
74.25
HDTV 720P
4
1280*720
37.500
50
74.25
HDTV 720P
5
1920*1080
33.75
60.00
74.25
HDTV 1080I
6
1920*1080
28.125
50.00
74.25
HDTV 1080I
7
1920*1080
27.00
24.00
74.25
HDTV 1080P
8
1920*1080
28.12
25
74.25
HDTV 1080P
9
1920*1080
33.75
30.00
74.25
HDTV 1080P
10
1920*1080
67.50
60.00
148.5
HDTV 1080P
11
1920*1080
56.250
50
148.5
HDTV 1080P
53.95
23.976
297.00
54
24.00
296.703
56.25
25.00
297.00
61.43
29.970
297.00
67.5
30.00
296.703
12
3840*2160
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
HDTV 2160P
-9-
3D input proposed mode
2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Frame Sequential, Row
Interleaving, Column Interleaving
2D to 3D, Side by Side(Half), Top & Bottom
2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Row Interleaving, Column
Interleaving
2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Single Frame Sequential,
Row Interleaving, Column Interleaving
2D to 3D,
Top & Bottom(half), Side by Side(half)
LGE Internal Use Only
(4) HDMI 1.4b (3D supported mode automatically)
No.
Resolution
1
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
VIC
3D input proposed mode
Top-and-Bottom
Side-by-side(half)
Frame packing
Line alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Line alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Line alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Field alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Line alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Line alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Field alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Field alternative
Side-by-side(Full)
Proposed
Secondary(SDTV 480P)
Secondary(SDTV 480P)
Secondary(SDTV 480P)
(SDTV 480P)
(SDTV 480P)
Secondary(SDTV 480P)
Secondary(SDTV 480P)
Secondary(SDTV 480P)
(SDTV 480P)
(SDTV 480P)
Secondary(SDTV 576P)
Secondary(SDTV 576P)
Secondary(SDTV 576P)
(SDTV 576P)
(SDTV 576P)
Primary(HDTV 720P)
Primary(HDTV 720P)
Primary(HDTV 720P)
(HDTV 720P)
(HDTV 720P)
Primary(HDTV 720P)
Primary(HDTV 720P)
Primary(HDTV 720P)
(HDTV 720P)
(HDTV 720P)
Secondary(HDTV 1080I)
Primary(HDTV 1080I)
Primary(HDTV 1080I)
(HDTV 1080I)
(HDTV 1080I)
Secondary(HDTV 1080I)
Primary(HDTV 1080I)
Primary(HDTV 1080I)
(HDTV 1080I)
(HDTV 1080I)
Primary(HDTV 1080P)
Primary(HDTV 1080P)
Primary(HDTV 1080P)
(HDTV 1080P)
(HDTV 1080P)
31.469 / 31.5
59.94/ 60
25.125/25.2
1
62.938/63
59.94/ 60
50.35/50.4
1
3
31.469 / 31.5
59.94/ 60
50.35/50.4
1
4
31.469 / 31.5
59.94 / 60
27.00/27.03
2,3
62.938/63
59.94 / 60
54/54.06
2,3
6
31.469 / 31.5
59.94 / 60
54/54.06
2,3
7
31.25
50
27
17,18
62.5
50
54
17,18
9
31.25
50
54
17,18
10
37.500
50
74.25
19
11
75
50
148.5
19
37.500
50
148.5
19
44.96 / 45
59.94 / 60
74.18/74.25
4
14
89.91/90
59.94 / 60
148.35/148.5
4
15
44.96 / 45
59.94 / 60
148.35/148.5
4
16
33.72 / 33.75
59.94 / 60
74.18/74.25
5
17
67.432/67.50
59.94 / 60
148.35/148.5
5
18
33.72 / 33.75
59.94 / 60
148.35/148.5
5
19
28.125
50.00
74.25
20
20
56.25
50.00
148.5
20
21
28.125
50.00
148.5
20
22
26.97 / 27
23.97 / 24
74.18/74.25
32
23
43.94/54
23.97 / 24
148.35/148.5
32
26.97 / 27
23.97 / 24
148.35/148.5
32
25
28.12
25
74.25
33
Top-and-Bottom
Side-by-side(half)
Primary(HDTV 1080P)
Primary(HDTV 1080P)
26
56.24
25
148.5
33
Frame packing
Line alternative
Primary(HDTV 1080P)
(HDTV 1080P)
27
28.12
25
148.5
33
28
33.716 / 33.75
29.976 / 30.00
74.18/74.25
34
29
67.432 / 67.5
29.976 / 30.00
148.35/148.5
34
30
33.716 / 33.75
29.976 / 30.00
148.35/148.5
34
31
56.250
50
148.5
31
32
67.43 / 67.5
59.94 / 60
148.35/148.50
16
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Frame packing
Line alternative
Side-by-side(Full)
Top-and-Bottom
Side-by-side(half)
Top-and-Bottom
Side-by-side(half)
(HDTV 1080P)
Secondary(HDTV 1080P)
Secondary(HDTV 1080P)
Secondary(HDTV 1080P)
(HDTV 1080P)
(HDTV 1080P)
Primary(HDTV 1080P)
Secondary(HDTV 1080P)
Primary(HDTV 1080P)
Secondary(HDTV 1080P)
2
5
8
12
13
24
640*480
720*480
720*576
1280*720
1920*1080
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 10 -
LGE Internal Use Only
(5) HDMI-PC Input (3D) (3D supported mode manually)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
3D input proposed mode
Proposed
1
1024*768
48.36
60
65
2D to 3D, Side by Side(half)
Top & Bottom
HDTV 768P
2
1360*768
47.71
60
85.5
2D to 3D, Side by Side(half)
Top & Bottom
HDTV 768P
HDTV 1080P
3
1920*1080
67.500
60
148.50
2D to 3D, Side by Side(half)
Top & Bottom, Checker Board,
Single Frame Sequential,
Row Interleaving,
Column Interleaving
4
3840*2160
54
56.25
67.5
24
25
30
296.703
297
296.703
HDTV 2160P
2D to 3D,
Top & Bottom(half),
Side by Side(half),
2D to 3D
640*350
720*400
640*480
800*600
1152*864
5
3840*2160
-
-
-
(6) Component Input ( 3D) (3D supported mode manually)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock
3D input proposed mode
Proposed
1
1280*720
37.5
50
74.25
2D to 3D, Side by Side(half), Top & Bottom
HDTV 720P
2
1280*720
45.00
60.00
74.25
2D to 3D, Side by Side(half), Top & Bottom
HDTV 720P
3
1280*720
44.96
59.94
74.176
2D to 3D, Side by Side(half), Top & Bottom
HDTV 720P
4
1920*1080
33.75
60.00
74.25
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080I
5
1920*1080
33.72
59.94
74.176
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080I
6
1920*1080
28.12
50
74.25
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080I
7
1920*1080
67.500
60
148.50
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080P
8
1920*1080
67.432
59.94
148.352
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080P
9
1920*1080
27.000
24.000
74.25
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080P
10
1920*1080
28.12
25
74.25
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080P
11
1920*1080
56.25
50
74.25
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080P
12
1920*1080
26.97
23.976
74.176
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080P
13
1920*1080
33.75
30.000
74.25
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080P
14
1920*1080
33.71
29.97
74.176
2D to 3D, Side by Side(half), Top & Bottom
HDTV 1080P
(7) USB, DLNA - Movie (3D) (3D supported mode manually)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
1
Under 704x480
-
-
-
2D to 3D
2
Over 704x480
interlaced
-
-
-
2D to 3D, Side by Side(Half), Top & Bottom
-
50 / 60
-
2D to 3D, Side by Side(Half), Top & Bottom, Checker Board,
Row Interleaving, Column Interleaving, Frame Sequential
-
others
-
2D to 3D, Side by Side(Half), Top & Bottom, Checker Board,
Row Interleaving, Column Interleaving
3
4
Over 704x480
progressive
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 11 -
3D input proposed mode
LGE Internal Use Only
(8) USB, DLNA -Photo (3D) (3D supported mode manually)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
3D input proposed mode
1
Under 320x240
-
-
-
2D to 3D
2
Over 320x240
-
-
-
2D to 3D, Side by Side(Half), Top & Bottom
(9) USB, DLNA (3D) (3D supported mode automatically)
No.
1
Resolution
H-freq(kHz)
1080p
33.75
V-freq.(Hz)
Pixel clock(MHz)
30
3D input proposed mode
Side by Side(Half), Top & Bottom, Checker
Board, MPO(Photo), JPS(Photo)
74.25
(10) Miracast, Widi (3D supported mode manually)
No.
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
1
1024x768p
Resolution
-
30 / 60
-
2.
1280x720p
-
30 / 60
-
3
1920x1080p
4
Others
3D input proposed mode
2D to 3D, Side by Side(Half), Top & Bottom
30 / 60
-
2D to 3D
■ Remark: 3D Input mode
No.
Side by Side
Top & Bottom
Checker board
Single Frame
Sequential
Frame
Packing
Line
Interleaving
Column
Interleaving
2D to 3D
1
ii.
iii.
iv.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
v.
- 12 -
vi.
LGE Internal Use Only
ADJUSTMENT INSTRUCTION
1. Application Range
3.1.3. Adjustment
(1) Adjustment method
- U sing RS-232, adjust items in the other shown in
"3.1.3.3)"
This specification sheet is applied to all of the LED TV with
LD34N chassis.
(2) Adj. protocol
2. Designation
Protocol
(1) Because this is not a hot chassis, it is not necessary to
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
humidity if there is no specific designation.
(4) The input voltage of the receiver must keep AC 100-240
V~, 50/60 Hz.
(5) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15.
a 00 OK00x
Source change
xb 00 04
xb 00 06
b 00 OK04x (Adjust 480i, 1080p Comp1 )
b 00 OK06x (Adjust 1920*1080 SCART RGB)
Begin adj.
ad 00 10
OKx (Case of Success)
NGx (Case of Fail)
(main)
ad 00 20
(main)
000000000000000000000000007c007b006dx
(sub )
ad 00 21
(Sub)
000000070000000000000000007c00830077x
Confirm adj.
ad 00 99
NG 03 00x (Fail)
NG 03 01x (Fail)
NG 03 02x (Fail)
OK 03 03x (Success)
End adj.
aa 00 90
a 00 OK90x
Read adj. data
Ref.) ADC Adj. RS232C Protocol_Ver1.0
(3) Adj. order
- aa 00 00 [Enter ADC adj. mode]
- xb 00 04 [Change input source to Component1 (480i&
1080p)]
- ad 00 10 [Adjust 480i&1080p Comp1]
- xb 00 06 [Change input source to RGB(1024*768)]
- ad 00 10 [Adjust 1920*1080 SCART RGB]
- ad 00 90 End adj.
In case of keeping module is in the circumstance of below
-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.
3. Automatic Adjustment
Set ACK
aa 00 00
Return adj. result
In case of keeping module is in the circumstance of 0 °C, it
should be placed in the circumstance of above 15 °C for 2
hours.
[Caution]
When still image is displayed for a period of 20 minutes or
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.
Command
Enter adj. mode
3.2. M
AC address D/L, CI+ key D/L, Widevine
key D/L, ESN key D/L, HDCP key D/L,
DTCP key D/L
Connect: PCBA Jig → RS-232C Port== PC → RS-232C Port
Communication Prot connection
3.1. ADC Adjustment
3.1.1. Overview
ADC adjustment is needed to find the optimum black level
and gain in Analog-to-Digital device and to compensate RGB
deviation.
3.1.2. Equipment & Condition
(1) USB to RS-232C Jig
(2) M SPG-925 Series Pattern Generator (MSPG-925FA,
pattern - 65)
- Resolution :480i Comp1
1080P Comp1
1920*1080P SCART RGB
- Pattern : Horizontal 100% Color Bar Pattern
- Pattern level : 0.7 ± 0.1 Vp-p
- Image
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 13 -
▪ Com 1,2,3,4 and 115200(Baudrate)
Mode check: Online Only
▪ Check the test process: DETECT → MAC → CI → Widevine
→ ESN → HDCP → DTCP
▪ Play: START
▪ Result: Ready, Test, OK or NG
▪ Printer Out (MAC Address Label)
LGE Internal Use Only
3.3. LAN Inspection
3.4. LAN PORT INSPECTION(PING TEST)
Connect SET → LAN port == PC → LAN Port
3.3.1. Equipment & Condition
SET
▪ Each other connection to LAN Port of IP Hub and Jig
PC
3.4.1. Equipment setting
(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program.
*IP Number : 12.12.2.2
3.4.2. LAN PORT inspection(PING TEST)
3.3.2. LAN inspection solution
▪ LAN Port connection with PCB
▪ Network setting at MENU Mode of TV
▪ Setting automatic IP
▪ Setting state confirmation
→ If automatic setting is finished, you confirm IP and MAC
Address.
(1) Play the LAN Port Test Program.
(2) Connect each other LAN Port Jack.
(3) Play Test (F9) button and confirm OK Message.
(4) Remove LAN cable.
3.3.3. WIDEVINE key Inspection
- Confirm key input data at the "IN START" MENU Mode.
3.3.4. DTCP Inspection
- Confirm Key input at the “IN START” MENU Mode
- Below DTCP check on “IN START” MENU is enabled only
for Models which “DTCP key” tool option is “ON”
- O nly EU suffix models DTCP key option is on. (ex.
47LA790V-ZA.KEUYLJG)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 14 -
LGE Internal Use Only
3.5. Model name & Serial number Download
2) Check the key download for transmitted command
(RS232: ci 00 10)
3.5.1. Model name & Serial number D/L
Press "Power on" key of service remote control.
(Baud rate : 115200 bps)
▪ Connect RS-232C Signal to USB Cable to USB.
▪ Write Serial number by use USB port.
▪ Must check the serial number at Instart menu.
▪
CMD 1
CMD 2
C
I
Data 0
1
0
3) Result value
- Normally status for download : OKx
- Abnormally status for download : NGx
3.5.2. Method & notice
(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing
Technology Group.
(3) Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0.
3.6.2. Check the method of CI+ key value(RS232)
1) Into the main ass’y mode(RS232: aa 00 00)
CMD 1
CMD 2
A
A
Data 0
0
0
2) Check the mothed of CI+ key by command
(RS232: ci 00 20)
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or service man, sometimes
model name or serial number is initialized.(Not always)
It is impossible to download by bar code scan, so It need
Manual download.
1) Press the "Instart" key of Adjustment remote control.
2) Go to the menu "7.Model Number D/L" like below photo.
3) Input the Factory model name(ex 47LM960V-ZB) or Serial
number like photo.
CMD 1
CMD 2
C
I
Data 0
2
0
3) Result value
i 01 OK 1d1852d21c1ed5dcx
CI+ Key Value
3.7. WIFI MAC ADDRESS CHECK
(1) Using RS232 Command
Transmission
H-freq(kHz)
V-freq.(Hz)
[A][I][][Set ID][][20][Cr]
[O][K][X] or [NG]
(2) Check the menu on in-start
4) Check the model name Instart menu. → Factory name
displayed. (ex 47LM960V-ZB)
5) C heck the Diagnostics.(DTV country only) → Buyer
model displayed. (ex 47LM960V-ZB)
3.6. CI+ Key checking method
* Check the Section 3.2
Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).
=> Check the Download to CI+ Key value in LGset.
3.6.1. Check the method of CI+ Key value
(1) Check the method on Instart menu
(2) Check the method of RS232C Command
1) Into the main ass’y mode(RS232: aa 00 00)
CMD 1
CMD 2
A
A
Data 0
0
0
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 15 -
LGE Internal Use Only
4. Manual Adjustment
* ADC adjustment is not needed because of OTP(Auto ADC
adjustment)
ⓓ Model Name(Hex): LGTV
Cf) TV set’s model name in EDID data is below.
MODEL NAME
MODEL NAME(HEX)
LG TV
00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 (LG TV)
4.1. EDID(The Extended Display Identification
Data)/DDC(Display Data Channel) download
ⓔ Checksum(LG TV): Changeable by total EDID data.
4.1.1. Overview
FHD
EDID C/S data
It is a VESA regulation. A PC or a MNT will display an optimal
resolution through information sharing without any necessity
of user input. It is a realization of "Plug and Play".
HDMI
Block 0
check sum (Hex)
4.1.2. Equipment
42
23 (HDMI1)
Block 1
13 (HDMI2)
ⓕ Vendor Specific(HDMI)
- Since embedded EDID data is used, EDID download JIG,
HDMI cable and D-sub cable are not need.
- Adjustment remote control
INPUT
MODEL NAME(HEX)
HDMI1
78030C001000801E
HDMI2
78030C002000801E
4.1.3. Download method
(1) Press "ADJ" key on the Adjustment remote control then
select "12.EDID D/L", By pressing "Enter" key, enter EDID
D/L menu.
(2) S elect "Start" button by pressing "Enter" key, HDMI1/
HDMI2/ HDMI3 are writing and display OK or NG.
(1) EDID
# HDMI 1(C/S : E8 81)
EDID Block 0, Bytes 0-127 [00H-7FH]
00
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
00
FF
FF
FF
FF
FF
FF
00
1E
6D
01
00
01
01
01
01
For HDMI EDID
10
01
17
01
03
80
A0
5A
78
0A
EE
91
A3
54
4C
99
26
DVI-D to HDMI or HDMI to HDMI
20
0F
50
54
A1
08
00
31
40
45
40
61
40
71
40
81
80
2C
30
01
01
01
01
01
01
02
3A
80
18
71
38
2D
40
58
40
45
00
40
84
63
00
00
1E
66
21
50
B0
51
00
1B
30
50
40
70
36
00
40
84
63
00
00
1E
00
00
00
FD
00
3A
60
3E
1E
53
10
00
0A
20
20
20
20
20
20
00
00
00
FC
70
00
4C
47
20
54
56
0A
20
20
20
20
20
20
20
01
E8
EDID Block 1, Bytes 128-255 [80H-FFH]
4.1.4. EDID DATA
▪ HDMI
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
0x00
00
0x01
FF
FF
FF
FF
FF
FF
00
1E
6D
ⓐ
ⓑ
01
03
80
A0
5A
78
0A
EE
91
A3
54
4C
99
26
0x02 0F
50
54
A1
08
00
31
40
45
40
61
40
71
40
81
80
0x03
01
01
01
01
01
01
02
3A
80
18
71
38
2D
40
58
2C
0x04
45
00
40
84
63
00
00
1E
66
21
50
B0
51
00
1B
30
0x05
40
70
36
00
40
84
63
00
00
1E
00
00
00
FD
00
3A
0x06 3E
1E
53
10
00
0A
20
20
20
20
20
20
01
ⓔ1
13
05
14
03
02
20
21
07
50
09
57
07
ⓒ
0x07
02
03
3A
F1
4E
10
9F
04
0x01
22
15
01
29
3D
06
C0
15
0x02
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
80
02
03
3E
F1
4E
10
9F
04
13
05
14
03
02
12
20
21
90
22
15
01
29
3D
06
C0
15
07
50
09
57
07
7C
03
0C
A0
00
10
00
B8
3C
20
C0
8E
01
02
03
04
01
4F
3F
FC
B0
08
10
18
10
06
10
16
10
28
10
E3
05
03
01
02
3A
C0
80
18
71
38
2D
40
58
2C
45
00
40
84
63
00
00
1E
D0
01
1D
80
18
71
1C
16
20
58
2C
25
00
40
84
63
00
E0
00
9E
01
1D
00
72
51
D0
1E
20
6E
28
55
00
40
84
F0
63
00
00
1E
00
00
00
00
00
00
00
00
00
00
00
E0
# HDMI 2(C/S : E8 D0)
EDID Block 0, Bytes 0-127 [00H-7FH]
ⓓ
ⓓ
0x00
0
12
ⓕ
00
ⓕ
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
00
FF
FF
FF
FF
FF
FF
00
1E
6D
01
00
01
01
01
01
26
E3
05
03
01
02
3A
80
18
71
38
10
01
17
01
03
80
A0
5A
78
0A
EE
91
A3
54
4C
99
0x04 2D
40
58
2C
45
00
40
84
63
00
00
1E
01
1D
80
18
0x05
71
1C
16
20
58
2C
25
00
40
84
63
00
00
9E
01
1D
20
0F
50
54
A1
08
00
31
40
45
40
61
40
71
40
81
80
0x06
00
72
51
D0
1E
20
6E
28
55
00
40
84
63
00
00
1E
30
01
01
01
01
01
01
02
3A
80
18
71
38
2D
40
58
2C
0x07
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ⓕ
▪ Detail EDID Options are below
- HDMI1 ~ HDMI3
- In the data of EDID, bellows may be different by S/W or
Input mode.
ⓐ Product ID
MODEL NAME
HEX
EDID Table
DDC Function
HD/FHD Model
0001
01 00
Analog/Digital
ⓑ Serial No: Controlled on production line.
ⓒ Month, Year: Controlled on production line:
ex) Monthly : ‘01’ → ‘01’, Year : ‘2013’ → ‘17’
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 16 -
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LGE Internal Use Only
4.2.4. Equipment connection MAP
# HDMI 3(C/S : E8 C0)
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E8
Co lo r Analyzer
RS -232C
Probe
Co m p ut er
RS -232C
RS -232C
Pat t ern Generat o r
Signal Source
* If TV internal pattern is used, not needed
4.2.5. Adj. Command (Protocol)
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C0
<Command Format>
START 6E
A
A LEN A 03
A
CMD
A
00
A
VAL
A
CS STOP
▪ RS-232C Command used during auto-adjustment.
4.2. White Balance Adjustment
4.2.1. Overview
▪ W/B adj. Objective & How-it-works
(1) Objective: To reduce each Panel's W/B deviation
(2) How-it-works : When R/G/B gain in the OSD is at 192, it
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one
of R/G/B is fixed at 192, and the other two is lowered to
find the desired value.
(3) Adjustment condition : normal temperature
1) Surrounding Temperature : 25 °C ± 5 °C
2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
4) B efore White balance adjustment, Keep power on
status, don’t power off
4.2.2. Adj. condition and cautionary items
(1) Lighting condition in surrounding area surrounding lighting
should be lower 10 lux. Try to isolate adj. area into dark
surrounding.
(2) Probe location: Color Analyzer (CA-210) probe should be
within 10cm and perpendicular of the module surface
(80°~ 100°)
(3) Aging time
1) After Aging Start, Keep the Power ON status during 5
Minutes.
2) In case of LCD, Back-light on should be checked using
no signal or Full-white pattern.
RS-232C COMMAND
[CMD
ID DATA]
wb
00
00
wb
00
10
wb
00
1f
wb
00
20
wb
00
2f
wb
(1) Color Analyzer: CA-210 (LED Module : CH 14)
(2) Adjustment Computer(During auto adj., RS-232C protocol
is needed)
(3) Adjustment Remote control
(4) Video Signal Generator MSPG-925F 720p/216-Gray
(Model: 217, Pattern: 49)
→ Only when internal pattern is not available
▪ Color Analyzer Matrix should be calibrated using CS-100.
- 17 -
00
ff
Explantion
Begin White Balance adjustment
Gain adjustment(internal white pattern)
Gain adjustment completed
Offset adjustment(internal white pattern)
Offset adjustment completed
End White Balance adjustment
(internal pattern disappears )
Ex)
wb 00 00 -> Begin white balance auto-adj.
wb 00 10 -> Gain adj.
ja 00 ff -> Adj. data
jb 00 c0
...
...
wb 00 1f → Gain adj. completed
*(wb 00 20(Start), wb 00 2f(end)) → Off-set adj.
wb 00 ff → End white balance auto-adj.
▪ Adj. Map
Adj. item
Cool
4.2.3. Equipment
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
50
- LEN: Number of Data Byte to be sent
- CMD: Command
- VAL: FOS Data value
- CS: Checksum of sent data
- A: Acknowledge
Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
Medium
Warm
R Gain
G Gain
B Gain
R Cut
G Cut
B Cut
R Gain
G Gain
B Gain
R Cut
G Cut
B Cut
R Gain
G Gain
B Gain
R Cut
Command
(lower caseASCII)
CMD1
CMD2
j
g
j
h
j
i
Data Range
(Hex.)
MIN
MAX
00
C0
00
C0
00
C0
j
j
j
a
b
c
00
00
00
C0
C0
C0
j
j
j
d
e
f
00
00
00
C0
C0
C0
Default
(Decimal)
G Cut
LGE Internal Use Only
4.2.6. Adj. method
How to adjust
1. If G gain is adjusted over 172 and R gain and B gain
less than 192 , Adjust is O.K.
2. If G gain is less than 172 , increase G gain by up to
172, and then increase R gain and B gain same
amount of increasing G gain.
3. If R gain or B gain is over 255 , Readjust G gain less
than 172, Conform to R gain is 255 or B gain is 255
(1) Auto adj. method
1) Set TV in adj. mode using POWER ON key.
2) Zero calibrate probe then place it on the center of the
Display.
3) Connect Cable.(RS-232C to USB)
4) Select mode in adj. Program and begin adj.
5) When adj. is complete (OK Sign), check adj. status pre
mode. (Warm, Medium, Cool)
6) Remove probe and RS-232C cable to complete adj.
▪ W/B Adj. must begin as start command “wb 00 00” , and
finish as end command “wb 00 ff”, and Adj. offset if need.
(2) Manual adjustment method (LA965x)
1) Set TV in Adj. mode using POWER ON.
2) Zero Calibrate the probe of Color Analyzer, then place it
on the center of LCD module within 10 cm of the
surface.
3) Press ADJ key → EZ adjust using adj. R/C → 9. WhiteBalance then press the cursor to the right(key ►). When
right key(►) is pressed 216 Gray internal pattern will be
displayed
4) Adjust Cool modes
a. Fix the one of R/G/B gain to 192 (default data) and
decrease the others. (If G gain is adjusted over 172
and R and B gain less than 192 , Adjust is O.K.)
b. If G gain is less than 172, Increase G gain by up to
172, and then increase R gain and G gain same
amount of increasing G gain.
c. If R gain or B gain is over 255, Readjust G gain less
than 172, Conform to R gain is 255 or B gain is 255
5) Adjust two modes(Medium/Warm) Fix the one of R/G/B
gain to 192(default data) and decrease the others.
6) Adjustment is completed, Exit adjust mode using “EXIT”
key on Remote control.
▪ If internal pattern is not available, use RF input. In EZ Adj.
menu 6.White Balance, you can select one of 2 Testpattern: ON, OFF. Default is inner(ON). By selecting OFF,
you can adjust using RF signal in 206 Gray pattern.
* CASE Medium / Warm
First adjust the coordinate far away from the target
value(x, y).
1. x, y > target
i) Decrease the R, G.
2. x, y < target
i) First decrease the B gain,
ii) Decrease the one of the others.
3. x > target, y < target
i) F
irst decrease B, so make y a little more than the target.
ii) Adjust x value by decreasing the R
4. x < target, y > target
i) F
irst decrease B, so make x a little more than the target.
ii) Adjust y value by decreasing the G
▪ Adjustment condition and cautionary items
1) Lighting condition in surrounding area
Surrounding lighting should be lower 10 lux. Try to
isolate adj. area into dark surrounding.
2) Probe location
: Color Analyzer(CA-210) probe should be within 10 cm
and perpendicular of the module surface (80° ~ 100°)
3) Aging time
- After Aging Start, Keep the Power ON status during 5
Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern.
4.2.7. Reference (White balance Adj. coordinate and
color temperature)
* CASE Cool
First adjust the coordinate far away from the target
value(x, y).
1. x, y > target
i) Decrease the R, G.
2. x, y < target
i) First decrease the B gain,
3. x > target, y < target
i) First decrease B, so make y a little more than the target.
ii) Adjust x value by decreasing the R
4. x < target, y > target
i) First decrease B, so make x a little more than the target.
ii) Adjust x value by decreasing the G
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 18 -
▪ Luminance : 216 Gray
▪ Standard color coordinate and temperature using CS-1000
(over 26 inch)
Coordinate
Mode
Temp
∆uv
x
y
Cool
0.271
0.270
13000 K
0.0000
Medium
0.285
0.293
9300 K
0.0000
Warm
0.310
0.325
6500 K
0.0000
▪ Standard color coordinate and temperature using CA-210(CH 18)
Mode
Coordinate
x
y
Temp
∆uv
Cool
0.271 ± 0.002
0.270 ± 0.002
13000 K 0.0000
Medium
0.285 ± 0.002
0.293 ± 0.002
9300 K
0.0000
Warm
0.310 ± 0.002
0.325 ± 0.002
6500 K
0.0000
LGE Internal Use Only
4.2.8. EDGE LED White balance table
(1) EDGE LED module change color coordinate because of
aging time.
(2) Apply under the color coordinate table, for compensated
aging time.
(3) Normal line(Edge, Direct)
- Gumi (Mar ~ Dec) & Global
X
271
y
270
Medium
x
y
285
293
Warm
x
y
313
329
0-2
281
287
295
310
320
342
3-5
280
285
294
308
319
340
6-9
10-19
20-35
36-49
50-79
80-119
Over 120
278
276
275
274
273
272
271
284
281
277
274
272
271
270
292
290
289
288
287
286
285
307
304
300
297
295
294
293
317
315
314
313
312
311
310
339
336
332
329
327
326
325
X
271
y
270
Medium
x
y
285
293
Warm
x
y
313
329
NC4.0
Aging time
(Min)
1
2
3
4
5
6
7
8
9
Cool
(4) Aging Chamber
NC4.0
Aging time
(Min)
Cool
1
0-5
280
285
294
308
319
340
2
6-10
276
280
290
303
315
335
3
4
5
6
7
8
9
11-20
21-30
31-40
41-50
51-80
81-119
Over 120
272
269
267
266
265
264
264
275
272
268
265
263
261
260
286
283
281
280
279
278
278
298
295
291
288
286
284
283
311
308
306
305
304
303
303
330
327
323
320
318
316
315
X
271
y
270
Medium
x
y
285
293
0-2
283
292
297
315
322
347
3-5
282
290
296
313
321
345
6-9
10-19
20-35
36-49
50-79
80-119
Over 120
280
277
275
274
273
272
271
288
284
279
275
272
271
270
294
291
289
288
287
286
285
311
307
302
298
295
294
293
319
316
314
313
312
311
310
343
339
334
330
327
326
325
X
271
y
270
Medium
x
y
285
293
Warm
x
y
313
329
NC4.0
Aging time
(Min)
1
2
3
4
5
6
7
8
9
Warm
x
313
y
329
Step 1) Turn on TV.
Step 2) Press “TILT” key on the Adj. R/C
Step 3) At the Local Dimming mode, module Edge Backlight
moving left to right. Back light of IOP module moving
Step 4) confirm the Local Dimming mode.
Step 5) Press “exit” key.
4.4. Magic Motion Remote control test
(1) Equipment : RF Remote control for test, IR-KEY-Code
Remote control for test
(2) You must confirm the battery power of RF-Remote control
before test(recommend that change the battery per every lot)
(3) Sequence (test)
1) if you select the "Start(Mute)" key on the Adjustment
remote control, you can pairing with the TV SET.
2) You can check the cursor on the TV Screen, when select
the "OK" key on the Adjustment remote control.
3) You must remove the pairing with the TV Set by select
"OK" key + "Mute" key on the Adjustment remote control
for 5 seconds.
(5) Gumi winter table(Jan, Fab) - Gumi producing model use only
(Normal line)
Cool
4.3. Local Dimming Function Check
4.5. 3D function test
(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
* HDMI mode NO. 872 , pattern No.83
(1) Please input 3D test pattern like below.
(aging chamber)
NC4.0
Aging time
(Min)
Cool
1
0-5
280
285
294
308
319
340
2
6-10
276
280
290
303
315
335
(2) When 3D OSD appear automatically, then select OK key.
3
4
5
6
7
8
9
11-20
21-30
31-40
41-50
51-80
81-119
Over 120
272
269
267
266
265
264
264
275
272
268
265
263
261
260
286
283
281
280
279
278
278
298
295
291
288
286
284
283
311
308
306
305
304
303
303
330
327
323
320
318
316
315
(3) Don't wear a 3D Glasses, check the picture like below.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 19 -
LGE Internal Use Only
4.6. Wi-Fi Test
4.8. Inspection of light scattering
Step 1) Turn on TV
Step 2) Select Network Connection option in Network Menu.
▪ Test Method
Step 3) Select Start Connection button in Network Connection.
(1) Push “Power only” key.
(2) Push “HDMI” hot key.
(3) Inspect whether light scattering is occurred in internal
black pattern or not.
(4) Push “Power only” key.
4.9. Option selection per country
Step 4) If the system finds any AP like blow PIC, it is working
well.
4.9.1. Overview
- Option selection is only done for models in Non-EU.
4.9.2. Method
(1) Press ADJ key on the Adjustment Remote Control, then
select Country Group Meun
(2) Depending on destination, select Country Group Code 04
or Country Group EU then on the lower Country option,
select US, CA, MX. Selection is done using +, - or ►◄
key.
4.10. MHL Test
4.7. LNB voltage and 22KHz tone check
(only for DVB-S/S2 model)
▪ Test method
(1) Set TV in Adj. mode using POWER ON.
(2) Connect cable between satellite ANT and test JIG.
(3) Press Yellow key(ETC+SWAP) in Adj Remote control to
make LNB on.
(4) Check LED light ‘ON’ at 18 V menu.
(5) Check LED light ‘ON’ at 22 KHz tone menu.
(6) Press Blue key(ETC+PIP INPUT) in Adjustment Remote
control to make LNB off.
(7) Check LED light ‘OFF’ at 18 V menu.
(8) Check LED light ‘OFF’ at 22 KHz tone menu.
▪ Test result
(1) After press LNB On key, ‘18 V LED’ and ‘22 KHz tone
LED’ should be ON.
(2) After press LNB OFF key, ‘18 V LED’ and ‘22 KHz tone
LED’ should be OFF.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 20 -
(1) Turn on TV
(2) Select HDMI4 mode using input Menu.
(3) Set MHL Zig(M1S0D3617) using MHL input, output and
power cord.
(4) Connect HDMI cable between MHL Zig and HDMI4 port.
(5) Check LED light of Zig and Module of Set.
Result) I f, the LED light is green and the Module shows
normal stream → OK, Else → NG
LGE Internal Use Only
4.11. HDMI ARC Function Inspection
4.14. GND and Internal Pressure check
(1) Test equipment
- Optic Receiver Speaker
- MSHG-600 (SW: 1220 ↑)
- HDMI Cable (for 1.4 version)
4.14.1. Method
(1) GND & Internal Pressure auto-check preparation
- Check that Power cord is fully inserted to the SET.
(If loose, re-insert)
(2) Test method
1) Insert the HDMI Cable to the HDMI ARC port from the
master equipment (HDMI1)
(2) Perform GND & Internal Pressure auto-check
- Unit fully inserted Power cord, Antenna cable and A/V
arrive to the auto-check process.
- Connect D-terminal to AV JACK TESTER
- Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
- If NG, Buzzer will sound to inform the operator.
- If OK, changeover to I/P check automatically.
(Remove CORD, A/V form AV JACK BOX.)
- Perform I/P test
- If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
pallet to move on to next process.
2) Check the sound from the TV Set
4.14.2. Checkpoint
▪ TEST voltage
- GND: 1.5 KV / min at 100 mA
- SIGNAL: 3 KV / min at 100 mA
▪ TEST time: 1 second
▪ TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL
▪ LEAKAGE CURRENT: At 0.5 mArms
3) Check the Sound from the Speaker or using AV & Optic
TEST program (It’s connected to MSHG-600)
5. Audio
* Remark: I nspect in Power Only Mode and check SW
version in a master equipment
4.12. Ship-out mode check(In-stop)
▪ After final inspection, press "IN-STOP" key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.
No.
Item
Min
Typ
Max
Unit
Remark
9.0
10.0
12.0
W
Measurement condition
1.
Audio practical
max Output, L/R
(Distortion=10%
max Output)
8.5
8.9
9.8
Vrms
2.
Speaker (8 Ω
Impedance)
10.0
15.0
W
Auto Volume :Off
Audio EQ : Off
Clear Voice : Off
Virtual Surround:Off
Measurement condition:
(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
(3) RGB PC: 1 KHz sine wave signal 0.7 Vrms
4.13. Tool Option selection
- Method: Press ADJ key on the Adj. R/C, then select Tool option.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 21 -
LGE Internal Use Only
6. USB S/W Download(Service only)
(1) Put the USB Stick to the USB socket.
(2) Automatically detecting update file in USB Stick.
- If your downloaded program version in USB Stick is Low,
it didn't work. But your downloaded version is High, USB
data is automatically detecting.(Download Version High &
Power only mode, Set is automatically Download)
(3) Show the message "Copying files from memory".
(4) Updating is starting.
(5) Updating Completed, The TV will restart automatically.
(6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more high than your TV have, TV
can lost all channel data. In this case, you have to channel
recover. if all channel data is cleared, you didn’t have a DTV/
ATV test on production line.
* After downloading, have to adjust Tool Option again.
(1) Push "IN-START" key in service remote control.
(2) Select "Tool Option 1" and push "OK" key.
(3) Punch in the number. (Each model has their number)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 22 -
LGE Internal Use Only
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
120
560
122
810
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Dual Play
(Option)
* Set + Stand
AG1
A10
- 23 -
(Option)
A2
A22
200
830
510
LV1
AG2
AT1
530
832
LV2
121
123
831
541
540
300
521
310
811
500
570
571
900
700
400
710
901
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by
in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
LGE Internal Use Only
System Configuration
Clock for LG1154D
NVRAM
EEPROM_ST
IC102-*1
M24256-BRMN6TP
+3.3V_NORMAL
E0
MAIN Clock(24Mhz)
E1
X-TAL_1
C101
E2
A0
1
8
2
7
3
6
4
5
VCC
WC
SCL
SDA
- Low : Normal Operation
- High : Write Protection
VCC
1M
8
1
Write Protection
VSS
R108
1
GND_1
8pF
C103
0.1uF
IC102
R1EX24256BSAS0A
XIN_MAIN
2
7
WP
4
A1
GND_2
X-TAL_2
3
2
C100
EEPROM_RENESAS
24MHz
X100
8pF
A2
XO_MAIN
VSS
3
A0’h
4
6
5
SCL
SDA
R139
33
I2C_SCL5
R140
33
I2C_SDA5
System Clock for Analog block(24Mhz)
OPT
R100
33
R101
33
EPHY_RXD1
EPHY_TXD0
EPHY_RXD0
EPHY_TXD1
EPHY_MDIO
EPHY_EN
EPHY_MDC
EPHY_REFCLK
EMMC_DATA[1]
EMMC_DATA[0]
EMMC_DATA[2]
EMMC_DATA[5]
EMMC_DATA[3]
EMMC_DATA[4]
EMMC_DATA[6]
EMMC_DATA[7]
EMMC_CLK
EMMC_RST
EB_DATA[2]
EB_DATA[0]
EB_DATA[3]
EB_DATA[1]
EB_DATA[4]
EB_DATA[5]
EB_DATA[6]
EB_ADDR[0]
EB_DATA[7]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]
EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[8]
EB_ADDR[6]
EB_ADDR[7]
EB_ADDR[9]
EB_ADDR[10]
EB_ADDR[11]
EB_ADDR[12]
EB_BE_N0
EB_ADDR[14]
EB_ADDR[13]
EB_BE_N1
EB_OE_N
Mhz)
Mhz)
Mhz)
Mhz)
USB_CTL3
EB_WE_N
/USB_OCD2
USB_CTL2
/USB_OCD3
PLL SET[1:0] : internal pull up
"00" : CPU(1200Mhz),M0 / M1 DDR(792,792
"01" : CPU(1056Mhz),M0 / M1 DDR(672,672
"10" : CPU(1056Mhz),M0 / M1 DDR(792,792
"11" : CPU( 960Mhz),M0 / M1 DDR(792,792
EMMC_CMD
EMMC_DATA[0-7]
EB_DATA[0-7]
EPHY_CRS_DV
EB_ADDR[0-14]
GPIO29
GPIO28
XTAL_BYPASS
GPIO27
H13DA_XTAL
GPIO26
+3.3V_NORMAL
+3.3V_NORMAL
GPIO25
(internal pull down)
3.3K
R117
OPT
BOOT MODE
"0 : EMMC
"1 : TEST MODE
SOC_RESET
PORES_N
3.3K
R118
AD33
H13A_SCL
AU26
H13A_SDA
AN9
AP11
TCK0
AN11
TDI0
AN10
TDO0
AM10
+3.3V_NORMAL
AM9
AM11
Jtag I/F For Main
AM12
AL11
T32
0.1uF
AL9
PLLSET1
AE34
BOOT_MODE
T32
TRST_N0
TDO0
4
TMS0
5
TCK0
EPHY_INT
1/16W
5%
TDI0
3
R149
10K
R151
33
W33
R174
33
W34
SOC_RESET
AU13
M_REMOTE_RX
AT13
M_REMOTE_TX
AP12
M_REMOTE_RTS
M_REMOTE_CTS
AR12
GPIO16
GPIO15
TRST_N0
GPIO14
TMS0
GPIO13
TCK0
GPIO12
TDI0
GPIO11
TDO0
GPIO10
TRST_N1
GPIO9
TMS1
GPIO8
TCK1
GPIO7
TDI1
GPIO6
TDO1
GPIO5
IC100
LG1154D_H13D
PLLSET1
PLLSET0
EXT_INTR3/GPIO70
EXT_INTR2/GPIO69
EXT_INTR1/GPIO68
GPIO4
GPIO3
GPIO2
GPIO1
AE36
11
R165
4.7K
AF36
AF35
DDCD0_DA
SOC_SPI0_CS0
R107
33
SOC_SPI0_MOSI
R156
33
AF33
AG33
SOC_SPI0_MISO
PHY0_RX0N_0
UART1_TXD
PHY0_RX0P_0
UART1_RTS
PHY0_RX1N_0
UART1_CTS
PHY0_RX1P_0
PHY0_RX2N_0
33
AJ7
M_RFModule_RESET
AH6
HP_DET
AG7
PA168_RESET
AG6
/TU_RESET1
/S2_RESET
AG5
AF5
D13_RESET
AH30
FRC_FLASH_WP
/RST_HUB
AG30
AN33
FE_LNA_Ctrl2
AK33
/TU_RESET2
AE30
HDMI_S/W_RESET
AD30
AN32
FE_LNA_Ctrl1
AK32
HDMI_INT
AC32
R169
3.3K
AC33
R170
3.3K
AB33
AC36
AC37
AB36
AB37
AA36
AA37
AD36
AD37
SPDIF_OUT_ARC
HDMI_RX0HDMI_RX0+
HDMI_RX1HDMI_RX1+
HDMI_RX2HDMI_RX2+
HDMI_CLKHDMI_CLK+
/USB_OCD1
USB_CTL1
GPIO139
GPIO138
GPIO137
GPIO136
NC_4
NC_3
NC_2
NC_1
USB3_REFPADCLKP
USB3_REFPADCLKM
USB3_RESREF
USB3_TX0M
USB3_TX0P
USB3_RX0M
USB3_RX0P
USB3_DM0
USB3_DP0
USB2_0_TXRTUNE
USB2_0_DM
USB2_0_DP
USB2_1_TXRTUNE
Not Support
HW_OPT_4
USB2_1_DM0
Support
SDA5
USB2_1_DP0
D13(HEVC)
SCL5
non AJ_JA
USB2_2_TXRTUNE
MODEL_OPT_10
SDA4
USB2_2_DM0
I2C_SDA6
SCL4
USB2_2_DP0
AJ_JA
AH33
SD_DATA0/GPIO134
I2C_SCL6
Not Support
SDA3
SD_DATA1/GPIO135
Area2
AH34
SD_DATA2/GPIO120
MODEL_OPT_9
AJ33
I2C_SDA5
SD_DATA3/GPIO121
Support
S Tuner
I2C port
COMP1_DET
SCL3
SD_WP_N/GPIO122
Not Support
AJ6
SDA2/GPIO77
SD_CD_N/GPIO123
Support
local dimming
AV1_CVBS_DET
AJ5
SCL2/GPIO78
SD_CMD/GPIO124
OLED option
AH32
I2C_SCL5
T2 Tuner
SC_DET
AK5
SDA1/GPIO79
CAM_CE1_N
HW_OPT_3
AR6
I2C_SDA4
Disable
AK6
SCL1/GPIO64
SD_CLK/GPIO125
Enable
AP6
I2C_SCL4
FRC option
Pannel Resol
AR17
SC_DATA/GPIO132
CP BOX
MODEL_OPT_6
INSTANT_BOOT
AK7
SDA0/GPIO65
SC_RST/GPIO131
Default
AL6
SCL0/GPIO66
SC_VCC_SEL/GPIO128
Reserved
MODEL_OPT_5
MODEL_OPT_8
HW_OPT_2
AP17
I2C_SCL2_SOC
AREA option1
HW_OPT_1
AP16
I2C_SDA_MICOM_SOC
V12
AMP_RESET_N
AM7
HUB_VBUS_CTRL0
SC_VCCEN/GPIO129
AR16
I2C_SDA2_SOC
MODEL_OPT_7
HW_OPT_0
V13
AM6
R33
SPI_DI1
SC_DETECT/GPIO133
Module
AM5
HUB_PORT_OVER0
SPI_DO1
SC_CLK/GPIO130
MODEL_OPT_4
Default
SPI_CS1
CAM_IOIS16_N/GPIO83
D13
10K
R131
AJ_JA
R129
10K
DVB_S_TUNER
R128
10K
CP_BOX
R124
10K
DVB_T2_TUNER
R126
10K
OPT
10K
OPT
10K
R116
R122
FHD
10K
R114
V13_MODULE
R120
10K
OPT
10K
R112
Reserved
For ISP
AR9
SPI_SCLK1
AP15
I2C_SDA1
I2C_SCL_MICOM_SOC
MODEL_OPT_3
+3.3V_NORMAL
AL32
AR15
I2C_SCL1
UD
AG32
100K
R171
RF_SWITCH_CTL
AL33
R32
CAM_REG_N/GPIO72
FHD
R158
PHY0_RXCP_0
SPI_SCLK0/GPIO37
CAM_WAIT_N/GPIO84
Default
PHY0_RXCN_0
SPI_DI0/GPIO39
CAM_VCCEN_N/GPIO87
Panel
SOC_SPI0_SCLK
non Taiwan
SPI_DO0/GPIO38
CAM_INPACK/GPIO74
MODEL_OPT_2
Taiwan
PHY0_RX2P_0
CAM_RESET
Area1
Reserved
SPI_CS0/GPIO36
CAM_IREQ_N/GPIO73
MODEL_OPT_0
MODEL_OPT_1
100K
R172
/RST_PHY
AK34
AE37
PHY0_ARC_OUT_0
UART1_RXD
CAM_VS2_N/GPIO85
Model Option+3.3V_NORMAL
AN34
HPD0
UART0_TXD
CAM_VS1_N/GPIO86
LOW
AF30
+3.3V_NORMAL
DDCD0_CK
UART0_RXD
CAM_CD2_N/GPIO75
HIGH
AG34
AM32
GPIO0
AE35
10
TAIWAN
R110
10K
H13DA_SDA
EXT_INTR0/GPIO67
AT12
SOC_TX
OPT
OPT
R168
10K
10K
OPT
R166
10K
9
R163
8
OPT
R160
10K
7
GPIO17
AU12
SOC_RX
6
H13DA_SCL
BOOT_MODE
W32
R164
33
2
GPIO18
Y33
D13_INT
1
GPIO19
CAM_CD1_N/GPIO76
P100
12505WS-10A00
AL10
PLLSET0
OPT
R167
33
GPIO20
OPM0
AP9
TMS0
BOOT_MODE0
GPIO21
OPM1
AT26
TRST_N0
INSTANT_MODE0
GPIO22/UART2_RX
AD34
OPM1
OPM0
BOOT_MODE
INSTANT_BOOT
GPIO23/UART2_TX
AU16
CAM_CE2_N
3.3K
R150
OPT
GPIO24
INSTANT boot MODE
"1 : Instant boot
"0 : normal
Do not move !!!
DFT jig LVDS 120Hz
CAM_SLIDE_DET
AM33
3.3K
GPIO30
B27
AT37
AL34
GPIO31
R103
RMII_RXD0
AR11
AU10
AT10
AT11
RMII_RXD1
RMII_TXD0
RMII_TXD1
RMII_TXEN
AR10
RMII_MDC
AT8
AR8
RMII_MDIO
RMII_REF_CLK
RMII_CRS_DV
AU11
U36
U37
EMMC_DATA0
EMMC_DATA1
EMMC_DATA2
U35
EMMC_DATA3
V36
V35
W36
V37
EMMC_DATA4
EMMC_DATA5
EMMC_DATA6
EMMC_DATA7
T36
Y36
Y37
W35
EMMC_RESETN
EMMC_CMD
EMMC_CLK
A36
EB_DATA0/GPIO114
EB_DATA1/GPIO115
C34
EB_DATA2/GPIO116
B34
A34
EB_DATA3/GPIO117
EB_DATA4/GPIO118
A33
B33
C33
EB_DATA5/GPIO119
EB_DATA6/GPIO104
EB_DATA7/GPIO105
C32
EB_ADDR0/GPIO106
B35
EB_ADDR1/GPIO107
B37
B36
EB_ADDR2/GPIO108
EB_ADDR3/GPIO109
C35
C36
D35
EB_ADDR6/GPIO96
EB_ADDR4/GPIO110
EB_ADDR5/GPIO111
D37
D36
EB_ADDR7/GPIO97
EB_ADDR8/GPIO98
E35
EB_ADDR9/GPIO99
E37
F35
F36
G35
G36
G37
H37
J36
J35
H36
H35
L35
K37
K36
E36
EB_ADDR10/GPIO100
EB_ADDR11/GPIO101
XOUT
EB_ADDR14/GPIO88
XIN
EB_ADDR12/GPIO102
B26
EB_ADDR13/GPIO103
560
EB_BE_N0/GPIO80
R152
EB_ADDR15/GPIO89
XO_MAIN
EB_OE_N/GPIO82
A26
XIN_MAIN
EB_WAIT/GPIO94
OPM1
OPM0
EB_CS0/GPIO90
33
OPT
EB_WE_N/GPIO95
33
R134
EB_BE_N1/GPIO81
OPT
R133
EB_CS1/GPIO91
K35
EB_CS3/GPIO93
+3.3V_NORMAL
EB_CS2/GPIO92
OP MODE[1:0]
"00" : Normal Mode
"01/10/11" : Internal Test mode
AU8
PLLSET1
PLLSET0
OPT
J34
K32
J33
J32
M31
L33
AJ31
L32
P32
P33
N34
R37
R36
N37
N36
P36
P37
AP7
AT7
AU7
K33
M36
M37
K34
L36
L37
C24
D24
E24
D25
E25
B25
C25
A25
V34
V33
V32
T32
U33
T33
H33
D34
E33
H32
D33
F32
G33
G32
G34
200 1%
R162
0.1uF
C105
USB3_TX0M
0.1uF
C104
USB3_TX0P
USB3_RX0P
USB3_RX0M
USB3_DM
USB3_DP
WIFI_DM
R161
200 1%
WIFI_DP
USB_DM2
R159 200 1%
USB_DP2
USB2_HUB_IC_IN_DM
R157 200 1%
USB2_HUB_IC_IN_DP
Only SMART CARD
interface
SMARTCARD_DATA/SD_EMMC_CLK
SMARTCARD_RST/SD_EMMC_DATA[2]
SMARTCARD_VCC/SD_EMMC_CMD
SMARTCARD_DET/SD_EMMC_DATA[3]
CAM_REG_N
CAM_WAIT_N
PCM_RESET
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
I2C for tuner
CI
I2C for tuner
I2C_SDA5
+3.3V_NORMAL
SMARTCARD_CLK/SD_EMMC_DATA[0]
I2C_SDA4
I2C_SCL4
R155
10K
I2C_SDA2_SOC
I2C_SCL2_SOC
PCM_5V_CTL
I2C_SCL1
I2C_SDA_MICOM_SOC
I2C_SCL_MICOM_SOC
I2C_SDA6
I2C_SCL6
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
I2C_SCL2_SOC
I2C_SDA1
I2C_SCL5
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
I2C_SDA2_SOC
CAM_INPACK_N
R104
I2C_SCL_MICOM_SOC
CAM_IREQ_N
I2C_SCL2
I2C_SDA_MICOM_SOC
R154
10K
CI
I2C_SDA2
E32
R102
R106
R148
3.3K
R147
3.3K
R145
3.3K
R144
3.3K
R143
3.3K
R141
3.3K
R142
3.3K
R137
3.3K
33
33
/PCM_CE1
NON_D13
R132
10K
NON_AJ_JA
R130
10K
NON_DVB_S_TUNER
R127
10K
NON_CP_BOX
R123
10K
NON_DVB_T2_TUNER
R125
10K
10K
R121
R115
V12_MODULE
R119
10K
10K
10K
R113
UD
10K
R111
NON_TAIWAN
R109
10K
EPI selection
R138
3.3K
HW_OPT_10
KR_PIP
R136-*1 1.5K
AREA option2
KR_PIP
R135-*1 1.5K
KR_PIP_NOT
R135
3.3K
KR_PIP_NOT
R136
3.3K
satellite support
R146
3.3K
I2C PULL UP
HW_OPT_8
HW_OPT_9
R105
CAM_CD2_N
+3.3V_NORMAL
+3.3V_NORMAL
T2 support
33
33
I2C_SCL_MICOM
/PCM_CE2
HW_OPT_7
+3.3V_TU
CAM_CD1_N
I2C_SDA_MICOM
+3.3V_TU
CI
R153
10K
reserved
CP BOX
D32
HW_OPT_5
HW_OPT_6
F34
F33
EPI PANEL version
AC-coupling CAP
Place near by LG1154D
BSD-NC4_H001-HD
2012-11-14
H13 D CHIP
LGE Internal Use Only
LG1154A
LG1154D
LG1154A
IC100
LG1154D_H13D
H13A_NON_BRAZIL
+3.3V_Bypass Cap
IC101
LG1154AN_H13A
VREF_M0_0
VREF_M0_1
SDRAM_VDDQ_3
K15
SDRAM_VDDQ_4
K16
SDRAM_VDDQ_5
VDD10_XTAL
VDD10_XTAL
G7
VDDC10_1
G8
VDDC10_2
G9
VDDC10_3
H7
VDDC10_4
H12
VDDC10_5
J7
J12
K7
GND_63
VDDC10_12
M12
VDDC10_13
T17
AVDD10_CVBS
T18
AVDD10_VSB
M8
AVDD10_LLPLL
G10
DVDD10_APLL_1
G11
DVDD10_APLL_2
G12
GND_68
GND_69
GND_70
GND_72
VDDC10_11
M7
GND_67
VDDC10_7
VDDC10_10
L12
GND_66
GND_71
VDDC10_9
L7
GND_65
VDDC10_6
VDDC10_8
K12
VDD10_XTAL
GND_62
GND_64
R18
VDDC10
GND_61
LTX_VDD
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
V5
VSS25_REF
VSS25_REF
C3
GND_1
D3
GND_2
D4
D17
E4
GND_4
GND_91
GND_7
F8
GND_8
F9
GND_9
F10
GND_10
F12
GND_11
F13
GND_12
F17
GND_13
F18
GND_14
G4
GND_15
G6
GND_16
G13
GND_17
G14
GND_18
G15
GND_19
G16
GND_20
G17
GND_21
G18
GND_22
H4
GND_23
H5
GND_24
H6
H8
H9
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_26
GND_113
GND_28
H11
GND_92
GND_25
GND_27
H10
GND_89
GND_90
GND_6
F7
GND_88
GND_3
GND_5
F4
GND_87
GND_29
GND_114
GND_115
C2974.7uF
C3514.7uF
C2794.7uF
C2554.7uF
L11
L226
BLM15BD121SN1
0.1uF
AE14
VDD25_XTAL
AF14
L13
N25
L14
VSS25_REF
AD26
VDDC11_7
VDDC11_8
VDD33_1
VDDC11_9
VDD33_2
VDDC11_10
VDD33_3
VDDC11_11
VDD33_4
VDDC11_12
VDD33_5
VDDC11_13
VDD33_6
VDDC11_14
VDD33_7
VDDC11_15
VDDC11_16
VDDC11_17
AVDD33_USB_1
AVDD33_USB_2
VDDC11_19
AVDD33_BT_USB_1
VDDC11_20
AVDD33_BT_USB_2
VDDC11_22
AVDD33_HDMI_2
VDDC11_23
VDDC11_25
VDDC11_26
VDDC11_27
VDD25_LVRX_1
VDDC11_28
VDD25_LVRX_2
VDDC11_29
VTXPHY_VDD25_1
VDDC11_30
VTXPHY_VDD25_2
VDDC11_31
VDD25_DR3PLL
1005 size bead
Bottom side of chip
VDDC11_32
L16
H10
+1.1V_VDD
L17
H11
VDD11_VTXPHY
L18
+1.5V
H12
L201
BLM18PG121SN1D
M1
H13
M2
M3
+2.5V_Normal
M4
M5
+2.5V_Normal
VDD25_LTX
L207
BLM18PG121SN1D
M9
M11
M14
M15
M16
N4
VDD25_AUD
L200
BLM18PG121SN1D
M10
VDDC11_33
VDDC11_34
H14
VDDC15_M0
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
N5
H25
VDD15_M0_1
C5
+1.1V
N22
C26
C27
D5
N23
D26
E5
P15
E6
E7
P16
E8
E22
P17
E23
E26
P18
F7
F8
R15
F22
F23
+1.1V_VDD
T15
F24
F25
T22
F26
F27
T23
F31
T24
G8
G7
G9
U15
G10
G11
U22
G12
U23
G14
G13
G15
U24
G16
G17
V15
G18
V22
G20
G19
G21
V23
G22
V24
G24
G23
G25
W22
G26
G27
W23
G28
W24
G30
G29
G31
AB15
H9
H26
AB24
H27
AC15
H29
H28
H30
AC24
H31
J7
AD15
J30
J31
AD16
K7
K30
AD17
K31
AD18
L31
L30
M7
AD21
M12
M13
AD22
M14
AD23
M16
M15
M17
AD24
M18
M19
VDDC11_35
M20
M24
VDD15_M0_2
M25
M26
VDD15_M0_3
M30
VDD11_VTXPHY
VDD15_M0_4
M32
M33
M34
VDD15_M0_5
AB14
VDD15_M0_6
VTXPHY_VDD11_1
VDD15_M0_7
VTXPHY_VDD11_2
VDD15_M0_8
VTXPHY_VDD11_3
N12
N13
AC14
N14
AD14
N16
N15
VDDC11_XTAL
N17
N18
N19
VDD15_M0_9
VDD15_M0_10
AVDD11_DR3PLL
VDD15_M0_11
AVDD11_DCO
VDD15_M0_12
P25
N20
AA15
N30
N24
AC26
N31
+1.1V_VDD
N32
N33
GPLL_VDD11
P7
VDD15_M0_13
P12
VDD15_M0_14
P14
P13
P19
P20
VDD15_M0_15
P21
P22
VDD15_M0_16
N14
P23
P24
N15
H7
N17
H8
P4
J8
P5
K8
P6
L7
P7
L8
P8
+3.3V_Bypass Cap
P9
P10
VDDC15_M1
M8
N7
+3.3V_NORMAL
N8
VDD33
P11
P8
P14
R7
L203
BLM18PG121SN1D
P15
R8
P16
R4
R7
+1.0V_Bypass Cap
R8
R9
+1.0V_VDD
R10
VDD10_XTAL
T8
U8
V8
W8
P30
P31
VDD15_M1_1
R12
VDD15_M1_2
R13
VDD15_M1_3
R16
VDD15_M1_4
R18
VDD15_M1_5
R20
R14
R17
R19
R21
R22
VDD15_M1_6
R23
VDD15_M1_7
R24
VDD15_M1_8
R26
R25
R30
VDD15_M1_9
R34
VDD15_M1_10
T12
VDD15_M1_11
T14
T7
T13
T16
T17
VDD15_M1_12
T18
T19
VDD15_M1_13
T20
T21
VDD15_M1_14
T25
VDD15_M1_15
T26
VDD15_M1_16
T31
T30
T34
U7
U12
U13
R11
U14
U16
R12
L211
BLM18PG121SN1D
R13
U17
U18
U19
R14
R15
R16
R17
T4
T7
U20
U21
U25
U26
AAD_ADC_SIF
XIN_SUB
D18
M18
T10
M17
+1.0V_VDD
AUDA_OUTL
XTAL_BYPASS
AUDA_OUTR
CLK_24M
XTAL_SEL0
AUD_SCART_OUTL
XTAL_SEL1
AUD_SCART_OUTR
AUAD_L_CH4_IN
+2.5V_Bypass Cap
VDDC10
AUAD_R_CH4_IN
E3
PORES_N
AUAD_L_CH3_IN
OPM0
AUAD_L_CH2_IN
OPM1
AUAD_R_CH2_IN
H13A_SCL
AUAD_R_CH1_IN
H13A_SDA
AUAD_R_REF
AUAD_R_CH3_IN
K3
L206
BLM18PG121SN1D
U18
V4
V16
GND_116
V18
V19
N1
V20
N2
V21
N3
V25
V26
P1
V30
V31
P3
T12
U6
V17
H17
P2
AUDA_VBG_EXT
N18
T9
V16
AAD_ADC_SIFM
XO_SUB
VSB_AUX_XIN
U4
V12
H18
P17
T8
T16
V7
V13
P18
T15
U31
V14
J17
T11
U30
H13A_BRAZIL
IC101-*1
LG1154AN_H13A_ISDB-T (LG1154AN-IT)
+2.5V_Normal
+2.5V_Normal
K2
(1)
VDD25_XTAL
L234
BLM18PG121SN1D
VDD25_LVDS(4)
AUAD_L_CH1_IN
A8
B8
L238
BLM18PG121SN1D
AUAD_M_REF
AUAD_L_REF
V14
V15
V13
W7
U2
W12
U3
W13
V2
W14
V3
W15
U1
W16
T3
W17
T2
W18
W19
R3
W20
W21
CVBS_IN1
RFAGC
CVBS_VCM
IFAGC
BUF_OUT1
ADC_I_INCOM
BUF_OUT2
ADC_I_INP
K18
W25
J18
W26
W30
U16
W31
U17
Y3
V17
Y4
GND_1
GND_185
GND_2
GND_186
GND_3
GND_187
GND_4
GND_188
GND_5
GND_189
GND_6
GND_190
GND_7
GND_191
GND_8
GND_192
GND_9
GND_193
GND_10
GND_194
GND_11
GND_195
GND_12
GND_196
GND_13
GND_197
GND_14
GND_198
GND_15
GND_199
GND_16
GND_200
GND_17
GND_201
GND_18
GND_202
GND_19
GND_203
GND_20
GND_204
GND_21
GND_205
GND_22
GND_206
GND_23
GND_207
GND_24
GND_208
GND_25
GND_209
GND_26
GND_210
GND_27
GND_211
GND_28
GND_212
GND_29
GND_213
GND_30
GND_214
GND_31
GND_215
GND_32
GND_216
GND_33
GND_217
GND_34
GND_218
GND_35
GND_219
GND_36
GND_220
GND_37
GND_221
GND_38
GND_222
GND_39
GND_223
GND_40
GND_224
GND_41
GND_225
GND_42
GND_226
GND_43
GND_227
GND_44
GND_228
GND_45
GND_229
GND_46
GND_230
GND_47
GND_231
GND_48
GND_232
GND_49
GND_233
GND_50
GND_234
GND_51
GND_235
GND_52
GND_236
GND_53
GND_237
GND_54
GND_238
GND_55
GND_239
GND_56
GND_240
GND_57
GND_241
GND_58
GND_242
GND_59
GND_243
GND_60
GND_244
GND_61
GND_245
GND_62
GND_246
GND_63
GND_247
GND_64
GND_248
GND_65
GND_249
GND_66
GND_250
GND_67
GND_251
GND_68
GND_252
GND_69
GND_253
GND_70
GND_254
GND_71
GND_255
GND_72
GND_256
GND_73
GND_257
GND_74
GND_258
GND_75
GND_259
GND_76
GND_260
GND_77
GND_261
GND_78
GND_262
GND_79
GND_263
GND_80
GND_264
GND_81
GND_265
GND_82
GND_266
GND_83
GND_267
GND_84
GND_268
GND_85
GND_269
GND_86
GND_270
GND_87
GND_271
GND_88
GND_272
GND_89
GND_273
GND_90
GND_274
GND_91
GND_275
GND_92
GND_276
GND_93
GND_277
GND_94
GND_278
GND_95
GND_279
GND_96
GND_280
GND_97
GND_281
GND_98
GND_282
GND_99
GND_283
GND_100
GND_284
GND_101
GND_285
GND_102
GND_286
GND_103
GND_287
GND_104
GND_288
GND_105
GND_289
GND_106
GND_290
GND_107
GND_291
GND_108
GND_292
GND_109
GND_293
GND_110
GND_294
GND_111
GND_295
GND_112
GND_296
GND_113
GND_297
GND_114
GND_298
GND_115
GND_299
GND_116
GND_300
GND_117
GND_301
GND_118
GND_302
GND_119
GND_303
GND_120
GND_304
GND_121
GND_305
GND_122
GND_306
GND_123
GND_307
GND_124
GND_308
GND_125
GND_309
GND_126
GND_310
GND_127
GND_311
GND_128
GND_312
GND_129
GND_313
GND_130
GND_314
GND_131
GND_315
GND_132
GND_316
GND_133
GND_317
GND_134
GND_318
GND_135
GND_319
GND_136
GND_320
GND_137
GND_321
GND_138
GND_322
GND_139
GND_323
GND_140
GND_324
GND_141
GND_325
GND_142
GND_326
GND_143
GND_327
GND_144
GND_328
GND_145
GND_329
GND_146
GND_330
GND_147
GND_331
GND_148
GND_332
GND_149
GND_333
GND_150
GND_334
GND_151
GND_335
GND_152
GND_336
GND_153
GND_337
GND_154
GND_338
GND_155
GND_339
GND_156
GND_340
GND_157
GND_341
GND_158
GND_342
GND_159
GND_343
GND_160
GND_344
GND_161
GND_345
GND_162
GND_346
GND_163
GND_347
GND_164
GND_348
GND_165
GND_349
GND_166
GND_350
GND_167
GND_351
GND_168
GND_352
GND_169
GND_353
GND_170
GND_354
GND_171
GND_355
GND_172
GND_356
GND_173
GND_357
GND_174
GND_358
GND_175
GND_359
GND_176
GND_360
GND_177
GND_361
GND_178
GND_362
GND_179
GND_363
GND_180
GND_364
GND_181
GND_365
GND_182
GND_366
GND_183
GND_367
GND_184
GND_368
Y8
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y31
Y35
AA8
AA12
AA13
AA14
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA31
AB6
AB8
AB12
AB13
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB25
AB26
AB30
AB31
AC8
AC12
AC13
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC25
AC30
AC31
AD8
AD12
AD13
AD19
AD20
AD25
AD31
AE12
AE13
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE24
AE25
AE26
AE31
AF12
AF13
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF24
AF31
AG8
AG31
AH8
AH31
AJ8
AJ30
AK8
AK9
AK10
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK26
AK27
AK28
AK29
AK30
AK31
AL8
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AM8
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AN6
AN12
AN13
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
F3
V6
T5
U8
V8
V9
U9
V10
U11
V11
U12
+1.5V_Bypass Cap
T1
K17
ANTCON
GPIO0
U7
T6
VDDC15_M0
W5
W6
ADC_I_INN
V7
+1.5V_DDR
CVBS_IN3
CVBS_IN2
U15
U14
R1
R2
AUAD_REF_PO
U13
V12
VDDC15_M0
REFT
GPIO1
REFB
GPIO2
ADC1_COM
GPIO3
ADC2_COM
GPIO4
ADC3_COM
GPIO5
SC1_SID
GPIO6
SC1_FB
GPIO7
PB1_IN
GPIO8
Y1_IN
GPIO9
SOY1_IN
GPIO10
PR1_IN
GPIO11
PB2_IN
GPIO12
Y2_IN
GPIO13
SOY2_IN
GPIO14
PR2_IN
GPIO15
+1.5V_DDR
VDDC15_M0
VDDC15_M1
F2
F1
G3
G2
G1
H3
H2
H1
J3
E18
E17
H16
J2
J1
K1
VDDC15_M1
VDDC15_M1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
R302
1K 1%
R300
1K 1%
VREF_M1_1
0.1uF
1%
1K
R303
OPT
C310
0.1uF
1%
1K
R301
OPT
C304
BLM18PG121SN1D
0.1uF
0.1uF
1%
R203
1K
C344
0.1uF
C296
1%
R201
OPT
C299 22uF
L228
C307
R202
1K 1%
R200
VREF_M0_0
VREF_M1_0
VREF_M0_1
OPT
1K
0.1uF
0.1uF
C372
0.1uF
C371
0.1uF
C370
0.1uF
C369
0.1uF
C367
C366
0.1uF
0.1uF
C365
0.1uF
C363
0.1uF
C362
0.1uF
C361
0.1uF
C360
0.1uF
C359
0.1uF
C358
0.1uF
C357
0.1uF
C356
0.1uF
C355
0.1uF
C354
0.1uF
C353
0.1uF
C352
C350
OPT
0.1uF
0.1uF
C314
OPT
0.1uF
C313
OPT
C312
0.1uF
OPT
C311
OPT
0.1uF
0.1uF
C309
OPT
C305
0.1uF
0.1uF
C308
0.1uF
C306
C302
MDS62110209
C303 22uF
JP205
JP204
JP203
BLM18PG121SN1D
NON_LA8600
GASKET_8.0X6.0X8.5H
M200
1K 1%
SMD TOP for EMI
L230
JP202
VDDC11_21
AVDD33_HDMI_1
U10
GND JIG POINT
VDDC11_18
GPLL_AVDD25
L15
0.1uF
J16
GND_60
L10
AF23
C381
SDRAM_VDDQ_2
GND_59
L9
C3784.7uF
SDRAM_VDDQ_1
J15
XTAL_VDDP
AE23
OPT
H15
GND_58
L8
0.1uF
LTX_LVDD_2
GND_57
VDDC11_6
SP_VQPS
C203
LTX_LVDD_1
F16
GND_56
XTAL_VDD
VDDC11_24
VDD25_LVDS
0.1uF
VDD25_AAD
F15
L6
C368
M13
GND_55
VDDC11_5
R31
OPT
VDD25_AUD_2
L5
0.1uF
VDD25_LTX
GND_54
VDDC11_4
+2.5V
C208
VDD25_AUD_1
N6
L220
BLM18PG121SN1D
C2014.7uF
M6
GND_53
L225
BLM15BD121SN1
AF26
C3644.7uF
VDD25_APLL
L3
L4
L227
BLM18PG121SN1D
VDD25_REF
AVDD25
C301
F14
GND_52
+2.5V_Normal
L2
0.1uF
VDD25_COMP_3
AF25
0.1uF
VDD25_AUD
GND_51
L1
C206
VDD25_COMP_2
N9
AK12
VDDC11_XTAL
C207
VDD25_LTX
AFE 3CH Power
C298 4.7uF
N8
GND_50
+1.1V_VDD
K14
OPT
VDD25_COMP_1
AK11
C205 4.7uF
N7
GND_49
K13
M23
C209 4.7uF
VDD25_REF
GND_48
+2.5V_Bypass Cap
K11
0.1uF
VDD25_VSB_2
U5
VDDC11_3
M1_DDR_VREF2
M22
C300
N13
GND_47
K10
0.1uF
VDD25_VSB_1
GND_46
VDDC11_2
M1_DDR_VREF1
VDD33_8
K9
4.7uF
VDD25_CVBS_2
N12
AK25
C204
N11
GND_45
K8
C202
VDD25_CVBS_1
AE8
AK24
0.1uF
GND_44
N10
VDD25_REF
GND_43
AA30
C288
AVDD33_CVBS_2
Y30
K6
C200 4.7uF
T14
GND_42
VDD33
AK13
0.1uF
AVDD33_CVBS_1
M0_DDR_VREF2
M21
K5
C2704.7uF
T13
GND_41
VDDC11_1
+3.3V
AF8
C274
VDD33_XTAL
GND_40
K4
N21
M0_DDR_VREF1
P26
0.1uF
VDD33_11
N16
Y1
C246
R6
GND_39
A4
N26
0.1uF
VDD33_10
GND_38
J14
B5
A24
A2
VDD25_XTAL
Y5
A27
VDDC11_XTAL
C251
VDD33_9
R5
GND_37
C2424.7uF
VDD33_8
P13
J11
0.1uF
P12
GND_36
J10
C223
VDD33_7
GND_35
J9
C2394.7uF
VDD33_6
J13
J8
C2144.7uF
H13
GND_34
C2114.7uF
VDD33_5
C2164.7uF
G5
GND_33
VREF_M1_1
+1.1V_VDD
L222
BLM18PG121SN1D
J5
J6
VREF_M1_0
AVDD33_CVBS(2)
L216
BLM18PG121SN1D
0.1uF
VDD33_4
GND_32
L209
BLM18PG121SN1D
J4
C218
GND_31
C2754.7uF
GND_30
VDD33_2
VDD33_3
F11
AVDD25
VDD33_1
C2414.7uF
F6
AVDD33_XTAL
AVDD33_CVBS
AVDD33_XTAL(1)
H14
F5
+1.1V_Bypass Cap
+3.3V_NORMAL
0.1uF
E11
+3.3V_NORMAL
(2)
0.1uF
AVDD33
C283
+3.3V_NORMAL
C259
AVDD33
IC100
LG1154D_H13D
+0.75V
BSD-NC4_H002-HD
2012-10-18
MAIN POWER
11/05/31
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
IC101
LG1154AN_H13A
+3.3V_NORMAL
OP MODE Setting
& Select XTAL Input
Clock for H13A
CLK_54M_VTT
INTR_GBB
INTR_AFE3CH
+3.3V_NORMAL
IC100
LG1154D_H13D
H13A_NON_BRAZIL
E1
AT16
E2
AU17
D1
AT17
1M
R460
R461
R462
10K
10K
AUD_FS20CLK
AUD_FS21CLK
R484 OPT
R441
10K
10K
R459
XTAL SEL[1:0] : SW[4:3]
00 => Xtal Input
01 => CLK 24M from H13D
10 => XTAL Bypass from H13D
XOUT_SUB
R482 OPT
OPT
R483
R481 OPT
X-TAL_1
GND_1
1
2
C427
OP MODE[0:1] : SW[2:1]
00 => Normal Operaiton Mode
/T32 Debug Mode
01 => Internal Test Purpose
10 => Internal Test Purpose
11 => Internal Test Purpose
4
3
12pF
1/16W
1%
R466
82
X-TAL_2
DAC_START_PULLDOWN
XIN_SUB
GND_2
12pF
C426
24MHz
X400
1/16W
1%
MAIN Clock(24Mhz)
C404
0.01uF
50V
1/16W
1%
R465
390
R464
1K
INTR_AGPIO
AUD_FS23CLK
AUD_FS24CLK
AUD_FS25CLK
100
OPM[1]
100
XTAL_SEL[0]
100
AUD_DAC1_SCK
XTAL_SEL[1]
AUD_DAC1_LRCH
AUD_ADC_LRCK
100 C424
AV1_CVBS_IN
IC101 H13A_NON_BRAZIL
LG1154AN_H13A
AUD_ADC_SCK
0.047uF
L409 1uH
R433
100 C425
XIN_SUB
330P18
J17
R453
0.047uF
AAD_ADC_SIF
XO_SUB
VSB_AUX_XIN
C462
150pF
EU
R411
75
1%
D18
SC_CVBS_IN_SOY
M18
XTAL_SEL[0]
R432
100
C423
M17
XTAL_SEL[1]
0.047uF
10K EU
SCART_FB_DIRECT
EU
R436
2.7K
R422
75
R427
33 C419
0.047uF
0.047uF
1000pF
V15
33 C420
33 C421
N2
N3
AUDA_OUTL
BB_TP_DATA7
AUDA_OUTR
BB_TP_DATA6
EU 100
EU 100
P1
R479
SCART_Lout_SOC
BB_TP_DATA5
R480
SCART_Rout_SOC
BB_TP_DATA4
R449
COMP2_PB_IN_SOC
COMP2_Y_IN_SOC
0.047uF
1000pF
33 C422
R431
R417 1% 75
R415 1% 75
R413 1% 75
50V 10pF
CVBS_IN2
ANTCON
CVBS_IN1
RFAGC
CVBS_VCM
IFAGC
U15
0.047uF
0.047uF
V7
0.047uF
U10
0.047uF
BUF_OUT1
ADC_I_INCOM
BUF_OUT2
ADC_I_INP
T5
T6
U8
COMP1_PB_IN_SOC
V8
COMP1_Y_IN_SOC
V9
COMP1_Y_IN_SOC_SOY
U9
COMP1_PR_IN_SOC
V10
COMP2_PB_IN_SOC
U11
COMP2_Y_IN_SOC
V11
COMP2_Y_IN_SOC_SOY
Near Place Scart AMP
GPIO0
V12
SC_FB_SOC
COMP2_PR_IN_SOC
EU R442
22K
AUAD_R_CH3_IN
U2
AUAD_L_CH2_IN
U3
U12
COMP2_PR_IN_SOC
BB_TP_DATA2
BB_TP_DATA1
CVBS_GC2
CVBS_GC1
V3
CVBS_GC0
U1
AUAD_R_REF
T3
CVBS_UP
AUAD_M_REF
T2
Close to IC4300
AUAD_REF_PO
FS00CLK
AUDCLK_OUT
NON_TU_W_BR/TW/CO
K18
REFT
GPIO1
REFB
GPIO2
ADC1_COM
GPIO3
ADC2_COM
GPIO4
ADC3_COM
GPIO5
SC1_SID
GPIO6
SC1_FB
GPIO7
PB1_IN
GPIO8
Y1_IN
GPIO9
SOY1_IN
GPIO10
PR1_IN
GPIO11
PB2_IN
GPIO12
Y2_IN
GPIO13
SOY2_IN
GPIO14
PR2_IN
GPIO15
DAC_START
R487
J18
IF_AGC
C454
ADC_I_INP
V17
DAC_DATA4
C459
0.1uF
TU_W_BR/TW/CO
0.1uF
U17
DAC_DATA3
DAC_DATA2
DAC_DATA1
ADC_I_INN
DAC_DATA0
HW_OPT_0
F2
AAD_GC4
HW_OPT_1
F1
HW_OPT_2
G3
HW_OPT_3
G2
TU_W_BR/TW/CO
R487-*1
AAD_GC3
10K
AAD_GC1
AAD_GC2
HW_OPT_4
G1
H1
J3
E18
E17
H16
AAD_DATA9
HW_OPT_7
AAD_DATA8
HW_OPT_8
AAD_DATA7
HW_OPT_9
AAD_DATA6
HW_OPT_10
AAD_DATA5
MHL_ON_OFF
AAD_DATA4
AAD_DATA3
J2
AAD_DATA2
J1
AAD_DATA1
K1
EU
SC_FB_BUF
AAD_DATA0
10K
AU20
B1
AT19
C2
AU19
C1
AT18
D2
AU18
B4
AU22
A3
AT21
B3
AU21
STPI1_CLK/GPIO42
AUD_FS23CLK
STPI1_SOP/GPIO41
AUD_FS24CLK
STPI1_VAL/GPIO40
AUD_FS25CLK
STPI1_ERR/GPIO55
HSR_AP0
HSR_AM0
Placed as close as possible to IC4300
HSR_BP0
+3.3V_NORMAL
HSR_BM0
L407
HSR_CM0
OPT
C447
1uF
25V
1%
R437
AUAD_L_CH3_IN
EU
IC400
MM1756DURE
10K 1%
C412
0.1uF
4.7uF
1%
R421
5
2
4
3
GND
AU25
B7
E8
AP23
D8
AR23
C8
AP22
E7
AR22
D7
AP21
C7
AR21
E6
AP20
D6
AR20
C6
AP19
E5
AR19
D5
AP18
C5
AR18
CLK_54M_VTT
R467 82
4.7uF
27K
AUAD_L_CH2_IN
10K 1%
C435
4.7uF
R440
1/16W 1%
TP_DVB_SOP
AUD_DAC1_LRCK
TP_DVB_VAL
AUD_DAC1_SCK
TP_DVB_ERR
AUD_DAC1_LRCH
TP_DVB_DATA0
AUD_DAC0_LRCK
TP_DVB_DATA1
AUD_DAC0_SCK
TP_DVB_DATA2
AUD_DAC0_LRCH
TP_DVB_DATA3
AUD_ADC_LRCK
TP_DVB_DATA4
AUD_ADC_SCK
TP_DVB_DATA5
AUD_ADC_LRCH
TP_DVB_DATA6
C455
10uF
HSR_DP0
1%
R457
51K
B9
AU27
A9
AT27
D9
AP24
E9
AR25
Close to LG1154A
B11 R492
330
A11 R407
330
AU29
AT29
DAC_START_PULLDOWN
D11
AP27
C11
AR27
E10
AP26
D10
AR26
C10
AP25
A10 R451
AT28
330
D13
AR30
C13
AP29
E12
AR29
D12
AP28
C12
AR28
HSR_DM0
HSR_EP0
TPI_CLK
BB_TPI_CLK
TPI_SOP
BB_TPI_ERR
TPI_VAL
BB_TPI_SOP
TPI_ERR
BB_TPI_VAL
TPI_DATA0
BB_TPI_DATA7
TPI_DATA1
BB_TPI_DATA6
TPI_DATA2
BB_TPI_DATA5
TPI_DATA3
BB_TPI_DATA4
TPI_DATA4
BB_TPI_DATA3
TPI_DATA5
BB_TPI_DATA2
TPI_DATA6
BB_TPI_DATA1
TPI_DATA7
TPIO_CLK/GPIO53
CLK_54M
TPIO_SOP/GPIO52
CVBS_GC2
TPIO_VAL/GPIO51
CVBS_GC1
TPIO_ERR/GPIO50
CVBS_GC0
TPIO_DATA0/GPIO58
CVBS_UP
TPIO_DATA1/GPIO59
CVBS_DN
TPIO_DATA2/GPIO60
TPIO_DATA3/GPIO61
FS00CLK
TPIO_DATA4/GPIO62
H13A_AUDCLK_OUT
TPIO_DATA5/GPIO63
TPIO_DATA6/GPIO48
DAC_START
E16
AR35
D16
AP34
C16
AR34
AP33
E15
D15
AR33
C15
AP32
E14
AR32
D14
AP31
C14
AR31
E13
AP30
B18
AT36
A12
AT30
DAC_DATA3
AUDCLK_OUT
DAC_DATA2
DACLRCH
DAC_DATA1
DACSLRCH/GPIO127
DAC_DATA0
PCMI3SCK/GPIO112
DACSCK
AAD_GC4
DACLRCK
AAD_GC3
PCMI3LRCK/GPIO113
AAD_GC2
PCMI3LRCH
AAD_GC1
DACCLFCH/GPIO126
AAD_GC0
IEC958OUT
DACSUBMCLK
AAD_DATA9
DACSUBLRCH
AAD_DATA8
DACSUBSCK
AAD_DATA7
DACSUBLRCK
AAD_DATA6
TEST1
AAD_DATA5
TEST2
AAD_DATA4
L/DIM0_VS
L/DIM0_SCLK
L/DIM0_MOSI
10K 1%
TX0N
AAD_DATA2
TX0P
AAD_DATA1
TX1N
AAD_DATA0
TX1P
AAD_DATAEN
TX2N
TX2P
SCART_FB_BUFFER
R446
4.7K
+3.3V_NORMAL
SCART_Lout_SOC
EU
100K
R409
EU
C406
SCART_Rout_SOC
2.2uF
10V
SCART_FB_BUFFER
R401
SC_FB
470
B
AUDA_OUTL
R430
22K
C400
0.01uF
R445
22K
C401
0.01uF
1/16W
5%
R6451
100
AUDA_OUTR
HP_ROUT_MAIN
SCART_FB_BUFFER
1K R406
R6450
100
HP_LOUT_MAIN
Tuner IF Filter
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
AU32
A15
AT33
B15
AU33
A16
AT34
B16
AU34
A17
AT35
B17
AU35
AU15
R402
33
AN5
R405
33
AR14
R400
33
AP14
C456
4.7uF
10V
AN14
AP13
TX4N
HSR_AM
TX4P
HSR_BP
TX5N
HSR_BM
TX5P
HSR_CP
TX6N
HSR_CM
TX6P
HSR_CLKP
TX7N
HSR_CLKM
TX7P
HSR_DP
TX8N
HSR_DM
TX8P
HSR_EP
TX9N
HSR_EM
TX9P
TX10N
AUD_HPDRV_LRCH
TX10P
AUD_HPDRV_LRCK
TX11N
AUD_HPDRV_SCK
TX11P
TX12N
FRC_LR_O_SYNC_FLAG
PWM1
AF7
PWM2
AD7
AE6
AN8
AP8
AR7
AFE 3CH REF Setting
L406
OPT
TX13N
DIM0_MOSI
TX13P
DIM1_SCLK
TX14N
DIM1_MOSI
TX14P
TX15N
PWM0
TX15P
PWM1
TX16N
PWM2
TX16P
PWM_IN
TX17N
TX17P
AN7
EPI_EO
TX18N
EPI_VST
TX18P
EPI_DPM
TX19N
EPI_MCLK
TX19P
EPI_GCLK
TX20N
TX20P
TX21N
Placed as close as possible to IC4300
TX21P
TX22N
C444
Placed as close as possible to IC100
REFT
TX22P
0.1uF
HP_OUT
L400
BLM18PG121SN1D
HP_LOUT_AMP
TX23N
C446
0.1uF
HP_OUT
L401
BLM18PG121SN1D
HP_OUT
C407
0.22uF
10V
HP_LOUT
HP_ROUT_AMP
D13_STPO_ERR
AG36
D13_STPO_DATA
FE_DEMOD1_TS_CLK
AL36
FE_DEMOD1_TS_SYNC
AL35
AL37
FE_DEMOD1_TS_VAL
AM35
FE_DEMOD1_TS_ERROR
FE_DEMOD1_TS_DATA[0]
AN36
FE_DEMOD1_TS_DATA[1]
AN37
FE_DEMOD1_TS_DATA[2]
AN35
FE_DEMOD1_TS_DATA[3]
AP37
FE_DEMOD1_TS_DATA[4]
AP36
FE_DEMOD1_TS_DATA[5]
AR37
FE_DEMOD1_TS_DATA[6]
AR36
FE_DEMOD1_TS_DATA[7]
B29
B28
C28
B32
FE_DEMOD1_TS_DATA[0-7]
TPI_CLK
TPI_SOP
TPI_ERR
TP402
TPI_VAL
TPI_ERR
TPI_DATA[0-7]
TPI_DATA[0]
C31
TPI_DATA[1]
B31
TPI_DATA[2]
A31
TPI_DATA[3]
C30
TPI_DATA[4]
A30
TPI_DATA[5]
B30
TPI_DATA[6]
C29
TPI_DATA[7]
D30
TPO_CLK
D31
TPO_SOP
F30
TPO_VAL
TPO_ERR
TP400
TPO_ERR
E31
E30
TPO_DATA[0]
F29
TPO_DATA[1]
E29
TPO_DATA[2]
TPO_DATA[0-7]
TPO_DATA[3]
F28
E28
TPO_DATA[4]
D28
TPO_DATA[5]
E27
TPO_DATA[6]
TPO_DATA[7]
D27
R495
100
AD6
R496
100
Y6
R452
100
AC6
R497
AC5
R498
AA6
AUD_LRCH1
100
AUD_SCK
AUD_LRCK
100
FRC_DONE
AB7
AB5
URSA7_RESET
C411
10pF
50V
OPT
AU14
SPDIF_OUT
AA32
AA34
AA33
AB34
AE32
33
R493
AE33
33
R494
+3.3V_NORMAL
TXB4N/TX0N
AU6
TXB4P/TX0P
AT5
TXB3N/TX1N
AU5
TXB3P/TX1P
TXBCLKN/TX2N
AT4
AU4
TXBCLKP/TX2P
AU3
TXB2N/TX3N
AU2
TXB2P/TX3P
TXB1N/TX4N
AT2
AT1
TXB1P/TX4P
TXB0N/TX5N
TXB0P/TX5P
AR4
AR3
AP1
TXA4N/TX6N
AP2
TXA4P/TX6P
AP4
TXA3N/TX7N
AP3
TXA3P/TX7P
TXACLKN/TX8N
AN4
AN3
TXACLKP/TX8P
AM4
TXA2N/TX9N
TXA2P/TX9P
AM3
AL4
TXA1N/TX10N
AL3
TXA1P/TX10P
AK1
AK2
AK4
AK3
AJ3
AH4
AH3
AG4
AG3
AF1
AF2
AF4
AF3
AE4
TXA0N/TX11N
H13 Ball Name
TXA0P/TX11P
EPI Output
TXB2N
TXD4N/TX12N
TXB2P
TXD4P/TX12P
TXB1N
TXD3N/TX13N
TXB1P
TXB0N
TXD3P/TX13P
TXB0P
TXDCLKP/TX14P
TXA4N
TXA4P
TXACLKN
TXD2N/TX15N
TXACLKP
TXD1P/TX16P
TXA1N
TXD0N/TX17N
TXA1P
TXD0P/TX17P
TXDCLKN/TX14N
TXD2P/TX15P
TXD1N/TX16N
TXC4N
TXC4P
AE3
AD4
TXC3N
AD3
TXC3P
TXCCLKN
AC4
AC3
TXCCLKP
TXC2N
AB1
AB2
TXC2P
AB4
TXC1N
AB3
TXC1P
AA4
TXC0N
TXC0P
AA3
AR5
TX_LOCKN
REFB
AUD_MASTER_CLK
AUD_LRCH
Y7
TX23P
Must be used
C445
HP_OUT
C409
0.22uF
10V
D13_STPO_VAL
AG35
AJ4
DIM0_SCLK
C438
0.01uF
D13_STPO_SOP
AH36
TX12P
L_VSOUT_LD
AF6
BPL_IN
SC_FB_BUF
MMBT3904(NXP)
Q400
E SCART_FB_BUFFER
AT32
B14
TX3P
IF_P
51
C
AU31
A14
0.01uF
ADC_I_INP
1/16W
1%
2.2uF
10V
B13
IF_N
51
NON_TU_W_BR/TW
C436
22pF
NON_TU_W_BR/TW
R444
100K
R408
EU
EU
AT31
C437
To ADC
C403
AU30
A13
TX3N
HSR_AP
AP5
ADC_I_INN
D13_STPO_CLK
AH37
AT6
AAD_DATA3
AC7
TU_W_BR/TW TU_W_BR/TW TU_W_BR/TW
R443-*1
R444-*1
C436-*1
100pF
220
220
SCART_Lout
B12
AT15
1%
R458
47K
FE_DEMOD2_TS_DATA
AH35
AD5
ADCO_OUT_CLK
NC
AUAD_M_REF
FE_DEMOD2_TS_ERROR
AJ36
TPIO_DATA7/GPIO49
DAC_DATA4
AT14
EU
FE_DEMOD2_TS_VAL
AJ35
A28
BB_SDA
AP35
HSR_EM0
C448 OPT
4.7uF
10V
NON_TU_W_BR/TW
R443
HSR_CLKM0
FE_DEMOD2_TS_SYNC
AK37
TP_DVB_DATA7
BB_SCL
AU28
AR24
AUAD_R_REF
AUAD_R_CH2_IN
+12V
HSR_CLKP0
TP_DVB_CLK
BB_TPI_DATA0
C9
BIAS
C413
C434
R439
1%
COMP1/AV1/DVI_R_IN
EU
DTV/MNT_V_OUT
27K
AUAD_L_REF
DTV/MNT_V_OUT_SOC
OUT
R420
1
10K 1%
PS
COMP1/AV1/DVI_L_IN
6
IN
4.7uF
R438
VCC
AUAD_R_CH3_IN
OPT
R454
2
C433
27K
EU
1%
R419
SC_R_IN
1%
R455
51K
47K R456 1%
4.7uF
1/10W
5%
C432
C414
0.1uF
SC_L_IN
27K
4.7uF C449
AUAD_REF_PO
R418
HSR_CP0
FE_DEMOD2_TS_CLK
AK36
AM36
AT25
ADCO_OUT_CLK
+2.5V_Normal
AUDIO IN
100K
R403
EU
AUD_FS21CLK
R6006
EU
SCART_AMP_L_FB
100K
R404
EU
B2
AAD_DATAEN
EU
1uF 25V 10K
R6005
C6001
SCART_Rout
STPI0_DATA/GPIO43
AT20
C17
HW_OPT_6
H2
AUD_FS20CLK
AUD_HDMI_MCLK
AAD_GC0
HW_OPT_5
H3
STPI0_ERR/GPIO44
AU36
CVBS_DN
AUAD_L_REF
R3
STPI0_VAL/GPIO45
STPI1_DATA/GPIO54
B10
CLK_F54M
SCART_AMP_R_FB
25V 1uF
C6006
C4
BB_TP_DATA0
AUAD_R_CH2_IN
V2
F3
68 C441
SC_ID_SOC
COMP2_Y_IN_SOC_SOY
AUAD_L_CH3_IN
T1
ADC_I_INN
68 C440
68 C442
R2
U16
U14
V6
REFB
R1
BB_TP_DATA3
K17
U7
R448
0.047uF
C429
C431
AUAD_R_REF
BB_TP_SOP
0
C439
100pF
50V
OPT
COMP1_PR_IN_SOC
R447
COMP1_Y
50V 10pF
C470
H13A_SDA
CVBS_IN3
0.047uF V13
REFT
R429
C430
AUAD_R_CH1_IN
Placed as close as possible to SOC
COMP1_Pb
50V 10pF
2.2uF
BB_TP_VAL
N1
AUAD_REF_PO
V14
DTV/MNT_V_OUT_SOC
COMP1_Y_IN_SOC_SOY
EU
EU
1% 75
R412
R414 1% 75
EU
R416 1% 75
OPT 50V 10pF
C473
OPT 50V 10pF
C474
C472
OPT 50V 10pF
AUAD_R_CH2_IN
H13A_SCL
U13
C443
R450 68
COMP1_PB_IN_SOC
COMP1_Y_IN_SOC
0.047uF
AT22
A4
STPI0_SOP/GPIO46
INTR_AGPIO
I2S_I/F
R425
33 C417
33 C418
R428
D406
OPM1
AUAD_L_REF
TU_CVBS_SOC
D403
AUAD_L_CH2_IN
AUAD_L_CH1_IN
B8
SC_CVBS_IN_SOC
5.5V
AUAD_R_CH3_IN
OPM0
AUAD_M_REF
C428
D401
AUAD_L_CH3_IN
A8
H13A_SDA
SC_G
SC_CVBS_IN_SOY
5.5V
AUAD_R_CH4_IN
K2
H13A_SCL
NON_EU
R436-*1
0
R424
5.5V
AUD_SCART_OUTR
K3
AV1_CVBS_IN_SOC
EU
AUD_SCART_OUTL
XTAL_SEL1
PORES_N
OPM[1]
SC_ID_SOC
SC_B
COMP1_Pr
XTAL_SEL0
E3
OPM[0]
SC_FB_SOC
SC_R
AUDA_OUTR
BB_TP_CLK
BB_TP_ERR
C458
EU
C460
SCART_FB_DIRECT
R423
100
0
AUDA_OUTL
CLK_24M
AUAD_L_CH4_IN
SC_FB
NON_EU
R422-*1
XTAL_BYPASS
C453
TUNER_SIF
C457
1000pF
OPT
P3
SOC_RESET
R435
0.1uF
10uF
TU_CVBS_SOC
C402
150pF
50V
OPT
SC_ID
0.1uF
C451
C452
EU R426
22K
TU_CVBS
AUDA_VBG_EXT
N18
EU
EU
C450
H17
P2
SC_CVBS_IN_SOC
C408
150pF
50V
EU
H18
AAD_ADC_SIFM
0.01uF
P17
XIN_SUB
XOUT_SUB
BB_SDA
EU
R410
75
1%
SC_CVBS_IN
AU23
A7
BB_SCL
0.01uF
C410
150pF
AT23
B5
AUD_ADC_LRCH
AV1_CVBS_IN_SOC
C405
150pF
50V
5.5V
D404
A5
A2
AUD_DAC1_LRCK
AUD_DAC0_LRCH
R434
AU24
C18
AUD_DAC0_SCK
L408 1uH
B6
AUD_HDMI_MCLK
OPM[0]
100
AUD_DAC0_LRCK
Place SOC Side
AT24
STPI0_CLK/GPIO47
INTR_AFE3CH
AUDCLK_OUT_SUB
FOR EMI
Place JACK Side
A6
AK35
INTR_GBB
4.7K
R463
0.1uF
HP_ROUT
DIMMING
Place at JACK SIDE
PWM_DIM2
R490
100
PWM_DIM
R489
100
LG1154A
LG1154D
PWM1
PWM2
BSD-NC4_H004-HD
2012-11-13
MAIN AUDIO/VIDEO
LGE Internal Use Only
DDR_VTT
IC100
LG1154D_H13D
F15
M0_DDR_A[0]
M0_DDR_A[1]
M0_DDR_A[2]
M0_DDR_A[3]
M0_DDR_A[4]
M0_DDR_A[5]
M0_DDR_A[6]
M0_DDR_A[7]
M0_DDR_A[8]
M0_DDR_A[9]
M0_DDR_A[10]
M0_DDR_A[11]
M0_DDR_A[12]
M0_DDR_A[13]
M0_DDR_A[14]
F19
M0_DDR_A3
E10
F18
M0_DDR_A11
E13
M0_DDR_A13
M0_DDR_A14
F12
F14
M0_DDR_D_CLK
M0_DDR_D_CLKN
M0_U_CLKN
M0_D_CLKN
E14
M0_DDR_RASN
M0_DDR_CASN
E21
E20
F20
E17
F9
M0_DDR_ZQCAL
H2
M0_DDR_CASN
G1
M0_DDR_DQS[1]
M0_DDR_DQS_N[1]
M0_DDR_DQS[2]
M0_DDR_DQS_N[2]
M0_DDR_DQS[3]
M0_DDR_DM[2]
A20
C19
M0_DDR_DQS1
D19
M0_DDR_DQS_N1
A11
M0_DDR_DQ[2]
M0_DDR_DQ[3]
M0_DDR_DQ[4]
M0_DDR_DQ[5]
M0_DDR_DQ[6]
M0_DDR_DQ[7]
M0_DDR_DQ[8]
M0_DDR_DQ[9]
M0_DDR_DQ[10]
M0_DDR_DQ[11]
M0_DDR_DQ[12]
M0_DDR_DQ[13]
M0_DDR_DQ[14]
M0_DDR_DQ[15]
M0_DDR_DQ[16]
M0_DDR_DQ[17]
M0_DDR_DQ[18]
M0_DDR_DQ[19]
M0_DDR_DQ[20]
M0_DDR_DQ[21]
M0_DDR_DQ[22]
M0_DDR_DQ[23]
M0_DDR_DQ[24]
M0_DDR_DQ[25]
M0_DDR_DQ[26]
M0_DDR_DQ[27]
M0_DDR_DQ[28]
M0_DDR_DQ[29]
M0_DDR_DQ[30]
A15
VDD_7
M0_DDR_A11
G2
M0_DDR_A12
G8
M0_DDR_A13
K1
M0_DDR_A14
K9
M0_DDR_A15
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J7
M9
M0_DDR_BA0
VDD_9
BA1
M0_DDR_BA1
BA2
M0_DDR_BA2
J3
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
C1
M0_D_CLK
E2
C559
0.1uF
M0_D_CLKN
E9
C560
0.1uF
M0_DDR_CKE
K2
L8
M0_DDR_A4
A4
A5
240
1%
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
A13
VDD_5
A14
VDD_6
A15
VDD_7
BA0
N8
M0_DDR_A8
M3
M0_DDR_A9
A9
H7
M0_DDR_A10
D7
M7
M0_DDR_A11
G2
K7
M0_DDR_A12
G8
N3
M0_DDR_A13
K1
N7
M0_DDR_A14
K9
J7
M0_DDR_A15
M1
VDD_8
M2
M0_DDR_A7
A2
A9
M8
M0_DDR_A6
ZQ
A7
A8
L2
M0_DDR_A5
VDDC15_M0
R560
H8
A6
M9
K8
M0_DDR_BA1
BA1
VDDQ_1
CK
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
J3
M0_DDR_BA2
B9
C1
E2
C583
0.1uF
E9
C574
0.1uF
M0_DDR_ODT
M0_DDR_RASN
RAS
M0_DDR_CASN
CAS
M0_DDR_WEN
WE
M0_DDR_RESET_N
RESET
G1
F3
G3
H3
A0
M0_U_CLK
G7
M0_U_CLKN
G9
M0_DDR_CKE
G1
F3
M0_DDR_RASN
G3
M0_DDR_CASN
CAS
H3
M0_DDR_WEN
WE
L7
L3
K2
M0_DDR_A3
A4
A5
R559
H8
A6
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
A13
VDD_5
A14
VDD_6
A15
VDD_7
VDD_8
BA0
M8
M0_DDR_A6
M2
M0_DDR_A7
A2
VDD_1
L2
M0_DDR_A5
240
1%
A9
L8
M0_DDR_A4
VDDC15_M0
ZQ
A7
A8
N8
M0_DDR_A8
A9
M3
M0_DDR_A9
D7
H7
M0_DDR_A10
G2
M7
M0_DDR_A11
G8
K7
M0_DDR_A12
K1
N3
M0_DDR_A13
K9
N7
M0_DDR_A14
M1
J7
M0_DDR_A15
M9
VDD_9
CK
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
K8
M0_DDR_BA1
B9
J3
M0_DDR_BA2
C1
E2
C568
0.1uF
E9
C569
0.1uF
A0
J8
VREFCA
A1
A2
E1
A3
VREFDQ
A4
A5
H8
A6
240
1%
A7
A8
A2
A9
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
A13
VDD_5
A14
VDD_6
A15
VDD_7
VDD_8
BA0
G7
G9
M0_DDR_CKE
CS
D7
G2
G8
K1
K9
M1
M9
BA1
B9
VDDQ_1
F7
M0_U_CLK
A9
VDD_9
BA2
M0_U_CLKN
VDDC15_M0
R561
ZQ
J2
M0_DDR_BA0
BA1
VDDQ_1
M0_1_DDR_VREFCA_T
M0_1_DDR_VREFDQ_T
DDR3
4Gbit
K3
M0_DDR_A2
VREFDQ
CK
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
C1
E2
C572
0.1uF
E9
C577
0.1uF
H2
ODT
G1
M0_DDR_ODT
RAS
CAS
M0_DDR_RASN
WE
M0_DDR_CASN
F3
G3
H3
M0_DDR_WEN
N2
M0_DDR_RESET_N
RESET
IC505
H5TQ4G83AFR-PBC
R3104
56
M0_DDR_A1
E1
A3
F7
M0_DDR_ODT
RAS
AR12
56
M0_DDR_A0
A2
BA2
CS
N2
AR11
56
J8
H2
ODT
AR10
56
VREFCA
A1
J2
M0_DDR_BA0
VDD_9
F7
G9
L3
M0_DDR_A3
VREFDQ
BA2
G7
L7
M0_DDR_A2
E1
A3
B9
CK
K3
M0_DDR_A0
M0_DDR_A1
A2
J2
K8
J8
VREFCA
A1
M1
N2
D3
M0_DDR_DQS_N0
DQS
M0_DDR_DQS_N1
A1
DM/TDQS
A7
VSS_1
NF/TDQS
M0_DDR_DQS3
D10
DQS
M0_DDR_DQS1
B7
M0_DDR_DM0
M0_DDR_DQS_N2
C10
C3
M0_DDR_DQS0
M0_DDR_DQS2
B11
VSS_2
VSS_3
M0_DDR_DQS_N3
VSS_4
VSS_5
M0_DDR_DM0
C20
M0_DDR_DM1
D9
D23
A15
C16
D21
D17
D2
M0_DDR_DQ6
E7
M0_DDR_DQ7
M0_DDR_DQ4
B15
E8
M0_DDR_DQ5
M0_DDR_DQ3
B24
E3
M0_DDR_DQ4
M0_DDR_DQ2
D16
C8
M0_DDR_DQ3
M0_DDR_DQ1
C23
C2
M0_DDR_DQ2
M0_DDR_DQ0
C15
C7
M0_DDR_DQ1
M0_DDR_DM3
VSS_6
B3
M0_DDR_DQ0
M0_DDR_DM2
C11
D22
M0_DDR_DQ[1]
VDD_6
M0_DDR_A10
D7
ODT
H3
M0_DDR_DQS_N0
M0_DDR_DM[3]
M0_DDR_DQ[0]
A14
A9
L3
AR9
56
AR8
56
AR7
56
CS
ODT
RAS
CAS
WE
RESET
N2
RESET
M0_DDR_DQS0
D18
M0_DDR_DM[1]
VDD_5
L7
A0
DDR3
4Gbit
M0_DDR_RESET_N
M0_DDR_DQS_N[3]
M0_DDR_DM[0]
VDD_4
A13
CS
G3
M0_DDR_WEN
M0_DDR_RESET_N
B20
M0_DDR_DQS_N[0]
M0_DDR_RASN
M0_DDR_CASN
M0_DDR_A8
M0_DDR_A9
DDR3
4Gbit
K3
H2
F3
R500
240
1%
M0_DDR_DQS[0]
M0_DDR_ODT
M0_DDR_RESET_N
M0_DDR_RESET_N
G9
M0_DDR_RASN
M0_DDR_WEN
M0_DDR_WEN
VDD_3
A12/BC
VDDQ_1
G7
M0_D_CLKN
M0_DDR_CKE
M0_DDR_ODT
VDD_2
A11
F7
M0_D_CLK
M0_DDR_CKE
F21
A10/AP
BA0
J3
M0_DDR_BA2
M0_D_CLK
B19
VDD_1
VDD_8
K8
M0_DDR_BA1
M0_DDR_A6
M0_DDR_A7
A2
A9
J2
M0_DDR_BA0
M0_U_CLK
A19
J7
M0_DDR_A15
M0_DDR_BA2
A10
N7
M0_DDR_A14
M0_DDR_BA1
E15
N3
M0_DDR_A13
M0_DDR_BA0
F10
M0_DDR_CKE
M0_DDR_ODT
K7
M0_DDR_A12
B10
M0_DDR_U_CLKN
M7
M0_DDR_A11
M0_DDR_A5
VDDC15_M0
R558
240
1%
A7
H7
M0_DDR_A10
M0_DDR_A15
M0_DDR_A4
H8
ZQ
A8
M3
M0_DDR_A9
VREFDQ
A6
N8
M0_DDR_A8
M0_DDR_A12
E16
M0_DDR_A1
A5
M2
M0_DDR_A7
M0_DDR_A3
A4
M8
M0_DDR_A6
E1
M0_DDR_A2
A3
L2
M0_DDR_A5
M0_DDR_A9
M0_DDR_A10
E12
L8
M0_DDR_A4
M0_DDR_A8
E9
M0_DDR_A0
VREFCA
A2
K2
M0_DDR_A3
M0_DDR_A7
F11
F16
J8
M0_DDR_VREFCA_T
M0_DDR_VREFDQ_T
M0_1_DDR_VREFDQ
A1
L3
M0_DDR_A2
M0_DDR_A6
A0
L7
M0_DDR_A1
M0_DDR_A5
E11
M0_DDR_BA[2]
M0_DDR_U_CLK
M0_DDR_A0
M0_DDR_A4
E18
DDR3
4Gbit
K3
IC504
H5TQ4G83AFR-PBC
M0_1_DDR_VREFCA
M0_DDR_VREFDQ
M0_DDR_A2
E19
M0_DDR_BA[1]
IC502
H5TQ4G83AFR-PBC
M0_DDR_VREFCA
M0_DDR_A1
F17
M0_DDR_A[15]
M0_DDR_BA[0]
IC500
H5TQ4G83AFR-PBC
M0_DDR_A0
F13
M0_DDR_DQ5
A3
M0_DDR_DQ6
F1
M0_DDR_DQ7
F9
M0_DDR_DQ8
H1
M0_DDR_DQ9
H9
VSS_7
DQ1
VSS_8
DQ2
VSS_9
DQ3
VSS_10
DQ4
VSS_11
DQ5
VSS_12
D3
DQS
M0_DDR_DQS2
DQS
M0_DDR_DQS_N2
B7
A7
A1
DM/TDQS
VSS_1
NF/TDQS
VSS_2
B1
D8
VSS_5
F8
VSS_6
J1
M0_DDR_DQ8
J9
M0_DDR_DQ9
L1
M0_DDR_DQ10
L9
B3
C7
C2
C8
M0_DDR_DQ11
N1
E3
M0_DDR_DQ12
N9
E8
M0_DDR_DQ13
M0_DDR_DQ14
DQ7
M0_DDR_DQ15
D2
E7
DQ0
VSS_7
DQ1
VSS_8
DQ2
VSS_9
DQ3
VSS_10
DQ4
VSS_11
DQ5
VSS_12
NC_1
VSSQ_2
NC_2
VSSQ_3
NC_3
VSSQ_4
NC_4
VSSQ_5
B8
C9
F1
D1
F9
D9
H1
H9
B7
A7
VSS_5
F8
J9
C7
M0_DDR_DQ17
L1
C2
M0_DDR_DQ18
L9
C8
M0_DDR_DQ19
N1
E3
M0_DDR_DQ20
N9
VSSQ_1
VSSQ_2
VSSQ_3
NC_3
VSSQ_4
NC_4
VSSQ_5
E8
M0_DDR_DQ21
D2
E7
M0_DDR_DQ23
DQ0
VSS_7
DQ1
VSS_8
DQ2
VSS_9
DQ3
VSS_10
DQ4
VSS_11
DQ5
VSS_12
B8
A3
C9
F1
D1
F9
D9
H1
H9
B7
M0_DDR_DM3
B1
A7
D8
VSSQ_2
NC_2
VSSQ_3
NC_3
VSSQ_4
NC_4
VSSQ_5
VSS_1
NF/TDQS
VSS_2
VSS_3
VSS_4
F8
VSS_5
J1
J9
L1
C7
M0_DDR_DQ25
L9
C2
M0_DDR_DQ26
N1
C8
M0_DDR_DQ27
N9
E3
M0_DDR_DQ28
E8
D2
M0_DDR_DQ30
E7
M0_DDR_DQ31
B8
VSS_6
B3
M0_DDR_DQ24
B2
NC_1
A1
DM/TDQS
F2
M0_DDR_DQ29
VSSQ_1
DQS
DQS
A8
DQ6
DQ7
NC_5
NC_5
VSS_6
B3
M0_DDR_DQ16
B2
NC_2
VSS_2
VSS_4
M0_DDR_DQ22
NC_1
VSS_1
NF/TDQS
D3
M0_DDR_DQS_N3
A1
DM/TDQS
F2
J1
C3
M0_DDR_DQS3
DQS
VSS_3
DQ6
B2
DQS
D8
DQ7
A3
D3
B1
VSS_4
F2
C3
M0_DDR_DM2
A8
VSS_3
DQ6
VSSQ_1
M0_DDR_DQ10
C22
DQ0
M0_DDR_DM1
A8
C3
DQ0
VSS_7
DQ1
VSS_8
DQ2
VSS_9
DQ3
VSS_10
DQ4
VSS_11
DQ5
VSS_12
A3
D1
F1
D9
F9
H1
NC_5
H9
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
DQ6
DQ7
C9
A8
B2
VSSQ_1
NC_1
VSSQ_2
NC_2
VSSQ_3
NC_3
VSSQ_4
NC_4
VSSQ_5
B8
C9
D1
D9
NC_5
M0_DDR_DQ11
C18
M0_DDR_DQ12
C21
M0_DDR_DQ13
C17
M0_DDR_DQ14
D20
M0_DDR_DQ15
C13
M0_DDR_DQ16
M0_DDR_DQ17
D7
D13
M0_DDR_DQ18
C6
M0_DDR_DQ19
D14
M0_DDR_DQ20
D6
M0_DDR_DQ21
C14
M0_DDR_DQ22
A5
M0_DDR_DQ23
C7
M0_DDR_DQ24
D12
Real USE : 1Gbit
M0_DDR_DQ25
D8
H5TQ1G63DFR-PBC(x16)
M0_DDR_DQ26
B13
M0_DDR_DQ27
C9
M0_DDR_DQ28
C12
1Gbit : T7(NC_6)
M0_DDR_DQ29
C8
DDR_SAMSUNG
IC501
K4B4G1646B-HCK0
M0_DDR_DQ30
D11
M0_DDR_DQ31
M0_DDR_DQ[31]
DDR_SAMSUNG
IC503
K4B4G1646B-HCK0
4Gbit : T7(A14)
DDR_HYNIX
IC501-*1
M1_DDR_VREFCA
DDR_HYNIX
IC503-*1
M1_1_DDR_VREFCA
H5TQ4G63AFR-PBC
H5TQ4G63AFR-PBC
M8
N3
P7
M8
N3
P3
M1_DDR_A1
M1_DDR_A2
M1_DDR_A3
M1_DDR_A4
IC100
LG1154D_H13D
M1_DDR_A5
M1_DDR_A6
M1_DDR_A7
M1_DDR_A8
M1_DDR_A[8]
M1_DDR_A[9]
M1_DDR_A[10]
M1_DDR_A[11]
M1_DDR_A[12]
M1_DDR_A[13]
M1_DDR_A[14]
M1_DDR_A12
J5
M1_DDR_A5
T5
K6
U6
M6
V5
R520
M1_DDR_A9
10K
M1_DDR_D_CLK
M1_DDR_D_CLKN
M1_DDR_A15
10K
L5
T6
M1_DDR_BA2
M1_D_CLK
M1_D_CLKN
R540
M1_DDR_A14
P6
M1_DDR_BA0
V6
M1_DDR_BA1
M5
M1_DDR_BA2
10K
R521
M1_DDR_RESET_N
M1_D_CLK
F2
M1_D_CLKN
N5
M1_DDR_RASN
M1_DDR_CASN
M0_U_CLKN
M1_DDR_WEN
M0_U_CLK
M0_D_CLK
M1_U_CLK
M1_D_CLK
M1_DDR_RESET_N
M0_U_CLKN
M1_D_CLKN
M1_U_CLKN
M1_DDR_DQS_N0
M1_DDR_ODT
F5
G5
H6
M1_DDR_RASN
M1_DDR_DQS1
M1_DDR_CASN
M1_DDR_DQS_N1
M1_DDR_WEN
M1_DDR_WEN
M1_DDR_DM0
K5
R501
M1_DDR_DM[2]
P3
M1_DDR_DM[3]
M1_DDR_DM2
R531
1K 1%
M1_DDR_DQ5
M1_DDR_DQ6
0.1uF
1%
R532
1K
M1_DDR_DQ8
M1_DDR_DQ9
M1_DDR_DQ10
C508
0.1uF
R510
1K 1%
1%
R511
1K
0.1uF
R554
1K 1%
1%
R555
1K
0.1uF
1K 1%
R550
R551
0.1uF
1%
1K 1%
R536
M1_DDR_DQ3
M1_DDR_DQ7
C500
M1_DDR_DM1
C552
T4
M1_DDR_DM0
1K
M1_DDR_DM[1]
E3
M1_DDR_DQS_N3
C550
M1_DDR_DM[0]
M1_DDR_DQS3
C512
G4
1%
R4
M1_DDR_DQS_N[3]
M1_DDR_VREFCA
M1_DDR_DQ4
M1_DDR_DQS_N2
R537
M1_DDR_DQS[3]
P2
R3
M1_DDR_DQS2
M1_1_DDR_VREFCA
M0_1_DDR_VREFCA_T
M0_DDR_VREFCA_T
1K
M1_DDR_DQS_N[2]
P1
M1_DDR_DQS_N1
0.1uF
M1_DDR_DQS[2]
F4
M1_DDR_DQS1
R514
M1_DDR_DQS_N[1]
F3
M1_DDR_DQ2
M0_DDR_VREFCA
M1_DDR_DQS_N0
1K 1%
M1_DDR_DQS[1]
E1
M1_DDR_DQ1
M0_1_DDR_VREFCA
M1_DDR_DQS0
1%
M1_DDR_DQS_N[0]
VDDC15_M1
VDDC15_M1
VDDC15_M0
VDDC15_M0
R515
E2
M1_DDR_DQS[0]
M1_DDR_DQ0
VDDC15_M0
VDDC15_M0
1%
1K
240
C504
F6
M1_DDR_ZQCAL
M1_DDR_DM1
M1_DDR_RESET_N
M1_DDR_RESET_N
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DM3
M1_DDR_DQ14
M1_DDR_DQ[17]
M1_DDR_DQ[18]
M1_DDR_DQ[19]
M1_DDR_DQ[20]
M1_DDR_DQ[21]
M1_DDR_DQ[22]
M1_DDR_DQ[23]
M1_DDR_DQ[24]
M1_DDR_DQ[25]
M1_DDR_DQ[26]
M1_DDR_DQ[27]
M1_DDR_DQ[28]
M1_DDR_DQ[29]
M1_DDR_DQ[30]
M1_DDR_DQ[31]
M4
W3
L4
W4
L3
Y2
V3
N4
U4
M2
T3
N3
U3
P4
T3
T7
M7
K9
L8
J3
K3
L3
A9
A10/AP
A11
A12/BC
A13
A14
BA0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDDQ_2
CK
VDDQ_3
VDDQ_4
VDDQ_5
CS
ODT
RAS
CAS
VDDQ_6
VDDQ_7
VDDQ_8
H8
G2
H7
C2
A7
A2
B8
A3
M1_DDR_A5
M1_DDR_A6
F1
H2
H9
M1_DDR_A7
J9
L1
M1_DDR_A8
L9
NC_4
DQSL
VSS_1
VSS_2
VSS_3
E7
D3
G7
K2
K8
N1
N9
R1
R9
A8
C1
C9
D2
E9
F1
H2
C529
0.1uF
H9
C530
0.1uF
J9
L1
L9
NC_4
DML
VSS_4
DMU
VSS_5
VSS_6
E3
F7
F2
F8
H3
H8
G2
H7
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
C3
C8
C2
A2
B8
A3
B3
M1_DDR_A10
E1
G8
J2
J8
M1_DDR_A11
M1
M9
P1
M1_DDR_A12
P9
T1
T9
M1_DDR_A13
DQL6
DQL7
B1
VSSQ_1
D7
A7
M1_DDR_A9
A9
DQSU
DQSU
DQU0
DQU1
VSSQ_2
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
DQU5
VSSQ_6
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
M1_DDR_A14
D1
D8
E2
M1_DDR_A15
E8
F9
M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2
M1_U_CLK
M1_U_CLKN
M1_DDR_CKE
VSS_1
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
M1_DDR_ODT
M1_DDR_RASN
M1_DDR_CASN
M1_DDR_WEN
M1_DDR_RESET_N
A9
M1_DDR_DQS3
B3
M1_DDR_DQS_N3
G8
M1_DDR_DM2
J2
M1_DDR_DM3
VSSQ_2
VSSQ_3
DQU6
DQU7
R3
L7
R7
N7
T3
T7
M7
A6
K1
J3
K3
L3
M1_DDR_DQ16
M9
M1_DDR_DQ17
P1
M1_DDR_DQ18
P9
M1_DDR_DQ19
T1
M1_DDR_DQ20
T9
M1_DDR_DQ21
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
B9
M1_DDR_DQ24
D1
M1_DDR_DQ25
D8
M1_DDR_DQ26
E2
M1_DDR_DQ27
E8
M1_DDR_DQ28
F9
M1_DDR_DQ29
G1
M1_DDR_DQ30
G9
M1_DDR_DQ31
VSSQ_9
H1
VREFDQ
L8
ZQ
B2
VDD_1
VDD_2
VDD_3
A13
VDD_5
A14
VDD_6
A15
VDD_7
BA0
VDD_9
VDD_8
K1
240
J3
K3
L3
A7
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
G3
A9
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
A13
VDD_5
VDD_6
A14
VDD_7
VDD_8
BA0
C7
D9
E7
B7
D3
G7
K2
K8
N1
N9
R1
R9
A1
VDDQ_1
VDDQ_2
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
A8
C1
C9
D2
E9
F1
H2
C561
0.1uF
H9
C562
0.1uF
J1
NC_1
T2
RESET
NC_2
J9
L1
L9
NC_4
F3
D2
E9
F1
H2
H9
J9
L1
L9
DQSL
A9
DQSU
DQSU
BA1
CK
A8
C1
C9
NC_4
DQSL
VDD_9
CK
NC_2
NC_3
B2
R9
J1
NC_1
RESET
F3
A8
K8
N1
N9
R1
A1
VDDQ_1
CK
CK
T2
VDDC15_M1
D9
G7
K2
BA1
WE
WE
G3
R545
ZQ
BA2
K9
VREFCA
VDD_4
L2
L8
J7
K7
A9
A10/AP
A11
A12/BC
CKE
A5
M2
M3
A6
A7
A8
J7
K7
K9
A15
N8
A3
A4
A5
M2
N8
M3
A4
DML
F7
F2
F8
H8
G2
H7
VSS_4
DMU
VSS_5
DQL0
VSS_7
VSS_6
E3
H3
VSS_1
VSS_2
VSS_3
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
C2
A7
A2
B8
A3
J2
J8
M1
M9
P1
P9
T1
T9
B1
VSSQ_1
D7
C3
C8
B3
E1
G8
DQL6
DQL7
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
DQU3
VSSQ_4
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
DQSL
DQSL
C7
B7
A9
DQSU
VSS_1
DQSU
VSS_2
VSS_3
E7
D3
DML
VSS_4
DMU
VSS_5
J8
M1
M1_DDR_DQ23
VSSQ_1
DQU5
T8
M7
A0
A1
A2
BA2
VSS_6
E3
F7
F2
F8
H3
H8
G2
H7
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
DQL7
C8
C2
A7
A2
B8
A3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
VSSQ_1
D7
C3
B3
DQL6
B1
DQU1
DQU4
R2
T3
T7
VREFDQ
E1
M1_DDR_DQ22
DQU0
DQU3
R8
N7
NC_3
DQL6
DQU2
P2
L7
H1
A3
L2
M1_DDR_DQS2
DQSU
N2
P8
A2
R2
T8
R3
R7
G1
M1_DDR_DQS_N2
DQSU
P3
G9
DQSL
D7
C8
C1
C9
D2
E9
DQSL
DQL7
C3
M1_DDR_A4
A8
DQSL
J1
NC_2
M1_DDR_A3
J1
NC_1
NC_2
C7
VDDQ_9
NC_1
E3
H3
D9
B7
A1
VDDQ_1
CK
E7
F8
B2
G3
VDD_9
C7
F2
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
WE
BA1
F3
F7
CS
ODT
RAS
CAS
F3
VDD_8
RESET
D3
VDDQ_3
VDDQ_4
NC_3
T2
B7
L3
VDDQ_2
VDDQ_5
RESET
WE
G3
CK
T2
A8
CKE
K1
K1
J3
K3
VDDC15_M1
BA2
K9
240
N9
R1
R9
A1
VDDQ_1
L2
R543
ZQ
M1_DDR_A2
BA1
CK
CKE
A7
J7
K7
VDD_8
BA2
K7
M2
M3
VDD_7
VDD_9
J7
A5
A15
N8
A15
BA0
K2
K8
N1
A1
P2
R8
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
0.1uF
R533
1K 1%
1%
1K
R534
* DDR_VTT
VDDC15_M0
C509
0.1uF
R512
1K 1%
1%
R513
R556
R552
1K 1%
R538
1K 1%
1%
0.1uF
M1_DDR_DQ14
M1_DDR_DQ15
M1_DDR_DQ16
M1_DDR_DQ17
R557
M1_DDR_DQ13
M1_1_DDR_VREFDQ
C501
V4
N7
M3
A4
A6
VDD_6
M2
N8
VDD_3
VDD_4
VDD_5
A14
P7
M8
VREFCA
M1_DDR_VREFDQ
1K
M3
M1_DDR_DQ12
1K
E4
M1_DDR_DQ11
0.1uF
H3
M1_DDR_DQ10
1%
D3
M1_DDR_DQ9
M0_1_DDR_VREFDQ_T
M0_DDR_VREFDQ_T
C553
M1_DDR_DQ[16]
G3
L7
R7
M7
A11
A12/BC
A13
D9
G7
DDR3
4Gbit
(x16)
VDDC15_M1
VDDC15_M1
VDDC15_M0
VDDC15_M0
R553
M1_DDR_DQ[15]
C3
R3
H1
VREFDQ
M1_DDR_A1
B2
VDD_1
VDD_2
A0
M0_1_DDR_VREFDQ
M0_DDR_VREFDQ
1K
M1_DDR_DQ[14]
H4
T8
T7
A8
A9
A10/AP
N3
VDDC15_M0
VDDC15_M0
C551
M1_DDR_DQ[13]
D4
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ8
0.1uF
M1_DDR_DQ[12]
J3
R2
N7
T3
N2
P8
M1_DDR_A0
L8
ZQ
M1_DDR_DQ3
M1_DDR_DQ7
C513
M1_DDR_DQ[11]
K1
1K 1%
M1_DDR_DQ[9]
B4
1%
M1_DDR_DQ[8]
M1_DDR_DQ[10]
K2
R539
M1_DDR_DQ[7]
A3
1K
M1_DDR_DQ[6]
0.1uF
M1_DDR_DQ[5]
R516
M1_DDR_DQ[4]
R8
T8
R3
L7
R7
P3
A4
A5
A6
A7
M1_DDR_DQ2
1K 1%
M1_DDR_DQ[3]
J4
P2
P2
R8
R2
M1_1_DDR_VREFDQ
M1_DDR_DQ1
1%
M1_DDR_DQ[2]
B3
M1_DDR_DQ0
R517
M1_DDR_DQ[1]
K3
1K
M1_DDR_DQ[0]
M1_DDR_DQ15
C505
C4
P8
A3
M8
VREFCA
NC_3
M1_DDR_DQS0
M1_DDR_CKE
N2
A2
L2
M1_DDR_ODT
M1_U_CLKN
F1
M1_DDR_CKE
10K
M0_D_CLKN
M1_U_CLK
R1
M0_U_CLK
M0_D_CLK
M1_DDR_A15
G6
M1_DDR_ODT
M1_DDR_CKE
VDDC15_M1
M1_DDR_A12
M1_DDR_A13
M0_D_CLKN
M1_DDR_CASN
M1_DDR_BA1
M0_DDR_RESET_N
M1_DDR_A11
P5
M1_DDR_CKE
M1_DDR_RASN
M1_DDR_BA0
M1_DDR_A10
R5
R2
M1_DDR_U_CLKN
M0_DDR_CKE
R541
M1_DDR_A8
M1_DDR_BA[2]
M1_DDR_U_CLK
VDDC15_M0
M1_DDR_A7
H5
M1_DDR_BA[1]
M1_DDR_A14
M1_DDR_A6
M1_DDR_A[15]
M1_DDR_BA[0]
M1_DDR_A13
M1_DDR_A4
P3
A1
DDR3
4Gbit
(x16)
H1
VREFDQ
+3.3V_NORMAL
IC506
TPS51200DRCR
R546
10K 1%
[EP]
L501
CIS21J121
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20
R549
10K
1%
C502
10uF
C510
1000pF
REFIN
VLDOIN
M1_DDR_DQ23
M1_DDR_DQ24
DDR_VTT
C511
10uF
M1_DDR_DQ25
VO
10
1
M1_DDR_DQ21
M1_DDR_DQ22
2
11
M1_DDR_A[7]
M1_DDR_A3
100
R530
M1_DDR_A[6]
M1_DDR_A11
100
R518
M1_DDR_A[5]
U5
M1_DDR_A2
200
R535
M1_DDR_A[4]
J6
M1_DDR_A10
200
R581
M1_DDR_A[3]
L6
M1_DDR_A1
200
R519
M1_DDR_A[2]
R6
M1_DDR_A9
200
R580
M1_DDR_A[1]
M1_DDR_A0
P7
A0
A1
A2
A3
THERMAL
N6
M1_DDR_A[0]
N3
P8
DDR3 1.5V bypass Cap - Place these caps near Memory
M1_DDR_A0
N2
M1_DDR_VREFDQ
VREFCA
A0
DDR3 1.5V bypass Cap - Place these caps near Memory
P7
9
3
8
4
7
5
6
VIN
PGOOD
C515
4700pF
GND
DDR_VTT
M1_DDR_DQ26
M1_DDR_DQ27
M1_DDR_DQ28
PGND
L500
CIS21J121
EN
M1_DDR_DQ29
VOSNS
M1_DDR_DQ30
M1_DDR_DQ31
C503
10uF
C506
10uF
C507
10uF
REFOUT
C519
0.1uF
16V
C514
0.1uF
C520
0.1uF
16V
C521
0.1uF
16V
C522
0.1uF
16V
Close to REFOUT pin
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-NC4_H005-HD
2012-09-14
MAIN DDR
LGE Internal Use Only
+5V_CI_ON
R711
10K
OPT
R712
10K
OPT
CI_DATA[0-7]
CI
JK700
10120698-015LF
R716
/CI_CD1
CI_TS_DATA[3]
R708
10K
OPT
R706
10K
OPT
100
CI
/PCM_WAIT
R700
33 OPT
5
CI_DATA[6]
CI_TS_DATA[6]
CI_TS_DATA[7]
6
CI_DATA[7]
CI R721
41
R707
10K
OPT
CI_ADDR[10]
8
43
9
44
10
CI_ADDR[11]
45
11
CI_ADDR[9]
46
12
CI_IN_TS_DATA[0]
47
13
CI_IN_TS_DATA[1]
48
14
CI_IN_TS_DATA[2]
49
15
CI_IN_TS_DATA[3]
50
16
51
17
52
18
0
OPT
0
OPT
R722
C706
0
R718
0.1uF
CI
CI_IN_TS_DATA[6]
55
21
CI_IN_TS_DATA[7]
56
22
57
23
58
24
59
25
60
26
61
27
62
28
63
29
64
30
CI_DATA[0]
65
31
CI_DATA[1]
66
32
67
33
68
34
CI_TS_SYNC
CI_TS_DATA[1]
CI_TS_DATA[2]
/CI_CD2
R717 CI 100
/PCM_CE2
R713
0
G2
69
C707
0.1uF
16V
CI
AR712
CI_DATA[1]
EB_DATA[0]
EB_DATA[1]
CI_DATA[2]
EB_DATA[2]
33
EB_DATA[3]
CI_DATA[3]
CI_ADDR[8]
R723
10K
CI
CI_ADDR[13]
CI_ADDR[14]
R725
10K
OPT
CI_DATA[4]
/PCM_WE
33
OPT
/PCM_IRQA
33
CI
AR713
EB_DATA[4]
CI_DATA[5]
EB_DATA[5]
CI_DATA[6]
EB_DATA[6]
CI_DATA[7]
EB_DATA[7]
EB_DATA[0-7]
OPT
20
CI_TS_VAL
CI
+5V_CI_ON
CI_DATA[0]
CI_ADDR[9]
CI_ADDR[13]
19
CI_TS_DATA[0]
CI_ADDR[11]
CI_ADDR[14]
54
0 CI
CI_ADDR[10]
CI_ADDR[8]
53
R714
R724
10K
OPT
/PCM_OE
CI_IN_TS_DATA[5]
/PCM_REG
PCM_INPACK
7
+5V_CI_ON
33
42
R710
R715
R709
10K
CI
CI_VS1
CI_DATA[5]
4
CI_TS_CLK
PCM_INPACK
CI_DATA[4]
40
CI_IN_TS_DATA[4]
33 CI
33 CI
CI_DATA[3]
3
39
+5V_CI_ON
R702
2
37
38
/PCM_CE2
CI_VS1
R701
1
36
CI_TS_DATA[4]
CI_IN_TS_DATA[0-7]
PCM_RESET
/PCM_CE1
35
CI_TS_DATA[5]
/PCM_IORD
/PCM_IOWR
R704
10K
OPT
R720
10K
OPT
EB_DATA[0-7]
+5V_CI_ON
C703
4.7uF
10V
CI
CI_DATA[0-7]
C702
0.1uF
CI
CI_DATA[0-7]
CI_ADDR[12]
CI_ADDR[7]
CI_ADDR[6]
CI_ADDR[5]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[0]
CI_ADDR[7]
CI_ADDR[5]
CI_ADDR[4]
CI_ADDR[1]
CI_ADDR[12]
CI_ADDR[6]
CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]
+5V_CI_ON
CI_DATA[2]
R719
10K
OPT
G1
OPT
CI_IN_TS_VAL
CI_IN_TS_CLK
CI_IN_TS_SYNC
C705
12pF
50V
OPT
TPO_DATA[0-7]
CI
AR701
TPO_DATA[0]
33
CI_IN_TS_DATA[0]
TPO_DATA[1]
CI_IN_TS_DATA[1]
TPO_DATA[2]
CI_IN_TS_DATA[2]
TPO_DATA[3]
CI_IN_TS_DATA[3]
TPO_DATA[4]
CI_IN_TS_DATA[4]
TPO_DATA[5]
CI_IN_TS_DATA[5]
TPO_DATA[6]
CI_IN_TS_DATA[6]
TPO_DATA[7]
CI_IN_TS_DATA[7]
AR706 CI
33
33
TPO_CLK
CI
AR705
CI_IN_TS_CLK
TPO_SOP
CI_IN_TS_SYNC
CI_IN_TS_VAL
TPO_VAL
33
CI
AR707
33
CI
AR711
EB_ADDR[12]
EB_ADDR[0]
CI_ADDR[12]
CI_ADDR[1]
EB_ADDR[1]
CI_ADDR[13]
EB_ADDR[13]
CI_ADDR[2]
EB_ADDR[2]
EB_ADDR[14]
CI_ADDR[3]
EB_ADDR[3]
CI_ADDR[14]
/PCM_REG
CI_ADDR[0]
CI_ADDR[4]
33
CAM_REG_N
CI
AR708
EB_ADDR[4]
CI_ADDR[5]
EB_ADDR[5]
/PCM_OE
CI_ADDR[6]
EB_ADDR[6]
/PCM_WE
CI_ADDR[7]
EB_ADDR[7]
/PCM_IORD
/PCM_IOWR
33
CI
AR710
EB_OE_N
EB_WE_N
EB_BE_N1
EB_BE_N0
+5V_NORMAL
CI_ADDR[8]
AR702
10K
10K
R705
R703
CI_ADDR[9]
/PCM_WAIT
EB_ADDR[8]
EB_ADDR[9]
CI_ADDR[10]
EB_ADDR[10]
CI_ADDR[11]
EB_ADDR[11]
CAM_WAIT_N
CAM_IREQ_N
/PCM_IRQA
/CI_CD2
/CI_CD1
33
CI
AR709
100
CAM_CD2_N
CAM_CD1_N
CI
C700
0.1uF
16V
CI
C701
0.1uF
16V
AR703 CI
PCM_INPACK
CAM_INPACK_N
TPI_CLK
CI_TS_CLK
CI_TS_VAL
100
TPI_VAL
TPI_SOP
CI_TS_SYNC
C704
12pF
50V
OPT
AR704 CI
CI_TS_DATA[7]
CI_TS_DATA[6]
TPI_DATA[7]
TPI_DATA[6]
CI_TS_DATA[5]
TPI_DATA[5]
CI_TS_DATA[4]
100
TPI_DATA[4]
AR700 CI
CI_TS_DATA[3]
TPI_DATA[3]
TPI_DATA[2]
CI_TS_DATA[2]
CI_TS_DATA[1]
CI_TS_DATA[0]
100
TPI_DATA[1]
TPI_DATA[0]
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-NC4_H007-HD
2012-10-20
PCMCIA
LGE Internal Use Only
+12V
UBW2012-121F
L2303
C2306
0.1uF
50V
4
PDIM#1
6
PDIM#2
8
GND
GND
7
24V
9
10
24V
GND
11
12
GND
12V
13
14
12V
12V
15
16
24V
GND
17
18
GND
19
20
21
19
23
L/DIM0_MOSI
S
R2309
100
INV_CTL
C2333
10uF
16V
PWM_DIM
PWM_DIM2
L2306
UBW2012-121F
+24V
C2316
0.1uF
50V
R2346
5.6K
5
INV ON
G
C
R2314
10K
22
L/DIM0_VS
24
L/DIM0_SCLK
2
POWER_DET
RESET
1
DIODES
IC2307-*1
GND
APX803D29
VCC
3
RESET
2
C2365
0.1uF
16V
1
GND
C2347
0.1uF
50V
PD_20_24V
R2336
100K
+24V
not to RESET at 8kV ESD
Q2301
MMBT3904(NXP)
B
PANEL_CTL
3
C2355
0.1uF
16V
PD_+12V
R2326
1.2K
1%
LVDS_DISCHARGE
3.5V
C2307
0.1uF
16V
2
R2338
10K
OPT
IC2307
VCC
LVDS_DISCHARGE
R2347
5.6K
PWR ON 1
3.5V
3
+3.5V_ST
NCP803SN293
Q2302
AO3407A
R2310
1K
R2317
33K
L2304
UBW2012-121F
R2337
100K
PD_+3.5V
R2330
0
5%
ONSEMI
D
P2300
SMAW200-H18S1
POWER_WAFER_18PIN
+3.5V_ST
PD_+12V
R2325
2.7K
1%
PANEL_VCC
C2331
0.1uF
50V
+3.3V_NORMAL
R2318
5.6K
1
MMBT3906(NXP)
+12V
L2313
UBW2012-121F
3
+3.5V_ST
Power_DET
PANEL_POWER
+12V
Q2300
R2300
10K
2
RL_ON
10K
R2301
+3.5V_ST
E
25
P2301
SMAW200-H24S2
POWER_WAFER_24PIN
PD_UHD_24V
R2327-*2
9.1K
1%
PD_20V
R2327-*1
5.6K
1%
PD_24V
R2327
8.2K
1%
PD_UHD_24V
R2328-*2
1.6K
1%
PD_20V
R2328-*1
1.3K
1%
PD_24V
R2328
1.5K
1%
PD_20_24V_ONSEMI
IC2308
NCP803SN293
VCC
3
2
C2356
GND
0.1uF
16V
PD_20_24V
RESET
PD_20_24V_DIODES
IC2308-*1
1
APX803D29
VCC
3
2
24V-->3.48V
20V-->3.51V
12V-->3.58V
ST_3.5V-->3.5V
RESET
1
GND
+2.5V
+2.5V_Normal
IC2302
AP7173-SPG-13 HF(DIODES)
DDR MAIN 1.5V
[EP]
LG1154D
0.1uF
16V
BOOT
PWRGD
IC2303
TPS54821RHL
VSENSE
8A
R2316
8
COMP
C2313
4.7uF
16V
+3.3V_NORMAL
C2315
4700pF
+3.3V_NORMAL
1K
NC_2
+24V
POWER_ON/OFF2_2
FB
L2311
BLM18PG121SN1D
C2309
10uF
35V
BOOT
10
DCDC_RT
4
9
6
7
SW_2
SW_1
SS/TR
8
RT/SYNC
AGND
5
6
5A
4
5
VIN
C2330
22uF
10V
C2334
22uF
10V
C2336
10uF
10V
C2338
0.1uF
50V
GND
EN
POWER_ON/OFF1
R2345
10K
1%
BLM18PG121SN1D
Vout=0.6*(1+R1/R2)
3
7
C2311
0.1uF
50V
Vout(1.24V)=0.6*(1+16k/15k)
L2305
2
SS/TR
50V
1/16W
1%
R2305
15K
R2
7
3
SW_3
L2310
4.7uH
40V
9
L2312
4.7uH
SW
D2300
B540C
10
6
NC_1
VIN
11
[EP]GND
8
1
9
15
5
EN
IC2304
RT8289GSP
THERMAL
R1
12
R2
51K
R2344
C2335
0.1uF
16V
R1
1%
C2302
180pF
50V
PVIN_2
R2343
16K
GND
Vout=0.765*(1+R1/R2)
+12V
C2324
0.01uF
50V
BOOT
ZD2302
5V
C2303
10uF
16V
C2323
22uF
22uF 22uF 10V
10V 10V
OPT
5
C2322
22uF
10V
PH_1
50V
6
4
11
C2321
3
4
C2366 C2341
BOOT
SW
13
14
IC2305-*1
RT8079AGQW
+5V_NORMAL
L2308
2.2uH
0.1uF
16V
PH_2
22000pF
7
12
1/16W
5%
SS
2
PVIN_1
GND_2
15
THERMAL
17
2
C2318
BOOT
[EP]GND
VIN
GND_1
1
+5.0V normal & USB
+1.1V_VDD
13
3
R2
Switching freq: 700K
16
VIN_1
3A $ 0.145
Vout=0.827*(1+R1/R2)=1.521V
PWRGD
R2315 0
FB
PVCC
C2312
3300pF
50V
C2310
1uF
10V
1%
C2319
22uF
10V
8
1
2
14
50V
33K
C2317
22uF
10V
GND_1
1
C2320
R2306
GND
5
1/16W
1%
47pF
3A
4
R2
[EP]GND
1.3K
EN
SS
RT/CLK
R2313
IC2300-*1
RT7266ZSP
R2307
120K
GND_2
+1.1V_VDD
DCDC_RT
1/16W
1%
6
NR5040T2R2N
L2307
2.2uH
R2303
16K
3
SW
L2301
9
C2308
100pF
50V
VBST
7
16V
0.1uF
C2314
THERMAL
VREG5
9
2
R2302
11K
DCDC_TI
THERMAL
R1
VFB
VIN
8
1
+12V
ZD2300
2.5V
TPS54327DDAR [EP]GND
THERMAL
DCDC_TI IC2300
1%
50V
R2340
56K
1/16W
1%
+1.23V_CORE
+1.0V_VDD
BLM18PG121SN1D
EN
DCDC_TI
C2364
100pF
50V
VIN_2
L2300
POWER_ON/OFF2_3
5%
LG1154A
+1.0V_VDD
R2304
10K
R1
C2360
4700pF
R2334
15K
1/16W
ESD
ZD2303
5V
0.01uF
50V
R2335
1/16W 330K 5%
+12V
C2301
10uF
16V
C2362
22uF
10V
PGOOD
SS/TR
C2361
22uF
10V
[EP]GND
AGND
5
3A
C2359
EN
PH_1
VIN_3
3 IC2305 DCDC_TI10
TPS54319TRE
4
9
2
L2320
3.3uH
NR5040T3R3N
COMP
11
PH_2
GND_1
GND_2
Vout=0.8*(1+R1/R2)
PH_3
THERMAL
17
FB
C2350
10uF
10V
12
1
VIN_2
R2339
C2300
22uF
10V
16V
47K 1%
VIN_1
C2305
0.1uF
16V
+1.5V_DDR
C2358
0.1uF
13
L2318
14
R2321
2K
1% R2
7
C2337
2200pF
50V
GND
ZD2304
5V
OPT
8
5
C2348
0.1uF
16V
COMP
4
C2346
10uF
10V
RT/CLK
1.5A
OPT
C2343
22uF
10V
EN
R2322
R1
4.3K
1%
SS
VIN_3
EN
6
15
R2312
10K
POWER_ON/OFF2_1
L2302
BLM18PG121SN1D
C2327
10uF
10V
3
C2354
+3.5V_ST
6
VCC
POWER_ON/OFF2_2
FB
VSENSE
+5V_NORMAL
3.3V_EMMC
7
EP[GND]
2
OUT
16
+3.3V_NORMAL
PG
8
9
eMMC POWER
1
THERMAL
IN
10K
R2331
+3.3V_NORMAL
C2329
150pF
50V
C2304
10uF
16V
IC2301
TPS54327DDAR [EP]GND
POWER_ON/OFF1
1%
R1
VFB
VREG5
C2325
100pF
50V
3
7
6
ZD2301
5V
ESD
VIN
VBST
SW
16V
0.1uF
C2332
L2309
3.6uH
SM-8040
SS
R2319
15K
1%
Switching freq: 700K
2
R2308
51K
OPT
8
1
9
EN
THERMAL
R2311
10K
C2326
1uF
10V
4
3A
5
GND
C2339
22uF
10V
C2340
22uF
10V
Vout=1.222*(1+R1/R2)
POWER UP SEQUENCE
5V/3.3V->2.5V->1.5V/1.1V->1.0V
LG1154D
: 3.3V->2.5V->1.5V->1.1V
LG1154AN : 3.3V->2.5V->1.0V
C2328
3300pF
50V
R2
Vout=0.765*(1+R1/R2)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-NC4_H023-HD
LG1154
2012-12-07
POWER
LGE Internal Use Only
Renesas MICOM
For Debug
HDMI_WAUP:HDMI_INIT
MICOM_DEBUG
LOGO_LIGHT
8pF
C3003
MICOM_RESET
DOOR_CLOSE_DET
+3.5V_ST
10K
R3030
P120/ANI19
37
270K
OPT
2
1
4
3
ST_BY_DET_CAM
ST_BY_DET_CAM
MICOM_RESET_33OHM
R3029-*1 33
R3021
P60/SCLA0
1
36
P140/PCLBUZ0/INTP6
P61/SDAA0
2
35
P00/TI00/TXD1
P62
3
34
P01/TO00/RXD1
4
P130
IC3000
33
32
P20/ANI0/AVREFP
R5F100GEAFB
31
P21/ANI1/AVREFM
30
I2C_SCL_MICOM
GP4 High/MID Power SEQUENCE
I2C_SDA_MICOM
MODEL1_OPT_1
P63
PANEL_CTL
P31/TI03/TO03/INTP4
5
P75/KR5/INTP9/SCK01/SCL01
6
WOL/WIFI_POWER_ON
IR
P74/KR4/INTP8/SI01/SDA01
HDMI_CEC
55/65_Motor
R3017
22
MOTOR_CTRL_A
P70/KR0/SCK21/SCL21
11
26
P30/INTP3/RTC1HZ/SCK11/SCL11
12
25
13
CAM_PWR_ON_CMD
CAM_PWR_ON_CMD
MOTOR_CTRL_B
MODEL1_OPT_0
SIDE_HP_MUTE
P26/ANI6
55/65_Motor
R3018
22
55/65_Motor
MOTOR_CTRL_C
P27/ANI7
R3019
22
MOTOR_CTRL_D
24
EYE_SCL
23
P25/ANI5
22
27
21
10
20
P24/ANI4
19
P23/ANI3
28
18
29
EYE_SDA
POWER_ON/OFF2_4
KEY1
P22/ANI2
9
P71/KR1/SI21/SDA21
POWER_ON/OFF2_3
LED_R
KEY2
8
POWER_ON/OFF2_3
SCART_MUTE
LED_R
55/65_Motor
R3015
22
P72/KR2/SO21
POWER_ON/OFF2_2
R3022
3.3K
17
EYE_Q
R3020
3.3K
MICOM_LEAD_Au
SCART_MUTE
POWER_ON/OFF2_1
P73/KR3/SO01
EYE_Q
POWER_ON/OFF2_2
7
16
+3.5V_ST
15
POWER_ON/OFF2_1
14
POWER_ON/OFF!
44
10K
+3.5V_ST
55/65_Motor
R3006 4.7K
55/65_Motor
R3007 4.7K
P41/TI07/TO07
38
MICOM_RESET_SW
SW3000
JTP-1127WEM
55/65_Motor
R3004 4.7K
55/65_Motor
R3005 4.7K
P40/TOOL0
39
R3031
MICOM_RESET_22OHM
R3029
22
RESET
P124/XT2/EXCLKS
C3004
0.1uF
16V
40
41
45
P123/XT1
P121/X1 0.47uF
46
+3.5V_ST
42
REGC
47
C3000
0.1uF
P137/INTP0
VSS
48
C3001
VDD
+3.5V_ST
43
55/65_Motor
R3009 22
5
R3028
GND
55/65_Motor
P122/X2/EXCLK
R3010 22
MICOM_RESET
X3000
32.768KHz
LOGO_LIGHT
4.7M
OPT
55/65_Motor
55/65_Motor
R3001 4.7K
MICOM_DEBUG
3
4
DOOR_OPEN_DET
+3.5V_ST
1
2
10K
R3032
Don’t remove R3014,
not making float P40
R3002 4.7K
12507WS-04L
R3016 1K
P3000
R3014 10K
MICOM_DEBUG
MICOM_DEBUG
8pF
MHL_DET
MHL_DET
C3002
+3.5V_ST
10
27
P25/ANI5
MODEL1_OPT_0
P70/KR0/SCK21/SCL21
11
26
P26/ANI6
MODEL1_OPT_1
P30/INTP3/RTC1HZ/SCK11/SCL11
12
25
P27/ANI7
23
24
P147/ANI18
P146
22
P10/SCK00/SCL00
21
P11/SI00/RXD0/TOOLRXD/SDA00
20
P12/SO00/TXD0/TOOLTXD
19
P13/TXD2/SO20
18
P14/RXD2/SI20/SDA20
17
P15/PCLBUZ1/SCK20/SCL20
15
14
13
16
P16/TI01/TO01/INTP5
P17/TI02/TO02
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
MICOM_NON_LOGO_LIGHT
R3012
10K
NONE_EYE_Q
R3003
10K
P146
P10/SCK00/SCL00
P12/SO00/TXD0/TOOLTXD
P147/ANI18
For CEC
+3.5V_ST
D3000
BAT54_SUZHO
S
D
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
HDMI_CEC
Q3001
RUE003N02
HDMI_CEC_FET_ROHM
G
CEC_REMOTE
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
R3034
120K
R3033
27K
G
P24/ANI4
P71/KR1/SI21/SDA21
S
28
D
9
CAM_CTL
P72/KR2/SO21
MICOM_LEAD_Cu
CAM_CTL
8
RL_ON
P73/KR3/SO01
AMP_MUTE
P23/ANI3
7
P11/SI00/RXD0/TOOLRXD/SDA00
P22/ANI2
29
P74/KR4/INTP8/SI01/SDA01
SOC_RX
P21/ANI1/AVREFM
30
6
SOC_TX
P120/ANI19
37
31
P75/KR5/INTP9/SCK01/SCL01
INV_CTL
P41/TI07/TO07
38
P20/ANI0/AVREFP
R5F100GEAFB#30
5
P13/TXD2/SO20
P40/TOOL0
39
32
P31/TI03/TO03/INTP4
P14/RXD2/SI20/SDA20
RESET
40
33
P130
IC3000-*1
SOC_RESET
P124/XT2/EXCLKS
41
4
WOL_CTL
P123/XT1
42
P01/TO00/RXD1
P63
P15/PCLBUZ1/SCK20/SCL20
P137/INTP0
43
P00/TI00/TXD1
34
P16/TI01/TO01/INTP5
P122/X2/EXCLK
44
P140/PCLBUZ0/INTP6
35
3
POWER_ON/OFF1
P121/X1
45
36
2
P62
P17/TI02/TO02
REGC
46
1
P61/SDAA0
POWER_DET
VSS
47
MICOM_LOGO_LIGHT
R3013
10K
EYE_Q
R3000
10K
P60/SCLA0
WOL/ETH_POWER_ON
P50/INTP1/SI11/SDA11
VDD
48
MICOM MODEL OPTION
+3.5V_ST
P51/INTP2/SO11
SOC_RESET
Q3001-*1
SI1012CR-T1-GE3
HDMI_CEC_FET_VISHAY
2012.02.22
MICOM
30
LGE Internal Use Only
DOOR MOTOR Sheet option : 55/65_Motor
55/65_Motor
P3100
SMAW200-H16S2
55/65_Motor
CLOSE_DET
1
2
12V
OPEN_DET
3
4
12V
CTRL_C
5
6
CTRL_D
CTRL_A
7
8
CTRL_B
GND
9
10
GND
SPK_R-
11
12
GND
SPK_R+
13
14
GND
SPK_L-
15
16
SPK_L+
DOOR_CLOSE_DET
IC3101
KID65003AF
DOOR_OPEN_DET
MOTOR_CTRL_C
I1
I2
I3
MOTOR_CTRL_D
I4
I5
I6
I7
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
L3100
CIS21J121
C3102
0.1uF
O1
O2
O3
C3103 C3104
0.1uF 0.1uF
O4
O5
H_SPK_RO6
+12V
H_SPK_R+
C3105 C3106
0.1uF 0.1uF
O7
H_SPK_L-
GND
+12V
H_SPK_L+
COMMON
17
GND
C3101
0.1uF
55/65_Motor
IC3100
KID65003AF
MOTOR_CTRL_A
I1
I2
I3
MOTOR_CTRL_B
I4
I5
I6
I7
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
O1
O2
O3
O4
O5
O6
+12V
O7
COMMON
C3100
0.1uF
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
GP4
Motor
31
LGE Internal Use Only
NC_2
7
+5V_NORMAL
5V_HDMI_1
NC_3
9
TMDS_CH1-
D1+_HDMI2
8
GND_1
7
TMDS_CH2-
D2-_HDMI2
TMDS_CH2+
1
10
2
9
3
8
4
7
5
6
DDC_SCL_3
HDMI3
NC_3
GND_2
CK-_HDMI3
NC_2
NC_1
CK+_HDMI3
D0-_HDMI3
D0+_HDMI3
+5V_NORMAL
D1-_HDMI3
D1+_HDMI3
R3204
10K
+3.3V_NORMAL
D2-_HDMI3
RESERVED
SCL
SDA
DDC/CEC_GND
VDD[+5V]
HOT_PLUG_DETECT
TMDS_CLK+
10
TMDS_CLK_SHIELD
11
TMDS_CLK-
12
CEC
13
RESERVED
14
SCL
15
SDA
16
DDC/CEC_GND
17
VDD[+5V]
18
HOT_PLUG_DETECT
19
TMDS_DATA0-
9
TMDS_CLK+
10
TMDS_CLK_SHIELD
11
TMDS_CLK-
12
CEC
13
RESERVED
14
SCL
15
SDA
16
DDC/CEC_GND
17
VDD[+5V]
18
HOT_PLUG_DETECT
19
BODY_SHIELD
BODY_SHIELD
VDD12_3
8
59
GPIO1
9
58
GPIO0
57
CD-SENSE4
56
CD_SENSE3
55
GPIO2
54
CD_SENSE1
53
CD_SENSE0
VDD12_1
10
R3XCN
11
R3XCP
12
R3X0N
13
R3X0P
14
IC3201
SII9587CNUC
FHD
Device Address : 0XB0
15
52
R3X1P
16
51
LPSBV
R3X2N
17
50
PWRMUX_OUT
R3X2P
18
49
SBVCC5
48
VDD33_1
20
47
DSCL5[VGA]
R4XCN
21
46
DSDA5[VGA]
R4XCP
22
45
R4PWR5V
23
19
R5PWR5V[VGA]
9
10
11
IN
14
ARC
TX2P
TX2N
TX1P
TX1N
TX0P
TX0N
TXCP
TXCN
TCVDD12
TPVDD12
R0XCN
R0XCP
R0X0N
R0X0P
R0X1N
R0X1P
R0X2N
R0X2P
AVDD12_3
VDD33_2
VDD12_3
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
44
CBUS_HPD4
42
41
43
DSCL4
DSDA4
R3PWR5V
40
CBUS_HPD3
39
38
DSDA3
DSCL3
37
R1PWR5V
36
35
DSCL1
CBUS_HPD1
34
DSDA1
32
33
R0PWR5V
31
DSCL0
CBUS_HPD0
29
30
DSDA0
28
R4X2P
R3216
10
AVDD12_2
8
13
85
1/16W
R3213
5.1K
5%
WKUP
IC3200
AZ1117BH-1.2TRE1
12
86
MHL_DET
+3.5V_ST
+5V_NORMAL
R3X1N
4
5
26
HDMI_S/W_RESET
C3209
0.1uF
16V
3
7
27
10K
R3202
67
ARC
68
TX2P
69
70
TX2N
71
TX1P
72
TX1N
TX0P
73
74
TX0N
TXCN
TXCP
75
76
77
R1X2P
AVDD12_1
2
6
25
HDMI_RX2+
HDMI_RX1+
HDMI_RX2-
HDMI_RX1-
HDMI_RX0+
HDMI_RX0-
HDMI_CLK-
HDMI_CLK+
D0-_HDMI1
CK-_HDMI1
L3203
TCVDD12
TPVDD12
78
R0XCN
79
TPWR
1
3
2
C3215
0.1uF
16V
C3212
1uF
10V
C3222
10uF
10V
C3218
10uF
10V
+5V_NORMAL
OUT
R3201
10
1
15
GND/ADJ
16
17
18
19
20
20
20
60
DSCL4
8
7
DSDA4
TMDS_DATA0+
TMDS_DATA0_SHIELD
R1X2N
CBUS_HPD4
TMDS_DATA0-
9
TMDS_DATA1-
7
RESET_N
BODY_SHIELD
C3219
0.33uF
C3204
0.1uF
16V
C3206
0.1uF
16V
16V
R3200
5.1K
C3207
0.1uF
16V
C3201
10uF
10V
Vout=0.8*(1+R1/R2)
C3203
10uF
10V
C3217
0.1uF
16V
D13_HDMI_HPD
CEC
8
TMDS_DATA1_SHIELD
5
6
I2C_SDA5
61
D13_HDMI_DDC_CK
TMDS_CLK-
TMDS_DATA0+
TMDS_DATA0_SHIELD
I2C_SCL5
6
D13_HDMI_DDC_DA
TMDS_CLK+
TMDS_DATA1-
7
C3211
0.1uF
16V
HDMI_INT
R1X1P
R3PWR5V
TMDS_DATA0-
TMDS_CLK_SHIELD
TMDS_DATA1_SHIELD
5
6
33
HDMI_HPD_3
TMDS_DATA0+
TMDS_DATA1+
4
R3214
5
CBUS_HPD3
TMDS_DATA1-
TMDS_DATA2-
3
CSDA
33
DDC_SCL_3
TMDS_DATA1_SHIELD
TMDS_DATA0_SHIELD
TMDS_DATA1+
4
TMDS_DATA2_SHIELD
2
62
R3237
R4X0N
TMDS_DATA1+
TMDS_DATA2-
3
TMDS_DATA2+
1
C3210
0.1uF
16V
1/16W
5%
TMDS_DATA2-
TMDS_DATA2_SHIELD
2
C3200
10uF
10V
DAADR019A
DAADR019A
TMDS_DATA2+
1
AO3438
Q3202
R3212
1
TMDS_DATA2+
TMDS_DATA2_SHIELD
HDMI_FOOSUNG
JK3202-*1
HDMI_FOOSUNG
JK3201-*1
DAADR019A
D
S
G
D2+_HDMI3
HDMI_FOOSUNG
JK3200-*1
33
NC_4
HDMI_ESD_SEMTEK
HDMI2
88
[EP]GND
D2+_HDMI2
6
JK3200
24
23
D2-_HDMI2
D2+_HDMI2
51U019S-312HFN-E-R-B-LG
33
R3236
DSCL3
5
R3211
CSCL
DSDA3
D2+
47K
INT
DDC_SDA_3
4
TMDS_CH1+
R4PWR5V
63
R1PWR5V
3
D2_GND
D1+_HDMI2
R3220
DDC_SDA_3
D3213-*1
IP4283CZ10-TBA
D1-_HDMI2
2
45
4
HDMI_ESD_NXP
D2-
22
R1X0P
R1X1N
D1-_HDMI2
NC_1
R3218
47K
D3213
RCLAMP0524PA
1
10
D1+
D0+_HDMI2
NC_2
D1D1_GND
D3205
D3201
GND_2
HDMI_ESD_SEMTEK
D0+
DSDA5[VGA]
R4XCP
10K
R3244
6
DSCL5[VGA]
46
+3.3V_NORMAL
44
7
5
D0-_HDMI2
NC_4
43
4
47
21
SPDIF_IN
42
8
20
R4XCN
64
41
TMDS_CH2+
3
R5PWR5V[VGA]
VDD33_1
16V
0.1uF
C3225
C3224
0.1uF
16V
THERMAL
89
40
TMDS_CH2-
D0+_HDMI2
D0_GND
9
48
3
39
6
GND_1
10
2
19
R1X0N
38
D0-_HDMI2
1
SBVCC5
AVDD12_2
RSVDL
37
TMDS_CH1+
D0-
5
D3212-*1
IP4283CZ10-TBA
TMDS_CH1-
PWRMUX_OUT
49
65
36
7
50
66
DSCL1
4
CK+_HDMI2
HDMI_ESD_NXP
CK+_HDMI2
17
18
2
CBUS_HPD1
CK+
8
LPSBV
R3X2N
R3X2P
1
DDC_SCL_2
9
3
51
R1XCP
HDMI_HPD_2
2
16
R1XCN
35
CK-_HDMI2
34
HDMI2
+3.5V_ST
33
+5V_NORMAL
5V_HDMI_3
CK-_HDMI2
CK_GND
CK+_HDMI1
L3202
A1
C
C
D3212
RCLAMP0524PA
1
10
DSDA1
1
DDC_SDA_2
R0PWR5V
2
47K
DDC_SDA_2
3
R3228
47K
32
4
R3225
DDC_SCL_1
CBUS_HPD0
6
5
DDC_SDA_1
VA3204
ESD_HDMI
HDMI_HPD_1
7
47K
DSCL0
8
22
DSDA0
9
MHL_DET
DDC_SCL_2
CEC_REMOTE
WKUP
R3X1P
D3202
NC
CE_REMOTE
CD_SENSE0
52
MMBT3904(NXP) E
R3219
R3217
47K
DDC_SCL_2
CK-
53
15
HDMI S/W OUTPUT
DDC_SCL_1
11
10
C
B
A2
EAG62611204
12
R3210
VA3203
ESD_HDMI
CD_SENSE1
14
R3X1N
Q3200
DDC_SDA_2
A1
13
C
C3223
0.047uF
25V
C
14
22
A2
15
VA3209
ESD_HDMI
DDC_DATA
DDC_CLK
1/16W
5%
A2
A1
D3200
R3209
54
+5V_NORMAL
5V_HDMI_2
HDMI_HPD_2
5V_HDMI_2
HDMI1
E MMBT3906(NXP)
Q3201
R3247
10K
B
HDMI3 With MHL
A1
16
NC_1
JK3201
C
17
6
51U019S-312HFN-E-R-B-LG
VA3205
ESD_HDMI
GND
7
5
R3243
1K
D2+_HDMI3
6
HDMI_FREEPORT HP_DET
19
5V
4
NC_2
R0XCP
1
HDMI1 With ARC
18
6
TMDS_CH2+
51U019S-312HFN-E-R-B-LG
20
7
5
HDMI_ESD_SEMTEK
D2+_HDMI1
BODY_SHIELD
13
GND_2
NC_1
HDMI_ESD_SEMTEK
R3251
33
GPIO2
R3X0N
R3X0P
NC_3
A2
5
8
4
NC_2
6
CD_SENSE3
55
NC_4
D2-_HDMI3
D2+
D2-_HDMI1
JK3202
3
8
R0X0N
5
D2_GND
NC_3
GND_2
9
3
80
7
56
12
+3.5V_ST
10
2
81
4
2
NC_4
TMDS_CH2-
1
31
8
D1+_HDMI3
GND_1
30
TMDS_CH2+
9
3
TMDS_CH1+
D0+_HDMI1
D2-
9
R0X0P
7
10
2
CD-SENSE4
11
R3XCP
HDMI_ESD_NXP
D3208-*1
IP4283CZ10-TBA
TMDS_CH1-
D1-_HDMI3
2
D1-_HDMI1
D1+
82
4
D3208
RCLAMP0524PA
1
10
D1_GND
29
TMDS_CH2-
1
GPIO0
57
R3XCN
HDMI_ESD_SEMTEK
VDD12_2
1
GND_1
GPIO1
58
NC_1
DDC_SDA_1
8
TMDS_CH1+
TPWR
59
NC_2
D1+_HDMI1
3
TMDS_CH1-
RESET_N
60
D1-
D3211-*1
IP4283CZ10-TBA
D1+_HDMI1
CSDA
61
GND_2
R0X1N
D2+
3
HDMI_ESD_NXP
D1-_HDMI1
CSCL
62
D0+_HDMI3
83
9
INT
63
NC_3
R4X2P
2
6
D13_HDMI_TX2P
D2D2_GND
5
R4X2N
3
2
SPDIF_IN
64
NC_4
28
5
4
D3211
RCLAMP0524PA
1
10
7
D2-_HDMI1
HDMI_ESD_SEMTEK
4
D0+
6
8
R0X1P
6
D1_GND
D1+
5
D0_GND
TMDS_CH2+
9
4
D13_HDMI_TX2N
6
10
RSVDL
65
NC_1
D0+_HDMI1
D1-
5
D0-_HDMI3
10
3
84
6
GND_1
TMDS_CH2-
2
27
7
5
7
1
D2+_HDMI1
4
GND_2
4
TMDS_CH1+
R0X2N
TMDS_CH2+
8
8
D0-
IC3201-*1
SII9587CNUC-3
66
HDMI_ESD_NXP
TMDS_CH1-
CK+_HDMI3
R0X2P
TMDS_CH2-
D0-_HDMI1
3
NC_3
8
9
THERMAL
89
D3209-*1
IP4283CZ10-TBA
CK-_HDMI3
85
6
9
8
26
5
2
9
3
R4X1P
7
GND_1
D0+
7
4
TMDS_CH1+
2
CK+
D13_HDMI_TX1P
8
8
10
9
CK_GND
R4X1N
D0_GND
3
1
NC_4
CK-
D3209
RCLAMP0524PA
1
10
AVDD12_3
CK+_HDMI1
D0-
9
TMDS_CH1-
7
CE_REMOTE
86
9
R1X2N
ESD_HDMI
ESD_HDMI
R4X0P
2
HDMI_ESD_NXP
D3210-*1
IP4283CZ10-TBA
A2
87
CK-_HDMI1
6
AVDD12_1
MHL_DET
[EP]GND
CK+
11
10
C
88
11
10
EAG62611204
12
D3210
RCLAMP0524PA
1
10
CK_GND
NC
4
5
R1X1P
VDD12_2
13
CEC_REMOTE
VA3201
VA3200
CEC_REMOTE
CK-
12
DDC_CLK
10K
R3245
3
R1X0P
R1X1N
R4X0N
14
DDC_DATA
1
2
R1X0N
R1X2P
A1
25
CE_REMOTE
13
EAG62611204
15
OPT
C3226
0.1uF
16V
4
3
EN
D13_HDMI_TX1N
VA3213
ESD_HDMI
ARC
14
OPT
R3249
3.9K
15
10V
OC
D13_HDMI_TX0P
DDC_CLK
DDC_SCL_3
5%
1/16W
UD
R1XCN
R1XCP
VDD12_1
D13_HDMI_TXCP
16
16
SPDIF_OUT_ARC
VA3214
ESD_HDMI
2
24
C3202
1uF
DDC_DATA
GND
GND
D13_HDMI_TXCN
17
17
R3205 22
C3205
10uF
10V
C3208
0.1uF
VDD33_2
GND
18
DDC_SDA_3
MHL_ON_OFF
1/16W
5%
D13_HDMI_TX0N
VA3206
ESD_HDMI
ARC
IN
5%
1/16W
18
VA3207
ESD_HDMI
5
R3246
10K
5V
OPT
R3248
1K
19
R3203 22
R3215
100K
DDC_SCL_1
HDMI_FREEPORT HP_DET
1
30V
HDMI_FREEPORT HP_DET
19
5V
5.6V
20
20
22
R3208
OUT
220K
R3206
DDC_SDA_1
R4X2N
22
D3207
R3207
OPT
R3254
100
D3206
MBR230LSFT1G
BODY_SHIELD
BODY_SHIELD
IC3202
TPS2051BDBVR
87
+5V_NORMAL
5V_HDMI_3
5V_HDMI_3
R4X1N
HDMI_HPD_3
VA3202
ESD_HDMI
R4X1P
VA3215
ESD_HDMI
VA3208
ESD_HDMI
R4X0P
R3252
33
HDMI_HPD_1
D3204
5V_HDMI_1
33
R3250
From D13
5V_HDMI_1
5V_HDMI_2
R3231
10
C3213
1uF
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
1/16W
R3233
5.1K
5%
5V_HDMI_3
R3240
10
R3232
10
C3214
1uF
1/16W
R3234
5.1K
5%
C3220
1uF
1/16W
R3241
5.1K
5%
GP4
HDMI
32
LGE Internal Use Only
JK3401
JSTIB15
R3400
33
VIN
A
VCC
B
GND
C
SPDIF_OUT
VA3400
5.5V
C3400
0.1uF
16V
1/10W
5%
OPT
JACK_PARK
JK3403
PEJ038-3B6
+3.3V_NORMAL
GND
5
JACK_KSD
JK3403-*1
KJA-PH-0-0177
GND
5
R3406
HP_OUT
R3409
100
4
10K
HP_OUT
HP_DET
1/16W
5%
SHIELD
C3402
47pF
50V
R3404
150
HP_LOUT
Fiber Optic
+3.3V_NORMAL
SPDIF OUT
L
4
L
4
DETECT
3
DETECT
3
R
1
R
1
R3405
150
HP_ROUT
ADUC 5S 02 0R5L
EAG61030009
1/10W
5%
COMPONENT 1 PHONE JACK
EAG61030001
VA3405
5.6V
CVBS 1 PHONE JACK
+3.3V_NORMAL
OPT
+3.3V_NORMAL
C3401
18pF
R3402
10K
R3407
100
R3403
330K
R3408
100
COMP1_DET
AV1_CVBS_DET
1/16W
5%
VA3401
5.6V
VA3402
5.6V
JACK_PARK
JK3400
PEJ038-4G6
JACK_PARK
JK3402
PEJ038-4Y6
for audio Hum noise (L)
5
M5_GND
4
M4
3
M3_DETECT
1
M1
1
M1
6
M6
6
M6
COMP1_Y
5
M5_GND
4
M4
3
M3_DETECT
COMP1/AV1/DVI_L_IN
VA3403
5.6V
EAG61030012
1/16W
5%
C3403
0.1uF
16V
OPT
C3405
0.01uF
25V
EAG61030011
COMP1_Pb
COMP1/AV1/DVI_R_IN
JACK_KSD
JACK_KSD
JK3400-*1
KJA-PH-1-0177-2
JK3402-*1
KJA-PH-1-0177-1
5
M5_GND
4
M4
3
M3_DETECT
VA3404
5.6V
5
M5_GND
4
M4
3
M3_DETECT
1
M1
6
M6
OPT
C3404
0.01uF
25V
COMP1_Pr
1
M1
6
M6
AV1_CVBS_IN
EAG61030007
EAG61030006
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-NC4_H034-HD
JACK HIGH/MID
2012.10.09
LGE Internal Use Only
Place Near Micom
+3.5V_ST
LOGO_LIGHT
R4003
33
10K
R4000
OPT
LOGO_LIGHT
R4004
33
LOGO_LIGHT
B
LOGO_LIGHT_WAFER
C
LOGO_LIGHT
LOGO_LIGHT
R4001
10K
LOGO_LIGHT
C4000
0.1uF
16V
1K Q4000
R4002
MMBT3904(NXP) E
LOGO_LIGHT
+3.5V_ST
84_EYE_Q_10P
P4001
R4008
10K
5%
R4009
10K
5%
12507WR-10L
55/65_NON_EYE_Q_8P
R4006
100
1
For 84" UD only
P4002
12507WR-08L
KEY1
R4007
100
2
VA4001
5.6V
AMOTECH CO., LTD.
KEY2
C4001
0.1uF
LOGO_LIGHT
C4002
0.1uF
1
VA4000
5.6V
AMOTECH CO., LTD.
+3.5V_ST
3
P4005
LOGO_LIGHT
2
4
3
5
4
6
12507WR-03L
L4004
BLM18PG121SN1D
1
+3.5V_ST
L4001
BLM18PG121SN1D
+3.5V_ST
C4005
1000pF
50V
R4005
10K
5%
LOGO_LIGHT
R4017
0
R4015
11K
LED_R
5
7
6
8
7
9
LOGO_LIGHT_WAFER
2
3
4
R4016
0
LOGO_LIGHT_WAFER
OPT
NON_OLED
NON_OLED
IR
C4006
100pF
50V
EYE_SCL
VA4002
5.6V
AMOTECH CO., LTD.
R4011
100
8
9
EYE_Q
VA4004
ADMC 5M 02 200L
10
9
11
10
OPT
R4010
100
11
EYE_SDA
EYE_Q
55/65_EYE_Q_10P
P4004
VA4003
ADMC 5M 02 200L
12507WR-10L
OPT
+3.3V_NORMAL
L4002
+3.5V_WOL
120-ohm
MAX 0.4A
120-ohm
BLM18PG121SN1D
P4000
SMAW200-H12S2
C4004
C4007
22uF
10V
0.1uF
+3.5V_WOL
3.3V
R4012
100
M_REMOTE_RTS
C4012
1000pF
50V
AR4000
100
1/16W
USB_DM
RTS
USB_DP
RX
GND
TX
M_REMOTE_RX
WOL
RESET
M_REMOTE_TX
GND
CTS
WIFI_DM
+3.3V_NORMAL
For EMI
R4014
10K
L4000
WIFI_DP
C4016
5pF
50V
C4015
5pF
50V
WOL/WIFI_POWER_ON
M_RFModule_RESET
M_REMOTE_CTS
OPT
C4008 C4009 C4013
47pF 47pF 47pF
50V
50V
50V
OPT
C4014
47pF
50V
.
For EMI
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-NC4_H040-HD
IR / KEY
2012.10.10
LGE Internal Use Only
+3.3V_NORMAL
CAMERA
C4202
4.7uF
17
RESET
6
16
DP4
7
15
DM4
14
13
/RST_HUB
C4209
0.1uF
CAMERA
AVDD_3
AVDD_2
CAMERA
R4214
1% 680
RREF
C4205
0.1uF
1/16W
5%
5
CAMERA
C4208
CAMERA
R4217
10K
TEST/SCL
DM2
DP2
100K CAMERA
R4216
PSELF R4215100K CAMERA
22
OVCUR2
PGANG
23
24
OVCUR1
SDA
25
V5
18
4
AVDD_1
12
USB_CAMERA_DP
IC4200
GL852G-31
0 R4210 CAMERA DP1
DP3
0.1uF
CAMERA
OVCUR4
DM3
USB_CAMERA_DM
19
3
11
C4201
CAMERA
0 R4206 CAMERA DM1
10
C4200
CAMERA
1uF
25V
OVCUR3
8
BLM18PG121SN1D
USB_DP3
20
2
X2
CAMERA
L4200
120-ohm
DVDD
THERMAL
29
9
USB_DM3
+3.3V_NORMAL
21
1
DP0
X1
USB2_HUB_IC_IN_DP
26
DM0
0 R4205 CAMERA
27
CAMERA
USB2_HUB_IC_IN_DM
+3.3V_NORMAL
28
0 R4204
V33
[EP]GND
CAMERA
10K R4218
0.1uF
OPT10K R4219
CAMERA
C4203
From HUB
USB_Camera
C4206
0.1uF
CAMERA
CAMERA
P4200
12507WR-12L
0.1uF
CAMERA
CAM_SLIDE_DET
3
CAMERA
C4204
22pF
X-TAL_2
2
C4213
4.7uF
10V
CAMERA
ZD4200
5V
4
2
R4211
33 CAMERA
OPT
1
GND_1
1
33pF
50V C4215
+3.5V_CAM
GND_2
C4207
22pF
CAMERA
X-TAL_1
CAMERA
OPT
X4200
12MHZ
R4212
33 CAMERA CAMERA
AUD_LRCK
CAMERA POWER ENABLE CONTROL
+3.5V_CAM
CAMERA
AUD_LRCH
AUD_SCK
4
33pF
R4213
50V C4212
33
CAMERA
CAMERA
5
33pF
50V C4211
6
CAMERA
+3.5V_ST
3
33pF
50V C4214
8
R4220
10K
CAMERA
VA4200
D
ST_BY_DET_CAM
USB_DM3
0 R4201
0 R4203
R4209
2.2K
CAMERA
C
USB_DP3
USB2_HUB_IC_IN_DP
NON_CAMERA
NON_CAMERA
CAM_CTL
R4207
3.3K
B
USB_CAMERA_DP
CAMERA
E
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
9
10
11
USB_CAMERA_DM
Q4200
MMBT3904(NXP)
CAMERA
RCLAMP0502BA
OPT D4200
USB2_HUB_IC_IN_DM
C4210
4.7uF
10V
CAMERA
7
CAMERA
NON_CAMERA
0 R4202
R4208
22K
CAM_PWR_ON_CMD
CAMERAVA4201
NON_CAMERA
0 R4200
CAMERA
G
S
Q4201
PMV48XP
12
13
BSD-NC4_H042-HD
USB3_HUB
2012.10.08
LGE Internal Use Only
+5V_USB_1
USB1 (3.0)
MAX 1.2A
10uF
10V
+3.3V_NORMAL
ZD4301
5V
JK4400
OPT
C4400
SJ113262
VBUS
OCP USB1
R4500
10K
OPT
DUSB3_DM
R4501
10K
D+
USB3_DP
IC4500
BD82020FVJ
GND
+5V_USB_1
1
2
3
4
+5V_NORMAL
7
3
6
4
5
USB3_RX0M
STDA_SSRX+
OUT_2
USB3_RX0P
OUT_1
C4501
GND_DRAIN
10uF
10V
STDA_SSTX-
OC
USB3_TX0M
STDA_SSTX+
USB_CTL1
OCP USB2/3
USB_CTL2
4
5
RCLAMP0502BA
D4401
RCLAMP0502BA
D4402
3AU04S-305-ZC-(LG)
JK4300
/USB_OCD2
1
2
2
3
USB_DM3
USB_DP3
C4310
10uF
10V
ZD4302
5V
RCLAMP0502BA
D4300
FLT2
ZD4300
5V
9
USB3 (2.0)
MAX 1.0A
+5V_USB_3
1
10K
USB DOWN STREAM
C4322
10uF
10V
C4337
10uF
10V
C4301
10uF
10V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
10K
USB_DP2
+5V_USB_2
OUT2
4
6
OUT1
5
7
8
OPT
EN2
3
USB_DM2
/USB_OCD3
RCLAMP0502BA
D4302
USB_CTL3
FLT1
+5V_USB_3
7
SHIELD
3AU04S-305-ZC-(LG)
JK4302
OPT
EN1
2
8
9
IN
1
THERMAL
GND
C4302
0.1uF
16V
R4302
+5V_NORMAL
R4301
IC4306
TPS2066CDGNR [EP]GND
6
10
USB2 (2.0)
MAX 1.0A
+5V_USB_2
+3.3V_NORMAL
D4400
RCLAMP0502BA
USB3_TX0P
5
3
EN
/USB_OCD1
2
STDA_SSRX-
OUT_3
USB DOWN STREAM
IN_2
8
4
IN_1
C4500
0.1uF
16V
1
5
GND
BSD-NC4_H044-HD
2012-11-09
USB JACK
LGE Internal Use Only
+3.3V_NORMAL
Full Scart(18 Pin Gender)
EU
R4801
10K
CLOSE TO JUNCTION
EU
R4802
100
EU
C4804
0.1uF
VA4801
5.6V
EU
SC_DET
1/16W
5%
SC_CVBS_IN
VA4807
5.5V
EU
SHIELD
19
AV_DET
18
17
16
15
14
13
12
11
75
COM_GND
R4800
EU
VA4808
5.5V
OPT
SYNC_IN
DTV/MNT_V_OUT
SYNC_OUT
SYNC_GND
RGB_IO
SC_FB
R_OUT
VA4802
5.6V
EU
R_GND
G_OUT
10
G_GND
9
SC_R
ID
8
VA4803
5.5V
EU
B_OUT
7
AUDIO_L_IN
6
B_GND
5
SC_G
AUDIO_GND
4
VA4804
5.5V
EU
AUDIO_L_OUT
3
AUDIO_R_IN
2
AUDIO_R_OUT
1
SC_B
VA4805
5.5V
EU
DA1R018H91E
JK4800
EU
SC_ID
SC_L_IN
VA4809
5.6V
EU
VA4800
20V
EU
SC_R_IN
VA4806
5.6V
EU
BLM18PG121SN1D
L4800
EU
EU
C4800
1000pF
50V
DTV/MNT_L_OUT
EU
C4802
4700pF
BLM18PG121SN1D
L4801
EU
EU
C4801
1000pF
50V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EU
C4803
4700pF
DTV/MNT_R_OUT
BSD-NC4_H048-HD
2012.10.31
SCART GENDER
LGE Internal Use Only
Ethernet Block
LAN_JACK_POWER
C5100
0.1uF
16V
C5101
0.01uF
50V
C5102
0.1uF
16V
C5103
0.01uF
50V
JK5100
XRJH-01A-4-DA7-180-LG(B)
LAN_XML
1
2
3
4
5
6
P1[CT]
P2[TD+]
EPHY_TDP
P3[TD-]
EPHY_TDN
P4[RD+]
EPHY_RDP
P5[RD-]
EPHY_RDN
P6[CT]
VA5100
5.5V
7
8
9
10
11
D1
D2
D3
D4
VA5101
5.5V
VA5102
5.5V
VA5103
5.5V
P7
P8
P9
EMI
P10[GND]
R5100
0
P11
YL_C
YL_A
GN_C
GN_A
12
SHIELD
JK5100-*1
TLA-6T764
LAN_TDK
1
2
3
4
5
6
7
8
9
10
11
D1
D2
D3
D4
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10[GND]
R11
YL_C
YL_A
GN_C
GN_A
12
SHIELD
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LAN_VERTICAL
2011.12.09
50
LGE Internal Use Only
Ethernet Block
R5215
3.3K
+3.3V_WOL
EPHY_ACTIVITY
R5217 3.3K
ET_RXER
LAN_JACK_POWER
+3.3V_WOL
Place this cap. near IC
EPHY_CRS_DV
C5203
0.1uF
16V
ET_RXER
33
8
17
TXD[1]
1/16W
5%
R5219
10K
1/16W
1%
3.3K
C5212
0.1uF
OPT
EPHY_TXD1
TXD[0]
+3.3V_WOL
C5202
R5209
C5211
0.1uF
16V
5pF
EPHY_INT
R5208
3.3K
TXC
DVDD33
RXC
RXD[3]/CLK_CTL
OPT
C5209
RXD[1]
33
EPHY_RXD0
EPHY_RXD1
33pF
R5201
R5207
33 RXD[2]/INTB
9
RXD[0]
33
R5206
EPHY_EN
16
RXDV
15
TXD[2]
14
18
13
7
12
AVDD33_1
11
TXD[3]
10
TXEN
19
3.3K
R5212
1.5K
R5205
/RST_PHY (from SOC)
20
R5200
D
ZD5200
5V
PHYRSTB
OPT
S
EPHY_MDC
21
EPHY_MDIO
Place near IC
G
MDC
6
+3.3V_WOL
C4325
4.7uF
10V
22
5
3.3K
R4317
22K
MDIO
MDI-[1]
R5203
+3.5V_WOL
LED0/PHYAD[0]/PMEB
23
MDI+[1]
+3.3V_WOL
EPHY_RDN
Q4301
PMV48XP
LED1/PHYAD[1]
IC5200
RTL8201F-VB-CG
WOL/ETH_POWER_ON
24
4
EPHY_RDP
+3.5V_ST
CRS/CRS_DV
COL
RXER/FXEN
DVDD10OUT
AVDD33_2
CKXTAL1
THERMAL
33
MDI-[0]
EPHY_TDN
WOL POWER ENABLE CONTROL
+3.3V_WOL
25
3
26
MDI+[0]
Route Single 50 Ohm, Differential 100 Ohm
EPHY_TDP
27
2
28
1
29
RSET
AVDD10OUT
30
R5204
2.49K 1%
32
[EP]
50V
Place this Res. near IC
31
CKXTAL2
C5207
15pF
Place this cap. near IC
C5205
0.1uF
16V
R5210
R5218
0
1M R5202
GND_1
X-TAL_1
OPT
25MHz
X5200
1
X-TAL_2
3
4
2
+3.3V_WOL
GND_2
C5206
15pF
50V
ET_COL/SNI
Place 0.1uF close to each power pins
51
C5201
0.1uF
16V
EPHY_TXD0
C5200
4.7uF
10V
EPHY_REFCLK
BLM18PG121SN1D
EPHY_ACTIVITY
C5208
0.1uF
16V
ET_COL/SNI
L5200 120-ohm
OPT
ZD5201
5V
+3.5V_WOL
R4318
2.2K
WOL_CTL
R4316
3.3K
C
Q4300
MMBT3904(NXP)
B
E
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
BSD-NC4_H052-HD
2012-09-12
ETHERNET
LGE Internal Use Only
R5602
0
Separate DGND AND AVSS
C5613 2200pF
50V
OUT_A
1
PVDD_AB_2
BST_A
PVDD_AB_1
2
3
4
NC_1
PBTL
AVSS
PLL_FLTM
NC_2
7
8
9
C5616
0.033uF
50V
NC_5
43
BST_B
42
BST_C
41
NC_4
40
NC_3
18
PDN
19
LRCLK
20
SCLK
21
SDIN
22
39
OUT_C
SDA
23
38
PGND_CD_2
SCL
24
37
PGND_CD_1
L5606
10.0uH
NRS6045T100MMGK
NRS6045T100MMGK
50V
0.033uF
C5625
L5604
10.0uH
SPK_R+
SPEAKER_R
C5631
0.47uF
50V
WOOFER_MUTE
C5606
0.1uF
16V
L5602
BLM18PG121SN1D
C5610
0.1uF
16V
C5617
C5619
0.1uF
50V
0.033uF
50V
C5621
10uF
35V
C5623
10uF
35V
C5638
2200pF
50V
C5634
0.1uF
50V
C5639
2200pF
50V
C5635
0.1uF
50V
C5629
330pF
50V
1/16W
OUT_D
PVDD_CD_2
BST_D
PVDD_CD_1
GVDD_OUT
VREG
GND
+3.3V_NORMAL
AGND
DVSS
DVDD
STEST
RESET
C5614
0.1uF
R5604
C5628
330pF
50V
+24V_AMP
R5614
18
33
C56151uF 25V
AMP_RESET_N
R5605
R5606
ZD5600
5V
WOOFER_MUTE
I2C_SCL1
33
33
OPT
I2C_SDA1
SPEAKER_L
SPK_L50V
0.033uF
C5624
AUD_SCK
AUD_LRCH
C5637
2200pF
50V
C5633
0.1uF
50V
R5612
18
36
AUD_LRCK
35
25
E
34
C5605
4.7uF C5607
0.1uF
10V
49
VR_DIG
33
10K
NC_6
44
17
TAS5733
IC5600
B
OUT_B
45
DVSSO
32
AMP_MUTE
46
16
AUD_MASTER_CLK
100 C5602
1000pF
Q5600
50V
MMBT3904(NXP)
PGND_AB_1
15
30
C
PGND_AB_2
47
MCLK
R5603
R5600
48
OSC_RES
29
18K
C5630
0.47uF
50V
C5627
330pF
50V
[EP]
C5636
2200pF
50V
C5632
0.1uF
50V
1/16W
14
C5618
0.1uF
50V
C5626
330pF
50V
C5620 C5622
10uF
10uF
35V
35V
R5613
18
13
R5607 1%
R5601
10K
12
AVDD
A_SEL_FAULT
28
R5608 15K
27
C5604
0.1uF
16V
26
C5603
10uF
10V
SPK_L+
R5611
18
+24V_AMP
THERMAL
+3.3V_NORMAL
10
L5601
BLM18PG121SN1D
11
VR_ANA
+3.3V_NORMAL
PLL_FLTP
470
SSTIMER
R5609
31
C5608
5
C5609 4700pF
0.047uF
Close to Speaker
NRS6045T100MMGK
L5605
10.0uH
6
C5601
0.1uF
50V
0.047uF
C5611 4700pF
L5600
UBW2012-121F
R5610
470
This parts are Located
on AVSS area.
+24V_AMP
C5612
+24V
SPK_RL5603
10.0uH
NRS6045T100MMGK
WAFER-ANGLE
SPK_L+
SPK_L-
SPK_R+
SPK_R-
4
3
2
1
P5600
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
GP4_MT5369
AUDIO[ST]
2011.11.21
58
LGE Internal Use Only
WOOFER
R5700
0
P5701
GND-4
FW25001-02(SPK 2P)
WOOFER
Separate DGND AND AVSS
2
21
PVDD_AB_1
OUT_A
1
2
BST_A
PVDD_AB_2
3
NC_1
5
4
WOOFER
C5713 2200pF
50V
SSTIMER
NC_2
AVSS
PLL_FLTM
PBTL
8
9
6
R5708
470
PLL_FLTP
WOOFER
C5716
0.033uF
50V
PGND_AB_1
46
OUT_B
45
NC_6
44
NC_5
43
BST_B
42
BST_C
41
NC_4
40
NC_3
WOOFER
39
23
38
PGND_CD_2
37
PGND_CD_1
36
35
34
33
32
25
31
24
OPT
R5710
22
SDA
WOOFER
C5710
0.1uF
16V
WOOFER
OUT_D
PVDD_CD_2
PVDD_CD_1
BST_D
GVDD_OUT
C5717
WOOFER_STEREO
C5719
0.1uF
50V
WOOFER
C5721
10uF
35V
C5723
10uF
35V
WOOFER_STEREO
0.033uF
50V
WOOFER
NRS6045T100MMGK
L5703
10.0uH
SPK_WOOFER_R+
WOOFER_STEREO
WOOFER_STEREO
C5734
0.1uF
50V
WOOFER_STEREO
C5726
330pF
50V
WOOFER_STEREO
C5731
0.47uF
50V
WOOFER_STEREO
C5727
330pF
50V
WOOFER_STEREO
C5735
0.1uF
50V
WOOFER_STEREO
C5738
2200pF
50V
WOOFER_R
WOOFER_STEREO
C5739
2200pF
50V
SPK_WOOFER_RL5705
10.0uH
NRS6045T100MMGK
10K
WOOFER
L5702
BLM18PG121SN1D
+24V_AMP_WOOFER
OPT
R5709
WOOFER
C5706
0.1uF
16V
OPT
ZD5700
5V
+3.3V_NORMAL
VREG
GND
C5714
0.1uF
WOOFER
WOOFER
R5702
C57151uF 25V
WOOFER
AMP_RESET_N
33
AGND
I2C_SDA1
I2C_SCL1
DVSS
R5703 WOOFER
33 R5704 WOOFER
DVDD
33
STEST
RESET
AUD_SCK
AUD_LRCH
SPK_WOOFER_LL5706
10.0uH
NRS6045T100MMGK
WOOFER
50V
0.033uF
C5725
OUT_C
AUD_LRCK
WOOFER
C5733
0.1uF
50V
WOOFER
C5737
2200pF
50V
R5714
18
WOOFER
WOOFER
50V
0.033uF
C5724
SDIN
SCL
WOOFER_L
1/16W
20
SCLK
PGND_AB_2
47
WOOFER
C5736
2200pF
50V
1/16W
19
[EP]
48
WOOFER
C5732
0.1uF
50V
WOOFER
C5730
0.47uF
50V
WOOFER
C5729
330pF
50V
WOOFER_STEREO
R5711
18
18
PDN
LRCLK
WOOFER
C5728
330pF
50V
WOOFER
C5720 C5722
10uF
10uF
35V
35V
WOOFER
WOOFER_STEREO
R5712
18
VR_DIG
WOOFER
C5718
0.1uF
50V
10K
17
49
DVSSO
SPK_WOOFER_L+
TAS5733
IC5700
16
WOOFER
15
30
C5707
0.1uF
MCLK
OSC_RES
29
WOOFER
18K
10
14
28
C5705
WOOFER
4.7uF
10V
12
A_SEL_FAULT
R5705 1%
WOOFER
AUD_MASTER_CLK
100 WOOFER
C5702
1000pF
50V
R5706 15K
13
11
VR_ANA
C5704
0.1uF
16V
WOOFER
AVDD
Close to Speaker
WOOFER
R5713
18
+24V_AMP_WOOFER
THERMAL
WOOFER
C5703
10uF
10V
WOOFER
BLM18PG121SN1D
WOOFER
470
26
0.047uF
L5701
C5712
WOOFER
R5707
27
WOOFER
C5708
+3.3V_NORMAL
WOOFER
R5701
SPK_WOOFER_L+
NRS6045T100MMGK
L5704
10.0uH
7
WOOFER
C5709 4700pF
WOOFER
0.047uF WOOFER
GND-4
WOOFER
C5701
0.1uF
50V
WOOFER 4700pF
C5711
WOOFER
L5700
UBW2012-121F
WOOFER_MUTE
1
This parts are Located
on AVSS area.
+24V_AMP_WOOFER
+24V
SPK_WOOFER_L-
WOOFER_STEREO
P5700
250A1-WR-H03B
SPK_WOOFER_R-
1
SPK_WOOFER_R+
2
3
WOOFER_STEREO
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
GP4_MT5369
AUDIO[ST]
2011.11.21
58
LGE Internal Use Only
Height_SPK option
R5800
0
GND-5
Separate DGND AND AVSS
20
SCLK
21
C5812 2200pF
50V
C5815
0.033uF
50V
OUT_A
1
PVDD_AB_2
BST_A
PVDD_AB_1
2
3
4
NC_1
PBTL
AVSS
PLL_FLTM
NC_2
7
8
[EP]
48
PGND_AB_2
47
PGND_AB_1
46
OUT_B
45
NC_6
44
NC_5
43
BST_B
42
BST_C
41
NC_4
40
NC_3
39
23
38
PGND_CD_2
37
PGND_CD_1
35
34
33
25
C5834
0.1uF
50V
R5814
18
36
22
SDA
24
50V
0.033uF
C5823
L5806
10.0uH
NRS6045T100MMGK
50V
0.033uF
C5824
NRS6045T100MMGK
L5803
10.0uH
H_SPK_R+
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
OUT_D
BST_D
PVDD_CD_1
GVDD_OUT
GND
VREG
PVDD_CD_2
C5818
0.1uF
50V
C5820
10uF
35V
C5822
10uF
35V
C5829
0.47uF
50V
C5826
330pF
50V
C5832
0.1uF
50V
L5802
BLM18PG121SN1D
OPT
C5805
0.1uF
16V
ZD5800
5V
+3.3V_NORMAL
AGND
DVSS
C5813
0.1uF
R5802
+24V_UD_AMP
C5809
0.1uF
16V
C5816
0.033uF
50V
C5837
2200pF
50V
Height Speaker R to 24P wafer
C5838
2200pF
50V
1/16W
33
R5804
C5831
0.1uF
50V
C5825
330pF
50V
R5812
18
AMP_RESET_N
33
C58141uF 25V
I2C_SCL2
R5803
DVDD
I2C_SDA2
33
STEST
RESET
AUD_SCK
AUD_LRCH1
Height Speaker L to 24P wafer
C5836
2200pF
50V
H_SPK_L-
OUT_C
AUD_LRCK
C5835
2200pF
50V
C5830
0.47uF
50V
C5828
330pF
50V
SDIN
SCL
C5833
0.1uF
50V
C5827
330pF
50V
C5819 C5821
10uF
10uF
35V
35V
1/16W
19
C5817
0.1uF
50V
R5813
18
R5811
18
18
PDN
LRCLK
49
VR_DIG
TAS5733
IC5800
17
32
C5806
0.1uF
DVSSO
30
4.7uF
10V
16
29
C5804
15
28
AUD_MASTER_CLK
R5801
WOOFER_MUTE
MCLK
OSC_RES
Height_SPK
27
18K
9
VR_ANA
14
10
13
R5805 1%
100 C5801
1000pF
50V
12
AVDD
A_SEL_FAULT
26
R5806 15K
C5803
0.1uF
16V
H_SPK_L+
+24V_UD_AMP
THERMAL
C5802
10uF
10V
11
L5801
BLM18PG121SN1D
PLL_FLTP
470
SSTIMER
R5807
0.047uF
31
C5807
5
C5808 4700pF
+3.3V_NORMAL
Close to Speaker
NRS6045T100MMGK
L5804
10.0uH
6
C5800
0.1uF
50V
0.047uF
C5811
C5810
GND-5
4700pF
L5800
CIS21J121
R5808
470
This parts are Located
on AVSS area.
+24V_UD_AMP
+24V
H_SPK_RL5805
10.0uH
NRS6045T100MMGK
H13_UD
AUDIO[HEIGHT CH.]
58
LGE Internal Use Only
+12V
EU
AUD_OUT >> EU/CHINA_HOTEL_OPT
IC6000
AZ4580MTR-E1
L6000
EU
EU
OUT1
R6000
C6000
1uF
25V
EU
OPT
C6002
6800pF
OPT
R6002
33K
EU
R6004
IN1-
470K
C6003
33pF
EU
IN1+
VEE
SCART_AMP_L_FB
1
8
2
7
4
C6004
EU
0.1uF
OUT2
R6011
2.2K
50V
SIGN600002
[SCART AUDIO MUTE]
EU
C6008
DTV/MNT_R_OUT
EU
3
VCC
6
IN2-
R6008
EU
33K
OPT
R6010
470K
5
OPT
1uF
C6007
25V
DTV/MNT_L_OUT
6800pF
EU
IN2+
C
C6005 EU
33pF
Q6000
MMBT3904(NXP)
SCART_AMP_R_FB
B
EU_SCART_MUTE_ISAHAYA
Q6002
RT1P141C-T112
EU
SCART_Lout
SCART_MUTE
B
C
E
R6013
1K
E
2.2K
DTV/MNT_L_OUT
SCART_Rout
DTV/MNT_R_OUT
Q6001
MMBT3904(NXP)
E
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
E
R6014
1K
B
B
PDTA114ET
Q6002-*1
C
EU
C
EU
EU_SCART_MUTE_NXP
SCART AUDIO AMP
2011.11.21
60
LGE Internal Use Only
HP_OUT_H13
HP_OUT_H13
C6109-*1
18pF
C6104-*1
18pF
EARPHONE AMP
IC6100
TPA6138A2
HP_OUT
C6100
R6100
1uF
10V
HP_OUT 10K
+INR
HP_OUT_MTK
C6104
180pF
HP_OUT
R6106
43K
HP_OUT
-INR
HP_ROUT_MAIN
1%
R6103
33K
HP_OUT_MTK
HP_OUT_H13
R6103-*1
43K
C6108
10pF
50V
OUTR
1
14
2
13
3
12
+INL
HP_OUT_MTK
HP_OUT
R6104
-INL HP_OUT
43K
C6109
180pF
HP_OUT
R6101
10K
C6101
1uF
10V
HP_OUT
HP_LOUT_MAIN
OUTL
C6106
10pF
50V
1%
R6102
33K
HP_OUT_MTK
HP_LOUT_AMP
HP_ROUT_AMP
GND_1
+3.3V_NORMAL
4
11
UVP
+3.3V_NORMAL
HP_OUT_H13
R6102-*1
43K
1%
MUTE
SIDE_HP_MUTE
HP_OUT
4.7K
R6105
VSS
5
10
6
9
GND_2
VDD
HP_OUT
C6102
1uF
10V
HP_OUT
1%
HP_OUT
CN
7
8
CP
L6100
120-ohm
BLM18PG121SN1D
C6105
1uF
10V
HP_OUT
C6107
0.1uF
16V
C6103
1uF
10V
HP_OUT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
HEADPHONE AMP
2011.09.29
61
LGE Internal Use Only
CI POWER ENABLE CONTROL
IC6200
AP2151WG-7
+5V_NORMAL
IN
5
+5V_CI_ON
1
OUT
CI
2
CI
R6217
100
PCM_5V_CTL
EN
4
3
GND
FLG
C6210
1uF
25V
CI
R6219
10K
CI
R6218
10K
CI
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
CI SLOT
2011.10.31
62
LGE Internal Use Only
B-CAS (SMART CARD) INTERFACE
+3.3V_NORMAL
INT
CMDVCC :
STATUS
--------------------------------HIGH
HIGH
CARD PRESENT
LOW
HIGH
CARD not PRESENT
+3.3V_NORMAL
IC6300
TDA8024TT
OPT
OPT
R6304
2.7K
JAPAN
R6306
5V/3V
R6300 22
R6302
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
PGND
+5V_NORMAL
S2
JAPAN
28
2
27
3
26
4
25
5
24
6
23
AUX2UC
AUX1UC
JAPAN
R6316
1.2K
JAPAN
1
OPT
R6319
1.2K
CLKDIV2
JAPAN
R6315
1.2K
CLKDIV1
OPT
R6318
1.2K
CLKDIV1 CLKDIV2 : F_CRD_CLK
----------------------------1
0
CLKIN
JAPAN
R6317
1.2K
2.7K
JAPAN
OPT
R6305
R6301
2.7K
JAPAN
R6303
SIGN630028
I/OUC
JAPAN
R6307
22
SMARTCARD_DATA/SD_EMMC_CLK
XTAL2
JAPAN
R6308
22
SMARTCARD_CLK/SD_EMMC_DATA[0]
XTAL1
JAPAN
R6309
22
SMARTCARD_DET/SD_EMMC_DATA[3]
OFF
JAPAN
R6310
22
SMARTCARD_RST/SD_EMMC_DATA[2]
L6300
VDDP
JAPAN
C6300
0.1uF
16V
JAPAN
C6301
10uF
10V
JAPAN
C6303
0.1uF
16V
S1
22
7
JAPAN
R6311
22
GND
VUP
JAPAN
C6302
0.1uF
16V
PRES
PRES
I/O
AUX2
AUX1
CGND
8
21
9
20
10
19
11
18
12
17
13
16
14
15
SMARTCARD_VCC/SD_EMMC_CMD
L6301 JAPAN
BLM18PG121SN1D
JAPAN
VDD
RSTIN
JAPAN
C6305
0.1uF
16V
JAPAN
C6306
0.1uF
16V
CMDVCC
+3.3V_NORMAL
BLM18PG121SN1D
B-CAS SLOT
P6300
10057542-1311FLF(B CAS Slot)
PORADJ
VCC
VCC
JAPAN
C6307
0.33uF
16V
RST
RST
Place CLK C3 far from C2,C7,C4 and C8
CLK
CLK
JAPAN
C6304
0.1uF
16V
RESERVED_1
GND
VPP
JAPAN
R6313
75
I/O
C1
C2
C3
C4
C5
JAPAN
C6
C7
75 ohm in I/O is for short circuit Protection
RESERVED
JAPAN
+3.3V_NORMAL
R6314
1K
JAPAN
ZD6300
5V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
SW2
JAPAN
10K
R6312
JAPAN
SW1
C8
S1
S2
ZD6301
5V
CI SLOT
2011.04.17
62
LGE Internal Use Only
/TU_RESET2
RF_SWITCH_CTL_50
FE_DEMOD1_TS_ERROR
TU_W_BR/TW/CO
L6508-*1
0
+3.3V_TU
close to TUNER
TU_Q/W_KR/JP/AU
L6508
BLM18PG121SN1D
TU_S/N/Q/W
/TU_RESET1
C6520
0.1uF
16V
TU_N/M/W_TW/BR/CO
R6508-*1
RF_SWITCH_CTL_TU
2
/TU_RESET1_TU
3
I2C_SCL6_TU
1K
5%
TU_N/Q_KR/TW/BR/CO/AU
4
I2C_SDA6_TU
5
+3.3V_TU
6
TUNER_SIF_TU
7
TU_+1.8V_TU
C6506
47pF
50V
C6508
47pF
50V
RF_SWITCH_CTL_50
C6502
TU_S/N/Q/W
0.1uF
R6508
150
R6501 1K
TU_M/W_BR/TW/CO/CN
R6534
8
TU_CVBS_TU
IF_AGC_TU
10
IF_P
11
IF_N
12
+3.3V_TU
13
Power_D_Demod_TU
CN_RESET_TU
C6503
0.1uF
16V
0.1uF
TU_A_GLOBAL_6/7
R6520
200
L6503
BLM18PG121SN1D
TU_A_GLOBAL_6/7
R6521
200
TUNER_SIF
E
OPT
C6522
E
OPT
Q6500
C
MMBT3906(NXP)
OPT
R6515
4.7K
C6529
22uF
10V
85C
C6526
0.1uF
16V
TU_CVBS
B
16V
+3.3V_TU
1608 perallel
because of derating
B
+1.8V_TU
C
C6530
0.1uF
16V
T2 : Max 1.0A
else : Max 0.7A
TU_A_GLOBAL_6/7
Q6501
MMBT3906(NXP)
output : 1.1V_D_Demod
for DVB-T2(V1.3.1) Sony Demod
close to Tuner
close to Tuner
R6506
100
TU_S/N/Q_T/US/KR/TW/AU
IF_AGC
+3.3V_TU
TU_N/M_CN/BR
L6502
BLM18PG121SN1D
R6506-*1
TU_W_BR/TW
TU_N_BR
R6502-*1
/S2_RESET
1K
100
TU_Q/W_KR/BR/TW/CO/JP/AU
L6507
TU_Q/N/M/W
1. should be guarded by ground
2. No via on both of them
3. Signal Width >= 12mils
Signal to Signal Width = 12mils
Ground Width >= 24mils
+3.3V_TU
1
2
FE_DEMOD1_TS_SYNC
18
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_VAL
19
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_ERROR
GND
7
ADJ
deleted resistor
+1.8V_TU
FE_DEMOD1_TS_ERROR
TU_Q/N/M/W
R6527
R2
20K
1%
TU_Q/N/M/W
R6528
11K
1%
R6529 R1
10K
1%
8
EN
17
+1.23V_D_Demod
[EP]
TU_Q/N/M/W
C6540
0.1uF
PG
16
1%
IC6501
AP2132MP-2.5TRG1
+1.23V_D_Demod
C6516
BLM18PG121SN1D
0.1uF
16V
TU_N/M/Q/W_KR/CN/BR/JP/AU
5%
TU_W_CO_T2
R6528-*1
6.8K
TU_W_BR/TW
C6503-*1
0.1uF
16V
IF_P
should be guarded by ground
IF_N
TU_N/M
R6502
10
+3.3V_TU
OPT
R6518
82
close to TUNER
+3.3V_TU
C6514
0.1uF
16V
TU_S/N/Q_T/US/KR/TW/AU
+3.3V_NORMAL
0
OPT
R6516
470
TU_W_BR/TW/CO/JP/_Q_AU
C6550
0.1uF
16V
mA(MAX)
220
+3.3V_TU
L6500
TU_W_BR/TW/CO/JP/_Q_AU BLM18PG121SN1D
9
300
TU_A_GLOBAL_6/7
NON_TU_W_BR/TW/CO
R6509
I2C_SCL6
33
NON_TU_W_BR/TW/CO
R6510
I2C_SDA6
33
C6554
100pF
50V
TU_W_BR/TW/CO TU_W_BR/TW/CO TU_W_BR/TW/CO TU_W_BR/TW/CO TU_W_BR/TW/CO
C6508-*1
C6506-*1
R6509-*1
R6534-*1
R6510-*1
18pF
18pF
RF_SWITCH_CTL
R6505
10K
100 TU_M/W_BR/TW/CO/CN
TU_N/Q_KR/TW/BR/CO/AU
14
R6500 1K
TU_N/M_TW/BR
TU_N/M_TW/BR
C6501
0.1uF
9
1
TU_N_TW/BR
THERMAL
TU_W_BR/TW/CO
C6501-*1
1000pF
3
C6516-*1
0.1uF
16V
TU_W_BR/TW/CO/JP
6
TU_Q/N/M/W
VOUT
VIN
C6533
10uF
16V
2A
4
+5V_NORMAL
5
NC
VCTRL
EAN61387601
Global F/E Option Name
1. TU
2. Tuner Name = TDS’S’,TDS’Q’...
3. Country Name = T,T2,S2,KR,US,BR ...
TU_Q/N/M/W
C6535
1uF
Vout=0.6*(1+R1/R2)
20 FE_DEMOD1_TS_DATA[0]
FE_DEMOD1_TS_DATA[0-7]
21 FE_DEMOD1_TS_DATA[1]
FE_DEMOD1_TS_DATA[0]
Example of Option name
TU_Q_T2 = apply TDSQ type tuner and T2 country
TU_M/W = apply TDSM&TDSW Type Tuner
22 FE_DEMOD1_TS_DATA[2]
13’ Tuner Type
TDS’S’-G501D :
TDS’Q’-G501D :
TDS’Q’-G601D :
TDS’Q’-G651D :
TDS’M’-C601D :
TDS’W’-J551F :
TDS’W’-B651F :
TDS’W’-A651F :
TDS’W’-K651F :
24 FE_DEMOD1_TS_DATA[4]
FE_DEMOD1_TS_DATA[1]
CHB : Max mA
else : Max mA
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[3]
23 FE_DEMOD1_TS_DATA[3]
+3.3V_TU
FE_DEMOD1_TS_DATA[4]
for Global
T/C Half NIM Horizontal Type
T/C/S2 Combo Horizontal type
T2/C/S2 Combo Horizontal Type
T2/C/S2 Combo Vertical Type
China NIM with Isolater Type
Japan Dual NIM
Brazil 2Tuner
Taiwan 2Tuner
Colombia DVB-T2 2Tuner
C6549
10uF
16V
FE_DEMOD1_TS_SYNC
+1.8V_TU
FE_DEMOD1_TS_DATA[5]
IC6503
FE_DEMOD1_TS_DATA[6]
25 FE_DEMOD1_TS_DATA[5]
AZ1117BH-1.8TRE1
FE_DEMOD1_TS_DATA[7]
IN
26 FE_DEMOD1_TS_DATA[6]
3
2
OUT
1
ADJ/GND
27 FE_DEMOD1_TS_DATA[7]
R6531
1
ZD6804
2.5V
TU_Q/W
+1.23V_D_Demod
L6501
BLM18PG121SN1D
30
31
+1.23V_D_Demod_TU
C6515
0.1uF
TU_Q/W
/S2_RESET_TU
32
+3.3V_TU
33
LNB_TX
34
I2C_SCL4_TU
35
I2C_SDA4_TU
C6546
10uF
10V
C6548
10uF
10V
TU_W
R6513-*1
1K
5%
TU_Q
R6513
10
/S2_RESET
+3.3V_TU
+3.3V_TU
LNB_TX
TU_Q/W_KR/BR/CO/TW/JP/AU R6503
36
22
C6521
0.1uF
OPT
I2C_SCL4
TU_Q/W
LNB_OUT
C6531
0.1uF
C6504
18pF
50V
TU_Q/W_KR/BR/CO/TW/JP/AU
R6504
22
C6538
10uF
10V
C6542
0.1uF
I2C_SDA4
TU_Q/W
LNB_OUT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C6500
18pF
50V
Close to the tuner
TUNER
2012.07.10
65
LGE Internal Use Only
4
5
6
7
8
9
10
11
A1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
SCL
SCL
SDA
SDA
I2C_SCL6_TU
+B1[3.3V]
I2C_SDA6_TU
SIF
+3.3V_TU
+B2[1.8V]
CVBS
+B1[3.3V]
TU6701
TDSM-C651D(B)
SIF
+B2[1.8V]
TUNER_SIF_TU
TU_M_CN
TU_+1.8V_TU
8
IF_AGC
9
DIF[P]
10
DIF[N]
11
A1
12
13
12
14
SHIELD
15
16
17
18
RF_S/W_CTL
RF_SWITCH_CTL_50
RESET
TU_PIN2
SCL
I2C_SCL6_TU
SDA
I2C_SDA6_TU
+B1[3.3V]
+3.3V_TU
SIF
TUNER_SIF_TU
+B2[1.8V]
TU_+1.8V_TU
50
19
51
20
52
21
53
22
54
23
55
24
56
25
26
27
CVBS
CVBS
NC_2
NC_1
NC_3
NC_2
NC_4
NC_3
+B3[3.3V]
+B3[3.3V]
+B4[1.23V]
+B4[1.23V]
NC_5
DEMOD_RESET
GND
GND
NC_4
ERROR
SYNC
SYNC
VALID
VALID
MCLK
MCLK
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
B1
B1
A1
59
B1
A1
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
A1
A1
29
28
A2
30
A2
SHIELD
31
TU_GND_B
32
TU_GND_A
TU_GND_B
B2
B2
SHIELD
B1
17
33
34
35
B1
B1
A1
1
RESET
2
TU_SCL
3
TU_SDA
4
+B2[3.3V_M]
5
S_SIF
6
+B3[1.8V_M]
7
S_CVBS
8
M_IF_AGC
9
M_DIF[P]
10
M_DIF[N]
11
+B4[3.3V_S]
12
+B5[1.8V_S]
13
NC_1
14
GND
15
SD_ERROR
16
SD_SYNC
17
SD_VALID
18
SD_MCLK
19
SD_SERIAL_D0
20
NC_2
21
NC_3
22
NC_4
23
NC_5
24
NC_6
25
NC_7
26
NC_8
27
GND_1
28
GND_2
29
+B6[1.23V_SD]
30
SD_RESET
31
+B7[3.3V_SD]
32
NC_9
33
SD_SCL
34
SD_SDA
35
36
A1
0 R6703
NON_CHINA
TU_GND_B
2
SCL
3
SDA
4
+B1[3.3V]
5
SIF
6
+B2[1.8V]
7
CVBS
8
NC_2
9
NC_3
10
NC_4
11
NC_5
12
NC_6
13
B1
38
A1
TU6702-*1
TDSQ-A651D(B)
TU6704-*4
TDSN-T751F
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LNA_CTRL1
LNA_CTRL2
R6704
100
TU_PIN2
B1
57
26
58
27
B1
A1
RF_S/W_CTL
2
SCL
3
SDA
4
+B1[3.3V]
5
SIF
6
+B2[1.8V]
7
CVBS
8
IF_AGC
9
DIF[P]
10
DIF[N]
11
NC_1
12
NC_2
13
NC_3
14
GND
15
NC_4
16
NC_5
17
NC_6
18
NC_7
19
NC_8
20
NC_9
21
NC_10
22
NC_11
23
NC_12
24
NC_13
25
NC_14
26
NC_15
27
A1
28
59
29
30
SHIELD
TU_M/W
C6700
0.1uF
31
TU_M/W
32
33
34
35
B1
B1
A1
+B1[+3.3V_S/P]
1
RESET
2
TU_SCL
3
TU_SDA
4
+B2[3.3V_M]
5
S_SIF
6
+B3[1.8V_M]
7
S_CVBS
8
M_IF_AGC
9
M_DIF[P]
10
M_DIF[N]
11
+B4[3.3V_S]
12
+B5[1.8V_S]
13
+B1(3.3V)_S/P
1
T_RESET
2
TU_SCL
3
TU_SDA
4
+B2[3.3V_M]
5
S_SIF
6
+B3[1.8V_M]
7
S_CVBS
8
M_IF_AGC
9
M_DIF[P]
10
M_DIF[N]
11
+B4[3.3V_S]
12
+B5[1.8V_S]
13
TU_CO
+B1(3.3V)_S/P
1
T_RESET
2
TU_SCL
3
TU_SDA
4
+B2[3.3V_M]
5
S_SIF
6
+B3[1.8V_M]
7
S_CVBS
8
M_IF_AGC
9
M_DIF[P]
10
M_DIF[N]
11
+B4[3.3V_S]
12
+B5[1.8V_S]
13
+B1(3.3V)_S/P
55
TUNER_SIF_TU
56
TU_+1.8V_TU
S_SIF
+B3[1.8V_M]
GND_2
28
GND_3
29
+B3[1.23V]
30
DEMOD_RESET
31
F22_OUTPUT
32
DEMOD_SCL
33
DEMOD_SDA
34
LNB
35
GND_4
TU_Q_T2/S2
M_DIF[N]
+B4[3.3V_S]
TU_W_JP
10K
FE_LNA_Ctrl1
R6705
TU_W_JP
10K
58
NC_7
NC_8
33
SD_SCL
34
SD_SDA
35
28
GND_2
29
+B6[1.23V_D]
30
D_RESET
31
+B7[3.3V_D]
32
NC_1
33
D_SCL
34
D_SDA
35
GND_1
28
GND_2
29
+B6[1.23V_D]
30
D_RESET
31
+B7[3.3V_D]
32
NC_1
33
SD_SCL
34
SD_SDA
35
GND_1
GND_2
A1
38
40
NC_7
38
39
40
NC_2
50
41
51
42
43
44
45
46
47
48
49
B1
B1
A1
GND_3
38
GND_4
39
MD_ERROR
MD_SYNC
MD_VALID
40
RF_S/W_CTRL
NC_7
50
41
51
42
MD_MCLK
43
MD_DATA
44
SD_ERROR
45
SD_SYNC
46
SD_VALID
47
SD_MCLK
48
SD_DATA
A1
49
B1
B1
A1
59
59
SHIELD
GND_3
38
GND_4
39
NC_2
40
NC_3
RF_S/W_CTRL
NC_4
NC_2
50
41
51
42
NC_5
43
NC_6
44
SD_ERROR
45
SD_SYNC
46
SD_VALID
47
SD_MCLK
48
SD_DATA
49
A1
B1
B1
A1
FE_LNA_Ctrl2
R6706
TU_W_JP
C6701
0.1uF
16V
LNA_CTR1
LNA_CTR2
FE_DEMOD1_TS_ERROR
16
FE_DEMOD1_TS_SYNC
17
FE_DEMOD1_TS_VAL
18
FE_DEMOD1_TS_CLK
19
FE_DEMOD1_TS_DATA[0]
20
FE_DEMOD1_TS_DATA[1]
21
FE_DEMOD1_TS_DATA[2]
22
FE_DEMOD1_TS_DATA[3]
23
FE_DEMOD1_TS_DATA[4]
24
FE_DEMOD1_TS_DATA[5]
25
FE_DEMOD1_TS_DATA[6]
26
FE_DEMOD1_TS_DATA[7]
27
+1.23V_D_Demod_TU
30
/S2_RESET_TU
31
+3.3V_D_Demod2
32
LNB_TX
33
I2C_SCL4_TU
34
I2C_SDA4_TU
35
LNB_OUT
36
FE_DEMOD2_TS_ERROR
40
FE_DEMOD2_TS_SYNC
41
FE_DEMOD2_TS_VAL
42
FE_DEMOD2_TS_CLK
43
FE_DEMOD2_TS_DATA
44
FE_DEMOD1_TS_ERROR
45
FE_DEMOD1_TS_SYNC
46
FE_DEMOD1_TS_VAL
47
FE_DEMOD1_TS_CLK
48
FE_DEMOD1_TS_DATA[0]
TU_QW
L6701
BLM18PG121SN1D
49
+B5[1.23V]
D_RESET
+B6[3.3V]
NC_6
D_SCL
D_SDA
LNB
50
41
51
42
52
43
53
44
54
45
55
46
56
47
57
48
58
49
GND_4
GND_5
GND_6
TS1_ERROR
TS1_SYNC
TS1_VALID
TS1_MCLK
TS1_DATA
TS2_ERROR
TS2_SYNC
TS2_VALID
TS2_MCLK
TS2_DATA
B1
C6702
0.1uF
16V
B1
A1
A1
+3.3V_D_Demod2
59
+B6[1.1V_D]
+3.3V_TU
TU_QW
C6708
0.1uF
+B7[3.3V_D]
NC_1
D_SCL
D_SDA
GND_3
GND_4
MD_ERROR
MD_SYNC
MD_VALID
MD_MCLK
MD_DATA
SD_ERROR
SD_SYNC
SD_VALID
SD_MCLK
SHIELD
TU_QW
C6709
10uF
10V
TU_MNQW
L6700
BLM18PG121SN1D
+3.3V_D_Demod
+3.3V_TU
TU_MNQW
C6703
0.1uF
SD_DATA
A1
59
SHIELD
14
GND_3
TU_W_JP
D_RESET
A1
RF_S/W_CTRL
36
37
NC_9
+B5[1.8V_S]
NC_5
GND_1
13
CN_RESET_TU
GND_2
0
SHIELD
M_IF_AGC
NC_6
32
12
Power_D_Demod_TU
+1.8V_T2
D7
M_DIF[P]
NC_3
30
11
+3.3V_D_Demod
+3.3V_T2
D6
NC_8
NC_4
31
10
IF_N
NC_5
D5
SCL_S
NC_2
29
9
IF_P
NC_4
D4
RESET_T2
SD_MCLK
28
8
IF_AGC_TU
NC_3
D3
+B4[3.3V]
SD_SERIAL_D0
+B7[3.3V_SD]
7
TU_CVBS_TU
NC_2
D2
S_CVBS
SD_SYNC
NC_9
6
TU_+1.8V_TU
+1.8V_T1
D1
39
SD_VALID
+B6[1.23V_SD]
5
D0
+B2[3.3V_M]
57
SD_RESET
+3.3V_TU
TUNER_SIF_TU
NC_1
MCLK
TU_SCL
SD_ERROR
GND_2
4
+3.3V_T1
VALID
TU_SDA
NC_1
GND_1
3
I2C_SDA6_TU
SDA_T
SYNC
+3.3V_S_TUNER
GND
SHIELD
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V_TU
2
I2C_SCL6_TU
SCL_T
T_RESET
36
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
54
/TU_RESET1_TU
ERROR
TU6704-*3
TDSW-K651F(B)
TU_TW
TU_BR
1
RESET
TU6704-*2
TDSW-A652F(B)
TU6704-*1
TDSW-B652F(B)
TU_AJJA
1
2
I2C_SDA6_TU
1
RESET_T1
GND
SDA_S
53
C6705
10uF
10V
+5V_OR_+3.3V_SPLITTER
NC_7
50 RF_SWITCH_CTL_50
51
TU_PIN2
I2C_SCL6_TU
52
TU_M_CN
C6706
1000pF
630V
TU_TW_SINGLE
/TU_RESET2
B1
SHIELD
TU_GND_B
NON_CHINA
0 R6702
NON_CHINA
TU_GND_A
TU_GND_B
0 R6701
C6707
630V
NON_CHINA
0 R6700
TU_M_CN
1000pF
1
RESET
R6707
37
36
GND seperation for CHINA tuner
N.C_1
TU_GND_B
TU_GND_B
B1
RESET
TU_W_JP
TU_Q_T2/S2
+B1[+3.3V_S/P]
R6708 0
3
RESET
TU_Korea_PIP
TU_W_JP
2
NC_1
TU6704
TDSW-J551F(B)
TU_GND_A
1
NC
TU6703
TDSQ-G651D(B)
RF_SWITCH_CTL_TU
TU_T2/C
TU_S_US
B1
TU6702
TDSQ-H651F(B)
TU6705
TDSN-G351D
TU6700
TDSS-H651F(B)
SHIELD
TU_MNQW
C6704
10uF
10V
BSD-NC4_H067-HD
TU_SYMBOL
2012.09.14
LGE Internal Use Only
RS-232C Control INTERFACE
JK6801
SPG13-SD-0402
5
9
4
8
R6820
100
3
+3.5V_ST
7
R6821
100
2
6
1
C6812
OPT
ZD6802
ADUC 20S 02 010L
20V
0.33uF
OPT
10
OPT
ZD6803
ADUC 20S 02 010L
20V
C6813
0.1uF
IC6801
MAX3232CDR
C1+
C6808
0.1uF
C6809
0.1uF
V+
C1-
C2+
C6810
0.1uF
C2-
VC6811
0.1uF
DOUT2
RIN2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
GND
DOUT1
RIN1
ROUT1
SOC_RX
DIN1
SOC_TX
DIN2
ROUT2
EAN41348201
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
RS232C
12/08/16
68
LGE Internal Use Only
DVB-S2 LNB Part Allegro
(Option:LNB)
Input trace widths should be sized to conduct at least 3A
3A
Ouput trace widths should be sized to conduct at least 2A
+12V
2A
D6904-*1
Max 1.3A
40V
LNB_SX34
VIN
14
GND
13
VREG
12
ISET
11
TCAP
LNB
5
A_GND
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LNB
A_GND
LNB
R6903
39K
C6912
1/16W
1%
LNB
0.1uF
LNB
LNB_TX
I2C_SDA4
I2C_SCL4
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
R6904
0
0.22uF
GNDLX
LX
16
NC_2
17
NC_3
19
18
BOOST
20
15
C6911
A_GND
TDO
D6903-*1
LNB_SX34
40V
3
IC6900
4
A8303SESTR-T
Caution!! need isolated GND
C6910
0.1uF
50V
10
C6902
0.22uF
25V
TDI
9
LNB
C6904
0.1uF
50V
TONECTRL
Close to Tuner
Surge protectioin
LNB
2
ADD
D6900
LNB
R6900
2.2K
1W
LNB
NC_1
8
C6901
33pF
LNB
D6903
LNB_SMAB34
40V
7
30V
LNB
THERMAL
21
SDA
LNB_OUT
1
R6902 33
LNB
6
VCP
D6901
MBR230LSFT1G
close to VIN pin(#15)
SCL
A_GND
C6909
10uF
25V
LNB
A_GND
A_GND
LNB
R6901 33
close to Boost pin(#1)
[EP]GND
C6907
10uF
25V
LNB
IRQ
C6906
10uF
25V
LNB
LNB
C6905
10uF
25V
LNB
C6908 0.1uF
C6903
0.01uF
50V
LNB
SP-7850_15
15uH
L6900
LNB
40V
LNB_SMAB34
30V
C6900
18pF
LNB
3.5A
D6904
LNB
D6902
LNB
LNB
2012.03.08
69
LGE Internal Use Only
LVDS
[51Pin LVDS OUTPUT Connector]
[41Pin LVDS OUTPUT Connector]
P7202
FI-RE41S-HF-J-R1500
LVDS
P7201
FI-RE51S-HF-J-R1500
LVDS
OLED : FRC_RESET = LVDS_VAL
INV_CTL = ELVDD_ON
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
UD
0
PA168_RESET
OLED R7209
0
I2C_SCL1
OLED R7208
0
I2C_SDA1
UD_CPBOX R7200 0
I2C_SDA1
UD_CPBOX R7201 0
I2C_SCL1
NC
NC
NC
NC
NC
LVDS_SEL
NC
NC
UD
R7204
0
OLED
R7213
0
ALEF
R7203
0
1
2
R7202
3
4
5
6
UD
INV_CTL
BPL_IN
FRC_DONE
7
R7217
0
8
FRC_FLASH_WP
9
10K
R7215
10
TXC0N
11
TXC0P
GND
12
TXC1N
RA0N
13
TXC1P
14
TXC2N
15
TXC2P
L/DIM_ENABLE
UD R7205
0
URSA7_RESET
TXA0N/TX11N
RA0P
TXA0P/TX11P
RA1N
TXA1N/TX10N
16
RA1P
TXA1P/TX10P
RA2N
17
TXCCLKN
18
TXCCLKP
TXA2N/TX9N
RA2P
TXA2P/TX9P
19
GND
RACLKN
20
TXC3N
21
TXC3P
22
TXC4N
23
TXC4P
TXACLKN/TX8N
RACLKP
TXACLKP/TX8P
GND
RA3N
TXA3N/TX7N
24
RA3P
TXA3P/TX7P
25
RA4N
TXA4N/TX6N
RA4P
26
TXA1N
TXD0N/TX17N
27
TXA1P
TXD0P/TX17P
28
TXACLKN
TXD1N/TX16N
29
TXACLKP
TXD1P/TX16P
30
TXA4N
TXD2N/TX15N
31
TXA4P
TXD2P/TX15P
33
TXB0N
TXDCLKN/TX14N
34
TXB0P
TXDCLKP/TX14P
36
TXB1N
TXD3N/TX13N
37
TXB1P
TXD3P/TX13P
38
TXB2N
TXD4N/TX12N
39
TXB2P
TXD4P/TX12P
TXA4P/TX6P
GND
BIT_SEL
BIT_SEL
RB0N
TXB0N/TX5N
RB0P
TXB0P/TX5P
R7214
10K
LVDS_BIT_SEL_LOW
RB1N
TXB1N/TX4N
32
RB1P
TXB1P/TX4P
RB2N
TXB2N/TX3N
RB2P
TXB2P/TX3P
H13 BALL NAME
2
NC
UD_OLED
1
35
GND
RBCLKN
TXBCLKN/TX2N
RBCLKP
TXBCLKP/TX2P
GND
RB3N
TXB3N/TX1N
40
RB3P
TXB3P/TX1P
41
RB4N
TXB4N/TX0N
RB4P
42
TXB4P/TX0P
GND
PANEL_VCC
GND
GND
GND
L7201
120-ohm
LVDS
T_CON_SYS_POWER_OFF
GND
C7201
10uF
16V
OPT
NC
VLCD
C7203
0.1uF
16V
LVDS
VLCD
VLCD
VLCD
52
GND
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
T_CON_SYS_POWER_OFF
R7216
0
OLED
LED_R
BSD-NC4_H072-HD
2012-10-15
LVDS INTERFACE
LGE Internal Use Only
eMMC I/F
A5
B2
B3
3.3V_EMMC
B4
B5
47K
B6
NC_23
DAT1
NC_24
DAT2
NC_25
DAT3
NC_26
DAT4
NC_27
DAT5
NC_28
DAT6
NC_29
DAT7
NC_30
R8116
10K
M6
M5
C5
A5
EMMC_DATA[3]
EMMC_DATA[4]
B2
EMMC_DATA[5]
B4
B3
EMMC_DATA[6]
B5
EMMC_SERIAL_22
AR8101
22
1/16W
EMMC_DATA[7]
B6
DAT1
NC_26
DAT2
NC_27
DAT3
NC_28
DAT4
NC_29
DAT5
NC_30
DAT6
NC_31
DAT7
NC_32
NC_33
NC_34
M6
M5
CLK
NC_35
CMD
NC_36
NC_37
NC_38
A6
A7
C5
E5
E8
EMMC_SERIAL_22
22
E10
EMMC_CMD
F10
EMMC_RST
G3
G10
H5
OPT
J5
C8107
10pF
50V
K6
K7
K10
EMMC_SERIAL_100
AR8100-*1 AR8101-*1 AR8102-*1
100
100
100
1/16W
1/16W
1/16W
EMMC_SERIAL_100
EMMC_SERIAL_100
eMMC serial 100 ohm option
P7
P10
NC_39
NC_4
NC_40
NC_23
NC_41
NC_42
NC_46
NC_43
NC_47
NC_44
NC_48
NC_45
NC_49
NC_52
NC_50
NC_58
NC_51
NC_59
NC_53
NC_66
NC_54
NC_73
NC_55
NC_80
NC_56
NC_81
NC_57
NC_82
NC_60
NC_116
NC_61
NC_119
NC_62
NC_63
NC_64
K5
RESET
OPT
C8100
0.1uF
16V
NC_65
NC_67
NC_68
C6
3.3V_EMMC
M4
3.3V_EMMC
N4
P3
EMMC_RESET_BALL
EMMC_CMD_BALL
EMMC_CLK_BALL
DAT6
DAT5
DAT4
DAT3
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
C8105
0.1uF
16V
C8106
2.2uF
10V
E6
F5
J10
K9
VCC_1
VCC_2
VCC_3
VCC_4
EMMC_VDDI
C2
VDDI
C8104
1uF
10V
E7
G5
H10
K8
C8102
0.1uF
16V
C8103
2.2uF
10V
C4
N2
N5
P4
P6
VSS_1
VSS_2
VSS_3
VSS_4
NC_69
HYNIX_EMMC_4GB
AR8102
EMMC_CLK
E9
NC_3
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
VSSQ_1
NC_93
VSSQ_2
NC_94
VSSQ_3
NC_95
VSSQ_4
NC_96
VSSQ_5
NC_97
NC_98
NC_99
DAT3
DAT4
A2
A8
A9
A10
A11
A12
A13
A14
B1
B7
B8
B9
B10
B11
B12
Don’t Connect Power At VDDI
B13
EMMC_VDDI
B14
C1
(Just Interal LDO Capacitor)
DAT5
NC_100
A1
C3
C7
NC_1
NC_101
NC_2
NC_102
NC_5
NC_103
NC_6
NC_104
NC_7
NC_105
NC_8
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_24
NC_122
NC_36
C9
E8
C10
E9
C11
E10
C12
F10
C13
G3
G10
C14
D1
D2
DAT5
H5
J5
D3
K6
D4
K7
K10
D12
D13
P7
D14
P10
E1
RFU_1
NC_37
RFU_2
NC_38
NC_21
NC_39
RFU_3
NC_40
RFU_4
NC_41
RFU_5
NC_42
RFU_6
NC_43
RFU_7
NC_44
RFU_8
NC_45
RFU_9
NC_46
RFU_10
NC_47
RFU_11
NC_48
RFU_12
NC_49
RFU_13
NC_50
RFU_14
NC_51
RFU_15
NC_52
RFU_16
NC_53
E2
K5
E3
RST_N
E12
E13
C6
E14
F1
F2
DAT6
M4
N4
P3
F3
P5
F12
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
F13
F14
G1
E6
G2
F5
G12
J10
G13
K9
VCC_1
VCC_2
VCC_3
VCC_4
G14
H1
C2
H2
VDDI
H3
H12
E7
H13
G5
H14
J1
H10
J2
K8
J3
C4
J12
N2
N5
J13
J14
EMMC_RESET_BALL
P4
P6
K1
K2
VSS_1
DU7
DU8
DUMMY_6
DUMMY_7
DUMMY_8
DUMMY_13
DUMMY_14
DUMMY_15
DUMMY_16
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_82
VSSQ_5
NC_83
NC_84
NC_85
K12
K13
A1
K14
A2
L1
A8
L2
A9
L3
A10
L12
A11
L13
A12
L14
A13
M1
A14
M2
B1
M3
B7
M7
B8
M8
B9
M9
B10
M10
B11
M11
B12
M12
B13
M13
B14
M14
C1
C3
N1
N3
EMMC_CMD_BALL
N6
C7
NC_86
NC_1
NC_87
NC_2
NC_88
NC_3
NC_89
NC_4
NC_90
NC_5
NC_91
NC_6
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
NC_104
NC_19
NC_105
NC_20
NC_106
NC_22
NC_107
C10
A5
C11
B2
C12
B3
C13
B4
C14
B5
B6
D1
D2
DAT0
NC_25
DAT1
NC_26
DAT2
NC_27
DAT3
NC_28
DAT4
NC_29
DAT5
NC_30
DAT6
NC_31
DAT7
NC_32
NC_33
D3
D4
M6
D12
M5
D13
NC_34
CLK
NC_35
CMD
NC_36
NC_37
D14
NC_38
A6
E1
E2
A7
E3
C5
E12
E5
E13
E8
E14
E9
E10
F1
F2
F10
F3
G3
F12
G10
F13
H5
F14
J5
G1
K6
G2
K7
K10
G12
G13
P7
G14
P10
H1
NC_3
NC_39
NC_4
NC_40
NC_23
NC_41
NC_42
NC_46
NC_43
NC_47
NC_44
NC_48
NC_45
NC_49
NC_52
NC_50
NC_58
NC_51
NC_59
NC_53
NC_66
NC_54
NC_73
NC_55
NC_80
NC_56
NC_81
NC_57
NC_82
NC_60
NC_116
NC_61
NC_119
NC_62
H2
K5
H3
RESET
H12
H13
C6
H14
J1
M4
J2
N4
P3
J3
P5
J12
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
J13
J14
K1
E6
K2
F5
J10
K3
K9
K12
VCC_1
VCC_2
VCC_3
VCC_4
K13
K14
C2
L1
VDDI
L2
L3
E7
L12
L13
G5
L14
H10
K8
M1
M2
C4
M3
N2
N5
M7
M8
P4
M9
P6
M10
VSS_1
VSS_2
VSS_3
VSS_4
NC_63
NC_64
NC_65
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
VSSQ_1
NC_93
VSSQ_2
NC_94
VSSQ_3
NC_95
VSSQ_4
NC_96
VSSQ_5
NC_97
NC_98
M11
NC_99
M12
M13
A1
M14
A2
N1
A8
N3
A9
N6
A10
N7
A11
N8
A12
N9
A13
N10
A14
N11
B1
N12
B7
N13
B8
N14
B9
P1
B10
P2
B11
P8
B12
P9
B13
P11
B14
P12
C1
P13
C3
P14
C7
NC_100
NC_1
NC_101
NC_2
NC_102
NC_5
NC_103
NC_6
NC_104
NC_7
NC_105
NC_8
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_122
NC_24
NC_123
C8
A3
C9
A4
C10
A5
C11
B2
C12
B3
C13
B4
C14
B5
B6
D1
D2
NC_26
DAT2
NC_27
DAT3
NC_28
DAT4
NC_29
DAT5
NC_30
DAT6
NC_31
DAT7
NC_32
NC_33
D3
D4
M6
D12
M5
NC_34
D13
CLK
NC_35
CMD
NC_36
NC_37
D14
NC_38
A6
E1
E2
A7
E3
C5
E12
E5
E13
E8
E14
E9
E10
F1
F2
F10
F3
G3
F12
G10
F13
H5
F14
J5
G1
K6
G2
K7
K10
G12
G13
P7
G14
P10
H1
NC_3
NC_39
NC_4
NC_40
NC_23
NC_41
NC_42
NC_46
NC_43
NC_47
NC_44
NC_48
NC_45
NC_49
NC_52
NC_50
NC_58
NC_51
NC_59
NC_53
NC_66
NC_54
NC_73
NC_55
NC_80
NC_56
NC_81
NC_57
NC_82
NC_60
NC_116
NC_61
NC_119
NC_62
NC_63
H2
NC_64
K5
H3
RSTN
H12
H13
C6
H14
J1
M4
J2
N4
VDD_1
VDD_2
VDD_3
P3
J3
VDD_4
P5
J12
VDD_5
J13
J14
K1
E6
K2
F5
VDDF_1
VDDF_2
J10
K3
VDDF_3
K9
K12
VDDF_4
K13
K14
C2
L1
VDDI
L2
L3
C4
L12
L13
E7
L14
G5
VSS_1
VSS_2
VSS_3
H10
M1
M2
K8
M3
N2
N5
M7
M8
P4
M9
P6
M10
NC_65
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
VSS_4
NC_92
VSS_5
NC_93
VSS_6
NC_94
VSS_7
NC_95
VSS_8
NC_96
VSS_9
NC_97
NC_98
M11
NC_99
M12
M13
A1
M14
A2
N1
A8
N3
A9
N6
A10
N7
A11
N8
A12
N9
A13
N10
A14
N11
B1
N12
B7
N13
B8
N14
B9
P1
B10
P2
B11
P8
B12
P9
B13
P11
B14
P12
C1
P13
C3
P14
C7
NC_100
NC_1
NC_101
NC_2
NC_102
NC_5
NC_103
NC_6
NC_104
NC_7
NC_105
NC_8
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_122
NC_24
NC_123
C9
C10
C11
C12
C13
C14
D1
A3
A4
A5
B2
B3
B4
B5
B6
C8
DAT0
NC_23
DAT1
NC_24
DAT2
NC_25
DAT3
NC_26
DAT4
NC_27
DAT5
NC_28
DAT6
NC_29
DAT7
NC_30
D2
D3
D4
D12
NC_31
NC_32
M6
M5
CLK
NC_33
CMD
NC_34
D13
D14
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G12
G13
G14
NC_35
NC_36
A6
A7
C5
E5
E8
E9
E10
F10
G3
G10
H5
J5
K6
K7
K10
P7
P10
RFU_1
NC_37
RFU_2
NC_38
NC_21
NC_39
RFU_3
NC_40
RFU_4
NC_41
RFU_5
NC_42
RFU_6
NC_43
RFU_7
NC_44
RFU_8
NC_45
RFU_9
NC_46
RFU_10
NC_47
RFU_11
NC_48
RFU_12
NC_49
RFU_13
NC_50
RFU_14
NC_51
RFU_15
NC_52
RFU_16
NC_53
H1
NC_54
H2
NC_55
H3
K5
RSTN
H12
H13
H14
J1
J2
J3
J12
C6
M4
N4
P3
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
J13
J14
K1
K2
K3
K12
E6
F5
J10
K9
VCC_1
VCC_2
VCC_3
VCC_4
K13
K14
L1
C2
VDDI
L2
L3
L12
L13
L14
M1
M2
M3
M7
M8
M9
E7
G5
H10
K8
C4
N2
N5
P4
P6
VSS_1
VSS_2
VSS_3
VSS_4
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
M10
M11
M12
M13
M14
N1
N3
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
P13
P14
A1
A2
A8
A9
A10
A11
A12
A13
A14
B1
B7
B8
B9
B10
B11
B12
B13
B14
C1
C3
C7
NC_1
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_2
NC_88
NC_3
NC_89
NC_4
NC_90
NC_5
NC_91
NC_6
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
NC_104
NC_19
NC_105
NC_20
NC_106
NC_22
NC_107
C9
C10
C11
C12
C13
C14
D1
D2
D3
D4
D12
D13
D14
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G12
G13
G14
H1
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
M7
M8
M9
M10
M11
M12
M13
M14
N1
N3
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
P13
P14
N9
N10
N11
N12
N13
N14
P1
P2
P8
IC8100-*8
H26M42002GMR
IC8100-*5
KLM4G1FE3B-B001
EMMC_CLK_BALL
P9
A5
B2
B4
B5
B6
DAT0
NC_25
DAT1
NC_26
DAT2
NC_27
DAT3
NC_28
DAT4
DAT5
DAT6
DAT7
P12
M6
M5
CLK
CMD
P13
A6
P14
A7
C5
E5
E8
NC_3
NC_4
NC_23
NC_42
NC_43
NC_44
NC_45
NC_52
NC_58
NC_59
NC_66
NC_73
NC_80
NC_81
NC_82
NC_116
K5
RSTN
DU10
C6
M4
DU11
N4
P3
P5
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
DU12
E6
F5
DU13
DU14
DU15
J10
K9
VDDF_1
VDDF_2
VDDF_3
VDDF_4
C2
VDDI
E7
G5
H10
DU16
IC8100-*7
KLMAG2GE4A-A001
A4
B3
P11
IC8100-*6
THGBM5G6A2JBAIR
A3
A3
A4
K8
C4
N2
N5
P4
VSS_2
VSS_3
VSS_4
VSS_5
VSS_1
VSS_6
VSS_7
VSS_8
VSS_9
A1
A2
A8
A9
A10
A11
A12
A13
A14
B1
B7
B8
B9
B10
B11
B12
B13
B14
C1
C3
C7
NC_1
NC_2
NC_5
NC_6
NC_7
NC_8
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_53
NC_54
NC_55
NC_56
NC_57
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
NC_93
NC_94
NC_95
NC_96
NC_97
NC_98
NC_99
NC_100
NC_101
NC_102
NC_103
NC_104
NC_105
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_122
NC_24
NC_123
C8
A3
C9
A4
C10
A5
C11
B2
C12
B3
C13
B4
C14
B5
D1
B6
DAT0
NC_23
DAT1
NC_24
DAT2
NC_25
DAT3
NC_26
DAT4
DAT5
DAT6
DAT7
D2
D3
D4
M6
D12
M5
CLK
CMD
D13
D14
E1
A6
E2
A7
E3
C5
E12
E5
E13
E8
E14
E9
F1
E10
F2
F10
F3
F12
F13
G3
G10
H5
F14
J5
G1
K6
G2
G12
K7
K10
G13
P7
G14
P10
RFU_1
RFU_2
NC_21
RFU_3
RFU_4
RFU_5
RFU_6
RFU_7
RFU_8
RFU_9
RFU_10
RFU_11
RFU_12
RFU_13
RFU_14
RFU_15
RFU_16
H1
H2
H3
K5
RSTN
H12
H13
H14
C6
J1
M4
J2
N4
J3
P3
J12
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
J13
J14
K1
E6
K2
F5
K3
J10
K12
K9
VCC_1
VCC_2
VCC_3
VCC_4
K13
K14
L1
C2
VDDI
L2
L3
L12
E7
L13
G5
L14
H10
M1
K8
M2
C4
M3
N2
M7
N5
M8
P4
M9
P6
VSS_1
VSS_2
VSS_3
VSS_4
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
M10
M11
M12
M13
M14
A1
A2
N1
A8
N3
A9
N6
A10
N7
A11
N8
A12
N9
A13
N10
A14
N11
B1
N12
B7
N13
N14
P1
B8
B9
B10
P2
B11
P8
B12
P9
B13
P11
B14
P12
C1
P13
C3
P14
C7
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
NC_44
NC_45
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_52
NC_53
NC_54
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
NC_104
NC_19
NC_105
NC_20
NC_106
NC_22
NC_107
C8
A3
C9
A4
C10
A5
C11
B2
C12
B3
C13
B4
C14
B5
D1
B6
C8
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
D2
D3
D4
M6
D12
M5
CLK
CMD
D13
D14
E1
A6
E2
A7
E3
C5
E12
E5
E13
E8
E14
E9
F1
E10
F2
F10
F3
F12
F13
G3
G10
H5
F14
J5
G1
K6
G2
G12
K7
K10
G13
P7
G14
P10
RFU_1
RFU_2
RFU_3
RFU_4
RFU_5
RFU_6
NC_39
RFU_7
RFU_8
RFU_9
RFU_10
RFU_11
RFU_12
RFU_13
RFU_14
RFU_15
NC_104
H1
H2
H3
K5
RESET
H12
H13
H14
C6
J1
M4
J2
N4
J3
P3
J12
P5
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
J13
J14
K1
E6
K2
F5
K3
J10
K12
K9
VDDF_1
VDDF_2
VDDF_3
VDDF_4
K13
K14
L1
C2
VDDI
L2
L3
L12
E7
L13
G5
L14
H10
M1
K8
M2
C4
M3
N2
M7
N5
M8
P4
M9
P6
VSS_2
VSS_3
VSS_4
VSS_9
VSS_1
VSS_5
VSS_6
VSS_7
VSS_8
M10
M11
M12
M13
M14
A1
A2
N1
A8
N3
A9
N6
A10
N7
A11
N8
A12
N9
A13
N10
A14
N11
B1
N12
B7
N13
N14
P1
B8
B9
B10
P2
B11
P8
B12
P9
B13
P11
B14
P12
C1
P13
C3
P14
C7
NC_1
NC_2
NC_3
NC_4
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_40
NC_41
NC_42
NC_43
NC_44
NC_45
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_52
NC_53
NC_54
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_5
NC_91
NC_6
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
RFU_16
NC_19
NC_105
NC_20
NC_106
NC_21
NC_107
C9
A5
C10
B2
C11
B3
C12
C13
C14
B4
B5
B6
D1
M6
M5
DU2
DU4
DU5
DU6
DU7
DU8
DUMMY_1
DUMMY_9
DUMMY_2
DUMMY_10
DUMMY_11
DUMMY_4
DUMMY_12
DUMMY_5
DUMMY_13
DUMMY_6
DUMMY_14
DUMMY_7
DUMMY_15
DUMMY_8
DUMMY_16
CLK
CMD
D13
E1
E2
E3
A6
A7
E12
C5
E13
E5
E14
F1
E8
E9
F2
F3
F12
E10
F10
F13
G3
F14
G10
G1
G2
H5
J5
G12
G13
G14
H1
K6
K7
K10
H2
P7
H3
P10
NC_3
NC_4
NC_23
NC_42
NC_43
NC_44
NC_45
NC_52
NC_58
NC_59
NC_66
NC_73
NC_80
NC_81
NC_82
NC_116
NC_119
H12
H13
H14
J1
K5
RESET
J2
J3
J12
J13
C6
M4
J14
K1
N4
K2
P3
K3
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
K12
K13
K14
E6
L1
L2
L3
L12
F5
J10
K9
VCC_1
VCC_2
VCC_3
VCC_4
L13
L14
M1
C2
M2
VDDI
M3
M7
M8
M9
M10
M11
E7
G5
H10
K8
M12
M13
M14
C4
N2
N1
N5
N3
P4
N6
P6
N7
VSS_1
VSS_2
VSS_3
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_53
NC_54
NC_55
NC_56
NC_57
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
VSS_4
NC_92
VSSQ_1
NC_93
VSSQ_2
NC_94
VSSQ_3
NC_95
VSSQ_4
NC_96
VSSQ_5
NC_97
N8
NC_98
N9
NC_99
N10
N11
A1
N12
A2
N13
N14
A8
A9
P1
P2
P8
A10
A11
P9
A12
P11
A13
P12
P13
A14
B1
P14
B7
DU9
DUMMY_3
DAT5
DAT6
D14
B9
DU3
NC_26
NC_27
DAT3
DAT4
D3
D4
D12
NC_25
DAT1
DAT2
DAT7
B10
DU1
C8
DAT0
D2
B8
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
NC_25
DAT1
N8
P6
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
C8
DAT0
N7
DU9
DUMMY_5
NC_68
VSSQ_4
NC_119
DU6
NC_67
NC_81
P7
DU5
NC_66
VSSQ_3
P10
DUMMY_12
NC_65
NC_80
K7
DUMMY_4
NC_64
VSSQ_2
K10
DUMMY_11
NC_63
NC_79
H5
DUMMY_3
NC_62
VSSQ_1
J5
DU4
NC_61
NC_78
K6
DU3
NC_60
VSS_4
G3
DUMMY_10
NC_59
NC_77
G10
DUMMY_2
NC_58
VSS_3
E9
DU2
NC_57
NC_76
E10
DUMMY_9
NC_56
VSS_2
F10
DUMMY_1
NC_55
K3
NC_123
DU1
NC_54
A4
HYNIX_EMMC_8GB
A4
EMMC_DATA[2]
NC_25
NC_34
A3
C9
SAMSUNG_EMMC_16G
EMMC_DATA[1]
E5
C8
DAT0
CMD
A6
A7
EMMC_DATA[0]
NC_33
NC_35
IC8100
H26M31002GPR
A3
CLK
TOSHIBA_EMMC_4GB
R8117
10K
10K
R8107
10K
10K
10K
R8104
R8106
R8105
10K
10K
10K
10K
R8103
R8102
EMMC DATA LINE
10K PULL/UP
FOR M13
NC_32
SAMSUNG_EMMC_4GB
EMMC_DATA[0-7]
R8100
EMMC_SERIAL_22
AR8100
22
1/16W
R8101
R8107-*1
R8104-*1
R8106-*1
R8105-*1
R8103-*1
R8102-*1
R8101-*1
R8100-*1
NC_31
C8
TOSHIBA_EMMC_8GB
47K
47K
47K
47K
47K
47K
47K
EMMC DATA LINE 47K PULL/UP
DAT0
IC8100-*4
THGBM5G7A2JBAIR
IC8100-*3
KLM2G1HE3F-B001
TOSHIBA_EMMC_16GB
A4
HYNIX_EMMC_2GB
A3
IC8100-*2
H26M21001ECR
SAMSUNG_EMMC_2GB
IC8100-*1
THGBM5G5A1JBAIR
DU10
B11
B12
DU11
DU12
B13
DU13
B14
DU14
C1
DU15
C3
DU16
C7
NC_100
NC_1
NC_101
NC_2
NC_102
NC_5
NC_103
NC_6
NC_104
NC_7
NC_105
NC_8
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_122
NC_24
NC_123
C9
C10
C11
C12
C13
C14
D1
D2
D3
D4
D12
D13
D14
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G12
G13
G14
H1
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
M7
M8
M9
M10
M11
M12
M13
M14
N1
N3
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
P13
P14
eMMC
11.09.29
81
LGE Internal Use Only
XTAL(24.75MHz)
HEVC option sheet
R12007
1M
X-TAL_1
XTAL_IN
X12000
24.75MHz
1
4
2
3
GND_1
C12000
27pF
50V
GND_2
X-TAL_2
C12003
27pF
50V
R12049
10
XTAL_OUT
IC12000
LG1132-D13
D13_INT
+3.3V_NORMAL
+3.3V_NORMAL
C3
D13_TMS_0
D1
D13_TCK_0
B1
R12021
10K
2
R12000
D13_TRST_N_0
D13_TDI_1
D13_TMS_0
D13_TDO_1
SMODE[1:0]
- 00 : Normal Mode
- Other : Test Mode
D13_TDI_0
D13_UART_RX_0
D13_TDO_0
D13_UART_TX_0
D13_UART_RX_0
D13_UART_RX_1
D13_UART_TX_0
D13_UART_TX_1
4
R12001
D13_TDI_1
33
R12002
D13_TCK_1
6
B9
A9
D20
D19
SOC_SPI0_MISO
R12024
D13_SPI_SCLK_M
R12025
R12026
D13_SPI_DO_M
33
D13_TDO_1
33
D13_TRST_N_1
D13_SPI_CS/GPIO[0]
R12011
10K
OPT
I2C_SCL2
I2C_SDA2
R12027
33C19
33A14
33B14
33B13
A13
TMS0
GPIO[1]
TCK0
GPIO[0]
TDI0
B5
3.3K
A6
HDMI_DDC_CK
TRST_N1
HDMI_DDC_DA
TMS1
HDMI_HPD
TCK1
HDMI_REXT
TDI1
HDMI_CEC
TDO1
HDMI_DDCCEC
B4
D13_FLASH_WP
A4
D13_SPI_CS/GPIO[0]
D13_HDMI_DDC_CK
G2
D13_HDMI_DDC_DA
J2
D13_HDMI_HPD
J1
HDMI_TX0N
UART_TXD0
HDMI_TX0P
UART_RXD1
HDMI_TX1N
UART_TXD1
HDMI_TX1P
HDMI_TX2N
SPI_SCLK_S
HDMI_TX2P
SPI_CS_S
HDMI_TXCN
SPI_DO_S
HDMI_TXCP
SPI_DI_S
H1
Closed to D13
D13_HDMI_TX0N
M2
D13_HDMI_TX0P
L1
D13_HDMI_TX1N
L2
D13_HDMI_TX1P
K1
D13_HDMI_TX2N
K2
D13_HDMI_TX2P
N1
D13_HDMI_TXCN
N2
D13_HDMI_TXCP
F2
SPI_SCLK_M
SMODE[0]
SPI_CS_M
SMODE[1]
SPI_DO_M
R12037
1.6K 1%
H2
M1
UART_RXD0
GPIO[0]
- 1 : Serial Flash Boot
- 0 : Live Boot
9
D13_SMODE[0]
E3
D13_SMODE[1]
A16
SPI_DI_M
TMODE[0]
33A11
33B11
SCL_S
TMODE[2]
TMODE[3]
R12030
OPT
R12031
33A12
33B12
SDA_S
SCL_M
D13_STPO_CLK
R12008
33
G20
D13_STPO_SOP
R12012
33
H19
D13_STPO_VAL
R12022
33
G19
D13_STPO_ERR
R12023
33
H20
D13_STPO_DATA
R12033
33
J19
J20
C12261
10pF
Serial Flash Boot Test
K19
K20
L19
L20
+3.3V_NORMAL
P12002
M19
12507WS-10L
M20
TMODE[1]
B16
A17
B17
* Default Internal Pull-Up
SDA_M
UART For HEVC
STPI_CLK
STPI_SOP
STPI_VAL
STPI_ERR
STPI_DATA[0]
STPI_DATA[1]
STPI_DATA[2]
STPI_DATA[3]
STPI_DATA[4]
STPI_DATA[5]
STPI_DATA[6]
STPI_DATA[7]
R12043
1K
1
2
+3.3V_NORMAL
12507WS-04L
3
4
1
R12005
33
5
D13_UART_RX_1
R12038
0
R12039
0
D13_SPI_CS/GPIO[0]
SPI FLASH(4MByte)
+3.3V_NORMAL
D13_SPI_DO_M
R12040
0
R12041
0
D13_SPI_SCLK_M
R12017
D13_SPI_DI_M
IC12001
MX25L3206EM2I-12G
C12005
0.1uF
10K
6
3
4
H/W Option : default low
SPI Clock Frq. &
DDR density
(High:512MB, LOW:256MB)
A5
G1
TDO0
R12048
B6
3.3K OPT
A7
OPT
8
2
GPIO[2]
OPT
R12028
OPT
R12029
7
P12001
TRST_N0
C20
D13_SPI_DI_M
5
R12003
A10
SOC_SPI0_MOSI
R12010
10K
GPIO[3]
B10
SOC_SPI0_CS0
D13_TMS_1
33
R12004
C2
SOC_SPI0_SCLK
33
+3.3V_NORMAL
3
B2
D13_TCK_0
12507WS-08L
1
D2
D13_TCK_1
D13_SMODE[1]
+3.3V_NORMAL
C12001
0.1uF
16V
B3
D13_TMS_1
D13_SMODE[0]
R12013
10K
E2
D13_TRST_N_1
JTAG for HEVC
P12000
D3
D13_TDO_0
R12020
10K
OPT
GPIO[4]
E1
D13_TDI_0
R12009
10K
OPT
GPIO[5]
PORES_N
D13_TRST_N_0
C12004
0.01uF
GPIO[6]
R12051
33
A18
SPI_DL_MODE
B7
GPIO[7]
XTALO
3.3K
XTAL_OUT
XTALI
R12035
R1
R12014
33
D13_RESET
IC_D13
R12050
33
R2
XTAL_IN
3.3K
R12016
3.3K
R12034
+3.3V_NORMAL
R12036
+3.3V_NORMAL
R12006
33
R12042
7
D13_UART_TX_1
5
8
C12002
0.1uF
16V
9
10
0
CS#
SPI_DL_MODE
R12044
R12045
OPT
OPT
R12046
R12019
0
0
SO/SIO1
D13_SPI_DI_M
R12015
0
D13_FLASH_WP
1
8
2
7
3
6
VCC
HOLD#
WP#
R12018
10K
OPT
R12032
3.3K
33
D13_FLASH_WP
1/16W
5%
0
I2C_SDA2
R12047
D13_SPI_CS/GPIO[0]
GND
4
5
SCLK
D13_SPI_SCLK_M
SI/SIO0
D13_SPI_DO_M
0
I2C_SCL2
11
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
IC12000
LG1132-D13
HEVC option sheet
D13_DDR_A[0-13]
D13_DDR_A[9]
U17
D13_DDR_A[10]
U14
D13_DDR_A[11]
U13
D13_DDR_A[12]
U10
D13_DDR_A[13]
D13_DDR_A[10]
L7
D13_DDR_A[11]
R7
T16
U11
D13_D0_CLK
D13_D0_CLK
U12
D13_DDR_RAS
D13_DDR_WE
Y7
DDR_DQ[6]
DDR_DQ[7]
DDR_DQ[8]
DDR_DQ[9]
DDR_DQ[10]
DDR_DQ[11]
DDR_DQ[12]
DDR_DQ[13]
DDR_DQ[14]
DDR_DQ[15]
DDR_DQ[16]
DDR_DQ[17]
D13_DDR_DQS[3]
Y16
DDR_DQ[18]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[21]
DDR_DQ[22]
DDR_DQ[23]
DDR_DQ[24]
DDR_DQ[25]
DDR_DQ[26]
DDR_DQ[27]
DDR_DQ[28]
DDR_DQ[29]
DDR_DQ[30]
D13_DDR_DQ[0]
W10
D13_DDR_DQ[1]
V2
D13_DDR_DQ[2]
V9
D13_DDR_DQ[3]
Y2
D13_DDR_DQ[4]
Y10
D13_DDR_DQ[5]
W2
D13_DDR_DQ[6]
V10
D13_DDR_DQ[7]
W9
D13_DDR_DQ[8]
W4
D13_DDR_DQ[9]
V8
D13_DDR_DQ[10]
V3
D13_DDR_DQ[11]
V7
D13_DDR_DQ[12]
Y4
D13_DDR_DQ[13]
W8
D13_DDR_DQ[14]
V4
D13_DDR_DQ[15]
V11
D13_DDR_DQ[0-15]
D13_DDR_DM[3]
W3
B7
D3
D13_DDR_DQ[0]
D13_DDR_DQ[1]
D13_DDR_DQ[0-15]
K2
D13_DDR_A[12]
K8
D13_DDR_A[13]
CK
VDDQ_3
CKE
VDDQ_4
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
D13_DDR_DQ[2]
D13_DDR_DQ[3]
F7
F2
F8
D13_DDR_DQ[4]
H3
D13_DDR_DQ[5]
H8
D13_DDR_DQ[6]
G2
D13_DDR_DQ[7]
H7
D13_DDR_DQ[9]
D13_DDR_DQ[10]
D13_DDR_DQ[11]
D13_DDR_DQ[12]
D13_DDR_DQ[13]
D13_DDR_DQ[14]
D13_DDR_DQ[15]
C3
C8
C2
A7
A2
B8
A3
K7
K9
D13_DDR_CKE
F1
H2
H9
C12104
0.1uF
C12105
0.1uF
K1
D13_DDR_ODT
J3
D13_DDR_RAS
K3
D13_DDR_CAS
L3
D13_DDR_WE
J9
T7
VSS_4
DMU
VSS_5
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
G3
G8
B7
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
K8
N1
VDD_6
N9
VDD_7
R1
VDD_8
R9
VDD_9
BA1
A1
VDDQ_1
CK
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
A8
C1
C9
D2
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
E9
F1
D3
D13_DDR_DM[3]
D13_DDR_DQ[16-31]
J8
M1
D13_DDR_DQ[16]
M9
D13_DDR_DQ[17]
P1
D13_DDR_DQ[18]
P9
D13_DDR_DQ[19]
T1
D13_DDR_DQ[20]
H3
T9
D13_DDR_DQ[21]
H8
D13_DDR_DQ[22]
G2
D13_DDR_DQ[23]
H7
D13_DDR_DQ[24]
D7
F7
F2
F8
C3
D13_DDR_DQ[26]
D8
0.1uF
C12107
0.1uF
L1
L9
NC_4
DQSL
T7
NC_6
A9
DQSU
VSS_1
DQSU
VSS_2
B3
E1
VSS_3
DML
VSS_4
DMU
VSS_5
G8
J2
J8
VSS_6
E3
D13_DDR_DQ[25]
D1
C12106
H9
J9
NC_2
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
M1
M9
P1
P9
T1
T9
DQL6
DQL7
B9
H2
J1
NC_1
E7
B1
VSSQ_2
K2
C7
D13_DDR_DM[2]
J2
VSSQ_1
G7
DQSL
D13_DDR_DQS[3]
DQL6
DQU0
VDD_5
F3
D13_DDR_DQS[3]
E1
VSS_6
DQL0
A13
RESET
D13_DDR_DQS[2]
B3
VSS_3
DML
VDD_4
D9
NC_3
A9
VSS_2
A12/BC
T2
D13_DDR_DQS[2]
VSS_1
VDD_3
L9
NC_6
DQSU
VDD_2
A11
WE
D13_DDR_RESET
L1
NC_4
DQSU
VDD_1
A10/AP
L2
E9
NC_2
A9
BA0
VDDC15_D13_DDR
B2
BA2
D13_D1_CLK
D2
1%
A8
J7
D13_D1_CLK
J1
D7
M3
D13_DDR_BA[2]
C9
DQL7
D13_DDR_DQ[8]
N8
ZQ
A7
M2
D13_DDR_BA[0]
C1
NC_1
E3
T3
R12114
240
L8
A6
NC_5
A8
VDDQ_5
DQSL
N7
A5
M7
A1
VDDQ_2
E7
D13_DDR_DM[1]
D13_DDR_DM[2]
Y14
R7
D13_DDR_BA[1]
C7
D13_DDR_DM[0]
D13_DDR_DM[1]
Y17
L7
D13_DDR_A[11]
DQSL
D13_DDR_DQS[1]
D13_DDR_DM[0]
Y5
D13_DDR_A[10]
G7
VDD_9
CK
F3
D13_DDR_DQS[1]
D13_DDR_DQS[3]
D9
R9
NC_3
G3
R3
R1
VDDQ_1
RESET
D13_DDR_DQS[0]
T8
D13_DDR_A[9]
BA1
T2
D13_DDR_DQS[0]
D13_DDR_A[8]
B2
N9
VDD_7
VDD_8
BA0
R2
N1
VDD_6
WE
D13_DDR_RESET
D13_DDR_DQS[2]
W16
V18
L3
D13_DDR_WE
D13_DDR_DQS[2]
V14
W12
VDD_5
R8
D13_DDR_A[7]
E2
D13_DDR_DQ[27]
E8
D13_DDR_DQ[28]
F9
D13_DDR_DQ[29]
G1
D13_DDR_DQ[30]
G9
D13_DDR_DQ[31]
C8
C2
A7
A2
B8
A3
B1
VSSQ_1
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
D13_DDR_DQ[16]
D13_DDR_DQ[17]
D13_DDR_DQ[16-31]
D13_DDR_DQ[18]
W19
D13_DDR_DQ[19]
Y11
D13_DDR_DQ[20]
Y19
D13_DDR_DQ[21]
W11
D13_DDR_DQ[22]
V19
D13_DDR_DQ[23]
W18
D13_DDR_DQ[24]
W13
D13_DDR_DQ[25]
V17
D13_DDR_DQ[26]
V12
D13_DDR_DQ[27]
V16
D13_DDR_DQ[28]
Y13
D13_DDR_DQ[29]
W17
D13_DDR_DQ[30]
V13
D13_DDR_DQ[31]
DDR_DQ[31]
VDDC15_D13_DDR
VDDC15_D13_DDR
VDDC15_D13_DDR
VDDC15_D13_DDR
VDDC15_D13_DDR
D13_DDR_CKE
D13_DDR0_VREFCA
R12102
R12108
10K
10K
D13_DDR0_VREFDQ
D13_DDR1_VREFCA
D13_DDR1_VREFDQ
D13_DDR_RESET
D13_D1_CLK
R12101
100
D13_D0_CLK
R12103
100
D13_D1_CLK
0.1uF
DDR_DQ[5]
A13
P2
D13_DDR_A[6]
H1
VREFDQ
A4
C12103
DDR_DQ[4]
VDD_4
D13_DDR_A[5]
A3
R12112
DDR_DQ[3]
A12/BC
P8
A2
1K 1%
DDR_DQ[2]
VDD_3
N2
D13_DDR_A[4]
VREFCA
A1
1%
DDR_DQ[1]
K3
D13_DDR_CAS
D13_DDR_DQS[1]
W14
DDR_DM[3]
DDR_DQ[0]
A11
D13_DDR_A[3]
A0
R12113
DDR_DM[2]
VDD_2
D13_DDR_DQS[1]
Y8
DDR_DM[1]
J3
D13_DDR_RAS
D13_DDR_DQS[0]
W7
K1
D13_DDR_ODT
D13_DDR_DQS[0]
V5
DDR_DQS_N[3]
DDR_DM[0]
VDD_1
A10/AP
P3
M8
1K
DDR_DQS[3]
A9
P7
D13_DDR_A[2]
0.1uF
DDR_DQS_N[2]
A8
D13_DDR_A[1]
C12102
DDR_DQS[2]
1%
A7
L2
D13_DDR_RESET
R12100
240
W5
DDR_DQS_N[1]
K9
D13_DDR_CKE
D13_DDR_CAS
T6
K7
VDDC15_D13_DDR
ZQ
J7
D13_D0_CLK
R12109
240
L8
A6
BA2
D13_D0_CLK
D13_DDR_ODT
U6
M3
D13_DDR_BA[2]
D13_DDR_CKE
U5
N8
D13_DDR_BA[1]
1%
DDR_DQS[1]
A5
M2
D13_DDR_BA[0]
DDR_ZQ_CALIB
DDR_DQS_N[0]
T3
VREFDQ
A4
NC_5
D13_D1_CLK
W6
T17
N7
H1
A3
M7
V6
DDR_RST_N
D13_DDR_BA[1]
D13_DDR_A[13]
D13_D1_CLK
W15
U9
D13_DDR_BA[0]
D13_DDR_A[12]
D13_DDR_BA[2]
DDR_WE_N
DDR_DQS[0]
R2
A2
R12110
DDR_CAS_N
D13_DDR_A[7]
T12
T5
DDR_RAS_N
R8
R3
DDR_CKE
DDR_ODT
P2
D13_DDR_A[6]
VREFCA
A1
1K 1%
DDR_D_CK_N
D13_DDR_A[5]
A0
1%
DDR_D_CK
P8
T8
V15
DDR_U_CK_N
N2
D13_DDR_A[4]
D13_DDR_A[9]
DDR_BA[2]
DDR_U_CK
D13_DDR_A[3]
D13_DDR_A[8]
U7
DDR_BA[1]
P3
T14
DDR_A[15]
DDR_BA[0]
P7
D13_DDR_A[2]
N3
R12111
DDR_A[14]
T10
D13_DDR_A[1]
D13_DDR_A[0]
1K
DDR_A[13]
D13_DDR_A[8]
0.1uF
DDR_A[12]
D13_DDR_A[7]
T15
D13_DDR1_VREFDQ
M8
C12101
DDR_A[11]
T8
D13_DDR_A[0-13]
N3
R12106
DDR_A[10]
D13_DDR_A[6]
D13_DDR1_VREFCA
D13_DDR0_VREFDQ
D13_DDR_A[0]
1K 1%
DDR_A[9]
U15
D13_DDR_A[0-13]
1%
DDR_A[8]
D13_DDR_A[5]
R12107
DDR_A[7]
D13_DDR_A[4]
U8
IC12101
H5TQ2G63DFR-PBC
D13_DDR0_VREFCA
1K
DDR_A[6]
U16
IC12100
H5TQ2G63DFR-PBC
0.1uF
DDR_A[5]
D13_DDR_A[3]
C12100
DDR_A[4]
D13_DDR_A[2]
T7
R12104
DDR_A[3]
D13_DDR_A[1]
T9
1K 1%
DDR_A[2]
T13
1%
DDR_A[1]
R12105
DDR_A[0]
1K
IC_D13
T11
D13_DDR_A[0]
D13_D0_CLK
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
HEVC option sheet
+12V
IC12000
LG1132-D13
+1.1V_D13_VDD
+1.1V_D13_VDD
H9
H10
H11
L12201
H12
BLM18PG121SN1D
H13
J8
J13
M8
K13
C12202
10uF
16V
L13
M9
IC12201
TPS54327DDAR [EP]GND
R12205
10K
M10
VDDC11_D13_XTAL
M13
+1.5V_D13_DDR
OPT
ZD12201
2.5V
R12209
1K 1%
1K 1%
R12207
C12214 C12218
1uF
3300pF
10V
50V
0.1uF
P8
P9
P10
P11
P12
P13
P14
P15
P16
Switching freq: 700K
R2
P17
VDD25_D13
Vout=0.765*(1+R1/R2)= 1.113V
+1.1V_D13_VDD
VDD25_D13_XTAL
VDD25_D13_XTAL
VDDC11_D13_XTAL
L12200
BLM18PG121SN1D
C12260 0.1uF
+1.5V_D13_DDR
C12257 4.7uF
C12249 0.1uF
+1.5V_D13_DDR
VDD33_D13
VSS_57
DVDD11_3
VSS_58
DVDD11_4
VSS_59
DVDD11_5
VSS_60
DVDD11_6
VSS_61
DVDD11_7
VSS_62
DVDD11_8
VSS_63
DVDD11_9
VSS_64
DVDD11_10
VSS_65
DVDD11_11
VSS_66
DVDD11_12
VSS_67
DVDD11_13
VSS_68
DVDD11_14
VSS_69
DVDD11_15
VSS_70
DVDD11_16
VSS_71
DVDD11_XTAL
VSS_72
AVDD11_HDMI_1
VSS_73
AVDD11_HDMI_2
VSS_74
AVDD11_PLL
VSS_75
VSS_76
DVDD15_DDR_1
VSS_77
DVDD15_DDR_2
VSS_78
DVDD15_DDR_3
VSS_79
DVDD15_DDR_4
VSS_80
DVDD15_DDR_5
VSS_81
DVDD15_DDR_6
VSS_82
DVDD15_DDR_7
VSS_83
DVDD15_DDR_8
VSS_84
DVDD15_DDR_9
VSS_85
DVDD15_DDR_10
VSS_86
DVDD15_DDR_11
VSS_87
DVDD15_DDR_12
VSS_88
DVDD15_DDR_13
VSS_89
VSS_90
E12
G6
J15
VDD33_D13_XTAL
VREF_D13_M0
VREF_D13_M1
DVDD25_OTP
VSS_91
AVDD25_HDMI_1
VSS_92
AVDD25_HDMI_2
VSS_93
AVDD25_PLL
VSS_94
VSS_95
E10
E11
C12246 4.7uF
+12V
L6
U2
L12211
BLM18PG121SN1D
L12209
BLM18PG121SN1D
DVDD11_2
J6
K6
+2.5V_Normal
DVDD11_1
P5
P6
1%
R12210
0.1uF
C12232
22uF
10V
1%
C12229
22uF
10V
VDDC15_D13_DDR
C12259
33K
1%
5
T2
VREF_D13_M1
1K
R12204
3A
C12253
4
GND
L8
P7
R12208
SS
VDDC15_D13_DDR
VREF_D13_M0
1K
NR5040T2R2N
0.1uF
6
BLM18PG121SN1D
0.1uF
C12247
SW
L12208
0.1uF
C12244
3
L12205
2.2uH
VDDC15_D13_DDR
T1
K8
C12242
C12208
100pF
50V
16V
0.1uF
C12225
VBST
7
VDDC15_D13_DDR
C12241 22uF
VREG5
9
2
R12201
1% 15K
VIN
8
THERMAL
1
VFB
R1
M11
M12
EN
IC_D13 VSS_56
H8
+1.1V_D13_VDD
K15
L15
U1
DVDD33_1
VSS_96
DVDD33_2
VSS_97
DVDD33_3
VSS_98
DVDD33_4
VSS_99
DVDD33_5
VSS_100
DVDD33_6
VSS_101
DVDD33_7
VSS_102
DVDD33_XTAL
VSS_103
VSS_104
W1
W20
VREF0_DDR
VSS_105
VREF1_DDR
VSS_106
VSS_107
A2
C12201
10uF
16V
A3
IC12200
TPS54327DDAR [EP]GND
R12206
10K
VREG5
C12207
100pF
50V
A19
3
7
6
OPT
ZD12200
2.5V
9
2
8
VIN
16V
0.1uF
C12224
VBST
L12204
3.6uH
SW
B15
B18
B19
B20
C4
C5
C6
C7
C8
C9
SM-8040
SS
4
3A
5
C10
GND
C12227
22uF
10V
R12203
C12231
22uF
10V
C11
C12
C13
C12213 C12216
1uF
3300pF
10V
50V
22K
1%
Switching freq: 700K
B8
C12248 0.1uF
3.6K
1%
A15
C12245 4.7uF
18K
1%
VFB
1
THERMAL
R1
A8
VDD33_D13_XTAL
L12207
BLM18PG121SN1D
EN
R12200 R12202
+3.3V_NORMAL
C14
C15
C16
C17
R2
C18
D4
Vout=0.765*(1+R1/R2)=1.516V
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
+3.3V_NORMAL
+2.5V_Normal
+1.1V_D13_VDD
E4
E5
VDD33_D13
VDD25_D13
L12210
BLM18PG121SN1D
E7
E9
E8
C12252 0.1uF
C12250 10uF
C12243 10uF
C12240 0.1uF
C12239 0.1uF
C12238 10uF
C12237 10uF
C12205 0.1uF
C12204 0.1uF
C12203 10uF
C12200 10uF
L12206
BLM18PG121SN1D
C12251 0.1uF
E6
E13
E14
E15
E16
E17
E18
E19
E20
F3
VSS_1
VSS_108
VSS_2
VSS_109
VSS_3
VSS_110
VSS_4
VSS_111
VSS_5
VSS_112
VSS_6
VSS_113
VSS_7
VSS_114
VSS_8
VSS_115
VSS_9
VSS_116
VSS_10
VSS_117
VSS_11
VSS_118
VSS_12
VSS_119
VSS_13
VSS_120
VSS_14
VSS_121
VSS_15
VSS_122
VSS_16
VSS_123
VSS_17
VSS_124
VSS_18
VSS_125
VSS_19
VSS_126
VSS_20
VSS_127
VSS_21
VSS_128
VSS_22
VSS_129
VSS_23
VSS_130
VSS_24
VSS_131
VSS_25
VSS_132
VSS_26
VSS_133
VSS_27
VSS_134
VSS_28
VSS_135
VSS_29
VSS_136
VSS_30
VSS_137
VSS_31
VSS_138
VSS_32
VSS_139
VSS_33
VSS_140
VSS_34
VSS_141
VSS_35
VSS_142
VSS_36
VSS_143
VSS_37
VSS_144
VSS_38
VSS_145
VSS_39
VSS_146
VSS_40
VSS_147
VSS_41
VSS_148
VSS_42
VSS_149
VSS_43
VSS_150
VSS_44
VSS_151
VSS_45
VSS_152
VSS_46
VSS_153
VSS_47
VSS_154
VSS_48
VSS_155
VSS_49
VSS_156
VSS_50
VSS_157
VSS_51
VSS_158
VSS_52
VSS_159
VSS_53
VSS_160
VSS_54
VSS_161
VSS_55
VSS_162
F4
F17
F18
F19
F20
G3
G4
G7
G8
G9
G10
G11
G12
G13
G14
G15
G17
G18
H3
H4
H6
H7
H14
H15
H17
H18
J3
J4
J7
J9
J10
J11
J12
J14
J17
J18
K3
K4
K7
K9
K10
K11
K12
K14
K17
K18
L3
L4
L7
L9
L10
L11
L12
L14
L17
L18
M3
M4
M6
M7
M14
M15
M17
M18
N3
N4
N17
N18
N19
N20
P1
P2
P3
P4
P18
P19
P20
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
T3
T4
T18
T19
T20
U3
U4
U18
U19
U20
V1
V20
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
IC2500
LGE7410
RXA0N
RXA0P
[51P HS-LVDS input wafer][41P HS-LVDS input wafer]
RXA1N
RXA1P
RXA2N
RXA2P
RXACLKN
RXACLKP
P100
H13_41pin LVDS
+3.3V
FI-RE51S-HF-J-R1500
RXA3N
RXA3P
RXA4N
RXA4P
1
PA168_AB_Reset
C103
2
OPT_41P_WAFER
G
0.1uF
16V
P101
3
R100
0
RXB2P
RXBCLKP
2
RXB4N
4
R3007
5
0
URSA7_Reset
RXC0N
+3.3V
17
C102
RXA0P
0.1uF
16V
RXA1N
20
RXA2N
R104
33
33
36
13
RXC1P
14
RXC2N
17
18
RXC2P
RXCCLKP
RXC3N
RXC3P
RXC4N
RXC4P
RXD0N
RXD0P
RXD1N
RXD1P
RXCCLKN
RXCCLKP
RXD2N
RXD2P
RXDCLKN
RXDCLKP
19
RXD3N
20
RXA4P
RXC3N
21
RXC3P
22
RXC4N
23
RXB0N
RXC4P
RXD3P
RXD4N
RXD4P
AH9
AJ9
AJ11
AH10
AH11
AG10
AG11
AG12
AJ12
AH12
RXB0P
AL4
AK4
AL5
AK5
AL6
AM6
AK6
AM7
AL7
AK7
AL8
AL9
AM9
AK9
AM10
AL10
AK10
AL11
AK11
AL12
AM12
AK12
AL13
AK13
AL14
AK14
AL15
AM15
AK15
AM16
AL16
AK16
AL17
AL18
AL19
27
RXD0P
28
RXD1N
29
RXD1P
RXB2P
30
RXD2N
31
RXD2P
RXBCLKN
RXBCLKP
RA2N
A2P/VBY2N
RA2P
A2M/VBY2P
RACKN
ACKP/VBY3N
RACKP
ACKM/VBY3P
RA3N
A3P/VBY4N
RA3P
A3M/VBY4P
RA4N
A4P/VBY5N
RA4P
A4M/VBY5P
B0P/VBY6N
RB0N
B0M/VBY6P
RB0P
B1P/VBY7N
RB1N
B1M/VBY7P
RB1P
B2P
RB2N
B2M
RB2P
BCKP
RBCKN
BCKM
RBCKP
B3P
RB3N
B3M
RB3P
B4P
RB4N
B4M
RB4P
C0P
C0M
RC0N
C1P
RC0P
C1M
RC1N
C2P
RC1P
C2M
RC2N
CCKP
RC2P
CCKM
RCCKN
C3P
RCCKP
C3M
RC3N
C4P
RC3P
C4M
RC4N
D0P
RC4P
D0M
D1P
RD0N
D1M
RD0P
D2P
RD1N
D2M
RD1P
DCKP
RD2N
DCKM
RD2P
D3P
RDCKN
D3M
RDCKP
D4P
RD3N
D4M
AK19
AL20
AK20
AL21
AM21
AK21
39
RXB3P
34
RXDCLKN
RD4N
RXDCLKP
35
40
RXB4N
41
RXB4P
36
37
42
38
43
39
44
40
45
AK22
AL23
AK23
RXD3N
RXD3P
RXD4N
RXD4P
AL24
AM24
AK24
AM25
AL25
AK25
AL26
AK26
41
PANEL_CTL
46
AL27
AM27
L100
MLB-201209-0120P-N2
42
AK27
AM28
48
AL28
C100
10uF
25V
C101
10uF
25V
AK28
AL29
E0M/VBY8P
E1P/VBY9N
RE0P
E1M/VBY10P
RE1N
E2P/VBY10N
RE1P
E2M/VBY10P
RE2N
ECKP/VBY11N
RE2P
ECKM/VBY11P
RECKN
E3P/VBY12N
RECKP
E3M/VBY12P
RE3N
E4P/VBY13N
RE3P
E4M/VBY13P
RE4N
F0P/VBY14N
RE4P
F0M/VBY14P
F2P
RXM[0]
F2M
RXP[0]
FCKP
RXM[1]
FCPM
RXP[1]
F3P
RXM[2]
F3M
RXP[2]
F4P
RXM[3]
F4M
RXP[3]
G0P
RXM[4]
G0M
RXP[4]
G1P
RXM[5]
G1M
RXP[5]
G2P
RXM[6]
G2M
RXP[6]
GCKP
RXM[7]
GCKM
RXP[7]
G3P
RXM[8]
G3M
RXP[8]
G4P
RXM[9]
G4M
RXP[9]
H0P
H0M
51
H1P
AD28
52
AD29
AC27
AC28
AB27
AB28
AK3
AK1
AJ3
AJ2
AH3
AH2
AG3
AG1
AG2
AF3
AE3
AE2
AE1
AD3
AA5
Y4
AC2
AB3
Y5
Y6
AB2
AB1
W6
MTXA0P
MTXA0M
MTXA1P
MTXA1M
MTXA2P
MTXA2M
MTXACKP
MTXACKM
MTXA3P
MTXA3M
MTXA4P
MTXA4M
MTXB0P
MTXB0M
MTXB1P
MTXB1M
MTXB2P
MTXB2M
MTXBCKP
MTXBCKM
MTXB3P
MTXB3M
MTXB4P
MTXB4M
V6
AA3
AA1
W5
W4
AA2
Y3
V5
U4
Y2
W3
U5
U6
W2
W1
V3
V1
T5
T4
V2
U3
R5
P4
T1
E0P/VBY8N
RE0N
F1P/VBY15N
AL22
AL1
RD3P
AM22
33
RXB3N
50
A1M/VBY1P
32
38
49
RA1P
F1M/VBY15P
37
47
A1P/VBY1N
RD4P
AM19
RXB2N
RA1N
AK17
26
RXD0N
A0M/VBY0P
AM13
25
RXB1P
A0P/VBY0N
RA0P
AK8
AK18
RXB1N
AL2
RA0N
AM4
AM18
24
34
35
RXC1N
RXA3N
27
32
12
16
26
31
RXC0P
RXACLKP
RXA4N
30
RXC0N
11
15
24
29
9
RXC2P
SCL_M1_A
OPT
RXACLKN
RXA3P
28
RXC2N
RXCCLKN
Q100
2N7002A
RXA2P
23
25
8
10
21
22
RXC1N
RXA1P
18
19
RXC0P
7
RXC1P
S
16
6
RXA0N
D
15
RXB4P
FRC_DONE
G
14
RXB3P
PWM_BPL
11
13
RXB3N
3
9
12
RXBCLKN
1
FLASH_WP
8
10
RXB2N
Q101
2N7002A
R103
33
OPT
6
RXB1P
SDA_M1_A
S
D
5
RXB0P
RXB1N
FI-RE41S-HF-J-R1500
4
7
RXB0N
OPTION (LVDS 4CH)
AG9
AJ10
VX1R_HTPD_O/GPIO[12]
H1M
VX1R_HTPD_V/GPIO[13]
H2P
GPIO[14]
H2M
VX1R_LOCK_O/GPIO[15]
HCKP
VX1R_LOCK_V/GPIO[16]
HCKM
GPIO[17]
H3P
H3M
H4P
R3
R1
R2
P2
N3
N2
N1
M1
M2
L3
L2
K2
K1
J3
J1
G3
G2
G1
F3
F1
F2
E3
E2
D3
MTXE0P
MTXE0M
MTXE1P
MTXE1M
MTXE2P
MTXE2M
MTXECKP
MTXECKM
MTXE3P
MTXE3M
MTXE4P
MTXE4M
MTXF0P
MTXF0M
MTXF1P
MTXF1M
MTXF2P
MTXF2M
MTXFCKP
MTXFCKM
MTXF3P
MTXF3M
MTXF4P
MTXF4M
D2
G4
G5
H5
H6
G6
F4
D1
D4
C1
C2
B1
B2
A2
C3
C4
B4
C5
B5
A5
C6
A6
B6
H4M
A3
NC_5
AK29
AL30
AM30
AK30
NC_1
NC_6
NC_2
NC_7
NC_3
NC_8
NC_4
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
B3
T6
R6
AD2
AC3
U2
T3
P5
P6
H3
H2
C7
B7
C8
B8
NC_20
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EAX65309301
U_LVDS INPUT
2013.03.18
2
22
LGE Internal Use Only
Master
IC100
PA168-ES
R105
100
R111
100
R117
100
R123
100
R129
100
R135
100
1%
1%
1%
1%
1%
1%
[A]
AK27
MTXA0M
MTXA0P
AK28
MTXA1M
AJ28
MTXA1P
AJ30
MTXA2M
AJ29
MTXA2P
AH30
MTXA3M
AH29
MTXA3P
AG30
MTXA4M
AG29
MTXA4P
AG28
MTXACKM
MTXACKP
AJ27
AG27
R145
100
R146
100
R147
100
R148
100
R149
100
R150
100
IC100
PA168-ES
LVDSRXA0N
LVDSRXA0P
R172
100
R173
100
R174
100
R175
100
R176
100
1%
1%
1%
1%
1%
[F]
LVDSRXA1N
HSRXN
LVDSRXA1P
HSRXP
LVDSRXA2N
VSRXN
LVDSRXA2P
VSRXP
LVDSRXA3N
EVSRXN
LVDSRXA3P
EVSRXP
LVDSRXA4N
CLKRXN
LVDSRXA4P
CLKRXP
LVDSRXACLKN
REFCLKRXN
LVDSRXACLKP
REFCLKRXP
J29
L27
L26
H30
H29
M27
M26
K30
K29
AF30
MTXB0M
1%
1%
1%
1%
1%
1%
MTXB0P
AE30
MTXB1M
AE29
MTXB1P
AD30
MTXB2M
AD29
MTXB2P
AC30
MTXB3M
AC29
MTXB3P
AB30
MTXB4M
AB29
MTXB4P
AC28
MTXBCKM
MTXBCKP
AF29
AC27
R106
100
R112
100
R118
100
R124
100
R130
100
R136
100
1%
1%
1%
1%
1%
1%
LVDSRXB0N
LVDSRXB0P
LVDSRXB1N
LVDSRXB1P
LVDSRXB2N
LVDSRXB2P
MTXE0P
Y30
MTXE1M
Y29
MTXE1P
W30
MTXE2M
W29
MTXE2P
V30
MTXE3M
V29
MTXE3P
U30
MTXE4M
U29
MTXE4P
V28
MTXECKM
MTXECKP
V27
R151
100
R152
100
R153
100
R154
100
R155
100
R156
100
LVDSRXB3P
LVDSRXB4N
LVDSRXB4P
LVDSRXBCLKN
1%
1%
1%
1%
1%
1%
LVDSRXC0N
LVDSRXC0P
LVDSRXC1N
MTXF0P
T29
R30
MTXF1M
R29
MTXF1P
P30
MTXF2M
P29
MTXF2P
N30
MTXF3M
N29
MTXF3P
M30
MTXF4M
M29
MTXF4P
P28
MTXFCKM
P27
MTXFCKP
iMXHSP
H5
iMXVSN
E1
iMXVSP
E2
iMXEVSN
G4
iMXEVSP
G5
iMXCLKN
J5
iMXCLKP
J4
iMXREFCLKN
F1
iMXREFCLKP
F2
C115
0.1uF
AK6
TXDAP7_L
C116
0.1uF
AJ6
TXDAN6_L
C117
0.1uF
AK8
TXDAP6_L
C118
0.1uF
AJ8
TXDAN5_L
C119
0.1uF
AK10
TXDAP5_L
C110
0.1uF
AJ10
0.1uF
AK12
C111
TXDAP4_L
C112
0.1uF
AJ12
TXDAN3_L
C113
0.1uF
AK14
TXDAP3_L
C114
0.1uF
AJ14
TXDAN2_L
C105
0.1uF
AK16
TXDAP2_L
C106
0.1uF
AJ16
TXDAN1_L
C107
0.1uF
AK18
TXDAP1_L
C108
0.1uF
AJ18
TXDAN0_L
C109
0.1uF
AK20
TXDAP0_L
C104
0.1uF
AJ20
LVDSRXC1P
LVDSRXC2N
LOCKAn
R143
LVDSRXC2P
HTPDAn
R144
100
LVDSTXA0P
HSTXN
LVDSTXA1N
HSTXP
LVDSTXA1P
VSTXN
LVDSTXA2N
VSTXP
LVDSTXA2P
EVSTXN
LVDSTXA3N
EVSTXP
LVDSTXA3P
CLKTXN
LVDSTXA4N
CLKTXP
LVDSTXA4P
REFCLKTXN
LVDSTXACLKN
REFCLKTXP
LVDSTXACLKP
TXD0N
LVDSTXB0N
TXD0P
LVDSTXB0P
TXD1N
LVDSTXB1N
TXD1P
LVDSTXB1P
TXD2N
LVDSTXB2N
TXD2P
LVDSTXB2P
TXD3N
LVDSTXB3N
TXD3P
LVDSTXB3P
TXD4N
LVDSTXB4N
TXD4P
LVDSTXB4P
TXD5N
LVDSTXBCLKN
TXD5P
LVDSTXBCLKP
TXD6N
LVDSRXC3N
LVDSRXC3P
LVDSTXC0N
TXD7N
LVDSTXC0P
TXD7P
LVDSTXC1N
LVDSTXC1P
LOCKN
LVDSTXC2N
HTPDN
LVDSTXC2P
LVDSTXC3N
LVDSTXC3P
R141
10K
LVDSRXC4N
LVDSTXC4N
HTPDn_pulldown
LVDSRXC4P
LVDSTXC4P
LVDSRXCCLKN
LVDSTXCCLKN
LVDSRXCCLKP
LVDSTXCCLKP
U5
R142
LVDSRXD0N
LVDSRXD0P
1%
AF2
AE1
AE2
AD1
AD2
AC1
AC2
AD3
AD4
AB2
AA1
AA2
Y1
Y2
W1
W2
V1
V2
W3
W4
U2
T1
T2
R1
R2
P1
P2
N1
N2
R3
R4
M1
LVDSTXRPI
12K
AF1
U1
TXD6P
AF22
AF23
AG2
AB1
100
T30
MTXF0M
H4
TXDAN4_L
LVDSRXB3N
LVDSRXBCLKP
AA29
iMXHSN
TXDAN7_L
AA30
MTXE0M
AG1
LVDSTXA0N
J30
LVDSTXD0N
LVDSTXD0P
LVDSRXD1N
LVDSTXD1N
LVDSRXD1P
LVDSTXD1P
LVDSRXD2N
LVDSTXD2N
LVDSRXD2P
LVDSTXD2P
LVDSRXD3N
LVDSTXD3N
LVDSRXD3P
LVDSTXD3P
LVDSRXD4N
LVDSTXD4N
LVDSRXD4P
LVDSTXD4P
LVDSRXDCLKN
LVDSTXDCLKN
LVDSRXDCLKP
LVDSTXDCLKP
M2
L1
L2
K1
K2
J1
J2
H1
H2
L3
L4
MXAON0
MXAOP0
MXAON1
MXAOP1
MXAON2
MXAOP2
MXAON3
MXAOP3
MXAON4
MXAOP4
MXAONCLK
MXAOPCLK
MXAEN0
MXAEP0
MXAEN1
MXAEP1
MXAEN2
MXAEP2
MXAEN3
MXAEP3
MXAEN4
MXAEP4
MXAENCLK
MXAEPCLK
MXBON0
MXBOP0
MXBON1
MXBOP1
MXBON2
MXBOP2
MXBON3
MXBOP3
MXBON4
MXBOP4
MXBONCLK
MXBOPCLK
MXBEN0
MXBEP0
MXBEN1
MXBEP1
MXBEN2
MXBEP2
MXBEN3
MXBEP3
MXBEN4
MXBEP4
MXBENCLK
MXBEPCLK
Slave
IC200
PA168-ES
MXAON0
R107
100
R113
100
R119
100
R125
100
R131
100
R137
100
1%
1%
1%
1%
1%
1%
AK27
MXAOP0
AK28
MXAON1
AJ28
MXAOP1
AJ30
MXAON2
AJ29
MXAOP2
AH30
MXAON3
AH29
MXAOP3
AG30
MXAON4
AG29
MXAOP4
AG28
MXAONCLK
MXAOPCLK
MXAEN0
AG27
R108
100
R114
100
R120
100
R126
100
R132
100
R138
100
1%
1%
1%
1%
1%
1%
AE29
MXAEP1
AD30
MXAEN2
AD29
MXAEP2
AC30
MXAEN3
AC29
MXAEP3
AB30
MXAEN4
AB29
MXAEP4
AC28
MXAENCLK
AC27
R109
100
R115
100
R121
100
R127
100
R133
100
1%
1%
1%
1%
1%
1%
AA29
Y30
Y29
MXBOP1
W30
MXBON2
W29
MXBOP2
V30
MXBON3
V29
MXBOP3
U30
MXBON4
U29
MXBOP4
V28
MXBONCLK
V27
R110
100
R116
100
R158
100
R159
100
R160
100
R161
100
1%
1%
1%
1%
LVDSRXA1N
HSRXN
LVDSRXA1P
HSRXP
1%
LVDSRXA2N
VSRXN
LVDSRXA2P
VSRXP
LVDSRXA3N
EVSRXN
LVDSRXA3P
EVSRXP
LVDSRXA4N
CLKRXN
LVDSRXA4P
CLKRXP
LVDSRXACLKN
REFCLKRXN
LVDSRXACLKP
REFCLKRXP
R162
J29
R163
L27
R164
L26
R165
H30
R166
H29
R167
M27
R168
M26
R169
K30
K29
R170
R171
0
0
0
0
0
0
0
0
0
0
iMXHSN
iMXHSP
iMXVSN
iMXVSP
iMXEVSN
iMXEVSP
iMXCLKN
iMXCLKP
iMXREFCLKN
iMXREFCLKP
LVDSRXB0N
LVDSRXB0P
LVDSRXB1N
LVDSRXB1P
LVDSRXB2N
LVDSRXB2P
LVDSRXB3N
LVDSRXB3P
LVDSRXB4N
LVDSRXB4P
LVDSRXBCLKN
R122
100
R128
100
R134
100
LVDSRXC0N
LVDSRXC0P
LVDSRXC1N
LVDSRXC1P
LVDSRXC2N
LVDSRXC2P
LVDSRXC3N
LVDSRXC3P
LVDSRXC4N
LVDSRXC4P
LVDSRXCCLKN
LVDSRXCCLKP
R140
100
T30
1%
1%
MXBEP0
MXBEN1
MXBEP1
MXBEN2
MXBEP2
MXBEN3
MXBEP3
MXBEN4
MXBEP4
MXBENCLK
MXBEPCLK
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
R157
100
J30
AA30
MXBON1
MXBEN0
LVDSRXA0P
LVDSRXBCLKP
R139
100
MXBOP0
MXBOPCLK
AF29
AE30
MXAEN1
MXBON0
[A]
LVDSRXA0N
AF30
MXAEP0
MXAEPCLK
AJ27
1%
1%
1%
1%
T29
R30
R29
P30
P29
N30
N29
M30
M29
P28
P27
LVDSRXD0N
LVDSRXD0P
LVDSRXD1N
LVDSRXD1P
LVDSRXD2N
LVDSRXD2P
LVDSRXD3N
LVDSRXD3P
LVDSRXD4N
LVDSRXD4P
LVDSRXDCLKN
LVDSRXDCLKP
EAX65309301
P_LVDS INPUT
2013.03.18
3
22
LGE Internal Use Only
[51P Vx1 output wafer]
AC2
11
TXDAP4_L
AD3
12
TXDAN4_L
AD4
13
LVDSTXACLKP
14
TXDBP7_L
A1[GN]
R200
22
SAM2333
LD200
TXDBN6_L
R201
220
R202
10K
Q200
C214
C215
0.1uF
AJ6
0.1uF
AK8
TXDBP6_L
C210
0.1uF
AJ8
TXDBN5_L
C211
0.1uF
AK10
TXDBP5_L
C212
0.1uF
AJ10
TXDBN4_L
C207
0.1uF
AK12
TXDBP4_L
C208
0.1uF
AJ12
TXDBN3_L
C209
0.1uF
AK14
TXDBP3_L
C203
0.1uF
AJ14
TXDBN2_L
C204
0.1uF
AK16
TXDBP2_L
C205
0.1uF
AJ16
TXDBN1_L
C206
0.1uF
AK18
TXDBP1_L
C200
0.1uF
AJ18
C
A2[RD]
+3.3V
0.1uF
TXDBN0_L
C201
0.1uF
AK20
TXDBP0_L
C202
0.1uF
AJ20
TXD0N
LVDSTXB0N
TXD0P
LVDSTXB0P
TXD1N
LVDSTXB1N
TXD1P
LVDSTXB1P
TXD2N
LVDSTXB2N
TXD2P
LVDSTXB2P
TXD3N
LVDSTXB3N
TXD3P
LVDSTXB3P
TXD4N
LVDSTXB4N
TXD4P
LVDSTXB4P
TXD5N
LVDSTXBCLKN
TXD5P
B
C
R205
LOCKBn
100
AF23
R206
HTPDBn
100
LVDSTXC0N
TXD7N
LVDSTXC0P
TXD7P
LVDSTXC1N
LVDSTXC1P
LOCKN
LVDSTXC2N
HTPDN
LVDSTXC2P
LVDSTXC3N
LVDSTXC3P
HTPDn_pulldown
TXDAN3_L
16
AA1
17
TXDAP2_L
18
TXDAN2_L
AA2
Y1
LVDSTXC4N
LVDSTXC4P
LVDSTXCCLKN
Y2
W1
21
TXDAN1_L
W2
22
23
V2
24
W3
25
W4
26
29
T1
30
T2
32
R2
33
P1
34
P2
36
N2
37
R3
38
R4
39
U5
1%
LVDSTXRPI
LVDSTXD0N
LVDSTXD0P
LVDSTXD1N
LVDSTXD1P
LVDSTXD2N
LVDSTXD2P
LVDSTXD3N
LVDSTXD3P
LVDSTXD4N
LVDSTXD4P
LVDSTXDCLKN
LVDSTXDCLKP
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
M1
41
M2
42
L1
43
L2
44
K1
45
K2
46
J1
47
J2
48
H1
49
H2
50
R1504
1.5K
LOCKAn
17
TXDAN0_L
LOCKn_IN
HTPDn_IN
R219
L_DIM_EN
TXDBP7_L
19
TXDBN7_L
R207
10K
OPT
21
TXDBP6_L
22
TXDBN6_L
23
33 OPT
L/D_EN(Pin30)
- T-Con L/D Function
HIGH : Enable
LOW or NC : Disable
BIT_SEL(Pin31)
- Bit Selection
HIGH or NC : 10Bit
LOW : 8Bit
0
R230
OPT
SCL_M1_A
0
Q202
2N7002A
R217
+3.3V
R208
10K
18
20
0
HTPDn_pullup
24
TXDBP5_L
25
TXDBN5_L
26
27
TXDBP4_L
28
TXDBN4_L
29
30
TXDBP3_L
31
TXDBN3_L
32
R218
3D_EN
+3.3V
R214
10K
SDA_M1_A
0
Input Data Format
- Data Format 0(Pin36) = High
Data Format 1(Pin37) = Low
: Mode 3
(Divide screen into 4 area)
R216
33 OPT
R212
10K
TXDBP2_L
34
TXDBN2_L
36
TXDBP1_L
37
TXDBN1_L
38
R213
10K
OPT
PANEL_VCC
33
35
Q201
2N7002A
+3.3V
40
12K
16
R220
R221
35
N1
15
0
OPT
TXDAP0_L
31
R1
14
HTPDBn
HTPDn_up
28
U2
13
R223
0
HTPDBn
TXDAP1_L
V1
12
HTPDn_pullup
R224
0
HTPDn_IN
20
LVDSTXCCLKP
R204
10K
19
U1
TXD6P
R203
10K
15
27
TXD6N
AF22
HTPDn_up
AB2
LVDSTXBCLKP
E
MMBT3906(NXP)
TXDAP3_L
11
R222
HTPDn_pullup
G
C213
AB1
9
10
S
TXDBN7_L
AK6
C219
10uF
25V
TCON_I2C_EN
10
8
C218
10uF
25V
D
REFCLKTXP
LVDSTXA4P
LVDSTXACLKN
AC1
6
7
+3.3V
D
REFCLKTXN
TXDAN5_L
5
R225
1
ADJ/GND
S
CLKTXP
9
OUT
TCON_I2C_EN
LVDSTXA4N
AD2
2
1
+1.8V
TXDAP5_L
3
HTPDAn
CLKTXN
8
D
LVDSTXA3P
AD1
S
EVSTXP
7
AO3438
Q1404
LVDSTXA3N
AE2
R211
1.5K
EVSTXN
TXDAN6_L
IN
G
F2
LVDSTXA2P
6
3
4
D
F1
VSTXP
AE1
LOCKn_IN
HTPDn_pullup
J4
LVDSTXA2N
TXDAP6_L
LOCKBn
G
J5
VSTXN
5
2
AZ1117BH-1.8TRE1
R210
0
4
AF2
+1.8V
IC2000
S
G5
LVDSTXA1P
TXDAN7_L
HTPDn_pullup
G4
HSTXP
AF1
3
1
+3.3V
AO3438
Q203
E2
LVDSTXA1N
TXDAP7_L
R209
4.7K
E1
HSTXN
AG2
2
HTPDn_pullup
LVDSTXA0P
FI-RE41S-HF-J-R1500
G
1
AG1
LVDSTXA0N
H5
+1.8V
R1505
4.7K
[F]
H4
P201
P200
FI-RE51S-HF-J-R1500
HTPDAn
IC200
PA168-ES
[41P Vx1 output wafer]
R215
10K
OPT
39
TXDBP0_L
40
TXDBN0_L
41
42
L200
MLB-201209-0120P-N2
L3
C216
10uF
25V
C217
10uF
25V
51
L4
52
EAX65309301
P_Vx1 OUTPUT
2013.03.18
4
22
LGE Internal Use Only
MVREFDQ_A
IC100
PA168-ES
IC300
H5TQ1G63EFR-PBC
MVREFCA_A
C27
E28
C14
MDM1_0
MD15_0
MDM0_1
MD11_1
MDM2
MD14_2
MDM3
MD10_3
MD13_4
B16
MMDQSAN0
MMDQSAP0
MMDQSAN1
MMDQSAP1
MMDQSAN2
MMDQSAP2
MMDQSAN3
MMDQSAP3
A16
B12
A12
B27
A27
E29
E30
MDQS1N_0
MD9_5
MDQS1P_0
MD12_6
MDQS0N_1
MD8_7
MDQS0P_1
MD3_8
MDQS2N
MD5_9
MDQS2P
MD0_10
MDQS3N
MD6_11
MDQS3P
MD2_12
MD7_13
D18
MMCKAN0
MMCKAP0
MMCKAN1
MMCKAP1
E19
A23
B23
MCK0N
MD1_14
MCK0P
MD4_15
MCK1N
MD19_16
MCK1P
MD23_17
MD18
D20
MMCKEA
MMODTA
MMRASA
MMCSA
MMCASA
MMWEA
A19
B19
E20
A20
C20
MCKE
MD22_19
MODT
MD17_20
MRAS
MD21
MCS
MD16_22
MCAS
MD20_23
MWE
MD31_24
MD28_25
A22
MMAA0
MMAA1
MMAA2
MMAA3
MMAA4
MMAA5
MMAA6
MMAA7
MMAA8
MMAA9
MMAA10
MMAA11
MMAA12
MMBKA0
MMBKA1
MMBKA2
E23
E22
C21
D23
C22
F23
B22
C24
C23
C19
C25
F25
A21
E24
E21
MA0
MD29_26
MA1
MD25_27
MA2
MD27_28
MA3
MD24_29
MA4
MD30
MA5
MD26_31
D15
B17
C15
C17
A15
C18
A11
A13
A10
B14
C12
A14
B11
D13
C26
D28
A26
C28
B25
B28
A25
A28
B29
C30
B30
F29
D30
F30
C29
F28
N3
MMAA0
MMAA1
MMAA2
MMAA3
MMAA4
MMAA5
MMAA6
MMAA7
MMAA8
MMAA9
MMAA10
MMAA11
MMAA12
MMDA0
MMDA1
MMDA2
MMDA3
MMDA4
MMDA5
MMDA6
MMDA7
MMDA8
MMDA9
MMDA10
MMDA11
MMDA12
MMDA13
MMDA14
MMDA15
MMDA16
MMDA17
MMDA18
MMDA19
MMDA20
MMDA21
MMDA22
MMDA23
MMDA24
MMDA25
MMDA26
MMDA27
MMDA28
MMDA29
MMDA30
MMDA31
A17
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
MA7
D22
22
N8
M3
120
5%
MMCKAP0
MMCKAN0
MMCKEA
K9
K1
J3
K3
L3
10K
R370
MA9
MA10
MREXT0
MA11
MREXT1
MA12
120
MVREF_1
MBANK1
MVREF_2
E16
R355
G25
R356
1% 240
MVREFDQ_A
R309
120
120
5%
120
5%
R341
5%
120
5%
MMAA3
R310
MMAA4
120
R307
5%
120
R339
5%
120
5%
120
5%
R342
MMAA5
R308
MMAA6
R304
MMAA7
120
R305
5%
120
R337
5%
120
5%
120
5%
120
MMAA8
MMAA9
MMAA11
H25
C302
120
MMRASA
MMCASA
C303
B7
D3
R365
R353
120
5%
R354
120
5%
R366
5%
120
5%
R363
R351
120
120
5%
120
R352
120
R349
5%
120
R361
5%
120
5%
120
5%
MMODTA
R350
VDD_5
VDD_6
MMBKA0
R346
MMBKA1
120
R347
5%
120
R359
5%
120
5%
120
5%
MMBKA2
5%
5%
VDD_8
BA0
R348
120
120
F2
F8
H3
H8
G2
H7
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
NC_4
DQSL
C8
C2
A7
A2
B8
A3
R360
5%
120
5%
AVDD_DDR_PA1
R331
1K
1%
R333
L7
R7
N7
T3
N8
M3
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
R375
120
C9
D2
5%
K9
F1
H2
H9
K1
J3
K3
L3
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
A8
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
NC_7
VDD_5
VDD_6
VDD_7
VDD_8
BA0
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
NC_2
F3
B7
D3
M1
T1
T9
F7
F2
F8
H3
H8
G2
H7
E2
E8
F9
G1
G9
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
R9
A8
C1
C9
D2
E9
F1
H2
H9
J9
L1
L9
T7
C3
C8
C2
A7
A2
B8
A3
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQL6
B1
VSSQ_1
D7
MMDA24
MMDA25
MMDA26
MMDA27
MMDA28
MMDA29
MMDA30
MMDA31
D8
VSS_1
DQSU
DQL7
B9
D1
R1
A9
DQSU
E3
MMDA16
MMDA17
MMDA18
MMDA19
MMDA20
MMDA21
MMDA22
MMDA23
P9
N9
NC_6
E7
MMDMA2
MMDMA3
P1
DQSL
C7
G8
M9
N1
DQSL
MMDQSAP3
MMDQSAN3
J8
K8
J1
NC_1
NC_4
J2
K2
A1
VDDQ_1
CK
T7
E1
G7
AVDD_DDR_PA1
NC_3
B3
AVDD_DDR_PA1
D9
BA1
RESET
G3
240
VDD_9
L9
MMDQSAP2
MMDQSAN2
1%
B2
A9
T2
MMRESETA
L1
R376
ZQ
WE
J9
0.1uF
A7
L2
MMCSA
MMODTA
MMRASA
MMCASA
MMWEA
B1
DQU0
L8
A6
J7
K7
E9
DQL6
VSSQ_1
A5
BA2
MMCKAP1
MMCKAN1
MMCKEA
C1
C343
VREFDQ
A4
M2
A9
VSS_1
DQSU
H1
A3
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
AVDD_DDR_PA1
L300
MVREFCA_A
5%
5%
MMBKA0
MMBKA1
MMBKA2
A8
NC_6
DQSU
D7
C3
R3
R9
+1.5V_P_DDR
5%
120
NC_2
T8
A2
NC_5
J1
NC_1
R2
0.1uF
MVREFDQ_A
M7
A1
VDDQ_2
R8
R1
AVDD_DDR_PA1
VDDQ_1
P2
N9
BA1
CK
P8
N1
VDD_9
DQL7
5%
120
R332
K8
N2
C344
VREFCA
A1
R358
120
R335
120
VDD_7
K2
P3
M8
A0
R362
5%
5%
NC_7
G7
P7
R364
120
120
VDD_4
D9
N3
MMAA0
MMAA1
MMAA2
MMAA3
MMAA4
MMAA5
MMAA6
MMAA7
MMAA8
MMAA9
MMAA10
MMAA11
MMAA12
5%
MMCSA
120
F7
R334
R301
A12/BC
E3
MMDA8
MMDA9
MMDA10
MMDA11
MMDA12
MMDA13
MMDA14
MMDA15
5%
5%
VDD_3
E7
0.1uF
120
R303
R300
A11
C7
MMDMA0
MMDMA1
MMWEA
5%
R338
5%
R302
120
MMAA12
120
R336
R306
120
MMAA10
R340
5%
VDD_2
DQSL
MMDQSAP1
MMDQSAN1
1%
MMCKEA
AVDD_DDR_PA1
240
AVDD_DDR_PA1
R344
5%
VDD_1
A10/AP
T2
G3
1%
B2
A9
E15
MBANK0
R343
5%
A8
F3
MMDQSAP0
MMDQSAN0
240
R372
A7
RESET
C300
0.1uF
16V
MMAA2
120
L8
ZQ
WE
MMRESETA
MMRESETA
MRESET
AVDD_DDR_PA1
R312
A6
L2
MMCSA
MMODTA
MMRASA
MMCASA
MMWEA
AVDD_DDR_PA1
H1
A5
J7
K7
R374
1K
1%
0.1uF
VREFDQ
BA2
R371
C322
16V
0.1uF
C328
A4
M2
MMDA0
MMDA1
MMDA2
MMDA3
MMDA4
MMDA5
MMDA6
MMDA7
MMAA1
A3
NC_5
R357
MBANK2
R311
A2
M7
MMBKA0
MMBKA1
MMBKA2
VREFCA
A1
NC_3
0.1uF
MMAA0
M8
A0
MA6
MA8
MVREFCA_A
1%
C16
C13
IC400
H5TQ1G63EFR-PBC
R373
1K
[B]
MMDMA0
MMDMA1
MMDMA2
MMDMA3
C325
0.1uF
16V
AVDD_DDR_PA1
R345
1K
1%
16V
0.1uF
C301
C304
0.1uF
16V
C305
0.1uF
16V
C306
0.1uF
16V
C307
0.1uF
16V
C308
0.1uF
16V
C309
0.1uF
16V
C310
1uF
10V
C311
10uF
10V
OPT
C312
10uF
10V
AVDD_DDR_PA1
5%
C313
0.1uF
16V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C314
0.1uF
16V
C315
0.1uF
16V
C316
0.1uF
16V
C317
0.1uF
16V
C318
0.1uF
16V
C319
1uF
10V
EAX65309301
P_DDR_A
C320
10uF
10V
OPT
C321
10uF
10V
2013.03.18
5
22
LGE Internal Use Only
C427
0.1uF
16V
AVDD_DDR_PA2
MVREFDQ_B
IC200
PA168-ES
IC500
H5TQ1G63EFR-PBC
R473
1K
C27
E28
MD15_0
MDM0_1
MD11_1
MDM2
MD14_2
MDM3
MD10_3
MD13_4
B16
MMDQSBN0
MMDQSBP0
MMDQSBN1
MMDQSBP1
MMDQSBN2
MMDQSBP2
MMDQSBN3
MMDQSBP3
A16
B12
A12
B27
A27
E29
E30
MDQS1N_0
MD9_5
MDQS1P_0
MD12_6
MDQS0N_1
MD8_7
MDQS0P_1
MD3_8
MDQS2N
MD5_9
MDQS2P
MD0_10
MDQS3N
MD6_11
MDQS3P
MD2_12
MD7_13
D18
MMCKBN0
MMCKBP0
MMCKBN1
MMCKBP1
E19
A23
B23
MCK0N
MD1_14
MCK0P
MD4_15
MCK1N
MD19_16
MCK1P
MD23_17
MD18
D20
MMCKEB
MMODTB
MMRASB
MMCSB
MMCASB
MMWEB
A19
B19
E20
A20
C20
MCKE
MD22_19
MODT
MD17_20
MRAS
MD21
MCS
MD16_22
MCAS
MD20_23
MWE
MD31_24
MD28_25
A22
MMAB0
MMAB1
MMAB2
MMAB3
MMAB4
MMAB5
MMAB6
MMAB7
MMAB8
MMAB9
MMAB10
MMAB11
MMAB12
MMBKB0
MMBKB1
MMBKB2
E23
E22
C21
D23
C22
F23
B22
C24
C23
C19
C25
F25
A21
E24
E21
MA0
MD29_26
MA1
MD25_27
MA2
MD27_28
MA3
MD24_29
MA4
MD30
MA5
MD26_31
D15
B17
C15
C17
A15
C18
A11
A13
A10
B14
C12
A14
B11
D13
C26
D28
A26
C28
B25
B28
A25
A28
B29
C30
B30
F29
D30
F30
C29
F28
N3
MMAB0
MMAB1
MMAB2
MMAB3
MMAB4
MMAB5
MMAB6
MMAB7
MMAB8
MMAB9
MMAB10
MMAB11
MMAB12
MMDB0
MMDB1
MMDB2
MMDB3
MMDB4
MMDB5
MMDB6
MMDB7
MMDB8
MMDB9
MMDB10
MMDB11
MMDB12
MMDB13
MMDB14
MMDB15
MMDB16
MMDB17
MMDB18
MMDB19
MMDB20
MMDB21
MMDB22
MMDB23
MMDB24
MMDB25
MMDB26
MMDB27
MMDB28
MMDB29
MMDB30
MMDB31
A17
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M3
120
5%
K9
22
D22
MA8
K1
J3
K3
L3
10K
R471
MMRESETB
MA9
MA10
MREXT0
MA11
MREXT1
MA12
MMRESETB
E16
R455
240
G25
R456
1% 240
120
MVREF_1
MBANK1
MVREF_2
120
5%
5%
5%
MMAB3
R408
MMAB4
120
R409
5%
120
R441
5%
120
5%
120
5%
R440
MMAB5
R406
MMAB6
R407
MMAB7
120
R404
5%
MMAB8
120
5%
R405
MMAB9
R402
120
120
MMAB10
MMAB11
120
1%
H25
120
R436
5%
120
5%
R437
5%
120
120
120
C403
NC_7
VDD_5
VDD_6
VDD_7
VDD_8
5%
120
5%
5%
120
R450
MMCSB
120
R451
5%
120
R463
5%
120
5%
120
5%
B7
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
NC_2
120
5%
120
5%
DQSL
D3
F2
F8
H3
H8
G2
H7
DQSU
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
C8
C2
A7
A2
B8
A3
R2
T8
R3
L7
R7
N7
T3
R9
MMBKB0
MMBKB1
MMBKB2
AVDD_DDR_PA2
A8
M3
120
5%
MMCKBP1
MMCKBN1
MMCKEB
C1
C9
D2
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
H1
A3
K9
A5
L8
A6
H2
H9
K1
J3
K3
L3
A8
L1
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
NC_7
VDD_5
VDD_6
VDD_7
VDD_8
BA0
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
NC_2
F3
B7
D3
M1
T1
T9
F7
F2
F8
H3
H8
G2
H7
E2
E8
F9
G1
G9
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
R9
A8
C1
C9
D2
E9
F1
H2
H9
J9
L1
L9
T7
C3
C8
C2
A7
A2
B8
A3
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQL6
B1
VSSQ_1
D7
MMDB24
MMDB25
MMDB26
MMDB27
MMDB28
MMDB29
MMDB30
MMDB31
D8
VSS_1
DQSU
DQL7
B9
D1
R1
A9
DQSU
E3
MMDB16
MMDB17
MMDB18
MMDB19
MMDB20
MMDB21
MMDB22
MMDB23
P9
N9
NC_6
E7
MMDMB2
MMDMB3
P1
N1
DQSL
G8
M9
DQSL
C7
MMDQSBP3
MMDQSBN3
J8
K8
J1
NC_1
T7
J2
K2
A1
VDDQ_1
CK
NC_4
E1
G7
AVDD_DDR_PA2
L9
B3
AVDD_DDR_PA2
D9
BA1
NC_3
G3
240
VDD_9
RESET
MMDQSBP2
MMDQSBN2
1%
B2
A9
T2
MMRESETB
R476
ZQ
WE
J9
0.1uF
A7
L2
MMCSB
MMODTB
MMRASB
MMCASB
MMWEB
F1
C447
VREFDQ
A4
J7
K7
E9
B1
VSSQ_1
A2
BA2
R475
0.1uF
MVREFDQ_B
M2
N8
C448
VREFCA
A1
NC_5
DQL6
D7
C3
R8
A9
VSS_1
DQL7
MMDB8
MMDB9
MMDB10
MMDB11
MMDB12
MMDB13
MMDB14
MMDB15
P2
R1
NC_6
DQSU
E3
F7
P8
M8
A0
M7
J1
NC_1
N2
N9
A1
VDDQ_1
P3
N1
VDD_9
CK
E7
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
120
5%
R462
MMODTB
R448
R449
MMBKB1
120
R446
5%
MMBKB2
120
5%
R447
+1.5V_P_DDR
R460
5%
120
5%
R461
120
R458
5%
120
5%
AVDD_DDR_PA2
R459
5%
120
5%
AVDD_DDR_PA2
L400
MVREFCA_B
R431
1K
1%
5%
K8
P7
R465
5%
MMBKB0
120
K2
N3
MMAB0
MMAB1
MMAB2
MMAB3
MMAB4
MMAB5
MMAB6
MMAB7
MMAB8
MMAB9
MMAB10
MMAB11
MMAB12
5%
R453
120
G7
R464
MMWEB
120
D9
BA1
0.1uF
MMCASB
5%
120
R435
R400
VDD_4
C7
MMDMB0
MMDMB1
R466
R452
R434
5%
16V
0.1uF
C401
C404
0.1uF
16V
C405
0.1uF
16V
C406
0.1uF
16V
C407
0.1uF
16V
C408
0.1uF
16V
C409
0.1uF
16V
C410
1uF
10V
C411
10uF
10V
OPT
C412
10uF
10V
C414
0.1uF
16V
C415
0.1uF
16V
C416
0.1uF
16V
C417
0.1uF
16V
C418
0.1uF
16V
C419
1uF
10V
C420
10uF
10V
OPT
C421
10uF
10V
AVDD_DDR_PA2
R432
5%
120
5%
R433
R401
120
MMRASB
R454
5%
R439
120
R403
120
MMAB12
R438
5%
A12/BC
BA0
AVDD_DDR_PA2
DQSL
MMDQSBP1
MMDQSBN1
C402
MMCKEB
R443
5%
VDD_3
T2
G3
1%
R411
120
A11
F3
MMDQSBP0
MMDQSBN0
MVREFDQ_B
E15
MBANK0
R442
5%
VDD_2
RESET
1K
R445
120
VDD_1
A10/AP
WE
R457
MRESET
AVDD_DDR_PA2
120
A9
L2
MMCSB
MMODTB
MMRASB
MMCASB
MMWEB
240
1%
B2
NC_4
R444
5%
A8
J7
K7
R472
A7
C400
0.1uF
16V
MMAB2
120
L8
ZQ
MA7
AVDD_DDR_PA2
R410
A6
BA2
R470
MMCKBP0
MMCKBN0
MMCKEB
AVDD_DDR_PA2
H1
VREFDQ
A5
M2
N8
0.1uF
A4
NC_5
MMDB0
MMDB1
MMDB2
MMDB3
MMDB4
MMDB5
MMDB6
MMDB7
MMAB1
A3
NC_3
MBANK2
R412
A2
M7
MMBKB0
MMBKB1
MMBKB2
C426
VREFCA
16V
0.1uF
C430
A1
MA6
0.1uF
MMAB0
M8
A0
1K
R474
C14
MDM1_0
1%
POWER Conn
C16
C13
MVREFCA_B
1%
[B]
MMDMB0
MMDMB1
MMDMB2
MMDMB3
IC600
H5TQ1G63EFR-PBC
MVREFCA_B
5%
120
5%
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C413
0.1uF
16V
EAX65309301
P_DDR_B
2013.03.18
6
22
LGE Internal Use Only
A4
100
C5
C500
3.3pF
50V
C502
3.3pF
50V
C507
3.3pF
50V
C508
3.3pF
50V
R512
R513
SLVRST2
TWOWSDA1
TWOWSCL2
TDI
TWOWSDA2
TMS
TCK
AJ24
AK24
CLOSE TO PA168_A
SLVRST1
TWOWSCL1
INTL
TRSTN
INTH
TDO
R508
SPICS0
SPITXD
AE23
100
C506
A8
SR Stable
R655
1K
21:9
R653
1K
SR CHIP
R1509
1K
OLED
R1508
1K
H13
R1507
1K
0.1uF
No SR Stable
R656
1K
NO 21:9
R654
1K
NO SR CHIP
R1512
1K
R519
100
AJ23
AH23
R521
FRC_DONE
R514
10K
0
R511
R524
OPT
R652 1K
R526
R527
R528
GPIOC0_A
GPIOC1_A
GPIOC2_A
GPIOC3_A
R529
R530
R531
R532
TCON_I2C_EN
C501
3.3pF
50V
R644
10K
C503
3.3pF
50V
AG23
GPIOA2
UARTTXD1
AJ25
R541
B6
R542
AH25
R533
R534
100
E9
100
D8
100
C6
100 OPT
D7
100
D6
100
B5
GPIOD0
GPIOA5
GPIOD1
GPIOA6
GPIOD2
GPIOA7
GPIOD3
GPIOB0
GPIOD5
GPIOB1
GPIOD6
GPIOB2
GPIOD7
GPIOB3
GPIOB4
GPIOE1
GPIOB6
GPIOE2
A3
100
C4
100
D5
100
E5
100
F6
100 OPT
D4
GPIOE3
GPIOE4
E7
100
GPIOE0
GPIOB5
GPIOB7
100
M5
R543
GPIOC0
GPIOE5
GPIOC1
GPIOE6
GPIOC2
GPIOE7
GPIOC3
GPIOC4
B3
+3.3V
R545
R546
P5
R547
T5
R548
C7
R549
A5
R550
AF24
C3
R551
R552
R553
R554
C2
R555
D3
R556
D2
R557
C1
R558
E3
D1
R559
R560
D10
R561
E11
R562
B8
R563
C9
R564
E10
A7
R565
R566
D9
R567
C8
R649
AF25
LVDSRXTESTOUT
GPIOC5
R544
N5
E4
GPIOA4
GPIOD4
A6
100
R523
GPIOB6_A
GPIOB7_A
UARTRXD1
B7
R525
+3.3V
100 OPT
100
R522
R509
47K
R540
AG25
GPIOA1
GPIOA3
AK23
LCD
R1511
1K
SPI2TXD
GPIOA0
AG22
L9
R1510
1K
TESTEN
AK22
R510
R539
AK25
UARTTXD0
AH22
R507
SPIRXD
UARTRXD0
AJ22
3D_EN
RESETN
TESTEN_A
GPIOB0_A
GPIOB1_A
GPIOB2_A
GPIOB3_A
PWM_BPL
E8
U4
100 OPT
PA168 HW OPT
RSTn_A
R538
100 OPT
100
PA_TDI_A
PA_TMS_A
PA_TCK_A
PA_TRST_A
PA_TDO_A
100
100
100
100
B4
100
A4
C5
100
C512
3.3pF
50V
OPT
C514
3.3pF
50V
OPT
C515
3.3pF
50V
C517
3.3pF
50V
CLOSE TO PA168_B
C522
3.3pF
50V
R585
OPT
100
R586
100 OPT
SLVRST1
TWOWSCL1
SLVRST2
TWOWSDA1
TDI
TWOWSDA2
TMS
TCK
AJ24
INTL
INTH
R535
100
100
TRSTN
100
R581
C520
0.1uF
XIN
GPIOC7
XOUT
A8
SPITXD
RESETN
SPIRXD
TESTEN
SPI2TXD
UARTRXD0
U_RX0_A
U_TX0_A
100
TESTEN_B
R587
R588
100 OPT
100 OPT
R589
FRC_DONE_Slave
R590
R591
100
GPIOD0_A
FRC_DONE_Slave
URSA7_stable
GPIOD3_A
SPI2TXD_B
100
100
100
100
100 OPT
R592
C513
3.3pF
50V
C516
3.3pF
50V
R583
R584
100 OPT
GPIOD7_A
R593
R594
100
100 OPT
GPIOB6_B
GPIOB7_B
GPIOE5_A
GPIOE6_A
GPIOC0_B
GPIOC1_B
GPIOC2_B
GPIOC3_B
100
100 OPT
AJ22
100 OPT
AH22
100 OPT
AG22
100 OPT
AK23
100
AJ23
100 OPT
AH23
100 OPT
AG23
A6
R595
R596
R598
100
100 OPT
B7
100
100
R612
AK25
R613
AJ25
R614
B6
R615
AH25
R616
R617
M5
R618
N5
R619
P5
R620
T5
R621
R599
R600
R601
R602
R603
R604
R605
100 OPT
R606
FLASH_WP_P2
R607
100
100
E9
D8
100 OPT
C6
100 OPT
D7
100
D6
100
B5
100
100
100
C4
100
D5
100 OPT
E5
100
F6
100 OPT
D4
B3
AJ1
GPIOA0
A5
R623
AG25
GPIOA1
UARTRXD1
GPIOA2
UARTTXD1
GPIOA3
GPIOA4
GPIOA5
GPIOD0
GPIOD1
GPIOA6
GPIOD2
GPIOA7
GPIOD3
GPIOD4
GPIOB0
GPIOD5
GPIOB1
GPIOD6
GPIOB2
GPIOD7
GPIOB3
GPIOB4
GPIOE0
GPIOB5
GPIOE1
GPIOB6
GPIOE2
GPIOB7
GPIOE3
GPIOE4
E7
A3
R622
UARTTXD0
AK22
100
R597
GPIOE0_A
GPIOE1_A
GPIOE2_A
GPIOE3_A
100 OPT
100
GPIOB2_B
GPIOB3_B
100
100
R611
C7
+3.3V
100
D11
U4
SPICS0
AE23
100
R610
TDO
SPICLK
RSTn_B
R609
C10
E8
TWOWSCL2
+3.3V
SPICS0_A 1K
SPICLK_A R568
SPITXD_A
SPIRXD_A
SPI2TXD_A
100
GPIOC0
GPIOE5
GPIOC1
GPIOE6
GPIOC2
GPIOE7
GPIOC3
GPIOC4
R624
AF24
R625
E4
R626
C3
R627
C2
R628
D3
R629
D2
R630
C1
R631
E3
R632
D1
R633
D10
R634
E11
R635
B8
R636
C9
R637
E10
R638
A7
R639
D9
R640
C8
R641
AF25
R608
LVDSRXTESTOUT
GPIOC5
100
SLVRST0_B
100 OPT
100 OPT
+3.3V
100
PA_TDI_B
PA_TMS_B
PA_TCK_B
PA_TRST_B
PA_TDO_B
100
100
100
100
100
SPICS0_B
SPICLK_B
SPITXD_B
SPIRXD_B
SPI2TXD_B
100
100
100
100
+3.3V
100
U_RX0_B
U_TX0_B
100
100 OPT
100 OPT
100
GPIOD0_B
100 OPT
100
URSA7_stable
GPIOD3_B
SPI2TXD_A
100
100
100 OPT
100 OPT
100
GPIOD7_B
100
GPIOE0_B
GPIOE1_B
GPIOE2_B
GPIOE3_B
100
100
100
100 OPT
100
GPIOE5_B
GPIOE6_B
100
100 OPT
100 OPT
AJ2
GPIOC6
XIN
GPIOC7
XOUT
AJ1
+3.3V
C525
C511
R569
2.2M
X500
27MHz
X-TAL_1
18pF
GND_2
1
4
2
3
GND_1
X-TAL_2
C510
18pF
R642
2.2M
18pF
GND_2
1
4
2
3
GND_1
X-TAL_2
C524
R580
10K
OPT
R579
220
E
X-TAL_1
X502
27MHz
18pF
R520
10K
OPT
R572
220
C521
3.3pF
50V
AK24
AJ2
GPIOC6
A1[GN]
A2[RD]
OPT R578
100
100
C
R571
22
SAM2333
LD501
R576
OPT R577
FLASH_WP_P1
MMBT3906(NXP)
Q501
R575
E6
SLVRST0
TWOWSDA0
100 OPT
SPICLK
+3.3V
D11
100
E12
TWOWSCL0
1K
R643
100
TWOWSDA0
AH24
1K
R651
B4
AG24
100
A1[GN]
R505
E6
100
R537
R574
100
R506
22
R504
100
C10
SLVRST0_A
100 OPT
R573
A2[RD]
R503
SLVRST0
SCL_S_B
SDA_S_B
SCL_M1_B
SDA_M1_B
100
SAM2333
LD502
R502
AH24
TWOWSCL0
R536
C
R501
100
E12
1K
R650
SCL_S_A
SDA_S_A
SCL_M1_A
SDA_M1_A
SCL_M2_A
SDA_M2_A
AG24
100
C523
[C]
[C]
R500
0.1uF
C509
IC200
PA168-ES
0.1uF
IC100
PA168-ES
E
MMBT3906(NXP)
Q502
C
B
C
GPIOC0_A
GPIOC1_A
GPIOC2_A
GPIOC3_A
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
R645
0
R646
0
R647
0
R648
0
GPIOC0_B
GPIOC1_B
GPIOC2_B
GPIOC3_B
R570
0
R582
0
GPIOD0_A
GPIOD3_A
B
GPIOD0_B
GPIOD3_B
EAX65309301
P_GPIO_AB
2013.03.18
8
22
LGE Internal Use Only
+3.3V
+3.3V
L601
MLB-201209-0120P-N2
L600
MLB-201209-0120P-N2
%WP[IO2]
6
OPT
0
DO[IO1]
SPIRXD_B
%WP[IO2]
CLK
SPICLK_A
R701
10K
GND
OPT
4
DI[IO0]
5
2
7
3
6
4
5
HOLD[IO3]
CLK
10K
SPICLK_B
GND
DI[IO0]
SPITXD_B
SPICLK_B
0
R1503
2MByte
FLASH_WP
SPITXD_B
OPT
R703
FLASH_WP_P1
8
0
OPT
2MByte
1
VCC
R727
SPITXD_A
R1502
FLASH_WP
10K
SPICS0_B
HOLD[IO3]
C603
0.1uF
25V
R735
OPT
3
VCC
C602
10uF
25V
0.1uF
25V
7
IC800
W25Q16BVSSIG(TRAY)
CS
0
OPT
R1501
SPIRXD_B
2
10K
OPT
R1500
SPICS0_B
8
R726
10K
OPT
DO[IO1]
SPIRXD_A
1
R709
0.1uF
25V
CS
SPICS0_A
C601
0.1uF
25V
C611
10K
C600
10uF
25V
C610
R700
IC700
W25Q16BVSSIG(TRAY)
R719
0
FLASH_WP_P2
0
OPT
OPT
+3.3V
P602
R704
R707
12507WS-04L
4.7K
4.7K
WAFER-STRAIGHT
IIC Slave A
3.3V 1
SCL_S_A
GND
2
SDA_S_A
SCL
3
SCL_S_B
SDA_S_B
IIC Slave B
R713
0
SDA
(Debug use)
R714
4
0
5
+3.3V
P601
R705
R708
12507WS-04L
1.2K
1.2K
WAFER-STRAIGHT
IIC Master 1 A
3.3V 1
SCL_M1_A
GND
2
SDA_M1_A
SCL
3
SCL_M1_B
SDA_M1_B
0
R715
IIC Master 1 B
OPT
(Main connection use)
SDA
R716
4
0
OPT
5
+3.3V
R706
R710
4.7K
4.7K
SCL_M2_A
SDA_M2_A
IIC Master 2 A
R717
0
R718
0
(Master/Slave connection use)
R712
0
GPIOB0_A
R711
0
GPIOB1_A
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EAX65309301
P_SPI,IIC
2013.03.14
9
22
LGE Internal Use Only
Master A
Master B
+3.3V
+3.3V
R737
4.7K
0
4
C700
0.1uF
OPT
1
3
R746
RSTn_B
2
0
4
C702
0.1uF
OPT
OPT
2
0
RSTn_A
R749
3
SW703
JTP-1127WEM
R739
0
1
R745
4.7K
R741
SW701
JTP-1127WEM
PA168_AB_Reset
PA168_AB_Reset
R751
1K
+3.3V
M701
R740
OPT
MDS62110215
SLVRST0_A
M702
OPT
MDS62110215
M703
OPT
MDS62110215
R738
10K
0
C701
0.1uF
OPT
R743
SLVRST0_A
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
0
SLVRST0_B
EAX65309301
P_RESET
2013.03.18
10
22
LGE Internal Use Only
Pin Header Insert
R812
1K
R827
1K
+3.3V
P911
1
R804
2
GPIOD7_A
0
3
R819
4
GPIOD7_B
R843
R834
0
DISPCNTCLR
GPIOB6_B
GPIOB6_A
5
R826
10K
R811
10K
0
0
R842
R833
0
INPUTCNTCLR
GPIOB7_B
GPIOB7_A
0
R841
R832
0
AUXDISPCNT
GPIOD7_A
GPIOD7_B
0
+3.3V
+3.3V
R840
R831
0
AUXINCNT2
GPIOE5_A
GPIOE5_B
BOOTSTRAP_A1
GPIOE0_A
R839
R830
0
AUXINCNT1
GPIOE6_A
GPIOE6_B
0
BOOTSTRAP_B1
GPIOE0_B
0
R801
R825
OPT 10K
R829
OPT 10K
R818
R824
10K
R821
10K
R810
10K
R814
OPT 10K
R803
R807
OPT 10K
R808
10K
0
0
R816
BOOTSTRAP_A2
BOOTSTRAP_B2
GPIOE1_B
GPIOE1_A
GPIO STATUS Connection
0
R817
0
R802
BOOTSTRAP_A3
BOOTSTRAP_B3
GPIOE2_B
GPIOE2_A
0
R800
0
R815
BOOTSTRAP_A4
BOOTSTRAP_B4
GPIOE3_B
GPIOE3_A
0
0
R828
1K
R806
1K
OPT
R809
1K
OPT
R813
1K
R820
1K
OPT
R822
1K
OPT
R823
1K
Slave: 1100
R805
1K
Master: 0110
R836
R838
0
iGPIOB2_A
GPIOB2_A
GPIOB2_B
0
R835
R837
iGPIOB3_A
GPIOB3_A
GPIOB3_B
0
Name
Bootstrap0
Bootstrap1
0
Function
0:From SPI Flash
1:From internal ROM
0:PA168 WORKS as the master chip
GPIO STATUS Connection
1:PA168 WORKS as the slave chip
Bootstrap2
Bootstrap3
Bootstrap4
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
TWOWO bus address selection
EAX65309301
2013.03.18
P_BOOTSTRAP
11
22
LGE Internal Use Only
+3.3V
+3.3V
R930
10K
OPT
R910
10K
OPT
TESTEN_B
TESTEN_A
R929
0
R909
0
+3.3V
+3.3V
UART FOR DEBUG PA138A
R903
0
UART FOR DEBUG PA138B
R900
0
P900
12507WS-04L
P901
12507WS-04L
WAFER-STRAIGHT
WAFER-STRAIGHT
1
1
2
U_RX0_A
2
U_RX0_B
3
3
4
U_TX0_A
4
U_TX0_B
5
5
+3.3V
R906
R907
R908
PA168_JTAG
1
1
2
10K
10K
10K
10K
2
R926
R927
R928
10K
10K
10K
10K
3
PA_TCK_A
3
4
PA_TDO_A
4
PA_TDO_B
5
PA_TMS_A
5
PA_TMS_B
6
PA_TRST_A
6
PA_TRST_B
7
PA_TDI_A
7
PA_TDI_B
RSTn_A
8
8
RSTn_B
10
10
11
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
PA_TCK_B
9
9
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
R925
10K
R905
10K
P909
12505WS-10A00
R913
P1909
R933
+3.3V
12505WS-10A00
PA168_JTAG
3.3V
11
EAX65309301
P_UART,JTAG
2013.03.18
12
22
LGE Internal Use Only
IC100
PA168-ES
DPLL_OSC_VDD1V_A
A1
A2
A29
B10
B13
B15
B18
B20
B24
B26
D12
D17
D25
D27
D29
E14
E18
E26
F7
F26
F27
G28
G29
L15
L18
L20
M11
M14
M16
N13
N15
N17
N20
P11
P14
P15
P16
P17
P18
R13
R14
R15
R16
R17
R19
T12
T14
T15
T16
T17
T18
U13
U14
U15
U16
U17
U19
V12
V14
V15
V16
V17
V18
W13
W15
W16
W17
AE8
AE25
AF5
AF7
AF9
AF11
AF13
AF17
AF19
AG4
AG8
AG10
AG12
AG14
AG16
AG18
AG21
AH5
AH7
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AK1
AK3
AK5
AK7
AK9
AK11
AK13
AK15
AK17
AK19
AK21
AK26
VSS_1
[D]
AH4
OSCVDD1V
VSS_2
VSS_3
VSS_4
VSS_5
+1.05V_A
AE7
+1.05V_A
VDD1V_34
VSS_6
L12
VSS_7
VDD1V_1
VSS_8
VDD1V_2
VSS_9
VDD1V_3
VSS_10
VDD1V_4
VSS_11
VDD1V_5
VSS_12
VDD1V_6
VSS_13
VDD1V_7
VSS_14
Close to PORVDD1V
AK2
DPLLVDD1V
VDD1V_8
VSS_15
VDD1V_9
VSS_16
VDD1V_10
VSS_17
VDD1V_11
VSS_18
VDD1V_12
VSS_19
VDD1V_13
VSS_20
VDD1V_14
VSS_21
VDD1V_15
VSS_22
VDD1V_16
VSS_23
VDD1V_17
VSS_24
VDD1V_18
VSS_25
VDD1V_19
VSS_26
VDD1V_20
VSS_27
VDD1V_21
VSS_28
VDD1V_22
VSS_29
VDD1V_23
VSS_30
VDD1V_24
VSS_31
VDD1V_25
VSS_32
VDD1V_26
VSS_33
VDD1V_27
VSS_34
VDD1V_28
VSS_35
VDD1V_29
VSS_36
VDD1V_30
VSS_37
VDD1V_31
VSS_38
VDD1V_32
VSS_39
VDD1V_33
VSS_40
L14
L16
M12
C1005
0.1uF
16V
M13
M15
M17
M18
C1012
0.1uF
16V
C1019
0.1uF
16V
C1025
0.1uF
16V
C1088
4.7uF
10V
C1039
1uF
10V
C1045
0.1uF
16V
M19
N12
N14
N16
N18
N19
P12
P13
P19
R12
R18
R20
Close to VTVDD1V Pin
T13
T19
U12
U18
V13
V19
W12
C1003
0.1uF
16V
W14
W18
W19
Y12
C1010
0.1uF
16V
C1023
0.1uF
16V
C1017
0.1uF
16V
C1030
4.7uF
10V
Y13
Y17
Y14
VSS_41
VTVDD1V_1
VSS_42
VTVDD1V_2
VSS_43
VTVDD1V_3
VSS_44
VTVDD1V_4
VSS_45
VTVDD1V_5
VSS_46
VTVDD1V_6
VSS_47
VTVDD1V_7
VSS_48
VTVDD1V_8
VSS_49
VTVDD1V_9
VSS_50
VTVDD1V_10
VSS_51
VTVDD1V_11
VSS_52
VTVDD1V_12
VSS_53
VTVDD1V_13
VSS_54
VTVDD1V_14
VSS_55
VTVDD1V_15
VSS_56
VTVDD1V_16
VSS_57
VTVDD1V_17
VSS_58
VTVDD1V_18
VSS_59
VTVDD1V_19
VSS_60
VTVDD1V_20
VSS_61
VTVDD1V_21
VSS_62
VTVDD1V_22
VSS_63
VTVDD1V_23
VSS_64
VTVDD1V_24
VSS_65
VTVDD1V_25
VSS_66
VTVDD1V_26
VSS_67
VTVDD1V_27
VSS_68
VTVDD1V_28
VSS_69
VTVDD1V_29
VSS_70
VTVDD1V_30
VSS_71
VTVDD1V_31
VSS_72
VTVDD1V_32
VSS_73
VTVDD1V_33
VSS_74
Y15
Y16
AF8
AF10
AF12
AF18
AF20
AG7
AG9
AG11
AG13
AG15
AG17
+1.05V_A
AG19
DPLL_OSC_VDD1V_A
AG20
AH6
AH8
L1002
MLB-201209-0120P-N2
AH10
AH12
AH14
C1026
1uF
10V
AH16
AH18
AH20
AJ5
C1033
0.1uF
16V
C1006
1uF
10V
C1013
0.1uF
16V
AJ7
AJ9
AJ11
AJ13
AJ15
AJ17
AJ19
AJ21
AVDD_DDR_PA1
Close to OSCVDD1V Pin
Close to DPLLVDD1V Pin
A9
VSS_75
VDDM18_15_1
VSS_76
VDDM18_15_2
VSS_77
VDDM18_15_3
VSS_78
VDDM18_15_4
VSS_79
VDDM18_15_5
VSS_80
VDDM18_15_6
VSS_81
VDDM18_15_7
VSS_82
VDDM18_15_8
VSS_83
VDDM18_15_9
VSS_84
VDDM18_15_10
VSS_85
VDDM18_15_11
VSS_86
VDDM18_15_12
VSS_87
VDDM18_15_13
VSS_88
VDDM18_15_14
VSS_89
VDDM18_15_15
VSS_90
VDDM18_15_16
VSS_91
VDDM18_15_17
VSS_92
VDDM18_15_18
VSS_93
VDDM18_15_19
VSS_94
VDDM18_15_20
VSS_95
VDDM18_15_21
VSS_96
VDDM18_15_22
VSS_97
VDDM18_15_23
A18
A24
A30
B21
C11
D14
D16
D19
D21
D24
D26
E17
E25
E27
AVDD_DDR_PA1
F24
G26
G27
G30
L17
L19
M20
P20
VSS_98
VSS_99
VSS_100
C1001
0.1uF
16V
C1008
0.1uF
16V
C1015
0.1uF
16V
C1021
0.1uF
16V
C1028
0.1uF
16V
C1034
1uF
10V
C1040
10uF
10V
OPT
C1046
10uF
10V
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EAX65309301
PA168_POWER_A1
2013.03.18
13
22
LGE Internal Use Only
+2.5V
C1126
1uF
10V
IC100
PA168-ES
[E]
R1103
1.2K
AF4
PORVDD25_1
AF14
AF6
REXT
PORVDD25_2
AF15
AG6
VPLLVSS25CAP
VPLLVDD25_A
R1102
10
C1104
4.7uF
10V
DPLLVSS25CAP
C1105
0.1uF
16V
AF16
H26
AJ4
MPLLVDD25
C1100
4.7uF
10V
LV1PLLVDD25
+2.5V
LV2PLLVSS25CAP
C1101
0.1uF
16V
C1106
0.1uF
16V
J27
AH3
MEPLLVDD25
P26
R27
T20
T26
T28
U27
V20
V26
W27
Y20
Y26
Y28
AA27
AB26
AB28
AC25
AD26
AD28
AE27
AF26
AF28
AH26
AH28
AK30
K28
LVRVSS_1
LVRVDD25_1
LVRVSS_2
LVRVDD25_2
LVRVSS_3
LVRVDD25_3
LVRVSS_4
LVRVDD25_4
LVRVSS_5
LVRVDD25_5
LVRVSS_6
LVRVDD25_6
LVRVSS_7
LVRVDD25_7
LVRVSS_8
LVRVDD25_8
LVRVSS_9
LVRVDD25_9
LVRVSS_10
LVRVDD25_10
LVRVSS_11
LVRVDD25_11
LVRVSS_12
LVRVDD25_12
LVRVSS_13
LVRVDD25_13
LVRVSS_14
LVRVDD25_14
LVRVSS_15
LVRVDD25_15
LVRVSS_16
LVRVDD25_16
LVRVSS_17
LVRVDD25_17
LVRVSS_18
LVRVDD25_18
LVRVSS_19
LVRVDD25_19
LVRVSS_20
LVRVDD25_20
LVRVSS_21
LVRVDD25_21
LVRVSS_22
LVRVDD25_22
LVRVSS_23
LVRVDD25_23
LVRVSS_24
LVRVDD25_24
LVRVSS_25
LVRVDD25_25
LVRVSS_26
LVRVDD25_26
K3
K5
L5
M3
N4
P3
R5
T3
T11
V3
V11
W5
Y3
Y11
AA4
AB3
AB5
AC4
AC6
AD5
AE4
AE6
AF3
AH1
DIFRXVDD25_1
DIFRXVSS_2
DIFRXVDD25_2
DIFRXVSS_3
DIFRXVDD25_3
M28
N26
LVRVDD25_A
LV1PLLVDD25_A
LV2PLLVDD25_A
LVRVDD25_A
N28
R26
L1111
MLB-201209-0120P-N2
R28
T27
C1162
0.1uF
16V
U20
U26
U28
W20
C1167
0.1uF
16V
C1172
0.1uF
16V
LVRVDD25_A
C1177
4.7uF
10V
L1109
MLB-201209-0120P-N2
LVTVDD25_A
W26
W28
L1110
MLB-201209-0120P-N2
Y27
DIF_LVTA_VDD25_A
AA26
AA28
AB27
L1101
MLB-201209-0120P-N2
LVTVDD25_A
AC26
VPLLVDD25_A
AD25
AD27
L1100
MLB-201209-0120P-N2
AE26
AE28
MPLLVDD25_A
AF27
AG26
AH27
AK29
DIF_LVTA_VDD25_A
C1113
0.1uF
16V
C1118
0.1uF
16V
C1123
0.1uF
16V
C1130
4.7uF
10V
L1102
MLB-201209-0120P-N2
MEPLLVDD25_A
L1104
MLB-201209-0120P-N2
K27
LVTVDD25_1
L28
DPLLVDD25_A
LVTVDD25_A
LVTVSS_2
LVTVDD25_2
LVTVSS_3
LVTVDD25_3
LVTVSS_4
LVTVDD25_4
LVTVSS_5
LVTVDD25_5
LVTVSS_6
LVTVDD25_6
LVTVSS_7
LVTVDD25_7
LVTVSS_8
LVTVDD25_8
LVTVSS_9
LVTVDD25_9
LVTVSS_10
LVTVDD25_10
LVTVSS_11
LVTVDD25_11
LVTVSS_12
LVTVDD25_12
LVTVSS_13
LVTVDD25_13
LVTVSS_14
LVTVDD25_14
LVTVSS_15
LVTVDD25_15
LVTVSS_16
LVTVDD25_16
LVTVSS_17
LVTVDD25_17
LVTVSS_18
LVTVDD25_18
LVTVSS_19
LVTVDD25_19
LVTVSS_20
LVTVDD25_20
LVTVSS_21
LVTVDD25_21
LVTVSS_22
LVTVDD25_22
LVTVSS_23
LVTVDD25_23
J3
K4
M4
N3
P4
R11
T4
U3
DIF_LVTA_VDD25_A
U11
Close to LVTAVDD25 (pin V5)
V4
W11
Y4
AA3
AA5
C1166
0.1uF
16V
AB4
AC3
AC5
AD6
C1171
0.1uF
16V
C1176
4.7uF
10V
C1164
0.1uF
16V
C1169
0.1uF
16V
C1174
4.7uF
10V
C1149
1uF
10V
C1157
0.1uF
16V
AE3
AE5
AG3
AH2
LVTVSS_24
Close to DIFTXVDD25 pin
LVTVSS_25
LVTVSS_26
H6
L1103
MLB-201209-0120P-N2
G2
LVTVSS_1
DIF_LVTA_VDD25_A
F3
F5
L1105
MLB-201209-0120P-N2
J28
DIFRXVSS_1
G1
H3
LV2PLLVDD25_A
L29
H28
K26
C1109
4.7uF
10V R1104
10
LV2PLLVDD25
L30
N27
LV1PLLVDD25_A
AJ3
MEPLLVSS25CAP
R1100
10
C1110
4.7uF
10V R1105
10
LV1PLLVSS25CAP
C1103
0.1uF
16V
J26
MEPLLVDD25_A
C1107
0.1uF
16V
DPLLVDD25_A
AK4
MPLLVSS25CAP
R1101
10
C1111
4.7uF
10V R1106
10
DPLLVDD25
H27
C1102
4.7uF
10V
C1108
0.1uF
16V
AG5
VPLLVDD25
MPLLVDD25_A
C1128
0.1uF
16V
F4
DIFTXVSS_1
DIFTXVDD25_1
DIFTXVSS_2
DIFTXVDD25_2
DIFTXVSS_3
DIFTXVDD25_3
G3
G6
+3.3V
V5
Y5
LVTAVSS
LVTAVDD25
B1
VDDIO33_1
VDDIO33_2
VDDIO33_3
VDDIO33_4
VDDIO33_5
VDDIO33_6
VDDIO33_7
VDDIO33_8
VDDIO33_9
VDDIO33_10
VDDIO33_11
VDDIO33_12
B2
B9
E13
F8
L11
L13
Y18
Y19
AE24
AF21
AJ26
VDDIO33_13
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V
N11
C1133
0.1uF
16V
C1139
0.1uF
16V
C1144
0.1uF
16V
C1148
4.7uF
10V
EAX65309301
PA168_POWER_A2
2013.03.18
14
22
LGE Internal Use Only
IC200
PA168-ES
DPLL_OSC_VDD1V_B
A1
A2
A29
B10
B13
B15
B18
B20
B24
B26
D12
D17
D25
D27
D29
E14
E18
E26
F7
F26
F27
G28
G29
L15
L18
L20
M11
M14
M16
N13
N15
N17
N20
P11
P14
P15
P16
P17
P18
R13
R14
R15
R16
R17
R19
T12
T14
T15
T16
T17
T18
U13
U14
U15
U16
U17
U19
V12
V14
V15
V16
V17
V18
W13
W15
W16
W17
AE8
AE25
AF5
AF7
AF9
AF11
AF13
AF17
AF19
AG4
AG8
AG10
AG12
AG14
AG16
AG18
AG21
AH5
AH7
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AK1
AK3
AK5
AK7
AK9
AK11
AK13
AK15
AK17
AK19
AK21
AK26
VSS_1
[D]
AH4
OSCVDD1V
VSS_2
VSS_3
VSS_4
VSS_5
+1.05V_B
AE7
+1.05V_B
VDD1V_34
VSS_6
L12
VSS_7
VDD1V_1
VSS_8
VDD1V_2
VSS_9
VDD1V_3
VSS_10
VDD1V_4
VSS_11
VDD1V_5
VSS_12
VDD1V_6
VSS_13
VDD1V_7
VSS_14
Close to PORVDD1V
AK2
DPLLVDD1V
VDD1V_8
VSS_15
VDD1V_9
VSS_16
VDD1V_10
VSS_17
VDD1V_11
VSS_18
VDD1V_12
VSS_19
VDD1V_13
VSS_20
VDD1V_14
VSS_21
VDD1V_15
VSS_22
VDD1V_16
VSS_23
VDD1V_17
VSS_24
VDD1V_18
VSS_25
VDD1V_19
VSS_26
VDD1V_20
VSS_27
VDD1V_21
VSS_28
VDD1V_22
VSS_29
VDD1V_23
VSS_30
VDD1V_24
VSS_31
VDD1V_25
VSS_32
VDD1V_26
VSS_33
VDD1V_27
VSS_34
VDD1V_28
VSS_35
VDD1V_29
VSS_36
VDD1V_30
VSS_37
VDD1V_31
VSS_38
VDD1V_32
VSS_39
VDD1V_33
VSS_40
L14
L16
M12
C1201
0.1uF
16V
M13
M15
M17
M18
C1204
0.1uF
16V
C1208
0.1uF
16V
C1212
0.1uF
16V
C1247
4.7uF
10V
C1249
1uF
10V
C1250
0.1uF
16V
M19
N12
N14
N16
N18
N19
P12
P13
P19
R12
R18
R20
T13
Close to VTVDD1V Pin
T19
U12
U18
V13
V19
W12
C1202
0.1uF
16V
W14
W18
W19
Y12
C1205
0.1uF
16V
C1209
0.1uF
16V
C1213
0.1uF
16V
C1216
4.7uF
10V
Y13
Y17
Y14
VSS_41
VTVDD1V_1
VSS_42
VTVDD1V_2
VSS_43
VTVDD1V_3
VSS_44
VTVDD1V_4
VSS_45
VTVDD1V_5
VSS_46
VTVDD1V_6
VSS_47
VTVDD1V_7
VSS_48
VTVDD1V_8
VSS_49
VTVDD1V_9
VSS_50
VTVDD1V_10
VSS_51
VTVDD1V_11
VSS_52
VTVDD1V_12
VSS_53
VTVDD1V_13
VSS_54
VTVDD1V_14
VSS_55
VTVDD1V_15
VSS_56
VTVDD1V_16
VSS_57
VTVDD1V_17
VSS_58
VTVDD1V_18
VSS_59
VTVDD1V_19
VSS_60
VTVDD1V_20
VSS_61
VTVDD1V_21
VSS_62
VTVDD1V_22
VSS_63
VTVDD1V_23
VSS_64
VTVDD1V_24
VSS_65
VTVDD1V_25
VSS_66
VTVDD1V_26
VSS_67
VTVDD1V_27
VSS_68
VTVDD1V_28
VSS_69
VTVDD1V_29
VSS_70
VTVDD1V_30
VSS_71
VTVDD1V_31
VSS_72
VTVDD1V_32
VSS_73
VTVDD1V_33
VSS_74
Y15
Y16
AF8
AF10
AF12
AF18
AF20
AG7
AG9
AG11
AG13
AG15
AG17
+1.05V_B
AG19
DPLL_OSC_VDD1V_B
AG20
AH6
AH8
L1200
MLB-201209-0120P-N2
AH10
AH12
AH14
C1206
1uF
10V
AH16
AH18
AH20
AJ5
C1210
0.1uF
16V
C1217
1uF
10V
C1221
0.1uF
16V
AJ7
AJ9
AJ11
AJ13
AJ15
AJ17
Close to OSCVDD1V Pin
AJ19
AJ21
Close to DPLLVDD1V Pin
AVDD_DDR_PA2
A9
VSS_75
VDDM18_15_1
VSS_76
VDDM18_15_2
VSS_77
VDDM18_15_3
VSS_78
VDDM18_15_4
VSS_79
VDDM18_15_5
VSS_80
VDDM18_15_6
VSS_81
VDDM18_15_7
VSS_82
VDDM18_15_8
VSS_83
VDDM18_15_9
VSS_84
VDDM18_15_10
VSS_85
VDDM18_15_11
VSS_86
VDDM18_15_12
VSS_87
VDDM18_15_13
VSS_88
VDDM18_15_14
VSS_89
VDDM18_15_15
VSS_90
VDDM18_15_16
VSS_91
VDDM18_15_17
VSS_92
VDDM18_15_18
VSS_93
VDDM18_15_19
VSS_94
VDDM18_15_20
VSS_95
VDDM18_15_21
VSS_96
VDDM18_15_22
VSS_97
VDDM18_15_23
A18
A24
A30
B21
C11
D14
D16
D19
D21
D24
D26
E17
E25
E27
AVDD_DDR_PA2
F24
G26
G27
G30
L17
L19
M20
P20
VSS_98
VSS_99
VSS_100
C1200
0.1uF
16V
C1203
0.1uF
16V
C1207
0.1uF
16V
C1211
0.1uF
16V
C1214
0.1uF
16V
C1218
1uF
10V
C1222
10uF
10V
OPT
C1225
10uF
10V
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EAX65309301
PA168_POWER_B1
2013.03.18
15
22
LGE Internal Use Only
+2.5V
C1312
1uF
10V
IC200
PA168-ES
[E]
R1303
1.2K
AF4
PORVDD25_1
AF14
AF6
REXT
PORVDD25_2
AF15
AG6
VPLLVSS25CAP
VPLLVDD25_B
R1300
10
C1300
4.7uF
10V
DPLLVSS25CAP
C1303
0.1uF
16V
AF16
H26
AJ4
+2.5V
AJ3
MEPLLVSS25CAP
C1302
4.7uF
10V
LV2PLLVSS25CAP
C1308
0.1uF
16V
C1305
0.1uF
16V
J27
AH3
MEPLLVDD25
P26
R27
T20
T26
T28
U27
V20
V26
W27
Y20
Y26
Y28
AA27
AB26
AB28
AC25
AD26
AD28
AE27
AF26
AF28
AH26
AH28
AK30
LVRVDD25_1
LVRVSS_2
LVRVDD25_2
LVRVSS_3
LVRVDD25_3
LVRVSS_4
LVRVDD25_4
LVRVSS_5
LVRVDD25_5
LVRVSS_6
LVRVDD25_6
LVRVSS_7
LVRVDD25_7
LVRVSS_8
LVRVDD25_8
LVRVSS_9
LVRVDD25_9
LVRVSS_10
LVRVDD25_10
LVRVSS_11
LVRVDD25_11
LVRVSS_12
LVRVDD25_12
LVRVSS_13
LVRVDD25_13
LVRVSS_14
LVRVDD25_14
LVRVSS_15
LVRVDD25_15
LVRVSS_16
LVRVDD25_16
LVRVSS_17
LVRVDD25_17
LVRVSS_18
LVRVDD25_18
LVRVSS_19
LVRVDD25_19
LVRVSS_20
LVRVDD25_20
LVRVSS_21
LVRVDD25_21
LVRVSS_22
LVRVDD25_22
LVRVSS_23
LVRVDD25_23
LVRVSS_24
LVRVDD25_24
LVRVSS_25
LVRVDD25_25
LVRVSS_26
K28
K3
K5
L5
M3
N4
P3
R5
T3
T11
V3
V11
W5
Y3
Y11
AA4
AB3
AB5
AC4
AC6
AD5
AE4
AE6
AF3
AH1
LV1PLLVDD25_B
N26
LVRVDD25_B
C1350
0.1uF
16V
N28
R26
R28
T27
C1352
0.1uF
16V
C1353
0.1uF
16V
C1354
4.7uF
10V
LV2PLLVDD25_B
L1301
MLB-201209-0120P-N2
LVRVDD25_B
U20
U26
L1302
MLB-201209-0120P-N2
U28
LVTVDD25_B
W20
W26
W28
L1303
MLB-201209-0120P-N2
Y27
DIF_LVTA_VDD25_B
AA26
AA28
AB27
AC26
L1305
MLB-201209-0120P-N2
AD25
VPLLVDD25_B
LVTVDD25_B
AD27
AE26
L1306
MLB-201209-0120P-N2
AE28
AF27
AG26
AH27
AK29
DIF_LVTA_VDD25_B
C1345
0.1uF
16V
C1347
0.1uF
16V
C1349
0.1uF
16V
MPLLVDD25_B
C1351
4.7uF
10V
L1307
MLB-201209-0120P-N2
MEPLLVDD25_B
J28
DIFRXVDD25_1
DIFRXVSS_2
DIFRXVDD25_2
DIFRXVSS_3
DIFRXVDD25_3
K27
L1308
MLB-201209-0120P-N2
L28
LVTVDD25_B
DPLLVDD25_B
G2
LVTVSS_1
LVTVDD25_1
LVTVSS_2
LVTVDD25_2
LVTVSS_3
LVTVDD25_3
LVTVSS_4
LVTVDD25_4
LVTVSS_5
LVTVDD25_5
LVTVSS_6
LVTVDD25_6
LVTVSS_7
LVTVDD25_7
LVTVSS_8
LVTVDD25_8
LVTVSS_9
LVTVDD25_9
LVTVSS_10
LVTVDD25_10
LVTVSS_11
LVTVDD25_11
LVTVSS_12
LVTVDD25_12
LVTVSS_13
LVTVDD25_13
LVTVSS_14
LVTVDD25_14
LVTVSS_15
LVTVDD25_15
LVTVSS_16
LVTVDD25_16
LVTVSS_17
LVTVDD25_17
LVTVSS_18
LVTVDD25_18
LVTVSS_19
LVTVDD25_19
LVTVSS_20
LVTVDD25_20
LVTVSS_21
LVTVDD25_21
LVTVSS_22
LVTVDD25_22
LVTVSS_23
LVTVDD25_23
J3
K4
M4
N3
P4
R11
T4
U3
DIF_LVTA_VDD25_B
U11
Close to LVTAVDD25 (pin V5)
V4
W11
Y4
AA3
AA5
C1316
0.1uF
16V
AB4
AC3
AC5
AD6
C1320
0.1uF
16V
C1324
4.7uF
10V
C1329
0.1uF
16V
C1333
0.1uF
16V
C1337
4.7uF
10V
C1341
1uF
10V
C1344
0.1uF
16V
AE3
AE5
AG3
AH2
LVTVSS_24
Close to DIFTXVDD25 pin
LVTVSS_25
DIF_LVTA_VDD25_B
F3
H6
L1300
MLB-201209-0120P-N2
M28
LVTVSS_26
F5
L1304
MLB-201209-0120P-N2
LVRVDD25_B
LVRVDD25_26
DIFRXVSS_1
G1
H3
LV2PLLVDD25_B
L29
LVRVSS_1
H28
K26
C1311
4.7uF
10V R1306
10
LV2PLLVDD25
L30
N27
LV1PLLVDD25_B
LV1PLLVDD25
J26
R1302
10
C1310
4.7uF
10V R1305
10
LV1PLLVSS25CAP
C1304
0.1uF
16V
MPLLVDD25
MEPLLVDD25_B
C1307
0.1uF
16V
DPLLVDD25_B
AK4
MPLLVSS25CAP
R1301
10
C1309
4.7uF
10V R1304
10
DPLLVDD25
H27
C1301
4.7uF
10V
C1306
0.1uF
16V
AG5
VPLLVDD25
MPLLVDD25_B
C1313
0.1uF
16V
F4
DIFTXVSS_1
DIFTXVDD25_1
DIFTXVSS_2
DIFTXVDD25_2
DIFTXVSS_3
DIFTXVDD25_3
G3
G6
+3.3V
V5
Y5
LVTAVSS
LVTAVDD25
B1
VDDIO33_1
VDDIO33_2
VDDIO33_3
VDDIO33_4
VDDIO33_5
VDDIO33_6
VDDIO33_7
VDDIO33_8
VDDIO33_9
VDDIO33_10
VDDIO33_11
VDDIO33_12
B2
B9
E13
F8
L13
N11
Y18
Y19
AE24
AF21
AJ26
VDDIO33_13
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V
L11
C1326
0.1uF
16V
C1330
0.1uF
16V
C1334
0.1uF
16V
C1338
4.7uF
10V
EAX65309301
PA168_POWER_B2
2013.03.18
16
22
LGE Internal Use Only
IC2500
LGE7410
D15
B12
U_MMAA4
D13
U_MMAA5
A12
U_MMAA6
E12
U_MMAA7
D17
U_MMAA8
C9
U_MMAA9
B13
U_MMAA10
D16
U_MMAA11
E16
U_MMAA12
A9
U_MMAA13
A11
U_MMAA14
E15
U_MMAA15
D11
U_MMBKA0
E17
U_MMBKA1
E11
U_MMBKA2
A_DDR3_A2
B_DDR3_A2
A_DDR3_A3
B_DDR3_A3
A_DDR3_A4
B_DDR3_A4
A_DDR3_A5
B_DDR3_A5
A_DDR3_A6
B_DDR3_A6
A_DDR3_A7
B_DDR3_A7
A_DDR3_A8
B_DDR3_A8
A_DDR3_A9
B_DDR3_A9
A_DDR3_A10
B_DDR3_A10
A_DDR3_A11
B_DDR3_A11
A_DDR3_A12
B_DDR3_A12
A_DDR3_A13
B_DDR3_A13
A_DDR3_A14
B_DDR3_A14
A_DDR3_A15
B_DDR3_A15
A_DDR3_BA0
B_DDR3_BA0
A_DDR3_BA1
B_DDR3_BA1
A_DDR3_BA2
B_DDR3_BA2
E14
U_MMRASA
B10
U_MMCASA
C10
U_MMWEA
E10
U_MMODTA
C14
U_MMCKEA
E13
U_MMRESETA
U_MMCKAP0
U_MMCKAN0
C15
22
A14
R1701
22
U_MMCSA0
D10
R1700
F10
U_MMAB0
E31
U_MMAB1
G29
U_MMAB2
C30
IC2600
H5TQ1G63EFR-PBC
U_MMAB3
F30
U_MMAB4
B31
F32
B_DDR3_RASZ
A_DDR3_CASZ
B_DDR3_CASZ
A_DDR3_WEZ
B_DDR3_WEZ
A_DDR3_ODT
B_DDR3_ODT
A_DDR3_CKE
B_DDR3_CKE
A_DDR3_RESETB
B_DDR3_RESETB
A_DDR3_MCLK
B_DDR3_MCLK
A_DDR3_MCLKZ
B_DDR3_MCLKZ
A_DDR3_CSB1
B_DDR3_CSB1
A_DDR3_CSB2
B_DDR3_CSB2
U_MMAB7
K29
U_MMAA0
U_MMAA1
U_MMAA2
U_MMAA3
U_MMAA4
U_MMAA5
U_MMAA6
U_MMAA7
U_MMAA8
U_MMAA9
U_MMAA10
U_MMAA11
U_MMAA12
U_MMAA13
U_MMAB8
C31
U_MMAB9
G31
U_MMAB10
J29
U_MMAB11
L28
U_MMAB12
C32
U_MMAB13
E30
U_MMAB14
K28
U_MMAB15
B30
U_MMBKB0
M28
U_MMBKB1
F29
U_MMBKB2
U_MMRASB
D31
U_MMCASB
D32
U_MMWEB
E29
U_MMAA15
U_MMODTB
G30
U_MMCKEB
H28
U_MMRESETB
J31
H30
22
R1706
A30
22
R1707
U_MMCSB0
D29
U_MMCKBP0
U_MMCKBN0
U_MMCKAP0
C1750
0.01uF
U_MMCKAN0
D22
U_MMDA0
U_MMDA1
U_MMDA2
U_MMDA3
U_MMDA4
U_MMDA5
U_MMDA6
U_MMDA7
U_MMDA8
U_MMDA9
U_MMDA10
U_MMDA11
U_MMDA12
U_MMDA13
U_MMDA14
U_MMDA15
U_MMDMA0
D18
D23
D19
B21
B15
A21
C16
B17
D21
E18
B20
D20
E21
E19
E20
C17
A20
R29
A_DDR3_DQ0
B_DDR3_DQ0
A_DDR3_DQ1
B_DDR3_DQ1
A_DDR3_DQ2
B_DDR3_DQ2
A_DDR3_DQ3
B_DDR3_DQ3
A_DDR3_DQ4
B_DDR3_DQ4
A_DDR3_DQ5
B_DDR3_DQ5
A_DDR3_DQ6
B_DDR3_DQ6
A_DDR3_DQ7
B_DDR3_DQ7
A_DDR3_DQ8
B_DDR3_DQ8
A_DDR3_DQ9
B_DDR3_DQ9
A_DDR3_DQ10
B_DDR3_DQ10
A_DDR3_DQ11
B_DDR3_DQ11
A_DDR3_DQ12
B_DDR3_DQ12
A_DDR3_DQ13
B_DDR3_DQ13
A_DDR3_DQ14
B_DDR3_DQ14
A_DDR3_DQ15
B_DDR3_DQ15
A_DDR3_DM0
B_DDR3_DM0
A_DDR3_DM1
U_MMDMA1
U_MMDQSAP0
U_MMDQSAN0
U_MMDQSAP1
C19
A18
C18
A_DDR3_DQS0
B_DDR3_DQS0
A_DDR3_DQS0B
B_DDR3_DQS0B
A_DDR3_DQS1
B_DDR3_DQS1
B28
E23
A29
B22
B29
C23
D25
D27
E24
C27
D26
B26
E25
C26
D24
A27
C24
A23
U_MMDB4
J30
U_MMDB5
R32
U_MMDB6
K32
U_MMDB7
L31
U_MMRESETA
U_MMDB8
P29
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
A0
A3
A4
A6
A8
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
NC_7
VDD_5
VDD_6
U_MMDQSAP0
U_MMDQSAN0
U_MMDB11
N29
U_MMDB12
T28
U_MMDB13
P28
U_MMDQSAP1
U_MMDQSAN1
U_MMDB14
R28
U_MMDB15
K30
U_MMDMB0
P30
U_MMDMA0
U_MMDMA1
U_MMDMB1
U_MMDQSBP0
N32
U_MMDA0
U_MMDA1
U_MMDA2
U_MMDA3
U_MMDA4
U_MMDA5
U_MMDA6
U_MMDA7
U_MMDQSBN0
M32
U_MMDQSBP1
M31
A_DDR3_DQ16
B_DDR3_DQ16
A_DDR3_DQ17
B_DDR3_DQ17
A_DDR3_DQ18
B_DDR3_DQ18
A_DDR3_DQ19
B_DDR3_DQ19
A_DDR3_DQ20
B_DDR3_DQ20
A_DDR3_DQ21
B_DDR3_DQ21
A_DDR3_DQ22
B_DDR3_DQ22
A_DDR3_DQ23
B_DDR3_DQ23
A_DDR3_DQ24
B_DDR3_DQ24
A_DDR3_DQ25
B_DDR3_DQ25
A_DDR3_DQ26
B_DDR3_DQ26
A_DDR3_DQ27
B_DDR3_DQ27
A_DDR3_DQ28
B_DDR3_DQ28
A_DDR3_DQ29
B_DDR3_DQ29
A_DDR3_DQ30
B_DDR3_DQ30
A_DDR3_DQ31
B_DDR3_DQ31
A_DDR3_DM2
B_DDR3_DM2
A_DDR3_DM3
B_DDR3_DM3
VDD_7
VDD_8
M2
BA0
J3
K3
L3
U_MMDQSBN1
U28
AB31
V28
U_MMDA8
U_MMDA9
U_MMDA10
U_MMDA11
U_MMDA12
U_MMDA13
U_MMDA14
U_MMDA15
AC31
T30
V29
Y29
W28
AA31
W29
G7
K2
K8
N1
CK
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
RESET
NC_4
F3
DQSL
C1709
A8
0.01uF
C1
U_MMCKBN0
C9
DQSU
VSS_1
DQSU
VSS_2
VSS_3
DML
DMU
F2
F8
H3
H8
G2
H7
VSS_4
VSS_5
VSS_6
E3
F7
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
DQL7
C8
C2
A7
A2
B8
A3
R2
T8
R3
L7
R7
N7
T3
H2
H9
N8
M3
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
H1
A3
VREFDQ
A4
A5
L8
A6
ZQ
A8
K9
A9
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
NC_7
VDD_5
VDD_6
VDD_7
VDD_8
BA0
J3
K3
L3
VDDQ_1
CK
VDDQ_2
CK
VDDQ_3
CKE
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
VDDQ_9
RESET
NC_2
NC_3
T7
NC_4
F3
E1
B7
D3
M1
P1
P9
T1
T9
F7
F2
F8
H3
H8
G2
H7
E2
E8
F9
G1
G9
Y31
VSS_1
DQSU
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
VSS_12
R9
AVDD_DDR_URSA7
A8
C1
C9
D2
E9
F1
H2
H9
J9
L1
L9
T7
U_MMAB14
C3
C8
C2
A7
A2
B8
A3
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQL6
B1
VSSQ_1
D7
U_MMDB8
U_MMDB9
U_MMDB10
U_MMDB11
U_MMDB12
U_MMDB13
U_MMDB14
U_MMDB15
D8
DQSU
DQL7
B9
D1
R1
A9
E3
U_MMDB0
U_MMDB1
U_MMDB2
U_MMDB3
U_MMDB4
U_MMDB5
U_MMDB6
U_MMDB7
M9
N9
NC_6
E7
U_MMDMB0
U_MMDMB1
J8
DQSL
C7
G8
J2
N1
DQSL
U_MMDQSBP1
U_MMDQSBN1
B3
K8
J1
NC_1
T2
G3
K2
A1
WE
U_MMDQSBP0
U_MMDQSBN0
G7
BA1
L9
U_MMAA14
AVDD_DDR_URSA7
D9
VDD_9
L2
K1
240
1%
B2
J7
K7
R1715
A7
BA2
U_MMRESETB
B1
VSSQ_1
DQU0
U_MVREFDQ_B0
A2
M2
J9
L1
VREFCA
A1
NC_5
U_MMCSB0
U_MMODTB
U_MMRASB
U_MMCASB
U_MMWEB
F1
M8
A0
M7
E9
DQL6
D7
C3
R8
A9
E7
D3
P2
U_MMCKEB
D2
DQSL
B7
P8
U_MMBKB0
U_MMBKB1
U_MMBKB2
AVDD_DDR_URSA7
NC_6
C7
N2
R9
J1
NC_2
P3
U_MMAB15
R1
VDDQ_9
NC_1
T2
P7
N9
A1
VDDQ_1
AC30
T31
D9
U_MMCKBP0
WE
G3
AVDD_DDR_URSA7
BA1
L2
K1
240
1%
VDD_9
BA2
K9
R1713
B2
A9
NC_3
U_MMDB10
P31
L8
ZQ
A7
NC_5
M3
H1
VREFDQ
A5
N3
U_MMAB0
U_MMAB1
U_MMAB2
U_MMAB3
U_MMAB4
U_MMAB5
U_MMAB6
U_MMAB7
U_MMAB8
U_MMAB9
U_MMAB10
U_MMAB11
U_MMAB12
U_MMAB13
U_MVREFDQ_A0
A2
M7
N8
VREFCA
A1
U_MMDB9
N28
AB32
C25
B24
R30
B_DDR3_DQS1B
C28
E22
U_MMDB3
P3
K7
U_MMCSA0
U_MMODTA
U_MMRASA
U_MMCASA
U_MMWEA
U_MMDB2
M29
P7
M8
J7
U_MMDB1
T29
N3
N31
A_DDR3_DQS1B
U_MMDQSAN1
U_MMBKA0
U_MMBKA1
U_MMBKA2
U_MMCKEA
U_MMDB0
L29
B_DDR3_DM1
B19
U_MVREFCA_B0
U_MMAB6
G28
J28
A_DDR3_RASZ
IC2800
H5TQ1G63EFR-PBC
U_MVREFCA_A0
U_MMAB5
56
U_MMAA3
B_DDR3_A1
56
D12
B_DDR3_A0
A_DDR3_A1
R1714 R1712
U_MMAA2
H29
A_DDR3_A0
56
D14
56
B11
U_MMAA1
R1751 R1750
U_MMAA0
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
B9
D1
D8
E2
E8
F9
G1
G9
Y28
W30
U29
AA32
W32
A_DDR3_DQS2
B_DDR3_DQS2
A_DDR3_DQS2B
B_DDR3_DQS2B
A_DDR3_DQS3
B_DDR3_DQS3
A_DDR3_DQS3B
V30
V31
U30
B_DDR3_DQS3B
DDR PHY VREF
+1.5V_P_DDR
AVDD_DDR_URSA7
Close to DDR POWER PIN
L1700
AVDD_DDR_URSA7
U_MVREFCA_A0
R1702
1K
1%
R1703
1K
1%
AVDD_DDR_URSA7
U_MVREFDQ_A0
R1704
1K
1%
C1700
0.1uF
C1701
1000pF
R1705
1K
1%
AVDD_DDR_URSA7
U_MVREFCA_B0
C1703
1000pF
R1709
1K
1%
C1704
0.1uF
C1705
1000pF
R1711
1K
1%
C1713
0.1uF
16V
C1715
1uF
10V
C1716
10uF
10V
OPT
C1717
10uF
10V
C1721
0.1uF
16V
C1722
1uF
10V
C1723
10uF
10V
OPT
C1724
10uF
10V
U_MVREFDQ_B0
C1708
0.1uF
16V
R1710
1K
1%
R1708
1K
1%
C1702
0.1uF
AVDD_DDR_URSA7
C1706
0.1uF
C1707
1000pF
C1710
0.1uF
16V
C1711
0.1uF
16V
C1712
0.1uF
16V
AVDD_DDR_URSA7
Close to DDR POWER PIN
C1714
0.1uF
16V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
C1718
0.1uF
16V
C1719
0.1uF
16V
C1720
0.1uF
16V
EAX65309301
URSA7_DDR_A
2013.03.18
17
22
LGE Internal Use Only
IC2500
LGE7410
URSA Reset
Clock for URSA7
AA28
URSA7_Reset
R1925
1M
24MHz
X1900
2
4
3
C1904
AL3
XO_URSA
+3.3V
I2CS_SDA
I2CS_SCL
SW1901
JTP-1127WEM
XO_URSA
1
OPT
C1902
22uF
10V
3
4
URSA7_Reset
0
R1924
100V
R1923
10K
D1900
1N4148W
R1963
R1964
33
AJ22
33
AH23
AG25
UART2_TX
UART2_RX
UART2_RX
UART1_TX
UART1_TX
UART1_RX
UART1_RX
R1929
33
E8
R1927
33
D8
33
D9
R1926
33
E9
SPI2_CK/PWM0/GPIO56
SPI2_DI/PWM1/GPIO57
I2CM_SDA
SPI3_CK/DIM10/GPIO54
I2CM_SCL/VSYNC_LIKE1
SPI3_DI/DIM11/GPIO55
SPI4_CK/DIM8/GPIO52
GPIO[0]/UART2_TX
AD32
SPI Flash
AE32
SPI_DO
URSA7_stable
+3.3V
L1900
MLB-201209-0120P-N2
0
AB29
OPT R1933
33
AA29
OPT R1931
33
AH25
OPT R1932
33
AG26
OPT R1934
33
F8
R1930
CS#
SPI_CZ
1
8
AF27
AG27
R1944
33
L_DIM_EN
AG28
AH20
DIM1/GPIO[33]
SPI_CZ
DIM2/GPIO[34]
SPI_CK
DIM3/GPIO[35]
SPI_DI
DIM4/GPIO[36]
SPI_DO
DIM5/GPIO[37]
DIM6/GPIO[38]
INT_R21/GPIO[41]
DIM0
AG20
DIM1
AJ21
AH21
DIM2
R1945
R1950
R1940
33 OPT
AH22
R1935
33 OPT
AG23
R1951
33 OPT
AG21
AG22
DIM7/GPIO[39]
33 OPT
33 OPT
INT_R20/GPIO[42]
GPIO[10]/PWM_DIM_IN[0]
E7
NC_21
NC_22
IRE
AA27
VCC
AG29
VSYNC_LIKE/PWM5/GPIO40
NC_23
NC_25
AA26
33
AE27
GPIO[2]/UART1_TX
NC_24
10K
AF28
AD27
GPIO[11]/PWM_DIM_IN[1]
C1901
0.1uF
25V
AE29
SPI4_DI/DIM9/GPIO53
GPIO[3]/UART1_RX
AD30
SPI_DI
R1903
I2CS_SCL
DIM0/GPIO[32]
SPI_CK
R1909
SPI1_DI/PWM3/GPIO59
AE31
SPI_CZ
IC1901
MX25L3206EM2I-12G
AE28
SPI1_CK/PWM2/GPIO58
I2CS_SDA
GPIO[1]/UART2_RX
R1928
AJ24
VSYNC_LIKE3
AG24
I2CM_SCL_URSA
UART2_TX
XTALO
XTALI
I2CM_SDA_URSA
2
AH24
VSYNC_LIKE2
AM3
XIN_URSA
GND_2
X-TAL_2
8pF
RESET
XIN_URSA
1
GND_1
X-TAL_1
8pF
C1903
TESTPIN
NC_26
GND_EFUSE
NC_27
F7
D6
D5
E6
E5
F6
F5
NC_28
R1904
33
SO/SIO1
R1905
1K
WP#
SPI_DO
2
7
3
6
HOLD#
Debugging for URSA
AF4
VX1T_HTPDN
UART2_TX
R1919
33
SPI_CK
R1910
OPT
OPT
SCLK
VX1T_LOCKN
I2CM_SDA1
I2C_S Port
10K
GND
4
5
SI/SIO0
R1920
33
SPI_DI
I2CM_SCL1
P1905
TGPIO12
12507WS-04L
WAFER-STRAIGHT
3D_FLAG
TGPIO14
SW1902
JS2235S
1
AE4
AF5
R1936
0
AG4
AH4
R1946
R1941
R1937
0
33 OPT
0
AH5
R1942
33 OPT
AG5
AJ5
TGPIO15
4MByte
FLASH_WP
R1939
FLASH_WP_U
2
1
SCL_M1_A
R1922
3
FLASH_WP_U
I2CM_SDA1_URSA
I2CM_SCL1_URSA
33
SCL2_+3.3V_DB
URSA_DEBUG
0
OPT
R1921
4
I2CS_SCL
R1960
0
OPT
33
SDA2_+3.3V_DB
URSA_DEBUG
R1958
0
URSA_MP
SCL2_+3.3V_DB
6
2
5
URSA_DEBUG
3
4
SDA_M1_A
R1959
0
URSA_MP
I2CS_SDA
R1961
0
OPT
SDA2_+3.3V_DB
5
I2C EEPROM
+3.3V
I2C_M Port
1
8
2
7
3
6
VCC
P1908
R1918
4.7K
A0
R1917
4.7K
IC2007
R1EX24256BSAS0A
C1900
0.1uF
25V
12507WS-04L
WAFER-STRAIGHT
1
A1
WP
2
A2
VSS
4
5
SCL
IC2500
LGE7410
I2CM_SCL_EEPROM
3
I2CM_SCL_M_Port
4
I2CM_SDA_M_Port
SDA
I2CM_SDA_EEPROM
5
AH28
AH29
R1913
33
I2CM_SCL_URSA
R1911
33 OPT
R1916
33
R1915
33
R1912
33 OPT
R1914
33
AJ27
AJ28
I2CM_SCL1_URSA
I2CM_SCL_EEPROM
AH32
I2CM_SCL_M_Port
I2CM_SDA_URSA
I2CM_SDA1_URSA
I2CM_SDA_EEPROM
I2CM_SDA_M_Port
AH31
AG32
AG30
AF30
AG31
AE30
AF31
GPIO[8]/HDMIRX_CEC
GPIO[9]/HDMIRX_HPD
GPIO[6]/DDCDA_CK
GPIO[7]/DDCDA_DA
HDMI_RXCP
HDMI_RXCN
HDMI_RX0P
HDMI_RX0N
HDMI_RX1P
HDMI_RX1N
HDMI_RX2P
HDMI_RX2N
AH26
Chip Config
AH27
AJ25
Debug/ISP ADDR
Slabe (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
CHIP_CONF=3’d7:111:boot from SPI Flash
AJ26
AL31
AM31
+3.3V
AK31
DIM0
10K
OPT
10K
R1902
R1908
10K
R1901
DIM1
AK32
AH30
R1907
AJ31
DIM2
OPT
10K
R1900
AJ30
10K
OPT
AL32
GPIO[4]/HDMITX_CEC
GPIO[5]/HDMITX_HPD
HDMITX_SCL
HDMITX_SDA
HDMITX_CLKP
HDMITX_CLKN
HDMI_TX0P
HDMI_TX0N
HDMI_TX1P
HDMI_TX1N
HDMI_TX2P
HDMI_TX2N
10K
R1906
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
EAX65309301
2013.03.18
U_UART,GPIO
20
22
LGE Internal Use Only
IC2500
LGE7410
IC2500
LGE7410
A8
+3.3V
AVDD_PLL
+3.3V
VDDP
G8
H8
J8
L2103
BLM18PG121SN1D
L2102
BLM18PG121SN1D
K8
C2100
4.7uF
10V
C2102
0.1uF
16V
C2145
0.1uF
16V
C2150
0.1uF
16V
C2154
0.1uF
16V
C2158
4.7uF
10V
C2162
4.7uF
10V
L8
C2164
4.7uF
10V
M8
N8
IC2500
LGE7410
P8
R8
T8
AVDD_LVDS
VDDC
AA10
Y11
AA11
AB11
Y12
AA12
AB12
AC7
AD7
AE7
AB8
AC8
AD8
AE8
AA9
AB9
AC9
AD9
AB10
AC10
AVDDL_TX_RX
AVDDL_TX_RX
AA14
AA13
AB13
VSS_2
VDDC_3
VSS_3
VDDC_4
VSS_4
VDDC_5
VSS_5
VDDC_6
VSS_6
VDDC_7
VSS_7
VDDC_8
VSS_8
VDDC_9
VSS_9
VDDC_10
VSS_10
VDDC_11
VSS_11
VDDC_12
VSS_12
VDDC_13
VSS_13
VDDC_14
VSS_14
VDDC_15
VSS_15
VDDC_16
VSS_16
VDDC_17
VSS_17
VDDC_18
VSS_18
VDDC_19
VSS_19
VDDC_20
VSS_20
VSS_21
AVDDL_HDMITX
VSS_22
AVDDL_LVDSRX_1
VSS_23
AVDDL_LVDSRX_2
VSS_24
AVDDL_VB1RX_1
VSS_25
AVDDL_VB1RX_2
DVDD_DDR
AVDDL_MOD_DRV
R11
W10
W11
AVDDL_MOD_DRV
Y10
R12
T11
T12
U11
U12
V11
AVDD_LVDS
VSS_28
DVDD_DDR
VSS_29
VSS_30
AVDDL_MOD_1
AVDDL_MOD_2
M12
N12
AA18
AA19
Y21
AB19
AB17
AB18
AC17
AA20
Y20
VSS_33
VSS_34
AVDDL_MOD_5
VSS_35
AVDDL_MOD_6
VSS_36
AVDDL_DRV_1
VSS_37
AVDDL_DRV_2
VSS_38
AVDDL_DRV_3
VSS_39
AVDDL_DRV_4
VSS_40
AVDDL_DRV_5
VSS_41
AVDDL_DRV_6
VSS_42
VSS_43
AVDD_MOD_1
VSS_44
AVDD_MOD_2
VSS_45
AVDD_MOD_3
VSS_46
AVDD_MOD_4
VSS_47
VSS_48
VDDP_1
VSS_50
VDDP_3
VSS_51
VDDP_4
VSS_52
AVDD_DVI
VSS_53
AVDD_HDMITX
VSS_54
AVDD_LVDSRX_1
VSS_55
AVDD_LVDSRX_2
VSS_56
AVDD_LVDSRX_3
VSS_57
AVDD_VB1RX_1
VSS_58
VSS_59
VSS_60
AA17
Y17
VSS_49
VDDP_2
AVDD_VB1RX_2
AVDD_PLL
VSS_32
AVDDL_MOD_4
Y18
Y19
VSS_31
AVDDL_MOD_3
M11
N11
VDDP
DVDD_DDR_RX
P11
P12
VSS_26
VSS_27
W15
Y15
VSS_1
VDDC_2
AA16
AB14
AVDDL_TX_RX
VDDC_1
AVDD_XTAL
VSS_61
AVDD_PLL
VSS_62
U8
AD1
V8
AH1
W8
L2104
BLM18PG121SN1D
J2
Y8
T2
C2146
0.1uF
16V
AF2
AK2
C2151
0.1uF
16V
C2155
0.1uF
16V
C2163
4.7uF
10V
C2159
4.7uF
10V
AA8
C2119
4.7uF
10V
AF8
AG8
AM2
AH8
K3
AJ8
M3
B9
P3
F9
J4
K4
G9
+1.15V
VDDC
H9
L4
J9
M4
L2108
BLM18PG121SN1D
K9
N4
L9
AA4
C2101
4.7uF
10V
AB4
AC4
L2110
BLM18PG121SN1D
C2104
4.7uF
10V
C2108
0.1uF
16V
C2117
0.1uF
16V
C2124
0.1uF
16V
C2111
10uF
10V
C2112
10uF
10V
C2007
10uF
10V
M9
N9
P9
AD4
R9
AJ4
T9
AB5
U9
AVDDL_MOD_DRV
AC5
V9
J5
W9
K5
L2105
BLM18PG121SN1D
Y9
L5
AE9
M5
C2109
0.1uF
16V
N5
AD5
C2118
0.1uF
16V
C2130
0.1uF
16V
C2136
0.1uF
16V
AE5
AF9
G10
H10
J10
J6
K10
K6
L10
DVDD_DDR
L6
M10
M6
N10
L2106
BLM18PG121SN1D
N6
P10
AA6
R10
C2110
0.1uF
16V
AB6
AC6
C2002
0.1uF
16V
C2004
1uF
10V
C2006
1uF
10V
AD6
T10
U10
V10
AE6
AD10
AF6
AE10
AG6
AVDDL_TX_RX
AF10
AH6
C11
AJ6
F11
L2107
BLM18PG121SN1D
G7
G11
C2000
0.1uF
16V
H7
J7
C2001
0.1uF
16V
C2003
0.1uF
16V
C2005
0.1uF
16V
H11
J11
K7
K11
L7
L11
M7
AC11
N7
AD11
P7
AE11
R7
AF11
T7
C12
U7
F12
V7
G12
W7
H12
Y7
J12
AA7
K12
AB7
L12
AF7
V12
AG7
W12
AH7
AC12
AJ7
AD12
VSS_63
AE12
AVDD_DDR_URSA7
M18
M19
M20
M21
M16
M17
AF12
AVDD_DDR0_D_1
C13
AVDD_DDR0_D_2
F13
AVDD_DDR0_D_3
G13
AVDD_DDR0_D_4
H13
AVDD_DDR0_C_1
J13
AVDD_DDR0_C_2
K13
L13
AVDD_DDR_URSA7
P21
R21
P22
R22
N21
N22
M13
AVDD_DDR1_D_1
DDR3 POWER
N13
AVDD_DDR1_D_2
AVDD_DDR1_D_3
AVDD_DDR1_D_4
AVDD_DDR1_C_1
AVDD_DDR1_C_2
C2103
0.1uF
16V
C2105
0.1uF
16V
C2106
0.1uF
16V
C2107
0.1uF
16V
C2148
0.1uF
16V
C2153
1uF
10V
C2157
10uF
10V
OPT
C2161
10uF
10V
VSS_64
VSS_150
VSS_65
VSS_151
VSS_66
VSS_152
VSS_67
VSS_153
VSS_68
VSS_154
VSS_69
VSS_155
VSS_70
VSS_156
VSS_71
VSS_157
VSS_72
VSS_158
VSS_73
VSS_159
VSS_74
VSS_160
VSS_75
VSS_161
VSS_76
VSS_162
VSS_77
VSS_163
VSS_78
VSS_164
VSS_79
VSS_165
VSS_80
VSS_166
VSS_81
VSS_167
VSS_82
VSS_168
VSS_83
VSS_169
VSS_84
VSS_170
VSS_85
VSS_171
VSS_86
VSS_172
VSS_87
VSS_173
VSS_88
VSS_174
VSS_89
VSS_175
VSS_90
VSS_176
VSS_91
VSS_177
VSS_92
VSS_178
VSS_93
VSS_179
VSS_94
VSS_180
VSS_95
VSS_181
VSS_96
VSS_182
VSS_97
VSS_183
VSS_98
VSS_184
VSS_99
VSS_185
VSS_100
VSS_186
VSS_101
VSS_187
VSS_102
VSS_188
VSS_103
VSS_189
VSS_104
VSS_190
VSS_105
VSS_191
VSS_106
VSS_192
VSS_107
VSS_193
VSS_108
VSS_194
VSS_109
VSS_195
VSS_110
VSS_196
VSS_111
VSS_197
VSS_112
VSS_198
VSS_113
VSS_199
VSS_114
VSS_200
VSS_115
VSS_201
VSS_116
VSS_202
VSS_117
VSS_203
VSS_118
VSS_204
VSS_119
VSS_205
VSS_120
VSS_206
VSS_121
VSS_207
VSS_122
VSS_208
VSS_123
VSS_209
VSS_124
VSS_210
VSS_125
VSS_211
VSS_126
VSS_212
VSS_127
VSS_213
VSS_128
VSS_214
VSS_129
VSS_215
VSS_130
VSS_216
VSS_131
VSS_217
VSS_132
VSS_218
VSS_133
VSS_219
VSS_134
VSS_220
VSS_135
VSS_221
VSS_136
VSS_222
VSS_137
VSS_223
VSS_138
VSS_224
VSS_139
VSS_225
VSS_140
VSS_226
VSS_141
VSS_227
VSS_142
VSS_228
VSS_143
VSS_229
VSS_144
VSS_230
VSS_145
VSS_231
VSS_146
VSS_232
VSS_147
VSS_233
VSS_148
VSS_234
VSS_149
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
P13
AG17
R13
AH17
T13
AJ17
U13
B18
V13
F18
W13
G18
Y13
H18
AC13
J18
AD13
K18
AE13
L18
AF13
N18
AG13
P18
AH13
R18
AJ13
T18
B14
U18
F14
V18
G14
W18
H14
AC18
J14
AD18
K14
AE18
L14
AF18
M14
AG18
N14
AH18
P14
AJ18
R14
F19
T14
G19
U14
H19
V14
J19
W14
K19
Y14
L19
AC14
N19
AD14
P19
AE14
R19
AF14
T19
AG14
U19
AH14
V19
AJ14
W19
A15
F15
AC19
G15
AD19
H15
AE19
J15
AF19
K15
AG19
L15
AH19
M15
AJ19
N15
C20
P15
F20
R15
G20
T15
H20
U15
J20
V15
K20
AA15
L20
AB15
N20
AC15
P20
AD15
R20
AE15
T20
AF15
U20
AG15
V20
AH15
W20
AJ15
B16
AC20
G16
AD20
H16
AE20
J16
AF20
K16
AJ20
L16
C21
N16
F21
P16
G21
R16
H21
T16
J21
U16
K21
V16
L21
W16
T21
Y16
U21
AB16
V21
W21
AD16
AE16
AA21
AF16
AB21
AG16
AC21
AH16
AD21
AJ16
AE21
A17
AF21
F17
C22
G17
F22
H17
G22
J17
H22
K17
J22
L17
K22
N17
L22
P17
M22
R17
T22
T17
AB22
U17
AA22
V17
Y22
W17
W22
AD17
V22
AE17
U22
AF17
P23
N23
M23
L23
K23
J23
H23
G23
F23
B23
AF22
AE22
AD22
AC22
U23
T23
R23
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
VSS_363
VSS_251
VSS_364
VSS_252
VSS_365
VSS_253
VSS_366
VSS_254
VSS_367
VSS_255
VSS_368
VSS_256
VSS_369
VSS_257
VSS_370
VSS_258
VSS_371
VSS_259
VSS_372
VSS_260
VSS_373
VSS_261
VSS_374
VSS_262
VSS_375
VSS_263
VSS_376
VSS_264
VSS_377
VSS_265
VSS_378
VSS_266
VSS_379
VSS_267
VSS_380
VSS_268
VSS_381
VSS_269
VSS_382
VSS_270
VSS_383
VSS_271
VSS_384
VSS_272
VSS_385
VSS_273
VSS_386
VSS_274
VSS_387
VSS_275
VSS_388
VSS_276
VSS_389
VSS_277
VSS_390
VSS_278
VSS_391
VSS_279
VSS_392
VSS_280
VSS_393
VSS_281
VSS_394
VSS_282
VSS_395
VSS_283
VSS_396
VSS_284
VSS_397
VSS_285
VSS_398
VSS_286
VSS_399
VSS_400
VSS_287
VSS_401
VSS_288
VSS_402
VSS_289
VSS_403
VSS_290
VSS_404
VSS_291
VSS_405
VSS_292
VSS_406
VSS_293
VSS_407
VSS_294
VSS_408
VSS_295
VSS_409
VSS_296
VSS_410
VSS_297
VSS_411
VSS_298
VSS_412
VSS_299
VSS_413
VSS_300
VSS_414
VSS_301
VSS_415
VSS_302
VSS_416
VSS_303
VSS_417
VSS_304
VSS_418
VSS_305
VSS_419
VSS_306
VSS_420
VSS_307
VSS_421
VSS_422
AB20
F16
AC16
V23
VSS_250
VSS_308
VSS_423
VSS_309
VSS_424
VSS_310
VSS_425
VSS_311
VSS_426
VSS_312
VSS_427
VSS_313
VSS_428
VSS_314
VSS_429
VSS_315
VSS_430
VSS_316
VSS_431
VSS_317
VSS_432
VSS_318
VSS_433
VSS_319
VSS_434
VSS_320
VSS_435
VSS_321
VSS_436
VSS_322
VSS_437
VSS_323
VSS_438
VSS_324
VSS_439
VSS_440
VSS_325
VSS_441
VSS_326
VSS_442
VSS_327
VSS_443
VSS_328
VSS_444
VSS_329
VSS_445
VSS_330
VSS_446
VSS_331
VSS_447
VSS_332
VSS_448
VSS_333
VSS_449
VSS_334
VSS_450
VSS_335
VSS_451
VSS_336
VSS_452
VSS_337
VSS_453
VSS_338
VSS_454
VSS_339
VSS_455
VSS_340
VSS_456
VSS_341
VSS_457
VSS_342
VSS_458
VSS_343
VSS_459
VSS_344
VSS_460
VSS_345
VSS_461
VSS_346
VSS_462
VSS_347
VSS_463
VSS_348
VSS_464
VSS_349
VSS_465
VSS_350
VSS_466
VSS_351
VSS_467
VSS_352
VSS_468
VSS_353
VSS_469
VSS_354
VSS_470
VSS_355
VSS_471
VSS_356
VSS_472
VSS_357
VSS_473
VSS_358
VSS_474
VSS_359
VSS_475
VSS_360
VSS_476
VSS_361
VSS_477
VSS_362
VSS_478
EAX65309301
U_Power
W23
Y23
AA23
AB23
AC23
AD23
AE23
AF23
A24
F24
G24
H24
J24
K24
L24
M24
N24
P24
R24
T24
U24
V24
W24
Y24
AA24
AB24
AC24
AD24
AE24
AF24
B25
F25
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
V25
W25
Y25
AA25
AB25
AC25
AD25
AE25
AF25
A26
E26
F26
G26
H26
J26
K26
L26
M26
N26
P26
R26
T26
U26
V26
W26
Y26
AB26
AC26
AD26
AE26
AF26
B27
E27
F27
G27
H27
J27
K27
L27
M27
N27
P27
R27
T27
U27
V27
W27
Y27
D28
E28
F28
C29
D30
L30
M30
N30
Y30
AA30
AB30
A31
F31
H31
K31
R31
U31
W31
AD31
B32
G32
J32
T32
V32
2013.03.18
21
22
LGE Internal Use Only
3.3V for URSA7+PA168
2.5V for PA168
MAX 1.58A
1.15V for URSA7
MAX 1.17A
MAX 3.9A
+12V
+2.5V
+3.3V
IC3001
AP2132MP-2.5TRG1
L1405
BLM18PG121SN1D
+1.15V
[EP]
+12V
C3001
1uF
5
C1408
2200pF
50V
1uF
10V
C1425
22uF
22uF
10V
10V
6A
5
R2305
6.8K
COMP
Vout=0.765*(1+R1/R2)=3.33V
C2319
47pF
50V
OPT
+3.3V
C2313
0.1uF
16V
R2306
10K
Vout=0.6*(1+R1/R2)=2.55V
R1
R2
Vout=0.8*(1+R1/R2)=1.209V
UD_VCC
1.5V for URSA7_DDR
C2318
10uF
10V
ZD2306
5V
4
C2317
10uF
10V
C2314
6800pF
50V
OPT
FB
R3000
1K
1%
GND
C1421
C2312
0.1uF
25V
OPT
EN
ZD2301
5V
3A
C3003
10uF
16V
C2311
10uF
25V
C2316
10uF
10V
C2315
10uF
10V
SW_1
1%
SW
OPT
C1404
4
EAN61387601
5V
L1403
3.6uH
NR8040T3R6N
SS
NC
6
3
SW_2
R2308
1.8K
R3008
1.3K
1%
C2310
10uF
25V
5
7
1%
6
2A
VCTRL
C1412
0.1uF 16V
2
R2309
220
3
VBST
4
AGND
8
1
1%
VREG5
R1406
15K
1%
7
+12V
VIN
GND JIG POINT
+12V
JP2200
MAX 1.59A
C1511
10uF
25V
+1.5V_P_DDR
C1514
0.1uF
25V
L2203
MLB-201209-0120P-N2
L2204
MLB-201209-0120P-N2
L2205
MLB-201209-0120P-N2
C1517
10uF
25V
JP2203
R2
2
C3000
10uF
16V
+3.3V
VIN
Placed on SMD-TOP
JP2202
VFB
8
9
1
PGND
R1
VOUT
JP2201
EN
R3009
3.9K
6
L2303
2uH
[EP]
R2310
3.3K
ADJ
3
IC2301
BD86106EFJ
9
EN
L2302
BLM18PG121SN1D
7
VIN
THERMAL
R1407
51K
1%
R3001
10K
[EP]GND
R2
ZD3000
5V
10K
OPT
C1405
100pF
50V
R3011
1.2K
GND
OPT
IC1100
TPS54327DDAR
R1410
R1
2
C1422
10uF
16V
8
9
PG
THERMAL
1
C3002
0.1uF
THERMAL
+3.3V
C1518
0.1uF
25V
+12V
DEV_BD9C401EFJ_4A
C1401
0.1uF
25V
FB
7
6
3
4
4A
5
SW_2
C1415
10uF
10V
SW_1
EN
COMP
C1416
10uF
10V
C1417
10uF
10V
C1419
10uF
10V
C1420
68pF
50V
C1414
R1400 0.0068uF
7.5K
1%
UD_VCC
PANEL_POWER
R1
ZD1400
5V
C1407
10uF
25V
2
50V
L1412
TYP 6000mA
L1413
MLB-201209-0120P-N2
OPT
AGND
C1403
10uF
25V
8
1
9
VIN
THERMAL
PGND
Placed on SMD-TOP
L1404
4.7uH
[EP]
1%
IC1401
BD9C401EFJ
R1402
16K
L1402
BLM18PG121SN1D
R1437
0
MLB-201209-0120P-N2
PANEL_VCC
OPT
[DEV]
C1454
10uF
25V
OPT
R1401
10K
1%
R1408
18K
+3.3V
C1411
0.1uF
16V
R2
C1455
0.1uF
25V
C1456
0.01uF
50V
Q1401
AO4423
S1
C1458
10uF
25V
R1434
10K
S2
C1459
10uF
25V
S3
PANEL_CTL
G
1
8
2
7
3
6
4
5
D4
D3
D2
R1438
2K
OPT
D1
R1440
2K
OPT
C1466
10uF
25V
OPT
C1467
0.1uF
25V
R1433
Vout=0.8*(1+R1/R2)=1.51V
1.8K
R1431
C1463
10uF
25V
10K
R1432
10K
R1430
C
Q1400
2SC3052
B
OPT
E
3.3K
1.05V for PA168_A
1.05V for PA168_B
MAX 3.5A
MAX 3.5A
P1400
SMAW200-10
+1.05V_A
UD_VCC
+1.05V_B
Wafer
1
+12V
+12V
3
4
6
6A
5
P1401
COMP
R1403
6.8K
C1410
6800pF
50V
C1423
10uF
10V
C1426
10uF
10V
C1431
47pF
50V
OPT
Placed on SMD-TOP
R1
VIN
AGND
C1432
10uF
25V
C1435
10uF
25V
C1436
0.1uF
25V
OPT
FB
1
2
8
3
4
7
6
6A
5
3
SW_2
C1449
10uF
10V
SW_1
EN
COMP
R1411
6.8K
C1469
10uF
10V
C1444
6800pF
50V
C1470
10uF
10V
C1471
10uF
10V
C1472
47pF
50V
OPT
R1514
3.3K
EN
C1418
10uF
10V
9
PGND
C1413
10uF
10V
THERMAL
SW_2
SW_1
2
[EP]
R1
20037WR-05A00
T-con power
4
ZD2305
5V
FB
7
IC1700
BD86106EFJ
L1407
2uH
1
5
OPT
C1406
0.1uF
25V
OPT
8
ZD2300
5V
C1402
10uF
25V
2
OPT
AGND
C1400
10uF
25V
1
9
VIN
THERMAL
PGND
Placed on SMD-TOP
L1406
BLM18PG121SN1D
[EP]
1%
IC1600
BD86106EFJ
R1513
3.3K
L1400
BLM18PG121SN1D
L1401
2uH
2
PANEL_VCC
R2
C1441
0.1uF
16V
R1412
10K
3
1%
R1404
10K
+3.3V
R1421
10K
C1409
0.1uF
16V
1%
+3.3V
R1405
10K
6
R2
7
L1419
MLB-201209-0120P-N2
4
8
L1418 MLB-201209-0120P-N2
5
9
6
10
Vout=0.8*(1+R1/R2)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Vout=0.8*(1+R1/R2)
EAX65309301
DC-DC POWER
C1462
10uF
25V
C1464
0.1uF
25V
C1465
10uF
25V
C1468
0.1uF
25V
2013.03.18
22
22
LGE Internal Use Only
LCD TV Repair Guide
`13 years New Models
< Applicable Model >
XXLA965V-ZA
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Main PCB
XXLA965V-ZA
Woofer
Power
From PSU
1
FRC B/D (ULTRA HD)
wifi
Motion assy
1
3
Front Spk
Local Key +IR
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
2
4
5
Main processor_Digital(LG1152D),
DDR Memory
eMMC Memory
2
Main processor_analog(LG1152A)
3
Micom for Key/IR sensing
4
Audio AMP (50W)
5
HDMI switch
LGE Internal Use Only
FRC PCB(ULTRA HD)
XXLA965V-ZA
2
3
1
Main B/D
1
Module
Power
Power
From PSU To Tcon
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Video processor (LGE7410:URSA7),
DDR Memory
Flash Memory
2
Video processor Master (PA168),
DDR Memory
Flash Memory
3
Video processor Slave (PA168),
DDR Memory
Flash Memory
LGE Internal Use Only
H13 Block diagram
External I/O
PC_Audio_L/R
PC_AUDIO
M-Remote_Rx/Tx
AV1_CVBS
AV1_Audio L/R
AV1
Comp1 Y,Pb,Pr
COMP1
Motion-R
H13
LG1154AN
H13
LG1154D
SPDIF
OPTIC
X-TAL
24MHZ
SC_CVBS, RGB, Audio L/R
SCART
DTV/MNT_LR/V_OUT
RS-232C
AUD_SCK/LRCK/LRCH
HDMI1
MHL
1A
H/P
Line out
H/P AMP
Tuner
Audio
AMP
L/R SPK
Audio
AMP
Woofer
Audio
AMP
Height SPK
SPDIF_OUT_ARC
AUD_LRCH1
HDMI2
HDMI
Switch
HDMI3
CI
CI
HDMI_CEC
MOTOR CTRL/SW DET
HEVC HDMI Tx
LG1132-D13
HEVC
DECODER
HEVC TS
LED/Logo Light
DDR3
WOL / WOW
LAN
1Gb X 4
16
(800Mhz)
PHY
LVDS 41P
USB 2.0
USB_W-iFi
LVDS 51P
USB 3.0
USB1(USB3.0)
USB2(USB2.0)
USB 2.0
USB3(USB2.0)
USB 2.0
BUILT-IN CAMERA
USB HUB
: Not applied for
55/65LA965V
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
URSA7
OCP
1A
DDR3
DDR3
1Gb X 2
16
(667Mhz)
PA168
MASTER
Vby1
51P
16
1Gb X 2
(667Mhz)
PA168
SLAVE
Vby1
41P
EEPROM
OCP
1A
T-CON
8
16
8
DDR3
4Gb×4
(1600)
DDR3
4Gb×2
(1600)
eMMC
16GB×1
LGE Internal Use Only
H13 Block diagram
23 [SDA]
33 Ω
33Ω
I2C_SCL1
AR15
[SCL0/GPIO66]
I2C_SDA1
AP15
[SDA0/GPIO65]
33 Ω
AP6
[SCL3]
I2C_SCL4
22 Ω
AR6
[SDA3]
I2C_SDA
4
22 Ω
I2C_SCL_MICOM_SO
C
I2C_SDA_MICOM_SOC
33Ω
H13
LG1154D
AR16
[SCL1/GPIO6
4]
AP16
[SDA1/GPIO7
9]
IC5800
TAS5733
AMP HEIGHT
I2C_SCL6
33 Ω
AH33
[SDA5]
I2C_SDA
6
33 Ω
[D_SDA]
35
[SCL_T]
3
[SDA_T]
4
+3.3V_NOR
3.3k Ω
3.3k Ω
3.3k Ω
33 Ω
34
TU6503
TDSQ-G651D
TUNER_T2/C/S2
AH34
[SCL5]
+3.3V_NOR
IC12000
B11
[
LG1132-D13
HEVC DECODER
[D_SCL]
+3.3V_TU
3.3k Ω
3.3k Ω
3.3k Ω
1 [P60/SCLA0]
2 [P61/SDAA0]
33 Ω
[SCL] 7 IC6900
A8303SESTR-T
[SDA] 8 LNB
33Ω
+3.3V_NOR
IC3000
R5F100GEAFB
RENESAS
MICOM
3.3k Ω
3.3k Ω
33 Ω
33 Ω
3.3k Ω
24 [SCL]
+3.3V_TU
3.3k Ω
IC5600
TAS5733
AMP MAIN
0Ω
+3.3V_NOR
3.3k Ω
24 [SCL]
IC5700
TAS5733
23 [SDA]
AMP WOOFER
0Ω
3.3k Ω
P7201
4 [SCL]
FI-RE51S-HF-J-R1500
LVDS 51P WAFER5 [SDA]
(to URSA7, PA168)
I2C Map
33 Ω
33 Ω
[SCL] 6 IC102
R1EX24256BSAS0A
[SDA] 5 NVRAM
33Ω
24
[SCL]
23
[SDA]
I2C_SCL2_SOC
33 Ω
I2C_SDA2_SOC
33 Ω
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
AP17
[SCL2/GPIO7
8]
AR17
[SDA2/GPIO7
7]
AH32
[SCL4]
I2C_SCL5
33 Ω
AJ33
[SDA4]
I2C_SDA
5
33 Ω
[CSCL]
[CSDA]
63
IC3201
SII9587CNUC
62HDMI_SW
LGE Internal Use Only
H13 Block diagram
TDSQG651D
[+3.3V_S2_DEMOD] 32
[+3.3V_TUNER] 5
+3.3V_D_Demod
+3.3V_TU
+1.8_TU
+1.23V_D_Demod
+3.3V_NORMAL
[+.1.8V_TUNER] 7
CI Slot
3.3K Ω
[+1.23V_S2_DEMOD] 30
[S2_F22_OUTPUT]
[LNB]
[S2_SCL]
[S2_SDA]
Tuner Block
PCM_5V_CTL
LNB_TX
33
36
34
35
22 Ω
I2C_SCL4
I2C_SDA4
LNB
2 [LNB]
IC6900
7 [SCL]
A8303SESTR-TB
[SLC] 3
[SDA] 4
[ERROR]
[SYNC]
[VALID]
[MCLK]
16
17
18
19
100Ω
+5V_CI_ON
LG1154
/TU_RESET1
AG6[GPIO10]
H32
[CAM_VCCEN_N]
D32[CAM_CD1_N]
F33[CAM_CE1_N]
AH33 [SDA5]
F34[CAM_CE2_N]
FE_DEMOD1_TS_ERROR
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_CLK
AL37[TP_DVB_ERR]
AL36 [TP_DVB_SOP]
AL35 [TP_DVB_VAL]
AM36 [TP_DVB_CLK]
G34[CAM_RESET]
FE_DEMOD1_TS_DATA [0-7]
[TP_DVB_DATA0-7]
E33[CAM_WAIT]
D33[CAM_INPACK]
D34[CAM_REG]
F32[CAM_IREQ]
[S2_RESET] 31
/S2_RESET
J36[EB_OE]
AM18 [ADIN7_SRV]
H35[EB_WE]
CVBS
V15[CVBS_IN1]
TUNER_SIF
CARD_EN1
CARD_EN2
IOWR
IORD
CI_ADDR[0-14]
CI_A_ADDR[0-14]
CI_DATA[0-7]
CI_A_DATA[0-7]
ADDR[0-14]
DATA[0-7]
PCM_RST
CI_RESET
/PCM_WAIT
PCM_INPACK
CI_WAIT
INPACK
/PCM_REG
REG
/PCM_IRQA
/IRQA
/PCM_OE
/PCM_WE
O_EN
WR_EN
CI_TS_CLK
TS_OUT_CLK
CI_TS_VAL
B28[TPI_VAL]
CI_TS_SYNC
TS_OUT_VAL
TS_OUT_SYNC
H18[AAD_ADC_SIF]
TPI_DATA[0-7]
TPO_DATA[0-7]
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
VS1
/PCM_IORD
B29[TPI_SOP]
[SIF] 6
CI_DET2
/PCM_IOWR
A28[TPI_CLK]
[CVBS] 8
CI_DET1
/PCM_CE2
H36[EB_BE_N1]
[EB_ADDR0-14]
10K Ω
/CI_CD1
/PCM_CE1
H37[EB_BE_N0]
[EB_DATA0-7]
[D0-7] 20-27
+5V_NORMAL
/CI_CD2
CI_VS1
G32[CAM_VS1_N]
IC2_SDA6
IC2_SCL6
33 Ω
10K Ω
E32[CAM_CD2_N]
AH34 [SCL5]
33Ω
VCC
8 [SDA]
AP6 [SCL3]
AR6 [SDA3]
[RESET] 2
+5V_CI_ON
CI 5V
Power detect
10 [TONECTRL]
LNB_OUT
100 Ω
CI_TS_DATA[0-7]
33 Ω
CI_IN_TS_DATA[0-7]
LGE Internal Use Only
H13 Block diagram
Analogue Input
AV1
Phone JACK
AV1_CVBS_IN
AV1_CVBS_IN_SOC
[CVBS_IN3]
COMP1/AV1/DVI_L_IN
AUAD_L/R_CH2_IN
[AUAD_L/R_CH2_IN]
FULL
SCART
(18P)
SC_CVBS_IN
SC_CVBS_IN_SOC
[CVBS_IN2]
SC_R
SC_G
SC_B
SC_CVBS_IN_SOY
SC_FB
SC_ID
SC_L/R_IN
COMP1_PR_IN_SOC
COMP1_Y_IN_SOC
COMP1_PB_IN_SOC
COMP1_Y_IN_SOC_SOY
SC_FB_SOC
SC_ID_SOC
[PR1/Y1/PB1/SOY1_IN]
[SC1_SID]
[SC1_FB]
H13
(LG1154AN)
AUAD_L/R_CH3_IN
[AUAD_L/R_CH3_IN]
Component
1
Phone JACK
COMP1_Y/Pb/Pr
Tuner
TU_CVBS
TUNER_SIF_TU
DIF[P/N]
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
COMP2_PB_IN_SOC
COMP2_Y_IN_SOC
COMP2_Y_IN_SOC_SOY
COMP2_PR_IN_SOC
[PB2/Y2/SOY2/PR2_IN]
TU_CVBS_ISOC
TUNER_SIF
ADC_I_INP/INN
[CVBS_IN1]
[AAD_ADC_SIF]
[ADC_I_INP/INN]
LGE Internal Use Only
H13 Block diagram
Audio I/O
MICOM
SC_L/R_IN
[AUAD_L_CH3_IN]
[AUD_SCART_OUTL/OUTR]
AV_L/R_IN
SCART_MUTE
Mute
CTRL
[TR]
[AUAD_L_CH1_IN]
SCART_Lout/Rout
[AUAD_L_CH2_IN]
[DACSCK]
[DACLRCK]
[DACLRCH]
AZ4580MTR
OP AMP
DTV/MNT_L/R_OUT
SCART
pi filter
AUDIO L/R OUT
MAIN
AUD_SCK/LRCK/LRCH
[SCL0/SDA0]
TAS5733
I2C_SCL1/SDA1
[GPIO21]
LPF
LPF
AMP_RESET_N
H13
LG1154
4P wafer
WOOFER
LPF
LPF
2P wafer
Tuner
AMP_MUTE
MICOM
TUNER_SIF
SIDE_HP_MUTE
[AAD_ADC_SIF]
[AUDA_OUTL]
[PHY0_ARC_OUT_0]
HP_L/ROUT_MAIN
[IEC958OUT]
TPA6138A2
Headphone
AMP
HEADPHONE
LPF
Phone Jack
LINE OUT
SPDIF_OUT
SPDIF_OUT_ARC
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
FRC B/D (ULTRA HD) Block diagram
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Interconnection - 1
XXLA965V-ZA
[PCBs]
7
1
Main PCB
2
PSU
3
WIFI ASSY
4
BT MOTION ASSY
5
IR PCB
1
2
6
4
6
Local Key
7
LED Driver
5
3
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Interconnection – sub PCB( XXLA965V Series )
4
BT MOTION ASSY
5
BT MOTION ASSY
IR PCB
IR Key PCB
3
WIFI ASSY
Local Key
PCB
WIFI ASSY
1
To Main
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Contents of LCD TV Standard Repair Process
No.
Error symptom (High category)
Error symptom (Mid category)
Page
1
No video/Normal audio
1
2
No video/No audio
2
Picture broken/ Freezing
3
4
Color error
4
5
Vertical/Horizontal bar, residual image,
light spot, external device color error
5
6
No power
6
Off when on, off while viewing, power
auto on/off
7
No audio/Normal video
8
9
Wrecked audio/discontinuation/noise
9
10
Remote control & Local switch checking
10
11
MR13 operating checking
11
Wifi operating checking
12
13
Camera operating checking
13
14
External device recognition error
14
3
A. Video error
B. Power error
7
8
Remarks
C. Audio error
12
D. Function error
15
E. Noise
Circuit noise, mechanical noise
15
16
F. Exterior error
Exterior defect
16
First of all, Check whether there is SVC Bulletin in GCSC System for these model.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
Error
symptom
LCD TV
A. Video error
Established
date
No video/ Normal audio
Revised date
2013.01.31
1/16
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, LVDS Cable,Speaker Cable,IR B/D Cable,,,)
☞A1
No video
Normal audio
Normal
audio
Y
☞A18
Check Back Light
On with naked eye
N
Move to No
video/No audio
Y
On
Check Power
Board
24V, 12V,3.5V etc.
N
☞A18
Y
Replace T-con/FRC
Board or module
And Adjust VCOM
N
Repair Power
Board or parts
Check Power Board 24V output
Normal
voltage
Normal
voltage
Y
Replace Inverter
or module
End
N
Repair Power
Board or parts
※Precaution
☞A4 & A2
Always check & record S/W Version and White
Balance value before replacing the Main Board
Replace Main Board
Re-enter White Balance value
1
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
A. Video error
Established
date
No video/ No audio
Revised date
2013.01.31
2/16
☞A18
No Video/
No audio
Check various
voltages of Power
Board ( 3.5V,12V,20V
or 24V…)
Normal
voltage?
Y
N
Check and
replace
MAIN B/D
End
Replace Power
Board and repair
parts
2
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
Error
symptom
LCD TV
☞ A3
Check RF Signal level
Normal
Signal?
Y
A. Video error
Established
date
Picture broken/ Freezing
Revised date
2013.01.31
3/16
. By using Digital signal level meter
. By using Diagnostics menu on OSD
( Setting→ Set up→ Manual Tuning → Check the Signal )
- Signal strength (Normal : over 50%)
- Signal Quality (Normal: over 50%)
Check whether other equipments have problem or not.
(By connecting RF Cable at other equipment)
→ DVD Player ,Set-Top-Box, Different maker TV etc`
N
☞ A4
Check RF Cable
Connection
1. Reconnection
2. Install Booster
Normal
Picture?
Y
Check
S/W Version
N
N
Check
Tuner soldering
Y
Close
N
Y
N
Normal
Picture?
SVC
Bulletin?
S/W Upgrade
Contact with signal distributor
or broadcaster (Cable or Air)
Normal
Picture?
Y
N
Replace
Main B/D
Y
Close
Close
3
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
Established
date
Color error
Revised date
2013.01.31
4/16
☞ A7
☞A6
Check color by input
-External Input
-COMPONENT
-AV
-HDMI
A. Video error
Color
error?
N
Y
※ Check
and replace
Link Cable
(EPI) and
contact
condition
Y
Color
error?
Y
Color
error?
Replace Main B/D
N
N
End
Check error
color input
mode
☞A8
Check Test pattern
Replace module
External Input/
Component
error
Check
external
device and
cable
External device Y
/Cable
normal
Replace Main/FRC B/D
N
Request repair
for external
device/cable
N
HDMI
error
Check external
device and
cable
External device Y
/Cable
normal
Replace Main/FRC B/D
4
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
A. Video error
Established
date
Vertical / Horizontal bar, residual image,
light spot, external device color error
Revised date
2013.01.31
5/16
Vertical/Horizontal bar, residual image, light spot
Replace
Module
☞A6
☞ A7
Check color condition by input
-External Input
-Component
-HDMI
Screen Y
normal?
Check external
device
connection
condition
Normal?
Check and
replace Link
Cable
N
N
Check Test pattern
Screen N
normal?
Y
Request repair
for external
device
Replace
module
☞A8
Y
N
End
Replace Main/FRC
B/D (adjust VCOM)
Screen
normal?
For LGD panel
Y
Replace Main B/D
End
For other panel
External device screen error-Color error
Check S/W Version
Check N
version
Y
External
Input
error
Component
error
S/W Upgrade
Normal
screen?
Check screen
condition by input
-External Input
-Component
-HDMI/DVI
HDMI/
DVI
N
Y
End
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Connect other external
device and cable
(Check normal operation of
External Input, Component,
RGB and HDMI/DVI by
connecting Jig, pattern
Generator ,Set-top Box etc.
Connect other external
device and cable
(Check normal operation of
External Input, Component,
RGB and HDMI/DVI by
connecting Jig, pattern
Generator ,Set-top Box etc.
Screen
normal?
N
Replace
Main/FRC
B/D
Y
Request repair for
external device
Y
Screen
normal?
N
Replace
Main /FRC
B/D
5
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
B. Power error
Established
date
No power
Revised date
☞A17
Check
Logo LED
2013.01.31
6/16
☞A18
DC Power on
by pressing Power Key
On Remote control
Y
Power LED
On?
. Stand-By: Red or Turn Off
N
. Operating: Turn Off
Normal N
operation?
Check Power
On ‘”High”
OK?
Y
Replace
Power
B/D
Y
Check Power cord
was inserted properly
Replace Main B/D
☞A18
Normal?
Measure voltage of each output of Power B/D
N
Y
Close
Y
※
Check ST-BY 3.5V
Normal
Y
voltage?
☞A18
Normal
voltage?
Y
Replace Main B/D
N
Replace Power B/D
N
Replace Power
B/D
6
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
B. Power error
Established
date
Off when on, off while viewing, power auto on/off
Revised date
2013.01.31
7/16
Check outlet
☞A19
Check A/C cord
Error?
N
Check Power Off
Mode
CPU
Abnormal
Normal?
Replace Main B/D
Y
End
N
Check for all 3- phase
power out
Y
Abnormal
1
☞A18
Fix A/C cord & Outlet
and check each 3
phase out
(If Power Off mode
is not displayed)
Check Power B/D
voltage
※ Caution
Check and fix exterior
of Power B/D Part
* Please refer to the all cases which
can be displayed on power off mode.
Replace Power B/D
Normal
voltage?
Y
Replace Main B/D
N
Replace Power B/D
Status
Power off List
"POWEROFF_REMOTEKEY"
"POWEROFF_OFFTIMER"
"POWEROFF_SLEEPTIMER"
"POWEROFF_INSTOP"
"POWEROFF_AUTOOFF"
Normal "POWEROFF_ONTIMER"
"POWEROFF_RS232C"
"POWEROFF_RESREC"
"POWEROFF_RECEND"
"POWEROFF_SWDOWN"
"POWEROFF_UNKNOWN"
"POWEROFF_ABNORMAL1"
Abnormal
"POWEROFF_CPUABNORMAL"
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
off
off
off
off
off
off
off
off
off
off
off
off
off
Explanation
by REMOTE CONTROL
by OFF TIMER
by SLEEP TIMER
by INSTOP KEY
by AUTO OFF
by ON TIMER
by RS232C
by Reservated Record
by End of Recording
by S/W Download
by unknown status except listed case
by abnormal status except CPU trouble
by CPU Abnormal
7
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
C. Audio error
Established
date
No audio/ Normal video
Revised date
☞A20
No audio
Screen normal
Check user
menu >
Speaker off
2013.01.31
8/16
☞A21+A18
Off
N
Check audio B+
24V of Power
Board
Normal
voltage
Y
N
Cancel OFF
Check
Speaker
disconnection
Y
Replace Power Board and repair parts
Disconnection
N
Replace MAIN Board
End
Y
Replace Speaker
8
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
C. Audio error
Established
date
Wrecked audio/ discontinuation/noise
Revised date
2013.01.31
9/16
→ abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio
Check input
signal
-RF
-External Input
signal
Wrecked audio/
Discontinuation/
Noise for
all audio
Signal
normal?
☞A21+A18
Check and replace
speaker and
connector
Check audio
B+ Voltage (24V)
Y
Y
Wrecked audio/
Discontinuation/
Noise only
for D-TV
N
N
Wrecked audio/
Discontinuation/
Noise only
for Analog
(When RF signal is not
received)
Request repair to external
cable/ANT provider
(In case of
External Input
signal error)
Check and fix
external device
Normal
voltage?
Replace Main B/D
Replace Power B/D
Replace Main B/D
Wrecked audio/
Discontinuation/
Noise only
for External Input
Connect and check
other external
device
Normal
audio?
End
N
Y
Check and fix external device
9
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
D. Function error
Error
symptom
LCD TV
Established
date
Remote control & Local switch checking
2013.01.31
Revised date
10/16
1. Remote control(R/C) operating error
☞A22
Check R/C itself
Operation
☞A22
Check & Repair
Cable connection
Connector solder
Normal Y
operating?
N
Normal
operating?
N
Y
Check R/C Operating
When turn off light
in room
Check & Replace
Baterry of R/C
If R/C operate,
Explain the customer
cause is interference
from light in room.
Y
Normal
operating?
Replace
Main B/D
Check B+
3.5V
On Main B/D
☞A18
Close
☞A22
Normal
Voltage?
Y
Check IR
Output signal
N
Check 3.5v on Power B/D
Replace Power B/D or
Replace Main B/D
(Power B/D don’t have problem)
Normal
Signal?
Y
N
Repair/Replace
IR B/D
Close
N
Replace R/C
10
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
D. Function error
Error
symptom
LCD TV
Established
date
MR13 operating checking
2013.01.31
Revised date
11/16
2. MR13(Magic Remocon) operating error
☞A4
Check the
INSTART menu
RF Receiver ver
is “00.00”?
N
Check MR13
itself Operation
Normal Y
operating?
Press the
wheel
N
☞A23
Y
Y
Check & Replace
Battery of MR13
Check & Repair
RF assy
connection
Y
Normal
operating?
☞A4
RF Receiver ver
is “00.00”?
N
Y
Close
Turn off/on the
set and press
the wheel
Is show ok N
message?
N
Close
Close
Is show ok
message?
N
Press the back
key about 5sec
Y
Replace
MR13
Close
Down load the Firmware
* If you conduct the loop at 3times, change the M4.
* INSTART MENUÆ14.RF
Remocon TestÆ3. Firmware
download
11
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
D. Function error
Error
symptom
Established
date
Wifi operating checking
2013.01.31
Revised date
12/16
3.Wifi operating error
☞A4
Check the
INSTART menu
☞A24
Wi-Fi Mac value
is “NG”?
☞A24
N
Check the Wifi wafer
1pin
Normal
Voltage?
N
Replace
Main B/D
Y
Y
Close
Check & Repair
Wifi cable
connection
☞A4
Wi-Fi Mac value
is “NG”?
N
Close
Y
Change the Wifi
assy
12
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Check
input
signal
Error
symptom
Signal
input?
Y
N
D. Function error
Established
date
External device recognition error
Revised date
Check technical
information
- Fix information
- S/W Version
Check and fix
external device/cable
Technical
information?
N
External Input and
Component
Recognition error
2013.01.31
14/16
Replace Main B/D
Y
Fix in
accordance
with technical
information
HDMI/
DVI, Optical
Recognition error
Replace Main B/D
14
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Identify
nose
type
Error
symptom
Circuit
noise
Mechanical
noise
E. Noise
Established
date
Circuit noise, mechanical noise
Revised date
Check
location of
noise
2013.01.31
15/16
Replace PSU
Check location of
noise
※ When the noise is severe, replace the module
(For models with fix information, upgrade the
S/W or provide the description)
※ Mechanical noise is a natural
phenomenon, and apply the 1st level
description. When the customer does not
agree, apply the process by stage.
※ Describe the basis of the description
in “Part related to nose” in the Owner’s
Manual.
OR
※ If there is a “Tak Tak” noise from the
cabinet, refer to the KMS fix information and
then proceed as shown in the solution manual
(For models without any fix information,
provide the description)
15
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
F. Exterior defect
Error
symptom
Zoom part with
exterior damage
Exterior defect
Module
damage
Replace module
Cabinet
damage
Replace cabinet
Remote
controller
damage
Stand
dent
Established
date
Revised date
2013.01.31
16/16
Replace remote controller
Replace stand
16
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Contents of LCD TV Standard Repair Process Detail Technical Manual
No.
Error symptom
Content
Page
Check LCD back light with naked eye
A1
Check White Balance value
A2
TUNER input signal strength checking
method
A3
LCD-TV Version checking method
A4
Tuner Checking Part
A5
LCD TV connection diagram
A6
Check Link Cable (EPI) reconnection
condition
A7
9
Adjustment Test pattern - ADJ Key
A8
10
Exchange Main Board (1)
A-1/5
Exchange Main Board (2)
A-2/5
Exchange Power Board (PSU)
A-3/5
Exchange Module (1)
A-4/5
Exchange Module (2)
A-5/5
1
2
A. Video error_ No video/Normal
audio
4
5
A. Video error_ video error /Video
lag/stop
6
7
8
11
12
13
A. Video error _Vertical/Horizontal bar,
residual image, light spot
A. Video error_ Color error
<Appendix>
Defected Type caused by T-Con/
Inverter/ Module
14
Remarks
Continue to the next page
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Contents of LCD TV Standard Repair Process Detail Technical Manual
Continued from previous page
No.
Error symptom
16
Content
Page
Check front display LED
A17
Check power input Voltage & ST-BY 3.5V
A18
POWER OFF MODE checking method
A19
Checking method in menu when there is
no audio
A20
Voltage and speaker checking method
when there is no audio
A21
Remote controller operation checking
method
A22
Motion Remote operation checking
method
A23
23
Wifi operation checking method
A24
24
Camera operation checking method
A25
Tool option changing method
A26
Remarks
B. Power error_ No power
17
18
19
20
B. Power error_Off when on, off
while viewing
C. Audio error_ No audio/Normal
video
21
22
25
D. Function error
E. Etc
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_No video/Normal audio
Content
Check LCD back light with naked eye
Established
date
Revised
date
2013.01.31
A1
<XXLA965V-ZA>
After turning on the power and disassembling the case, check with the naked eye,
whether you can see light from 2 locations.
A1
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_No video/Normal audio
Content
Check White Balance value
Established
date
Revised
date
2013.01.31
A2
<ALL MODELS>
Entry
Entrymethod
method
1.1.Press
Pressthe
theADJ
ADJbutton
buttonononthe
theremote
remotecontroller
controllerforforadjustment.
adjustment.
2.2.Enter
Enterinto
intoWhite
WhiteBalance
Balanceofofitem
item6.9.
3.3.After
Afterrecording
recordingthe
theR,R,G,G,B B(GAIN,
(GAIN,Cut)
Cut)value
valueofofColor
ColorTemp
Temp
(Cool/Medium/Warm),
re-enter
the
value
after
replacing
(Cool/Medium/Warm), re-enter the value after replacingthe
theMAIN
MAINBOARD.
BOARD.
A2
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Video error, video lag/stop
Content
TUNER input signal strength checking method
Established
date
Revised
date
2013.01.31
A3
<ALL MODELS>
Settings Æ Set up Æ Manual Tuning
Æ select channel
When the signal is strong, use the
attenuator (-10dB, -15dB, -20dB etc.)
A3
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Video error, video lag/stop
Content
LCD-TV Version checking method
<ALL MODELS>
Established
date
Revised
date
2013.01.31
A4
1. Checking method for remote controller for adjustment
Version
Press the IN-START with the remote
controller for adjustment
A4
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Video error, video lag/stop
Content
TUNER checking part
Established
date
Revised
date
2013.01.31
A5
<ALL MODELS>
Checking method:
1. Check the signal strength or check whether the screen is normal when the external device is connected.
2. After measuring each voltage from power supply, finally replace the MAIN BOARD.
A5
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error _Vertical/Horizontal bar,
residual image, light spot
Content
LCD TV connection diagram (1)
Established
date
Revised
date
2013.01.31
A6
<ALL MODELS>
As the part connecting to the external input, check
the screen condition by signal
A6
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Color error
Content
Check Link Cable (LVDS) reconnection condition
Established
date
Revised
date
2013.01.31
A7
<ALL MODELS>
Check the contact condition of the Link Cable, especially dust or mis insertion.
A7
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_Color error
Content
Adjustment Test pattern - ADJ Key
Established
date
Revised
date
2013.01.31
A8
You can view 6 types of patterns using the ADJ Key
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)
A8
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Appendix : Exchange Main Board (1)
Solder defect, CNT Broken
Solder defect, CNT Broken
Solder defect, CNT Broken
Solder defect, CNT Broken
T-Con
T-Con
Defect,
Defect,
CNT
CNT
Broken
Broken
Solder
defect,CNT
CNTBroken
Broken
T-Con
Defect,
Abnormal Power Section
Solder defect, Short/Crack
Abnormal Power Section
Solder defect, Short/Crack
A - 1/5
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Appendix : Exchange Main Board (2)
Abnormal Power Section
Solder defect, Short/Crack
GRADATION
Abnormal Power Section
Solder defect, Short/Crack
Fuse Open, Abnormal power section
Abnormal Display
Noise
GRADATION
A - 2/5
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Appendix : Exchange Power Board (PSU)
No Light
Dim Light
Dim Light
Dim Light
No picture/Sound Ok
A - 3/5
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Appendix : Exchange the Module (1)
Panel Mura, Light leakage
Crosstalk
Panel Mura, Light leakage
Press damage
Press damage
Crosstalk
Un-repairable Cases
In this case please exchange the module.
Press damage
A - 4/5
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Appendix : Exchange the Module (2)
Vertical Block
Source TAB IC Defect
Horizontal Block
Gate TAB IC Defect
Vertical Line
Source TAB IC Defect
Horizontal
Gate
TAB ICBlock
Defect
Gate TAB IC Defect
Vertical Block
Source TAB IC Defect
Horizontal line
Gate TAB IC Defect
Gate TAB IC Defect
Un-repairable Cases
In this case please exchange the module.
Horizontal Block
Gate TAB IC Defect
Gate TAB IC Defect
A - 5/5
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
B. Power error _No power
Check front Power Indicator
Established
date
Revised
date
2013.01.31
A17
<XXLA965V-ZA>
ST-BY condition: On or Off
Power ON condition: Turn Off
A17
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
B. Power error _No power
Check power input voltage and ST-BY 3.5V
Established
date
Revised
date
2013.01.31
A18
Check the DC 24V, 12V, 3.5V.
18 Pin (Power Board ↔ Main Board)
1
Power on
2
INV ON
3
3.5V
4
PDIM#1
5
3.5V
6
PDIM#2
7
GND
8
GND
9
24V
10
24V
11
GND
12
GND
13
12V
14
12V
15
12V
16
24V
17
GND
18
GND
A18
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
B. Power error _Off when on, off whiling viewing Established
date
Content
POWER OFF MODE checking method
Revised
date
2013.01.31
A19
<ALL MODELS>
Entry method
1. Press the IN-START button of the remote
controller for adjustment
2. Check the entry into adjustment item 3
A19
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
C. Audio error_No audio/Normal video
Content
Checking method in menu when there is no audio
Established
date
Revised
date
2013.01.31
A20
<ALL MODELS>
Checking method
1. Press the Setting button on the remote controller
2. Select the Sound function of the Menu
3. Select the Sound Setting
4. Select TV Speaker
A20
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
C. Audio error_No audio/Normal video
Content
Voltage and speaker checking method
when there is no audio
Established
date
Revised
date
2013.01.31
A21
<XXLA965V-ZA>
②
24 Pin (Power Board ↔ Main Board)
1
2
Power on
INV ON
3
4
3.5V
PDIM#1
5
6
3.5V
PDIM#2
7
8
GND
GND
9
10
24V
24V
11
12
GND
GND
13
12V
14
12V
15
12V
16
24V
17
GND
18
GND
①
③
Checking order when there is no audio
① Check the contact condition of or 24V connector of Main Board
② Measure the 24V input voltage supplied from Power Board
(If there is no input voltage, remove and check the connector)
③ Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the
GND and output terminal, the speaker is normal.
A21
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
D. Function error
Content
Remote controller operation checking method
Established
date
Revised
date
2013.01.31
A22
<XXLA965V-ZA>
③
④
1
2
3
4
5
6
7
8
P4002
GND
KEY1
KEY2
+3.5V_ST
GND
LED
+3.5V_ST
GND
①
②
Checking order
1, 2. Check IR cable condition between IR & Main board.
3.
Check the st-by 3.5V on the terminal 4,7.
4. When checking the Pre-Amp when the power is in ON condition, it is normal when the
Analog Tester needle moves slowly, and defective when it does not move at all.
A22
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
D. Function error
Motion Remote operation checking method
Established
date
Revised
date
2013.01.31
A23
< XXLA965V-ZA >
③
②
①
1
2
3
4
5
6
7
8
9
P4000
+3.5V_WOL
+3.3V
USB_DM
RTS
USB_DP
RX
GND
TX
WOL
10
RESET
11
GND
12
CTS
13
NC
14
+3.5V_ST(OLED)
15
IR(OLED)
16
GND
Checking order
1, 2. Check Motion cable condition between Motion assy & Main board.
3.
Check the 3.3V on the terminal 2.
A23
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
D. Function error
Wifi operation checking method
Established
date
Revised
date
2013.01.31
A24
< XXLA965V-ZA >
③
①
②
1
2
3
4
5
6
7
8
9
P4000
+3.5V_WOL
+3.3V
USB_DM
RTS
USB_DP
RX
GND
TX
WOL
10
RESET
11
GND
12
CTS
13
NC
14
+3.5V_ST(OLED)
15
IR(OLED)
16
GND
Checking order
1, 2. Check Wifi cable condition between Wifi assy & Main board.
3.
Check the 3.3V on the terminal 2.
A29
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
Error
symptom
LCD TV
Content
E. Etc
Tool option changing method
Established
date
Revised
date
2013.01.31
A26
< XXLA965V-ZA >
②
①
Changing method
1.
Contact the USB memory. (USB 1,2,3 jack)
2.
Enter the password. (ex. 000000)
* Access USB Memory has each password.
A30
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

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