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Am486® Microprocessor PCI Customer Development Platform User’s Manual Order #22408A Am486® Microprocessor PCI Customer Development Platform User’s Manual © 1998 by Advanced Micro Devices, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Advanced Micro Devices, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subdivision (b)(3)(ii) of the Rights in Technical Data and Computer Software clause at 252.227-7013. Advanced Micro Devices, Inc., 5204 E. Ben White Blvd., Austin, TX 78741. AMD, the AMD logo, and combinations thereof, Comm86, E86, E86MON, and PCnet are trademarks of, Am486, MACH, and PAL are registered trademarks of, and FusionE86 is a service mark of Advanced Micro Devices, Inc. Vantis is a trademark of Vantis Corporation. Microsoft and Windows are registered trademarks of Microsoft Corp. Other product or brand names are used solely for identification and may be the trademarks or registered trademarks of their respective companies. IF YOU HAVE QUESTIONS, WE’RE HERE TO HELP YOU. The AMD customer service network includes U.S. offices, international offices, and a customer training center. Technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86™ and Comm86™ microcontroller family hardware and software development questions. Frequently accessed numbers are listed below. Additional contact information is listed on the back of this manual. AMD’s WWW site lists the latest phone numbers. Technical Support Answers to technical questions are available online, through e-mail, and by telephone. Go to AMD’s home page at www.amd.com and follow the Service link for the latest AMD technical support phone numbers, software, and Frequently Asked Questions. For technical support questions on all E86 and Comm86 products, send e-mail to [email protected] (in the US and Canada) or [email protected] (in Europe and the UK). You can also call the AMD Corporate Applications Hotline at: (800) 222-9323 44-(0) 1276-803-299 Toll-free for U.S. and Canada U.K. and Europe hotline WWW Support For specific information on E86 and Comm86 products, access the AMD home page at www.amd.com and follow the Embedded Processors link. These pages provide information on upcoming product releases, overviews of existing products, information on product support and tools, and a list of technical documentation. Support tools include online benchmarking tools and CodeKit™ software—tested source code example applications. Many of the technical documents are available online in PDF form. Questions, requests, and input concerning AMD’s WWW pages can be sent via e-mail to [email protected]. Documentation and Literature Support Data books, user’s manuals, data sheets, application notes, and product CDs are free with a simple phone call. Internationally, contact your local AMD sales office for product literature. To order literature, call: (800) 222-9323 (512) 602-5651 (512) 602-7639 Toll-free for U.S. and Canada Direct dial worldwide Fax Third-Party Support AMD FusionE86SM program partners provide an array of products designed to meet critical time-to-market needs. Products and solutions available include emulators, hardware and software debuggers, board-level products, and software development tools, among others. The WWW site and the E86 Family Products Development Tools CD, order #21058, describe these solutions. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. iv Am486® Microprocessor PCI Customer Development Platform Contents About the Customer Development Platform Evaluation Board Features ................................................................................ xiii Am486® Microprocessor .............................................................................. xiii Core Logic Chipset ....................................................................................... xiii DRAM Main Memory................................................................................... xiv Boot ROM and Flash Memory...................................................................... xiv Onboard L2 Cache ........................................................................................ xiv PC and DOS Compatibility.............................................................................xv PC-Style Super I/O..........................................................................................xv Keyboard and Mouse Controller .....................................................................xv Onboard 10/100-Mbit/s Ethernet .................................................................. xvi Expansion Bus Support ................................................................................. xvi Development Support.................................................................................... xvi Form Factor ................................................................................................... xvi BIOS and Software ....................................................................................... xvi Customer Development Platform Documentation ........................................... xvii About This Manual ...................................................................................... xvii Suggested Reference Material..................................................................... xviii Documentation Conventions......................................................................... xix Am486® Microprocessor PCI Customer Development Platform v Chapter 1 Quick Start Setting Up the PCI CDP .................................................................................... 1-2 Installation Requirements.............................................................................. 1-3 Board Installation .......................................................................................... 1-4 Starting from Diskette ................................................................................... 1-6 Starting from an IDE Hard Drive .................................................................. 1-7 Installation Troubleshooting.......................................................................... 1-8 Chapter 2 Board Functional Description Feature and Layout Diagrams............................................................................ 2-2 Jumper Functions............................................................................................... 2-6 Board Restrictions ............................................................................................. 2-7 Board Features ................................................................................................... 2-7 Am486 Microprocessor (M14)...................................................................... 2-8 Core Logic Chipset (M8, I13, D15) ............................................................ 2-11 Onboard Ethernet Controller (F7) ............................................................... 2-13 4-Kbyte Serial EEPROM (C4) .................................................................... 2-14 Development Support.................................................................................. 2-15 PCI Bus (I7)................................................................................................. 2-19 Level-2 Cache Memory (K19–N19 and N11)............................................. 2-20 DRAM Main Memory (P7)......................................................................... 2-20 Boot ROM (C16)......................................................................................... 2-21 ISA Flash Memory (F20) ............................................................................ 2-23 EIP Flash Memory (L21) ............................................................................ 2-25 Real-Time Clock (G17)............................................................................... 2-27 ISA Bus Interface (A7)................................................................................ 2-28 vi Am486® Microprocessor PCI Customer Development Platform Super I/O (C19)........................................................................................... 2-28 IDE Hard Drive (L4 and M4)...................................................................... 2-31 Keyboard (O1) ............................................................................................ 2-31 Mouse (M1)................................................................................................. 2-31 CPU Voltage Adjustment (Q15–Q16)......................................................... 2-32 Power Supply Connectors (N2 and P2) ...................................................... 2-33 Reset and Interrupt Switches and Headers.................................................. 2-34 Resistor Options .......................................................................................... 2-35 Appendix A Default Settings Appendix B Bill of Materials and Schematics Board Bill of Materials (BOM) .........................................................................B-2 Schematics.......................................................................................................B-10 Index Am486® Microprocessor PCI Customer Development Platform vii List of Figures Figure 0-1. PCI CDP Overview............................................................................................. xii Figure 2-1. PCI CDP Overview (Same as Figure 0-1)......................................................... 2-3 Figure 2-2. PCI CDP Block Diagram................................................................................... 2-4 Figure 2-3. PCI CDP Layout ................................................................................................ 2-5 Figure 2-4. Am486 Microprocessor Block Diagram.......................................................... 2-10 Figure 2-5. JP32 and JP33 Jumper Configuration (B14–C14)........................................... 2-22 Figure 2-6. Typical Memory Map With ISA and EIP Flash Memory ............................... 2-24 Figure 2-7. Serial Port Connector Pins (J8, J9) .................................................................. 2-29 Figure 2-8. Parallel Port Socket (J4) .................................................................................. 2-30 Figure 2-9. Voltage Jumper Default Configuration (Q15–Q16) ........................................ 2-32 Figure 2-10. Ground Wire Connections ............................................................................... 2-33 viii Am486® Microprocessor PCI Customer Development Platform List of Tables Table 0-1. Notational Conventions ................................................................................. xix Table 1-1. Installation Troubleshooting ............................................................................. 1-8 Table 2-1. Board Jumper Summary .................................................................................. 2-6 Table 2-2. PCI Configuration Addressing ........................................................................ 2-11 Table 2-3. Analyzer Headers ............................................................................................ 2-16 Table 2-4. PCI Bus Master Test Points ............................................................................ 2-17 Table 2-5. TIP Interrupt Usage ......................................................................................... 2-18 Table 2-6. PCI Bus Interrupt Routing............................................................................... 2-19 Table 2-7. SIMM Socket Population Chart ...................................................................... 2-21 Table 2-8. Serial Port Pin/Signal Table ............................................................................ 2-29 Table 2-9. Parallel Port Pin/Signal Table ......................................................................... 2-30 Table 2-10. Switch Summary ............................................................................................. 2-34 Table 2-11. Resistor Options ............................................................................................. 2-35 Table A-1. Default Jumper Settings .................................................................................. A-1 Am486® Microprocessor PCI Customer Development Platform ix x Am486® Microprocessor PCI Customer Development Platform About the Customer Development Platform Congratulations on your decision to design with the Am486® microprocessor. The Am486 microprocessor PCI customer development platform (CDP) provides a reference design for embedded Am486 microprocessor-based systems using the Peripheral Component Interconnect (PCI) bus with an onboard 10- or 100-Mbit/s Ethernet connection. The PCI CDP includes 9 Mbytes of Flash memory, PCI and ISA expansion connectors, and standard PC peripherals to allow customers to develop and benchmark network-ready firmware and applications for their embedded products. In addition, the platform’s use of low cost, off-the-shelf components makes it a suitable example for use in training or as a reference for customer hardware designs. The PCI CDP demonstrates that a fifth-generation x86 microprocessor is not required to include a PCI bus in customer designs. Note: Advanced Micro Devices does not assume any responsibility for the maintenance of this evaluation tool. Changes to the schematics will be made only if the board is required to go back through a CAD layout. Refer to the Am486 microprocessor documentation (listed on page xviii) for detailed information on the Am486 microprocessor. Figure 0-1 on page xii provides an overview of the PCI CDP’s features. Am486® Microprocessor PCI Customer Development Platform xi Am486® Microprocessor DRAM Level-2 Cache Three 72-pin SIMM Sockets Supports 48 Mbytes of EDO or FPM DRAM 48 Mbytes of 60-ns DRAM Installed 512 Kbyte Write-Back Policy JTAG Port CPU Logic Analyzer Headers In-Circuit Emulator Support Zero-Insertion-Force Socket Fan/Heat Sink Included EIP Flash Memory CPU Bus Addressed as fourth DRAM bank 8-Mbyte Flash Memory Faster than ISA Bus Flash Memory Coexists with up to 48 Mbyte of DRAM ALi M1489 Cache, Memory, and DRAM Controller (Northbridge Chip) PCI Bus Logic Analyzer Headers NMI, SMI, Reset Switches Ethernet Controller PCI Bus Am79C972 Device 10/100Base-T Port Three Connection Status LEDs Extra EEPROM for User Data IDE Interface Supports up to Four Devices Two Connector Status LEDs PCI Expansion Two PCI Bus Connectors ALi M1487 ISA Bridge (Southbridge Chip) PCI Bus Arbiter ISA Bus Boot ROM Socket 8 Bits Wide BIOS Included ISA Expansion Two ISA Bus Connectors RTC DS1685 Real-Time Clock Year-2000 Compliant 242 Bytes Nonvolatile RAM ISA Flash Memory 1 Mbyte, 16 Bits Wide Super I/O IrDA Module 2 Serial Ports with Status LEDs 1 Parallel Port Floppy Disk Interface M5042 Keyboard Controller AT Keyboard Controller PS/2 Mouse Controller Hex Display I/O Port 80h, 8 Bits Wide I/O Port 680h, 8 Bits Wide Test Interface Port Figure 0-1. PCI CDP Overview xii Am486® Microprocessor PCI Customer Development Platform User’s Manual Evaluation Board Features This section describes the following features of the PCI CDP: • • • • • • • • • • • • • Am486® Microprocessor, page xiii Core Logic Chipset, page xiii DRAM Main Memory, page xiv Boot ROM and Flash Memory, page xiv Onboard L2 Cache, page xiv PC and DOS Compatibility, page xv PC-Style Super I/O, page xv Keyboard and Mouse Controller, page xv Onboard 10/100-Mbit/s Ethernet, page xvi Expansion Bus Support, page xvi Development Support, page xvi Form Factor, page xvi BIOS and Software, page xvi Am486® Microprocessor • AMD Am486 DX5 microprocessor is included. Supports Am486 DX2, DX4, and DX5 microprocessors (168-pin pin-grid array (PGA), 3.3 V or 3.45 V). • Zero insertion force (ZIF) PGA microprocessor socket for emulator support. • CPU voltage is jumper selectable. Core Logic Chipset • Acer Labs FINALi 486 PCI chipset – M1489 Cache, Memory, and PCI Controller – M1487 ISA Bridge Controller – M5402 Mouse/Keyboard Controller Am486® Microprocessor PCI Customer Development Platform xiii DRAM Main Memory • 48 Mbyte of 60-ns EDO DRAM installed. • Supports one, two, or three banks of 32- or 36-bit-wide DRAM using industry standard 5-V 72-pin SIMMs. DRAM can be fast page mode (FPM) or extended data out (EDO). • Supports 1-, 4-, or 16-Mbit technology DRAMs. • Three SIMM sockets. One or two banks per socket. Three banks DRAM maximum. • DRAM is accessible by CPU and PCI bus masters. • L1/L2 cache snoop cycles are generated for PCI master memory accesses. • Wait-state timing is configurable through chipset registers. Boot ROM and Flash Memory • Dip socket provided for one 8-bit-wide boot ROM, logically on the ISA bus. • 1 Mbyte of 16-bit-wide Flash memory soldered to the board, logically on ISA bus. • 8-Mbyte Flash memory for execute-in-place (EIP) applications, located on the memory bus in place of one DRAM bank. EIP Flash is implemented using an AMD 22V10 PAL® device for glue logic. Onboard L2 Cache • 512-Kbyte cache size, configured as 32-bit-wide memory. • Write-back or write-through protocol configurable through chipset registers. • One 32-Kbyte x8 SRAM for cache tag space, soldered to board. • Four 128-Kbyte x8 SRAMs for cache data space, soldered to board. • 2-1-1-1 (read) and 2-2-2-2 (write) burst timing with 15-ns data and 10-ns tag SRAMs. xiv Am486® Microprocessor PCI Customer Development Platform User’s Manual PC and DOS Compatibility • IDE interface in chipset. • Standard chipset configuration registers, known to BIOS and DOS. • Off-the-shelf PC chipset provides common I/O functions found in a PC: - Two 82C59 interrupt controllers (SMI, NMI, and INT support) - One 82C54 programmable interval timer - Two 82C37 DMA controllers (seven channels) - External boot ROM chip-select signal - PC-style real-time clock (RTC) (non-Y2K-compliant, disabled by default) • DS1285 Y2K-compliant RTC chip. The DS1285 RTC can be disabled, and the non-Y2K RTC enabled, by removing one resistor and populating another. PC-Style Super I/O • DOS and PC-AT compatible I/O. • Two 16550-compatible serial ports. • One parallel port. Supports enhanced parallel port (EPP) and extended capabilities port (ECP) modes. • Floppy disk interface. • IrDA port with external transceiver (115 Kbyte/s). Keyboard and Mouse Controller • 8042-compatible controller chip (included in chipset). • AT keyboard interface. • PS/2 Mouse interface. Am486® Microprocessor PCI Customer Development Platform xv Onboard 10/100-Mbit/s Ethernet • AMD PCnet™-Fast+ Ethernet Controller Chip, Am79C972. • 32-bit PCI bus interface with bus mastering capability. • Integrated 12-Kbyte buffer. • External PHY transceiver for full duplex operation at 10 or 100 Mbit/s. • IEEE802.3, PC97, PC98, and NetPC compliance. • Preprogrammed 1-Kbyte serial EEPROM included for Ethernet configuration. • Extra 4-Kbyte serial EEPROM included for user nonvolatile data. Expansion Bus Support • Two PCI 2.0 expansion connectors, desktop PC style. • Two ISA 16-bit expansion connectors, desktop PC style. Development Support • In-circuit emulator (ICE) support with socketed microprocessor in PGA package. • Logic analyzer headers for all CPU and PCI bus signals. • Switches (push-button) for NMI, SMI, and RESET. • LEDs for IDE, serial port, Ethernet activity, and Ethernet link speed. • I/O port 80h and 680h hexadecimal displays. • Am486 microprocessor JTAG support. • Connector for AMD embedded systems Test Interface Port (TIP) board. Form Factor • Baby-AT motherboard form factor. • Fits standard desktop-PC-style chassis. BIOS and Software The included diskette contains information about the included BIOS and any additional utility and demonstration software for the PCI CDP. xvi Am486® Microprocessor PCI Customer Development Platform User’s Manual Customer Development Platform Documentation The Am486® Microprocessor PCI Customer Development Platform User’s Manual provides information on the design and function of the development platform. The software shipped with the board is described in the README files and online BIOS manual included with your kit. The included online documentation is in text or Adobe Acrobat (PDF) format. The latest Acrobat Reader is available from Adobe’s site on the World Wide Web (currently at www.adobe.com). About This Manual Chapter 1, “Quick Start” helps you quickly set up and start using the PCI CDP. Chapter 2, “Board Functional Description” contains descriptions of the basic sections of the evaluation board: layout, microprocessor, core logic chipset, Ethernet controller, DRAM, boot ROM and Flash memory, PCI bus and ISA bus interfaces, super I/O, keyboard and mouse, drives, and interrupt switches. Appendix A, “Default Settings” summarizes the jumper and configuration resistor positions on the PCI CDP when it is shipped. Appendix B, “Bill of Materials and Schematics” shows the bill of materials for the evaluation board, and the actual CAD schematics used to build the board. Am486® Microprocessor PCI Customer Development Platform xvii Suggested Reference Material The following AMD documentation may be of interest to the PCI CDP user. For information on ordering literature, see page iii. • Enhanced Am486®DX Microprocessor Family Data Sheet, order #20736 • Am486®DX/DX2 Microprocessor Hardware Reference Manual, order #17965 • Am486® Microprocessor Software User’s Manual, order #18497 • Am79C972 PCnetTM-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support Data Sheet, order #21485 • E86 Family Products Development Tools CD, order #21058 • Flash Memory Products Data Book, order # 11796 • For current application notes and technical bulletins, see our World Wide Web page at www.amd.com. The following non-AMD documents are also recommended: • Application Note 77: DS1585/87, DS1685/87, and DS17x85/87 Accessing Extended User RAM via Software Dallas Semiconductor, www.dalsemi.com. • DS1685/DS1687 3 Volt/5 Volt Real Time Clock Data Sheet Dallas Semiconductor, www.dalsemi.com. • FINALi 486 M1489/1487 PCI Chip Set Preliminary Data Sheet Acer Laboratories Inc., see www.acerlabs.com for contact information. Related BIOS guidelines, errata, and application documents are also available. • M5113: Enhanced Super I/O Controller Data Sheet Acer Laboratories Inc., see www.acerlabs.com for contact information. xviii Am486® Microprocessor PCI Customer Development Platform User’s Manual Documentation Conventions The Advanced Micro Devices Am486® Microprocessor PCI Customer Development Platform User’s Manual uses the conventions shown in Table 0-1 (unless otherwise noted). These same conventions are used in all the E86 family support product manuals. Table 0-1. Notational Conventions Symbol Usage Boldface Indicates that characters must be entered exactly as shown, except that the alphabetic case is only significant when indicated. Italic Indicates a descriptive term to be replaced with a user-specified term. Typewriter face Indicates computer text input or output in an example or listing. [] Encloses an optional argument. To include the information described within the brackets, type only the arguments, not the brackets themselves. {} Encloses a required argument. To include the information described within the braces, type only the arguments, not the braces themselves. .. Indicates an inclusive range. ... Indicates that a term can be repeated. | Separates alternate choices in a list — only one of the choices can be entered. := Indicates that the terms on either side of the sign are equivalent. Am486® Microprocessor PCI Customer Development Platform xix xx Am486® Microprocessor PCI Customer Development Platform User’s Manual Chapter 1 Quick Start This chapter provides information that helps you quickly set up and start using the Am486® microprocessor PCI customer development platform (CDP). The PCI CDP is shipped with a BIOS that has been configured specifically for the chipset used on this platform. The BIOS contains the code that enables the PCI CDP to function as a standard AT-compatible PC, using AT-compatible displays, display adapters, and keyboards. Details on the BIOS can be found in the BIOS documentation shipped on diskette with your kit. The PCI CDP can run AT-compatible operating system software. You can start the system with either a bootable diskette or an ATA (IDE) hard disk drive that already has the operating system installed. Embedded BIOS software typically supports the configuration of onboard Flash memory as a resident flash disk (RFD) that can also be set up as a boot device. See the online BIOS manual included with your kit. For information on how to: • Set up the PCI CDP, see page 1-2. • Boot the PCI CDP from a diskette, see page 1-6. • Boot the PCI CDP from a hard disk drive, see page 1-7. • Troubleshoot installation problems, see page 1-8. Am486® Microprocessor PCI Customer Development Platform 1-1 Setting Up the PCI CDP ! CAUTION: As with all computer equipment, the PCI CDP may be damaged by electrostatic discharge (ESD). Please take proper ESD precautions when handling any board. Warning: Read before using this development platform Before applying power, the following precautions should be taken to avoid damage or misuse of the board: • Make sure power supply connectors (from a standard AT system power supply) are plugged onto the board correctly. The grounds (usually black wires) must meet at the center of the two power supply connectors on the board. See “Power Supply Connectors (N2 and P2)” on page 2-33. • See Figure 2-3 on page 2-5 for connector positions. • Check the diskette that was shipped with your kit for README or errata documentation. Read all the information carefully before continuing. For current application notes and technical bulletins, see the AMD World Wide Web page at www.amd.com and follow the link to Embedded Systems. 1-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual Installation Requirements You need to provide the following items (in addition to the PCI CDP from the kit). Required for all setups: • A VGA-compatible monitor • A PCI- or ISA-bus video card that supports VGA • A cable to connect the monitor to the video card • An AT-compatible keyboard • A PS/2-style mouse (if needed for your operating system) • A standard AT-style power supply To boot from a floppy diskette: • An AT-compatible 3.5-inch or 5.25-inch diskette drive • A bootable DOS diskette • A standard 34-wire AT diskette drive cable To boot from a hard disk drive: • An ATA-compatible hard disk drive • AT-compatible operating system (preinstalled on the hard disk drive) • A standard 40-pin ATA HDD cable If you install both a floppy diskette drive and a hard disk drive, you can boot from either device. Only one boot disk image (floppy or hard disk) is required. For example, you can boot from the floppy and then install the operating system on a blank hard disk drive. ! CAUTION: Use the configuration described here when you first start the PCI CDP. Before using other features, read the appropriate sections in Chapter 2, “Board Functional Description.” Am486® Microprocessor PCI Customer Development Platform 1-3 Board Installation Note: See Figure 2-2 on page 2-4 for a block diagram of the board. See Figure 2-3 on page 2-5 for a layout diagram of the board, including connector locations referenced in this section. ! DANGER: Make sure the power supply and the VGA monitor are not plugged into an electrical outlet during the following steps. 1. Remove the board from the shipping carton. Visually inspect the board to verify that it was not damaged during shipment. The board contains several jumpers. The following steps assume all jumpers are in the factory default configuration (settings are listed in Appendix A, “Default Settings”). 2. If you are installing a diskette drive, perform the following steps: a. Inspect the 34-wire, diskette-drive cable that you are providing. The red wire along one edge of the ribbon cable indicates wire 1. Most cables have a connector for the board at one end and two or more connectors along the length. There may be two different drive connectors at each location to accommodate different drive types. b. Connect one end of the diskette-drive cable to the 34-pin connector (connector J6 at location E20) on the PCI CDP (with wire 1 oriented towards the middle of the board). If there is a twist in one span of the cable, connect the opposite end to the board. c. Connect another connector on the diskette-drive cable to the diskette drive, just as you would for a standard PC installation. If there is a twist in the cable, the position you use determines whether the drive responds as A or B (typically drive A connects to the end of the cable, beyond the twist). The connector’s orientation should be indicated in the drive documentation, or marked near the connector on the drive. Usually wire 1 is oriented towards the drive’s power cable connector. d. Find one of the 4-wire power connectors from the PC power supply and attach it to the 4-pin connector on the diskette drive just as you would for a standard PC installation. 1-4 Am486® Microprocessor PCI Customer Development Platform User’s Manual 3. If you are installing a hard disk drive, perform the following steps: a. Inspect the 40-wire IDE cable that you are providing. The red wire along one edge of the ribbon cable indicates wire 1. b. Connect one end of the 40-wire IDE cable to the hard drive just as you would for a standard PC installation. The connector’s orientation should be indicated in the drive documentation, or marked near the connector on the drive. Usually wire 1 is oriented towards the drive’s power cable connector. c. Connect the other end of the 40-wire IDE cable to the first 40-pin connector (connector J5 at location L4) on the PCI CDP (with wire 1 oriented towards the edge of the board, near the power supply connector). d. Find one of the 4-wire power connectors from the PC power supply and attach it to the 4-pin connector on the hard drive just as you would for a standard PC installation. 4. Make sure the CPU heat sink is securely attached to the microprocessor and connect the heat sink fan power wires to a spare disk drive power connector. Fan power supply connectors are not all the same. Check the voltage printed on the fan and connect its wires to the correct voltage pins on the appropriate power supply connector. 5. Insert a PCI- or ISA-bus VGA-compatible video card into an appropriate slot on the PCI CDP. The PCI slots are labeled SLT1 and SLT2. The ISA slots are labeled SL1 and SL2. 6. Connect the monitor cable from the monitor to the D-connector on the video card just as you would for a standard PC. 7. Connect the AT keyboard to the keyboard connector (connector J1 at location O1). 8. Connect the PS/2 mouse (if used) to the mouse connector (connector J11 at location M1). 9. Connect the connectors (usually marked P8 and P9) from the standard PC power supply into the board’s power connectors J2 (at location Q2) and J3 (at location N2). P8 connects to J2 (the six pins closest to the corner of the board); P9 connects to the other six pins. Make sure the black ground wires from P8 and P9 meet in the middle of the board’s J2 and J3 connectors. ! CAUTION: Failure to verify the power supply connections can result in total destruction of the PCI CDP. Am486® Microprocessor PCI Customer Development Platform 1-5 Starting from Diskette Use the following steps to start the PCI CDP from a bootable diskette: 1. Make sure you have installed the PCI CDP correctly as described in “Setting Up the PCI CDP” on page 1-2. ! CAUTION: Failure to verify the power supply connections can result in total destruction of the PCI CDP. 2. Plug the VGA monitor into an electrical outlet and turn it on. 3. Insert a bootable DOS diskette (not included) in the disk drive. 4. Apply power to the PCI CDP by connecting the PC power supply to an electrical outlet. If the power supply is equipped with a switch, turn it on. The power supply fan should start running, and the port 80h LEDs should start to display power-on self-test (POST) status codes. Then the speaker should beep and the monitor should start displaying startup information. Make sure the CPU heat sink fan is running. Do not operate the microprocessor without a functioning heat sink fan. 5. The first time you start the system, the BIOS might display a message reporting a CMOS error or some other BIOS configuration problem. Follow the instructions shown on the screen to enter the Setup utility. Once you are in the Setup utility, you can set the system’s date, time, startup drive, and other options. For more information on the included BIOS, see the online BIOS manual included with your kit. 6. Save and exit the setup utility. 7. The system should now boot from the DOS diskette just like a standard PC. If you encounter any problems, see “Installation Troubleshooting” on page 1-8. 1-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual Starting from an IDE Hard Drive Use the following steps to start up the PCI CDP from an IDE hard drive on which you have preinstalled an operating system (while it was connected to another PC): 1. Make sure you have installed the PCI CDP correctly as described in “Setting Up the PCI CDP” on page 1-2. ! CAUTION: Failure to verify the power supply connections can result in total destruction of the PCI CDP. 2. Plug the VGA monitor into an electrical outlet and turn it on. 3. If a diskette drive is installed, make sure it is empty. 4. Apply power to the PCI CDP by connecting the PC power supply to an electrical outlet. If the power supply is equipped with a switch, turn it on. The power supply fan and hard disk should start running, and the port 80h LEDs should start to display power-on self-test (POST) status codes. Then the speaker should beep and the monitor should start displaying startup information. Make sure the CPU heat sink fan is running. Do not operate the microprocessor without a functioning heat sink fan. 5. The first time you start the system, the BIOS might display a message reporting a CMOS error or some other BIOS configuration problem. Follow the instructions shown on the screen to enter the Setup utility. Once you are in the Setup utility, you can set the system’s date, time, startup drive, and other options. 6. In the BIOS setup utility, use the automatic configuration option to set up Drive C. Select either physical addressing or logical block addressing (LBA) as appropriate for your hard disk drive. For more information on the included BIOS, see the online BIOS manual included with your kit. 7. Save and exit the setup utility. 8. The system should now boot using the operating system on the hard disk. If you encounter any problems, see “Installation Troubleshooting” on page 1-8. Am486® Microprocessor PCI Customer Development Platform 1-7 Installation Troubleshooting Table 1-1. Installation Troubleshooting Problem Solution The Port 80h LED readout is blank after I turn on the power supply. Check power supply connectors J2 and J3. The Port 80h LED readout is stuck at 00. I see nothing on the VGA monitor and do not hear any beeps from the speaker. I do not hear the head synchronization on the diskette drive (if attached). Ensure processor reset by pressing the Reset button, SW1 at location N5. The Port 80h LED readout displayed some power-on-selftest (POST) numbers, but then stopped at one number before the system finished starting. Make sure all cables are connected properly, all adapters are seated firmly in their slots, and the CMOS battery is correctly installed. I hear a beep on the speaker but see nothing on the VGA monitor. Check that the monitor is plugged in and turned on. Check that the BIOS ROM and the microprocessor are correctly installed, and that jumpers JP32 and JP33 are both off. See the online BIOS documentation included with your kit for a list of POST numbers and meanings. Check that the monitor is correctly connected to the video card. Check that the video card is correctly seated in the appropriate slot. Check that the video card supports VGA. I see the startup information on the monitor but the memory test stops at an incorrect memory size. (1 Mbyte equals 1024 Kbyte.) Make sure the SIMMs that came with the kit are securely installed in the SIMM sockets. I see the startup information on the monitor but it says there’s a battery problem or CMOS checksum error and the system doesn’t finish booting. Follow the BIOS instructions to run the Setup utility to configure the CMOS RAM and save settings. 1-8 Am486® Microprocessor PCI Customer Development Platform User’s Manual Table 1-1. Installation Troubleshooting (Continued) Problem Solution I configured the CMOS RAM and saved my settings, but settings are lost the next time I turn on the PCI CDP. Make sure a fresh 3.0-V 20-mm coin cell is installed correctly (“+” side facing up) in the BT1 battery holder at location E12. I don’t hear any sound from the diskette drive and the system does not boot from a diskette. Check that the 34-wire cable to the diskette drive is properly connected at both the drive end and the board end (board connector J6 at location E20). The red wire should be oriented towards pin 1 on both the drive and the board. Check that the CMOS setup indicates that drive A is the correct size and capacity for your diskette drive. I hear the diskette being accessed but get an error message “Non System disk” or “Drive A not found.” Check that the diskette in the drive is bootable, just as you would on a standard PC. Make sure the diskette drive is connected properly to the last connector on the cable. In the BIOS setup utility, make sure the BIOS is configured to boot from diskette, and that the diskette size and density is configured properly. I get a “Missing Keyboard” error message on the monitor during boot-up. Check that an AT-style keyboard is properly connected. The BIOS debugging monitor prompt is displayed. Make sure the NMI switch is not pressed. Check that the DRAM and any PCI or ISA-bus devices are installed correctly and known to be functional. Am486® Microprocessor PCI Customer Development Platform 1-9 Table 1-1. Installation Troubleshooting (Continued) Problem Solution I have installed a hard disk with a preinstalled operating system, but the PCI CDP won’t access the hard disk. Check that the 40-wire IDE cable is properly connected at both the drive end and the board end (board connector J5 at location L4). Check that the CMOS setup is configured correctly for your drive. Make sure the board will start from a bootable diskette in drive A. Then try to do a directory listing of drive C. If the directory listing of C works, the drive is functioning and there is a problem with the drive’s boot block or system image. (Note that some operating systems will display an error if you list an empty directory. If this happens, try copying a file to the drive; then do a directory listing again. If this fails, check the drive for boot block viruses.) Make sure the drive functions properly on a different system. There is a problem you cannot resolve. Check that the board is set to its default settings (see Appendix A, “Default Settings”). Contact the AMD Technical Support Hotline (see page iii). 1-10 Am486® Microprocessor PCI Customer Development Platform User’s Manual Chapter 2 Board Functional Description The Am486® microprocessor PCI customer development platform (CDP) provides a test and development platform for Am486 microprocessor-based designs. Read the following sections to learn more about the board: • • • • Feature and Layout Diagrams, page 2-2 Jumper Functions, page 2-6 Board Restrictions, page 2-7 Board Features, page 2-7 – – – – – – – – – – – – – – Am486 Microprocessor (M14), page 2-8 Core Logic Chipset (M8, I13, D15), page 2-11 Onboard Ethernet Controller (F7), page 2-13 4-Kbyte Serial EEPROM (C4), page 2-14 Development Support, page 2-15 - JTAG Ports (Q14 and D17), page 2-15 - Logic Analyzer Headers, page 2-15 - In-Circuit Emulator Compatibility (M14, Q15–Q16), page 2-17 - Hexadecimal Display (H23, J23), page 2-17 - Test Interface Port (TIP) (A16), page 2-18 PCI Bus (I7), page 2-19 Level-2 Cache Memory (K19–N19 and N11), page 2-20 DRAM Main Memory (P7), page 2-20 Boot ROM (C16), page 2-21 ISA Flash Memory (F20), page 2-23 EIP Flash Memory (L21), page 2-25 Real-Time Clock (G17), page 2-27 ISA Bus Interface (A7), page 2-28 Super I/O (C19), page 2-28 - Serial Ports (E23 and C23), page 2-29 - IrDA Interface (A19), page 2-29 - Parallel Port (A22), page 2-30 - Floppy Disk Drive (E20), page 2-30 Am486® Microprocessor PCI Customer Development Platform 2-1 – – – – – – – IDE Hard Drive (L4 and M4), page 2-31 Keyboard (O1), page 2-31 Mouse (M1), page 2-31 CPU Voltage Adjustment (Q15–Q16), page 2-32 Power Supply Connectors (N2 and P2), page 2-33 Reset and Interrupt Switches and Headers, page 2-34 Resistor Options, page 2-35 See the appendices for information about default board settings, bill of materials, and schematics. Feature and Layout Diagrams The following figures summarize the features and layout of the PCI CDP. • Figure 2-1 on page 2-3 provides an overview of the platform’s features. • Figure 2-2 on page 2-4 is the block diagram for the platform. • Figure 2-3 on page 2-5 shows the platform layout and component locations. 2-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual Am486® Microprocessor DRAM Level-2 Cache Three 72-pin SIMM Sockets Supports 48 Mbytes of EDO or FPM DRAM 48 Mbytes of 60-ns DRAM Installed 512 Kbyte Write-Back Policy JTAG Port CPU Logic Analyzer Headers In-Circuit Emulator Support Zero-Insertion-Force Socket Fan/Heat Sink Included EIP Flash Memory CPU Bus Addressed as fourth DRAM bank 8-Mbyte Flash Memory Faster than ISA Bus Flash Memory Coexists with up to 48 Mbyte of DRAM ALi M1489 Cache, Memory, and DRAM Controller (Northbridge Chip) PCI Bus Logic Analyzer Headers NMI, SMI, Reset Switches Ethernet Controller PCI Bus Am79C972 Device 10/100Base-T Port Three Connection Status LEDs Extra EEPROM for User Data IDE Interface Supports up to Four Devices Two Connector Status LEDs PCI Expansion Two PCI Bus Connectors ALi M1487 ISA Bridge (Southbridge Chip) PCI Bus Arbiter ISA Bus Boot ROM Socket 8 Bits Wide BIOS Included ISA Expansion Two ISA Bus Connectors RTC DS1685 Real-Time Clock Year-2000 Compliant 242 Bytes Nonvolatile RAM ISA Flash Memory 1 Mbyte, 16 Bits Wide Super I/O IrDA Module 2 Serial Ports with Status LEDs 1 Parallel Port Floppy Disk Interface M5042 Keyboard Controller AT Keyboard Controller PS/2 Mouse Controller Hex Display I/O Port 80h, 8 Bits Wide I/O Port 680h, 8 Bits Wide Test Interface Port Figure 2-1. PCI CDP Overview (Same as Figure 0-1) Am486® Microprocessor PCI Customer Development Platform 2-3 JTAG CPU Power CPU Jumpers Am486® Microprocessor Pin Grid Array (ZIF Socket) EDO DRAM 72-pin SIMM Socket 1 Logic Analyzer Header(s): CPU Signals EDO DRAM 72-pin SIMM Socket 2 Onboard 512K L2 Cache EDO DRAM 72-pin SIMM Socket 3 CPU Address CPU Data Cache Control CPU Control DRAM-to-Flash Interface 8-Mbyte Flash Memory For Execute-In-Place Memory Address ALi M1489 Cache, Memory, and PCI Controller & Control Logic Analyzer Header(s): PCI Signals IDE Connector PCI Bus (33 MHz, 5 V) AMD Am79C972 PCNet Fast+ Ethernet IDE Connector PHY CPU Interface 1-Kbyte Config SEEPROM ALi M1487 ISA Bridge Controller 4-Kbyte User SEEPROM ISA Bus PCI Expansion Connector ISA Expansion Connector ISA Expansion Connector IrDA DS1685 Y2K RTC PCI Expansion Connector Boot ROM Socket (x8) M5113A Super I/O Chip 1-Mbyte FLASH Memory (x16) MACH® Logic Floppy Disk Connector Serial Port1 Connector Serial Port2 Connector M5042 Keyboard Controller HEX LEDs for Debug TIP Board Interface PS/2 Mouse Connector LEDs NMI SMI Reset AT Keyboard Connector E/net SIO1 SIO2 IDE0 IDE1 Parallel Port Connector Switches System Clocks System Power Figure 2-2. PCI CDP Block Diagram 2-4 Am486® Microprocessor PCI Customer Development Platform User’s Manual A B C D 1 E F G H I J K L Ethernet Conn. M N O P Q 1 KBD Mouse 2 2 4 5 6 Pin 1 IDE Hard Disk Conn. 3 3 IDE Hard Disk Conn. Pin 1 Power Conn. 4 5 6 Am79C972 7 Ethernet Controller ISA Slots 8 DRAM SIMM Slots PCI Slots M1489 7 8 Northbridge 9 9 10 10 11 11 12 12 Battery M1487 13 13 Southbridge Pin A1 Speaker 14 15 M5042 Kbd/ Mouse TIP 16 14 Am486® Microprocessor 15 Boot ROM Conn. 16 MACH® Logic Chip 17 DS 1685 RTC 17 18 18 Floppy Conn. Super I/O 20 Parallel Port 21 EIP Flash Memory 22 COM 1 22 20 ISA Flash 23 COM 2 21 19 Pin 1 M5113 19 23 24 24 A B C D E F G H I J K L M N O P Q Figure 2-3. PCI CDP Layout Am486® Microprocessor PCI Customer Development Platform 2-5 Jumper Functions Table 2-1 describes the configuration jumpers on the PCI CDP. Table 2-1. Board Jumper Summary Part Signal Description Location in See App. B Figure 2-3 Schematics on Page 2-5 on: For More Info., See: JP2 CPUVCC3 Used with JP3 to select either 5-V CPU voltage or the adjustable voltage set by jumper JP4. Both JP2 and JP3 must be positioned the same. Q15 Sheet 3 page 2-32 JP3 CPUVCC3 Used with JP2 to select either 5-V CPU voltage or the adjustable voltage set by jumper JP4. Both JP2 and JP3 must be positioned the same. Q16 Sheet 3 page 2-32 JP4 CPUV1, CPUV2, CPUV3 Selects the CPU voltage used when JP2 and JP3 are set to “ADJ.” The selectable voltages are 3.45 V, 3.3 V, and 2.5 V. R15 Sheet 3 page 2-32 JP32 Boot ROM A17 Used to configure boot ROM address signal A17. C14 Sheet 17 page 2-21 JP33 Boot ROM A18 Used to configure boot ROM address signal A18. B14 Sheet 17 page 2-21 2-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual Board Restrictions • Using a PCI chipset with the Am486 microprocessor is a fast and effective way to design a working system, but the system’s features can be limited by the chipset’s capabilities. • The chipset used in the PCI CDP supports 5-V PCI 2.0 devices only. Three devices are supported: the onboard Ethernet controller and two PCI slots. • Except for the adjustable CPU supply voltage and 3.3-V Ethernet controller, the PCI CDP uses 5-V power throughout. (The Am486 microprocessor provides 5V-tolerant I/O.) • The chipset does not directly support ROM or Flash memory devices except for the boot ROM. It is possible to implement Flash memory on the DRAM, PCI or ISA bus, but the chipset only allows booting from the boot ROM. ISA-bus Flash memory is limited to 1 Mbyte because of addressing considerations. • The PCI CDP implements two banks of execute-in-place (EIP) Flash memory in place of one DRAM bank. Flash memory timing requirements limit the chipset’s DRAM interface to its Fast (not Fastest) speed when the Flash memory is used. This is equivalent to using 70-ns fast-page-mode (FPM) DRAM. • The chipset allows only three banks of DRAM to be attached without external buffers. Buffering the DRAM adds one wait state and reduces the available performance. “DRAM Main Memory (P7)” on page 2-20 describes additional DRAM device and configuration limits. • The ISA peripherals provided by the M1487 chip are configured for standard PC-AT compatibility, so there is not much flexibility in assigning interrupts and DMA channels. • The PCI CDP does not implement OnNow or Advanced Configuration and Power Interface (ACPI) power management. Board Features The remainder of this chapter describes the features of the PCI CDP. The number in parentheses following each heading indicates the part’s location in Figure 2-3 on page 2-5. In addition, other locations referenced can be found in the figure. Am486® Microprocessor PCI Customer Development Platform 2-7 Am486 Microprocessor (M14) The PCI CDP includes an Am486 microprocessor in a 168-pin, pin-grid-array package (part U25). The microprocessor is zero-insertion-force (ZIF) socketed and a CPU fan heat sink is provided for cooling. For debugging and analysis, access is provided to the Am486 microprocessor’s JTAG debugging port and to all of the microprocessor signals, and support is provided for Intel-compatible in-circuit emulators. See “Development Support” on page 2-15. The Enhanced Am486DX Microprocessor Family boosts system performance by incorporating a 16-Kbyte cache to the existing flexible clock control and enhanced System Management mode (SMM) features of a 486 CPU. The Enhanced Am486DX Microprocessor Family has the following characteristics: • Industry-standard write-back cache support • Frequent instructions execute in one clock • 105.6-million bytes/second burst bus at 33 MHz • Flexible write-through and write-back address control • Advanced 0.35-µ CMOS-process technology • 3.3-V or 3.45-V core with 5-V tolerant I/O • Dynamic data bus sizing for 8-, 16-, and 32-bit buses (the PCI CDP uses a 32bit data bus) • 32-bit address bus • 32-bit registers • Supports “soft reset” capability • 16-Kbyte unified code and data cache – Four-way set-associative – Write-through or write-back policy (the PCI CDP uses write-back policy) • Floating-point unit • Paged, virtual memory management • Stop clock control for reduced power consumption • Industry-standard two-pin System Management Interrupt (SMI) for power management independent of processor operating mode and operating system 2-8 Am486® Microprocessor PCI Customer Development Platform User’s Manual • Static design with Auto Halt power-down support • Wide range of chipsets supporting SMM available to allow product differentiation (the PCI CDP uses the Acer Laboratories Inc. FINALi 486 chipset) • Support available through the AMD FusionE86 Program Am486® Microprocessor PCI Customer Development Platform 2-9 VOLDET Power Plane 32-Bit Data Bus Clock Interface 32-Bit Data Bus Clock Generator 32-Bit Linear Address Barrel Shifter Register File Descriptor Registers 24 Physical Address ALU Limit and Attribute PLA Cache Unit 2 32 Paging Unit 24 Translation Lookaside Buffer Physical Address 16-Kbyte Cache Prefetcher 32 Micro-instruction Code Stream Floating Point Unit Floating Point Register File Central and Protection Test Unit Control ROM Instruction Decode 24 Address Drivers Write Buffers 4x32 A31–A2 BE3–BE0 Copyback Buffers 4x32 Writeback Buffers 4x32 128 Displacement Bus CLK CLKMUL STPCLK Bus Interface PCD, PWT Segmentation Unit VCC, VSS 32 Data Bus Transceivers 32-Byte Code Queue 2x16 Bytes Bus Control Request Sequencer Decoded Instruction Path D31–D0 ADS, W/R, D/C, M/IO, PCD, PWT, RDY, LOCK, PLOCK, BOFF, A20M, BREQ, HOLD, HLDA, RESET, INTR, NMI, FERR, UP, IGNNE, SMI, SMIACT, SRESET Burst Bus Control BRDY, BLAST Bus Size Control BS16, BS8 Cache Control Parity Generation and Control JTAG KEN, FLUSH, AHOLD, CACHE, EADS, INV, WB/WT, HITM PCHK, DP3–DP0 TDI, TCK, TDO, TMS Figure 2-4. Am486 Microprocessor Block Diagram 2-10 Am486® Microprocessor PCI Customer Development Platform User’s Manual Core Logic Chipset (M8, I13, D15) The PCI CDP uses the Acer Laboratories Inc. FINALi 486 chipset. The chipset consists of two very-large-scale-integration (VLSI) devices that provide bus interface and peripheral functions used in the system, plus an M5042 keyboard and mouse controller. See “Keyboard (O1)” on page 2-31. The M1489 Cache, Memory, and PCI Controller (often called a northbridge chip) interfaces the Am486 microprocessor to the memory and PCI bus. The M1489 (part U5 at location M8) performs the following functions: • Controls DRAM accesses and refresh cycles. See “DRAM Main Memory (P7)” on page 2-20 • Provides a 33-MHz, PCI 2.0-compliant interface with 5-V signalling. See “PCI Bus (I7)” on page 2-19 • Maintains Level-1 and Level-2 cache coherency for PCI-master-initiated memory cycles. See “Level-2 Cache Memory (K19–N19 and N11)” on page 2-20 • Provides an IDE controller for a hard disk drive. See “IDE Hard Drive (L4 and M4)” on page 2-31 The PCI CDP routes three PCI address signals via series resistors to the IDSEL pins on the two PCI slots and the onboard Ethernet controller. The chipset asserts one of these signals to configure each device according to the device number written to the chipset’s configuration address register. Table 2-2 relates each device to its device number and signal routing. Table 2-2. PCI Configuration Addressing PCI Device Device Number PCI Address Signal PCI ID Select Signal See App. B schematics on: Slot SLT1 Device 3 PAD19 PCIID1 Sheet 11 Slot SLT2 Device 4 PAD20 PCIID2 Sheet 11 Ethernet Controller Device 5 PAD21 PCIID3 Sheet 11, Sheet 13 Am486® Microprocessor PCI Customer Development Platform 2-11 All PCI bus signals are routed to logic analyzer headers. See “Development Support” on page 2-15. The M1487 ISA Bridge Controller (often called a southbridge chip) interfaces the ISA bus to the PCI bus and provides standard, PC-compatible peripherals devices common to desktop computers. The M1487 (Part U21 at location I13) provides the following peripheral functions: • Two 82C59 interrupt controllers • One 82C54 programmable interval timer • Two 82C37 DMA controllers • A real-time clock (RTC) (optional on the CDP, see “Real-Time Clock (G17)” on page 2-27) • External boot ROM decoding The M1487’s integrated peripherals are configured for standard PC-AT compatibility, so there is not much flexibility in assigning interrupts and DMA channels. The M1487 also contains the PCI bus arbiter, which allows three additional masters. The PCI CDP board uses one master request/grant interface for the onboard Am79C972 Ethernet controller. The other two master interfaces are routed to the PCI expansion slots. The M1489 and M1487 communicate with each other across their proprietary LinkBus. The LinkBus has no separate pins, but instead uses the CPU address pins A2 to A17. The LinkBus handles the RTC, keyboard controller, and boot ROM transactions as well; this is why CPU address pins are routed to these devices in the schematics. The chipset asserts the Am486 microprocessor’s AHOLD input to three-state its address pins when the LinkBus is in use. 2-12 Am486® Microprocessor PCI Customer Development Platform User’s Manual Onboard Ethernet Controller (F7) The PCI CDP includes an onboard, full-duplex 10/100BaseT Ethernet port based on the AMD Am79C972 PCnet™-FAST+ Ethernet Controller (part U51). A separate voltage regulator provides 3.3-V power for the Ethernet controller. The Ethernet port is part J10 at location E1 on the board. Three LEDs near the port indicate transmit and receive activity and link speed. The link LED lights if 100 Mbit/s operation is established. The Ethernet controller’s interrupt output (INTA) is routed to the chipset’s PCI INT2 signal. The initialization code dynamically assigns INT2 to an interrupt request (IRQ) in the chipset’s PCI INTx routing table mapping registers. See the chipset documentation for details on the mapping registers. The Am79C972 PCnet-FAST+ device is a highly integrated 10/100 Mbps PCI Ethernet controller. It includes an IEEE 802.3-compliant Ethernet Media Access Controller (MAC) with Auto-Negotiation of 10 or 100 Mbps and half- or fullduplex operation, and a Media Independent Interface (MII) for connection to any standard IEEE 802.3 compliant 10/100 Mbps physical layer (PHY) device. The Am79C972 contains a high performance 32-bit PCI bus master interface, as well as large, flexible internal memory buffers, to provide high-speed data throughput and low CPU and system bus utilization. For PCI configuration, the Ethernet controller is accessed as device number 5. The Am79C972 can be configured by the PCI configuration space mechanism or it can download its configuration from a 1-Kbyte serial EEPROM (part U54 at location D6). The PCI CDP uses the serial EEPROM interface to configure the Am79C972 device. The EEPROM is preprogrammed with an Ethernet configuration suitable for the PCI CDP. In addition to the Ethernet configuration EEPROM, a 4-Kbyte serial EEPROM is provided for user nonvolatile data. See “4-Kbyte Serial EEPROM (C4)” on page 2-14. For customer designs, the PCnet-FAST+ controller is offered with AMD’s extensive suite of industry-proven PCnet software drivers, remote boot ROM firmware (not supported by the PCI CDP), and a complete set of supporting utilities and design tools. Follow the Networking link at www.amd.com for information about networking software, support, and tools. Am486® Microprocessor PCI Customer Development Platform 2-13 The PCnet-FAST+ device supports the industry’s Net PC specification. The PCnetFAST+ device also complies with Microsoft’s PC97 and PC98 requirements by fully supporting the OnNow and ACPI power management initiatives; however, the PCI CDP does not implement OnNow or ACPI. A customer design could support these technologies by using an ATX-style power supply and motherboard design. 4-Kbyte Serial EEPROM (C4) An extra NM93C66M8 4-Kbyte serial EEPROM (part U81) is connected to the Am79C972 Ethernet controller’s serial EEPROM interface. This provides additional EEPROM space for storing user nonvolatile data. The M1487 device’s CLKCTL signal (controlled via chipset register 40h) is used to multiplex the Ethernet controller’s EEPROM chip select between the 1-Kbyte EEPROM and the 4-Kbyte EEPROM. When CLKCTL is asserted (the default), the Ethernet controller’s 1-Kbyte configuration EEPROM (part U54) is accessed normally. When CLKCTL is deasserted, the Ethernet controller’s EEPROM interface registers can be used to access the 4-Kbyte EEPROM to store or retrieve user data. See Sheet 13 of the schematics in Appendix B. Software for using the 4-Kbyte EEPROM is provided with the PCI CDP. See the readme file on the diskette that came with your kit for information about available utilities. 2-14 Am486® Microprocessor PCI Customer Development Platform User’s Manual Development Support The PCI CDP includes the following facilities for development support: • JTAG port • CPU-bus and PCI-bus logic analyzer headers • Port 80 and Port 680 hexadecimal displays • TIP board interface These features are described in the following paragraphs. JTAG Ports (Q14 and D17) The Am486 microprocessor provides an IEEE Standard 1149.1-1990 (JTAG) compliant test access port and boundary-scan architecture. The JTAG port provides a scan interface for testing the microprocessor in a production environment. The microprocessor’s JTAG port is available on connector J35 at location Q14. Do not attempt use the second JTAG port (part P48 at location D17). This port is used at AMD to program the Vantis™ MACH® programmable logic device. Reprogramming of the MACH device can cause improper system operation. The MACH device controls the ISA Flash memory space and the Port 80h and 680h hexadecimal displays. See “ISA Flash Memory (F20)” on page 2-23 and “Hexadecimal Display (H23, J23)” on page 2-17. Logic Analyzer Headers The CPU interface signals are buffered and routed to headers for a logic analyzer. The signals on the CPU bus logic analyzer headers are arranged to be compatible with the disassembler for the HP 16500 Logic Analyzer, but any analyzer can be used. Table 2-3 lists the available headers, their locations in Figure 2-3, and the Appendix B schematics sheet on which they appear. Sheet 4 of the schematics includes usage notes. Am486® Microprocessor PCI Customer Development Platform 2-15 Table 2-3. Analyzer Headers 2-16 Part Description Location in Figure 2-3 on Page 2-5 See App. B Schematics on: P36 POD 4, Microprocessor data (GD) signals P24 Sheet 4 P38 POD 3, Microprocessor data (GD) signals M24 Sheet 4 P39 POD 2, Microprocessor control signals, plus LA qualifier (see note on schematics Sheet 4) L11 Sheet 5 P40 POD 6, Microprocessor address (GA) signals I17 Sheet 5 P41 POD 1, Microprocessor control signals K16 Sheet 5 P42 POD 5, Microprocessor address (GA) signals, including logicderived GA0 and GA1 signals I20 Sheet 5 P43 PCI Address and Data (PAD) signals F11 Sheet 12 P44 PCI Address and Data (PAD) signals H9 Sheet 12 P45 PCI control signals C12–D13 Sheet 12 P46 PCI control signals C9–D10 Sheet 12 P47 POD 7, Miscellaneous microprocessor control signals K10 Sheet 4 Am486® Microprocessor PCI Customer Development Platform User’s Manual In addition to the logic analyzer headers, separate three-pin headers are provided for each PCI device’s bus request and bus grant signals. These headers are listed in Table 2-4: Table 2-4. PCI Bus Master Test Points Part Signal Location in Figure 2-3 on Page 2-5 See App. B Schematics on: JP29 PREQJ0 PGNTJ0 GND I6 Sheet 12 JP30 PREQJ1 PGNTJ1 GND K5 Sheet 12 JP31 PREQJ2 PGNTJ2 GND E7 Sheet 12 In-Circuit Emulator Compatibility (M14, Q15–Q16) The PCI CDP can be used with an in-circuit emulator that mates to the pin-gridarray (PGA) zero-insertion-force (ZIF) socket in place of the Am486 microprocessor. To support emulators that use an Intel microprocessor, the necessary CPU power-supply jumpers are provided so the board will work with Intel 486 DX2 and DX4 chips. See “CPU Voltage Adjustment (Q15–Q16)” on page 2-32. When connecting an in-circuit emulator, risers might be required to allow proper placement relative to the microprocessor socket and the ISA slots. Hexadecimal Display (H23, J23) The PCI CDP includes 2-digit hexadecimal displays for port 80h and port 680h debugging messages. To change the display value, perform an 8-bit write to I/O port 80h or 680h, respectively. The value written is latched by the display and cannot be read back by software. Am486® Microprocessor PCI Customer Development Platform 2-17 Test Interface Port (TIP) (A16) The PCI CDP includes a connector for the AMD Test Interface Port (TIP) board. The TIP board is used for testing and debugging AMD embedded product customer development platforms. It connects through a ribbon cable to the TIP connector on the platform. The TIP board provides a collection of peripherals, such as LEDs, hexadecimal displays, an LCD display, two serial ports, a parallel port, an Ethernet controller, and Flash memory, that can be convenient in system development. The PCI CDP’s TIP connector resides on the ISA bus and can use the ISA interrupt request (IRQ) signals if a TIP board is connected. Individual TIP connector IRQ signals are listed in Table 2-5. See the TIP board documentation for I/O addressing information. Table 2-5. TIP Interrupt Usage TIP Function Interrupt TIP Ethernet IRQ15 TIP parallel port IRQ12 TIP serial port 1 IRQ11 TIP test function IRQ14 TIP serial port 2 IRQ10 NOTE: The TIP board’s IRQ usage can conflict with the PCI CDP’s onboard PC peripherals. Some TIP or CDP peripherals may not operate correctly when the TIP board is in use. 2-18 Am486® Microprocessor PCI Customer Development Platform User’s Manual PCI Bus (I7) The PCI CDP has two desktop-PC-style PCI expansion connectors (parts SLT1 and SLT2) to allow the installation of a wide array of off-the-shelf 5-V PCI devices. These include standard devices such as video, sound, SCSI, or PCMCIA adapters, or diagnostic devices such as PCI bus analyzers, extender cards, and other diagnostic hardware. The slots do not support 3.3-V PCI peripherals. The PCI bus is implemented via the chipset’s M1489 northbridge chip except for bus arbitration, which is handled by the M1487. For PCI bus configuration, connector SLT1 is addressed as Device 3 and SLT2 is addressed as Device 4. See Table 2-2, “PCI Configuration Addressing,” on page 2-11. The PCI bus connector’s interrupt signals are routed as shown in Table 2-6. (The Ethernet interrupt signal is also shown for reference.) The initialization code dynamically assigns PCI interrupts to an interrupt request (IRQ) in the chipset’s PCI INTx routing table mapping registers. See the chipset documentation for details on the mapping registers. Table 2-6. PCI Bus Interrupt Routing PCI Bus Interrupt PCI Slot 1 Signal PCI Slot 2 Signal Ethernet Signal INT0 INTA INTD — INT1 INTB INTA — INT2 INTC INTB INTA INT3 INTD INTC — Am486® Microprocessor PCI Customer Development Platform 2-19 Level-2 Cache Memory (K19–N19 and N11) The PCI CDP includes an onboard 512-Kbyte, single-bank, direct-mapped, unified Level-2 cache. This is the largest single-bank cache allowed by the chipset. The cache tag and data static RAM (SRAM) devices are soldered onto the PCI CDP board. A 10-ns tag SRAM device and 15-ns data SRAM devices are used to achieve 2-1-1-1 timing on reads and 2-2-2-2 on writes. The tag SRAM is a single 32-K by 8-bit device, part U11, and the data SRAMs are 128-K by 8-bit devices, parts U7, U8, U9, and U10. Chipset registers allow the level-2 cache to be disabled or enabled. The level-2 cache can be configured for either write-back or write-through operation. NOTE: The benefit of level-2 cache varies, depending on the software being used. DRAM Main Memory (P7) The PCI CDP comes with three standard, 5-V, 72-pin single inline memory module (SIMM) sockets, populated with three 16-Mbyte, 60-ns, extended data out (EDO) SIMMs. The included SIMMs provide the largest and fastest DRAM configuration allowed in this design. For customer designs, the SIMM configurations supported depend upon the chipset and the initialization or BIOS code used to configure the chipset’s registers. See the chipset documentation for information about detecting and configuring DRAM. The BIOS provided will automatically detect the amount of DRAM installed. The chipset used in this design supports 2-, 4-, 8-, 16-, or 32-Mbyte SIMMS using 4- or 16-Mbit technology DRAM chips. Either fast page mode (FPM) or EDO SIMMs can be used, and the sockets can be filled with a combination of FPM or EDO SIMMs. All installed SIMMs must be run at the same speed, however. The chipset allows either 1, 2, or 3 DRAM banks. Single- and double-bank SIMMs can be combined as shown in Table 2-7 on page 2-21. 2-20 Am486® Microprocessor PCI Customer Development Platform User’s Manual Table 2-7. SIMM Socket Population Chart SIMM 0 SIMM 1 SIMM 2 Single Bank SIMM Single Bank SIMM Single Bank SIMM Double Bank SIMM Single Bank SIMM — NOTE: 32- or 36-bit-wide memory can be used. However, 36-bit EDO SIMMs are accessed as only 32 bits wide because the FINALi chipset does not support EDO SIMMs’ 32-bit data plus 4-bit error correction code (ECC) format. Only traditional byte-wide parity is supported. Boot ROM (C16) The PCI CDP provides a 0.5-inch wide 32-pin DIP socket (part U14) for an initialization or BIOS ROM device. The boot ROM is implemented on the M1487 chip’s LinkBus. The boot ROM socket is populated with a BIOS that allows the PCI CDP to boot and run DOS, Windows, or a real-time operating system (RTOS) immediately. The platform must always boot from the boot ROM because of chipset limitations. The chipset does not allow booting from another source such as DRAM-bus, ISAbus, or PCI-bus memory. The boot ROM address space size defaults to 128 Kbytes, using ROM device address bits A0–A16, but the board design provides jumpers JP32 and JP33 (at locations C14 and B14) for configuring the ROM device’s A17 and A18 address signals. The jumpers allow these address bits to be left High, tied Low, or connected to their corresponding ISA bus signal. This provides flexibility in addressing various sized Flash memory or ROM devices. See Figure 2-5 on page 2-22 Am486® Microprocessor PCI Customer Development Platform 2-21 JP33 (SA18) 1 2 JP32 (SA17) 3 1 2 5V 3 ISA Signal 1 2 3 (SA17 or SA18) Boot ROM ROM Pin (A17 or A18) ROM Jumper Locations Individual Jumper Schematic Figure 2-5. JP32 and JP33 Jumper Configuration (B14–C14) By default, jumpers JP32 and JP33 are not connected, so ROM device pins A17 and A18 are tied High to address the 128-Kbyte BIOS range, E0000h–FFFFFh. If these jumpers are changed to select ISA addressing for addresses C0000h–DFFFFh, software must enable ROM addressing for this space via chipset register index 12h, bits 2–1, and index 44h, bits 7–6. For software compatibility, the boot ROM image appears from E0000h to FFFFFh in the Am486 microprocessor’s lower 1-Mbyte address space. (This assumes that a 128-Kbyte boot ROM is used.) At reset, however, the microprocessor is in a special state that causes it to fetch its first instruction from FFFFFFF0h, at the top of its extended memory range. To provide the first instruction, the boot ROM is aliased to begin at FFFE0000h. One of the first instructions is typically a far jump, which ends the special state and causes the microprocessor to continue execution in the lower 1-Mbyte space. Because boot ROM accesses are relatively slow, subsequent initialization code typically copies the boot ROM contents into DRAM space and configures the chipset’s Shadow Region Register to direct all boot ROM accesses to this shadow image of the boot ROM. 2-22 Am486® Microprocessor PCI Customer Development Platform User’s Manual ISA Flash Memory (F20) The PCI CDP includes 1 Mbyte of 16-bit wide AMD Flash memory soldered onto the board and located logically on the ISA Bus. A Vantis MACH programmable logic device is used to control the interface between the ISA bus and the Flash device. This provides an example of how a small amount of ISA Flash memory might be implemented in customer designs. The ISA Flash memory employs one Am29F800 top-sector boot block Flash memory chip (part U58). This device occupies ISA memory space from address F00000h to FFFFFFh. See Figure 2-6 on page 2-24. Software should access this space in 16-bit words on even addresses. Software can enable this ISA memory space by setting bit 3 of the chipset’s ROM Function Register, index 12h. This disables DRAM access in the 1-Mbyte range from F00000h to FFFFFFh, allowing access to the ISA memory space instead. If bit 3 of index 12h is clear, access to the ISA Flash memory space is allowed only if 15 Mbytes or less of DRAM is installed. The Flash device is configured in word mode, so only 16-bit access is allowed. The ISA address signals are routed so that ISA address bit A1 is routed to bit A0 on the Flash device, so it can only be addressed on even word boundaries. When generating Flash command sequences, multiply the Flash address by two to generate the correct ISA address. For example, writing address F00AAAh asserts 555h (AAAh ÷ 2) on the Flash device’s address pins. The Am29F800 can be programmed using the JDEC single-power-supply Flash standard command set. See the Am29F800 documentation for details. Software for using Flash memory is provided with the PCI CDP. See the readme file on the diskette that came with your kit for information about available utilities. ISA space is limited to 16 Mbytes, and because the chipset provides limited support for mapping ISA memory windows over DRAM, only 1 Mbyte of Flash memory is provided. However, in a customer design with a small amount of DRAM, a larger ISA Flash memory space can be situated between the top of DRAM and the 16 Mbyte ISA address limit. Note that access to memory on the ISA bus is relatively slow when compared to DRAM or PCI bus transactions. See “EIP Flash Memory (L21)” on page 2-25 for another approach. Am486® Microprocessor PCI Customer Development Platform 2-23 (56 Mbyte) 37FFFFFh 3400000h (52 Mbyte) 33FFFFFh EIP Flash Bank 1 EIP Flash Bank 0 3000000h (48 Mbyte) 2FFFFFFh } Accessed as Fourth DRAM Bank (Bank 3) } Enabled Via Chipset Register 12h, Bit 3 EIP Location Depends on DRAM Size DRAM 1000000h (16 Mbyte) FFFFFFh ISA Flash Memory F00000h (15 Mbyte) EFFFFFh DRAM 100000h 128 Kbyte Boot ROM (1 Mbyte) 0FFFFFh DRAM 000000h Figure 2-6. Typical Memory Map With ISA and EIP Flash Memory 2-24 Am486® Microprocessor PCI Customer Development Platform User’s Manual EIP Flash Memory (L21) The PCI CDP includes 8 Mbytes of Flash memory for execute-in-place (EIP) applications. The EIP Flash memory is implemented in the fourth bank (bank 3) of the DRAM controller’s address space. This memory consists of eight 29F800B top-sector boot block Flash memory devices (parts U61, U62, U63, U64, U65, U66, U67, and U68), soldered to the board and organized as two 32-bit wide Flash memory banks. The EIP Flash memory is controlled by an AMD 22V10 PAL® device programmed to act as a simple DRAM-to-Flash interface that makes the Flash memory appear to the M1489 DRAM controller as a single bank of 32-bit-wide EDO DRAM. The provided BIOS enables the EIP Flash memory and configures the other DRAM banks accordingly. To enable the EIP Flash memory, the BIOS programs the chipset’s DRAM Configuration Register 2 (index 11h, bits 4–7) so the fourth DRAM bank is accessed as 2-Mbyte by 8 (11 row, 10 column) DRAM chips. The DRAM-to-Flash interface uses CPU address bit A22 for Flash memory bank switching (A22 is routed to DRAM address bit 8 in the selected configuration). Because of timing requirements, it is also necessary to program the chipset’s DRAM Configuration and Timing Control registers (index 1Ah and 1Bh) to disable hidden refresh, disable RAS-only refresh, select Fast access mode (not Fastest), and select CAS before RAS refresh. This affects all four DRAM banks. The EIP Flash memory can be accessed only by the CPU (no PCI bus-master access to the EIP Flash is allowed), and all accesses are 32 bits wide. During normal operation, the EIP Flash memory can be read like other DRAM memory, but data cannot be written directly. Instead, the Am29F800 devices are programmed using the JDEC single-power-supply Flash standard command set. See the Am29F800 documentation for details. Software for using Flash memory is provided with the PCI CDP. See the readme file on the diskette that came with your kit for information about available utilities. Software that writes to the EIP Flash memory must make sure that accesses to the Flash memory are not cached. This can be done by disabling Level-1 and Level-2 memory caching, or by appropriate programming of the page tables if paging is enabled in the microprocessor. Am486® Microprocessor PCI Customer Development Platform 2-25 Software that writes to the EIP Flash memory must also avoid any back-to-back write cycles (including back-to-back non-burst cycles) to the EIP Flash memory space. For reliable writes, always read or write a different DRAM bank (0, 1 or 2) before and after writes to the EIP space. For example, read location 00000h, write a value to Flash memory, and then read location 00000h again. (Simply running the Flash programming software in the normal DRAM space does not ensure reliable Flash programming, even though caching is disabled.) Reading the EIP Flash memory does not entail any of the timing restrictions that apply to writes. The microprocessor can read EIP Flash memory with any combination of single-beat or burst read cycles. The EIP Flash memory itself is organized in two banks. The base address of each EIP bank depends on how much DRAM is installed in DRAM banks 0–2. The board is shipped with 48 Mbytes installed, so by default the EIP first bank base address is 3000000h (48 Mbytes + 1 byte), and the EIP second bank base address is 3400000. See Figure 2-6 on page 2-24. Software can query the chipset’s DRAM Configuration Registers (index 10h and 11h) to determine the size of banks 0–2. See the chipset documentation for a description of these registers. Each Flash device is configured in byte mode, with four devices in each EIP bank. The CPU address signals are routed so that CPU address bit A2 is routed to bit A0 on the Flash devices, so the EIP space can only be addressed on even 4-byte (32bit double-word) boundaries. When writing to the devices’ control registers, multiply the byte-mode register offset by four to generate the correct CPU address. For example, if the bank base address is 3000000h, writing address 3002AA8h asserts AAAh (2AA8h ÷ 4) on each Flash device’s address pins. 2-26 Am486® Microprocessor PCI Customer Development Platform User’s Manual Real-Time Clock (G17) The real-time clock (RTC) function in the chipset’s 1487 chip is initially disabled on the PCI CDP. Instead, a separate DS1685 year-2000 (Y2K)-compliant RTC is enabled. The DS1685 provides the features of widely-used, non-Y2K-compliant RTCs such as the DS1287. In addition, the DS1685 provides a byte for storing century information, plus other registers and features not found in older RTC chips. Because of its extra features, the DS1685 RTC is not completely compatible with the DS1287. The provided BIOS operates correctly with the DS1685 RTC, but the extra RTC features can cause unexpected behavior if a customer-supplied BIOS is used in PC-AT compatible systems. One example is that the DS1685 provides some interrupt sources that are not present in the DS1287 RTC. Customer-written initialization software can take the following steps to disable the extended RTC interrupts: 1. Set the DV0 bit in CMOS register A to enable access to the extended register bank in the DS1685. 2. Write a value of 60h to CMOS address 4Bh to disable the extended interrupt addresses. 3. Clear the Dv0 bit in CMOS register a to disable access to the extended register bank (so that legacy software behaves as expected). 4. Read CMOS register C to clear any pending interrupts that were triggered while the extended interrupts were enabled. For DS1685 RTC programming details, see the DS1685/DS1687 3 Volt/5 Volt Real Time Clock Data Sheet, and Application Note 77: DS1585/87, DS1685/87, and DS17x85/87 Accessing Extended User RAM via Software, available from Dallas Semiconductor, www.dalsemi.com. If desired, the M1487’s internal RTC can be enabled instead of the DS1685 by removing resistor part R58 from the back side of the board, beneath location I14. (See Sheet 16 of the schematics in Appendix B.) Am486® Microprocessor PCI Customer Development Platform 2-27 ISA Bus Interface (A7) The PCI CDP is populated with two standard ISA bus connectors (parts SL1 and SL2) for developers who need to use ISA devices in their development systems. The ISA bus interface is provided by the chipset’s M1497 southbridge. ISA devices that use the F00000h to FFFFFFh address space cannot be used on the PCI CDP, because this area is used by the ISA Flash memory bank. See “ISA Flash Memory (F20)” on page 2-23. ISA devices that use the C0000h to DFFFFh address space cannot be used if this space is enabled for boot ROM addressing. See “Boot ROM (C16)” on page 2-21. Boot ROM addressing in this range might also cause conflicts with devices using the D0000h to DFFFF address space. Super I/O (C19) The PCI CDP uses an M5113 Super I/O chip to provide standard PC input/output functions. The Super I/O chip provides: • • • • Two 16450/16550-compatible serial ports IrDA 1.0 infrared interface AT-compatible parallel port 82077-compatible floppy disk interface The BIOS supplied with the platform configures these peripherals to operate as they would on a standard PC. See the Acer Laboratories Inc. M5113 data sheet for detailed configuration information. 2-28 Am486® Microprocessor PCI Customer Development Platform User’s Manual Serial Ports (E23 and C23) The platform’s Super I/O device includes two 16550-compatible serial ports. These are routed to two 9-pin D-shell connectors, J8 and J9. See Figure 2-7 and Table 28. Light-emitting diodes (LEDs) are provided near each serial port to indicate transmit and receive activity. 1 5 Notes: 6 9 See Figure 2-3 on page 2-5 for connector locations. Figure 2-7. Serial Port Connector Pins (J8, J9) Table 2-8. Serial Port Pin/Signal Table Pin Signal 1 DCD 2 RXD 3 TXD 4 DTR 5 GND 6 DSR 7 RTS 8 CTS 9 RIN IrDA Interface (A19) The Super I/O device is configured to support infrared data transfers via an IrDA LED module, part U44. The serial data transmission rates include all of the UART bit rates (up to 115 Kbps). The IrDA LED module is connected to dedicated pins on the M5113 Super I/O chip. The IrDA interface shares one UART with serial port COM2. A control bit in the M5113 chip controls whether the UART communicates over the COM2 port or the IrDA port. See the M5113: Enhanced Super I/O Controller Data Sheet, available from Acer Laboratories Inc. See www.acerlabs.com for contact information. Am486® Microprocessor PCI Customer Development Platform 2-29 Parallel Port (A22) Figure 2-8 and Table 2-9 show the parallel port pinouts. 13 1 Notes: 25 14 See Figure 2-3 on page 2-5 for connector locations. Figure 2-8. Parallel Port Socket (J4) Table 2-9. Parallel Port Pin/Signal Table Pin Signal 1 STRB 2–9 PD0–PD7 10 ACK 11 BUSY 12 PE 13 SLCT 14 AFDT 15 ERROR 16 INIT 17 SLCTIN 18–25 GND Floppy Disk Drive (E20) The PCI CDP’s Super I/O chip provides a floppy disk controller to support the system’s floppy disk drive connector (part J6). Either a 5.25-inch or 3.5-inch floppy disk drive can be installed with a standard 34-pin connector. For details, see “Board Installation” on page 1-4. 2-30 Am486® Microprocessor PCI Customer Development Platform User’s Manual IDE Hard Drive (L4 and M4) The PCI CDP contains two standard 40-pin IDE connectors (parts J5 and J7). The M1498 chip provides the IDE hard drive controller. For details on how to connect a single IDE hard drive to the PCI CDP, see “Board Installation” on page 1-4. An LED is located next to each IDE connector to indicate IDE activity. IDE devices on connector J5 can generate interrupts on IRQ14, and devices on connector J7 can generate interrupts on IRQ15. This interrupt mapping can be changed by reprogramming the chipset configuration registers. Each connector supports one master and one slave device. If only one device is attached to an IDE connector, that device must be configured as an IDE master. If a two-position cable is used to attach two devices to a single IDE connector on the board, one of the devices must be configured as an IDE master and the other as an IDE slave. See each IDE device’s documentation for configuration details. Keyboard (O1) The PCI CDP provides a standard AT-compatible keyboard connector (part J1) implemented via the chipset’s M5402 mouse/keyboard controller chip (part U79 at location D15). Mouse (M1) A port is provided for a PS/2-style mouse (connector J11). This device is driven by the M5402 mouse/keyboard controller chip. Am486® Microprocessor PCI Customer Development Platform 2-31 CPU Voltage Adjustment (Q15–Q16) The CPU power supply voltage can be adjusted by moving jumper JP4 or both jumpers JP2 and JP3 on the PCI CDP. Selectable voltages are 2.5 V, 3.3 V, 3.45 V, or 5 V. Figure 2-9 shows the default configuration of the CPU voltage jumpers (set for 3.45 V). To select either 3.3-V or 2.5-V CPU voltage, leave JP2 and JP3 set to “ADJ” and move jumper JP4 to the desired voltage. To select 5-V operation, move both jumpers JP2 and JP3 to their “5 V” position. JP2 JP3 ADJ ADJ JP4 3.45 V 3.3 V 5V 5V 2.5 V Figure 2-9. Voltage Jumper Default Configuration (Q15–Q16) ! 2-32 CAUTION: Jumpers JP2 and JP3 must both be placed in the same position. Positioning JP2 and JP3 differently can damage the PCI CDP. Am486® Microprocessor PCI Customer Development Platform User’s Manual Power Supply Connectors (N2 and P2) The PCI CDP accepts standard PC-style motherboard power connectors to supply power to the CPU and all onboard components. To ensure proper functionality of the power module, the board’s PC power supply sockets must be inserted correctly onto the board. ! CAUTION: It is important that the ground wires of one connector are adjacent to the ground wires of the other. See Figure 2-10. -5 GND Back of IDE Connector +5 GND -12 +12 +5 PWG PS2 Power Conn Power Supply Conn. Edge of Board Figure 2-10. Ground Wire Connections Am486® Microprocessor PCI Customer Development Platform 2-33 Reset and Interrupt Switches and Headers Three push-button switches are provided so the user can generate RESET, SMI, and NMI events. In addition, a two-pin header is provided for the RESET signal so that an external pushbutton switch can be attached. These switches and headers are routed to the appropriate chipset signals as listed in Table 2-10. Table 2-10. Switch Summary Part Signal Description Location in Figure 2-3 on Page 2-5 See App. B Schematics on: SW1, JP34 PWG Used to reset the system. N5, K23 Sheet 17 SW2 NMI Used to generate an NMI event. K6 Sheet 17 SW3 EXTSMI Used to generate an SMI event. H11 Sheet 17 Embedded BIOS software typically enters its debugging monitor when an NMI event is generated. In addition to pressing the NMI switch, an NMI event can be caused by a PCI-bus parity error, a DRAM parity error, or an ISA-bus IOCHCK error. 2-34 Am486® Microprocessor PCI Customer Development Platform User’s Manual Resistor Options The PCI CDP includes a number of resistor populate/depopulate options, which are listed in Table 2-11. Many are used only as manufacturing options, but some may be useful for exploring design options or better emulating a target design. Table 2-11. Resistor Options Part Signal Description Location in Figure 2-3 on Page 2-5 See App. B Schematics on: R11 CLKMUL When R11 is populated and R148 is removed, the clock multiplier for an Am486DX2-66 microprocessor is selected. M17 Sheet 2 R58 ENRTC When populated (the default), the M1487 chip’s internal RTC is disabled and the DS1685 Y2K-compliant RTC is enabled. I14 (back side) Sheet 16 R59 CMPSTJ When removed (the default), the 1X CPU-to-PCI bus frequency multiplier is selected. (1X is the only multiplier supported in this design.) I14 (back side) Sheet 16 R70 TURBO When R70 is removed and R71 is populated (the default), the M1487’s TURBO signal is High (asserted). This input must be enabled by software to have any effect. I14 (back side) Sheet 17 R71 TURBO When R71 is populated and R70 is removed (the default), the M1487’s TURBO signal is asserted. This input must be enabled by software to have any effect. I14 (back side) Sheet 17 R93 CLKPU2 When R93 is populated and R176 is removed, the system clock speed is 25 MHz. J3 (back side) Sheet 18 Am486® Microprocessor PCI Customer Development Platform 2-35 Table 2-11. Resistor Options (Continued) Part Signal Description Location in Figure 2-3 on Page 2-5 See App. B Schematics on: R145 KBINHIBIT When R145 is populated and R146 is removed (the default), the M5042 keyboard controller is enabled. D15 (back side) Sheet 25 R146 KBINHIBIT When R145 is populated and R146 is removed (the default), the M5042 keyboard controller is enabled. D15 (back side) Sheet 25 R148 CLKMUL When R148 is populated and R11 is removed (the default) the clock multiplier for an Am486DX4-100 or Am486DX5-133 microprocessor is selected. M17 Sheet 2 R170 IBCSTJ When populated (the default), the M1487’s internal keyboard controller is disabled. (The M1487 internal keyboard controller function is discontinued. The M5042 is provided instead.) I14 (back side) Sheet 16 R176 CLKPU2 When R176 is populated and R93 is removed (the default), the system clock speed is 33 MHz. J3 Sheet 18 2-36 Am486® Microprocessor PCI Customer Development Platform User’s Manual Appendix A Default Settings This chapter lists the default settings of the Am486 microprocessor PCI customer development platform when it is shipped. Table A-1. Default Jumper Settings Part Signal Location in Default Position Figure 2-3 on Page 2-5 Position Marking JP2 CPUVCC3 Q15 Pins 2–3 “ADJ” JP3 CPUVCC3 Q16 Pins 2–3 “ADJ” JP4 CPUV1, CPUV2, CPUV3 R15 Pins 1–2 “3.45 V” JP32 Boot ROM A17 C14 No connection (No marking) JP33 Boot ROM A18 B14 No connection (No marking) Am486® Microprocessor PCI Customer Development Platform A-1 A-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual Appendix B Bill of Materials and Schematics The bill of materials for the Am486 microprocessor PCI customer development platform (CDP) begins on page B-2. The actual schematics used to build the PCI CDP begin on page B-10. Am486® Microprocessor PCI Customer Development Platform B-1 Board Bill of Materials (BOM) Item Qty. Reference Part Package Description 1 119 C1, BC1, BC2, C3, BC3, C4, BC4, C5, BC5, C6, BC6, C7, BC7, C8, BC8, BC9, BC10, BC11, BC12, BC13, BC14, BC15, BC16, BC17, BC18, BC19, BC20, BC21, BC22, BC23, BC24, BC25, BC26, BC27, BC28, BC29, BC30, BC31, BC32, BC33, BC34, BC35, C36, BC36, C37, BC37, C38, BC38, C39, BC39, BC40, BC41, BC42, BC43, BC44, BC45, BC46, C47, BC47, C48, C50, C52, C65, C67, C69, C70, C71, C72, C73, C74, C75, C76, C77, C79, C80, C81, C82, C88, C89, C90, C91, C92, C93, C94, C95, C100, C105, C111, C112, C114, C115, C122, C123, C124, C125, C126, C127, C128, C129, C130, C131, C132, C133, C134, C135, C136, C137, C156, C157, C160, C166, C167, C168, C169, C170, C171, C172, C173, C174 0.1 µF 805 RC0805, X7R, ±10%, 50 V 2 1 BT1 3 V Coin cell (socket) 3 14 C9, C10, C11, C12, C13, C34, C35, C83, C96, C97, C102, C103, C104, C109 0.01 µF 805 RC0805, X7R, ±10%, 50 V 4 6 C14, C28, C58, C64, C158, C159 47 pF 805 RC0805, NPO, ±5%, 50 V 5 33 C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C29, C30, C31, C32, C138, C139, C140, C141, C142, C143, C144, C145, C146, C147, C148, C149, C150, C151, C152, C153 180 pF 805 RC0805, NPO, ±10%, 50 V KEYSTONE 103 or 106 Notes: An asterisk (*) indicates parts that are not populated. B-2 Am486® Microprocessor PCI Customer Development Platform User’s Manual Item Qty. Reference Part Package Description 6 10 C33, C41, C42, C43, C46, C56, C57, C60, C66, C154 15 pF 805 RC0805, NPO, ±5%, 50 V 7 1 C40 1000 pF 805 RC0805, 1/8 W, ±5%, 50 V 8 2 C44, C45 39 pF 805 RC0805, NPO, ±5%, 50 V 9 4 C53, C54, C155, C161 10 pF 805 RC0805, NPO, ±5%, 50 V 10 1 C55 22 pF 805 RC0805, NPO, ±5%, 50 V 11 1 C68 6.8 µF C-CASE TANTALUM, C-CASE, 16 V, ±20% 12 2 C86, C78 2.2 µF B-CASE TANTALUM, B-CASE, 20 V, ±20% 13 23 TC2, TC3, TC9, TC11, TC12, TC13, TC14, TC15, TC16, TC17, TC18, TC19, TC22, TC23, TC24, TC25, C84, C87, C106, C107, C108, C110, C113 10 µF C-CASE TANTALUM, C-CASE, 16 V, ±20% 14 1 C85 1 µF A-CASE TANTALUM, A-CASE, 16 V, ±20% 15 2 C98, C99 33 pF 805 RC0805, NPO, ±5%, 50 V 16 1 C101 0.001 µF, 2 KV (MIN.) TH SPRAGUE 30GAD10 17 4 C162, C163, C164, C165 0.015 µF 805 RC0805, X7R, ±10%, 50 V 18 6 D1, D5, D6, D7, D8, D9 MMBD4148 (SOT23) SOT-23 VISHAY MMBD4148 19 1 D10 LED (SOT23) SURSOT23 LUMEX SSL-LX15IC-RP 20 4 D11, D12, D13, D14 LED (SOT23) SURSOT23 LUMEX SSL-LX15GC-RP 21 2 D15, D17 LED (2mA, SOT23) SOT-23 KINGBRIGHT KM-23LSGC Notes: An asterisk (*) indicates parts that are not populated. Am486® Microprocessor PCI Customer Development Platform B-3 Item Qty. Reference Part Package Description 22 2 D16, D18 LED (2mA, SOT23) SOT-23 KINGBRIGHT KM-23LEC 23 2 F1, F2 FUSE, 0.5A 1206 BUSSMAN 3216FF-500mA 24 1 HS1 HEATSINK (TO-220) 25 7 JP2, JP3, JP29, JP30, JP31, JP32, JP33 HEADER 3X1 TH-1X3 1X3 HEADER; 0.025” SQ. POST AMP 87224-3 26 1 JP4 HEADER 3X2 TH-2X3 1X3 HEADER; 0.025” SQ. POST AMP 103186-3 27 1 JP34 HEADER 2X1 TH-1X2 1X2 HEADER; 0.025” SQ. POST AMP 87224-2 28 1 J1 KYBD CONN TH AMP 212044-1 29 2 J2, J3 PWR-CN6 TH MOLEX 15-48-0106 30 1 J4 Parallel Port DB25 AMP 745967-7 31 2 J7, J5 CNN-40C TH-2X20SHRD 2X20 HEADER; SHRD AMP 103308-8 32 1 J6 CNN-34C TH-2X17SHRD 2X17 HEADER; SHRD AMP 103308-7 33 2 J8, J9 SERIAL PORT DB9 AMP 745410-1 34 1 J10 AMP RJ45A TH AMP 555153-1 35 1 J11 MOUSE_CON TH AMP 750329-2 36 1 LS1 SPEAKER 37 9 L1, L2, L3, L4, L5, L6, L7, L8, L9 FB 38 10 MT1, MT2, MT3, MT4, MT5, MT6, MT7, MT8, MT9, MT10 Mounting Hole 39 1 P31 40 2 P35, P48 THERMALLOY ML32 ISL PROD. INTL. ISL-8032VT RC1206 MURATA ERIE BLM32A07 COND60 AMPMOD 50, 1X30, R-ANG AMP 104069-7 HEADER2X5; SHRD TH-1X5SHRD 2X5 HEADER; SHRD AMP 103308-1 Notes: An asterisk (*) indicates parts that are not populated. B-4 Am486® Microprocessor PCI Customer Development Platform User’s Manual Item Qty. Reference Part Package Description 41 11 P36, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47 HP CONN TH-1X10SHRD 3M:2520-6003UB or AMP 103308-5 42 1 Q1 MMBT3906 (SOT23) SOT-23 VISHAY MMBT3906 43 2 Q4, Q2 MMBT3904 (SOT23) SOT-23 VISHAY MMBT3904 44 1 Q5 TIP127 TO-220 MOTOROLA TIP127 45 9 RN1, RN2, RN3, RN4, RN8, RN9, RN10, RN11, RN12 33-8B CTS 743 08-3 330 J TR 46 7 RN5, RN6, RN7, RN13, RN14, RN15, RN16 22-8B CTS 743 08-3 220 J TR 47 12 RP1, RP2, RP5, RP6, RP7, RP12, RP14, RP16, RP17, RP18, RP19, RP20 10 K-10P SIP10 CTS 770 10 1 103 SP 48 2 RP4, RP3 1 K-10P SIP10 CTS 770 10 1 102 SP 49 6 RP8, RP9, RP10, RP11, RP15, RP21 4.7 K-10P SIP10 CTS 770 10 1 472 SP 50 1 RP13 330-8P SIP8 CTS 770 8 1 331 SP 51 19 R3, R4, R5, R13, R19, R49, R50, R52, R61, R64, R68, R76, R77, R91, R104, R131, R141, R142, R175 10 K 805 RC0805, 1/8 W, ±5%, 50 V 52 17 R6, R20, R21, R34, R58, R78, R85, R103, R105, R118, R130, R134, R170, R173, R174, R177, R178 1K 805 RC0805, 1/8 W, ±5%, 50 V 53 5 R7, R8, R27, R81, R124 33 805 RC0805, 1/8 W, ±5%, 50 V 54 1 R11 *10 K 805 RC0805, 1/8 W, ±5%, 50 V 55 6 R14, R15, R16, R17, R18, R147 22 805 RC0805, 1/8 W, ±5%, 50 V 56 11 R22, R31, R35, R36, R38, R41, R42, R54, R99, R100, R101 10 805 RC0805, 1/8 W, ±5%, 50 V 57 1 R23 27.4 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V Notes: An asterisk (*) indicates parts that are not populated. Am486® Microprocessor PCI Customer Development Platform B-5 Item Qty. Reference Part Package Description 58 1 R25 25.5 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 59 1 R26 15.8 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 60 10 R28, R94, R97, R135, R136, R137, R138, R156, R158, R160 330 805 RC0805, 1/8 W, ±5%, 50 V 61 1 R29 15.0 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 62 4 R30, R65, R139, R140 100 805 RC0805, 1/8 W, ±5%, 50 V 63 15 R33, R47, R57, R119, R120, R121, R122, R123, R127, R148, R163, R165, R167, R169, R176 0 805 RC0805, 1/8 W, ±5%, 50 V 64 9 R39, R44, R45, R75, R90, R92, R106, R171, R172 4.7 K 805 RC0805, 1/8 W, ±5%, 50 V 65 1 R48 51 K 805 RC0805, 1/8 W, ±5%, 50 V 66 1 R59 *1 K 805 RC0805, 1/8 W, ±5%, 50 V 67 5 R62, R63, R149, R150, R151 270 805 RC0805, 1/8 W, ±5%, 50 V 68 2 R70, R146 *2.2 K 805 RC0805, 1/8 W, ±5%, 50 V 69 9 R71, R80, R95, R96, R98, R145, R157, R159, R161 470 805 RC0805, 1/8 W, ±5%, 50 V 70 1 R79 10M 805 RC0805, 1/8 W, ±5%, 50 V 71 1 R93 *4.7 K 805 RC0805, 1/8 W, ±5%, 50 V 72 1 R102 47 805 RC0805, 1/8 W, ±5%, 50 V 73 1 R107 100, 1% 805 RC0805, 1/8 W, ±1%, 50 V 74 2 R108, R109 49.9, 1% 805 RC0805, 1/8 W, ±1%, 50 V Notes: An asterisk (*) indicates parts that are not populated. B-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual Item Qty. Reference Part Package Description 75 4 R110, R111, R112, R113 75, 1% 805 RC0805, 1/8 W, ±1%, 50 V 76 3 R114, R115, R117 1.00 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 77 1 R116 22 K, 1% 805 RC0805, 1/8 W, ±1%, 50 V 78 4 R152, R153, R154, R155 1.5 K 805 RC0805, 1/8 W, ±5%, 50 V 79 4 R162, R164, R166, R168 *0 805 RC0805, 1/8 W, ±5%, 50 V 80 3 SIMM1, SIMM2, SIMM0 SIMM72 AMP 822030-3 81 2 SLT1, SLT2 PCI Slot AMP 145154-4 82 2 SL1, SL2 ISA AT Connector AMP 645169-3 83 3 SW1, SW2, SW3 PBNO C&K KT11P2SM 84 4 TC1, TC4, TC7, TC10 47 µF D-CASE TANTALUM, D-CASE, 16 V, ±20% 85 4 TC5, TC6, TC20, TC21 10 µF D-CASE TANTALUM, D-CASE, 25 V, ±20% 86 1 TC8 100 µF E-CASE TANTALUM, E-CASE, 16 V, ±20% 87 1 T1 PE68515 88 1 U1 74F245 SOL20 SIGNETICS 74F245D 89 1 U5 M1489 PQFP208 ALi M1489 90 1 U6 LP2951 SO8 NATIONAL LP2951CM 91 4 U7, U8, U9, U10 128 Kx8-15 SOJ32(0.3” /0.4”) 128 Kx8, 15 ns, Corner Vcc/GND Pins, SOJ32 92 1 U11 32 Kx8-15 SOJ28(.3”) 32 Kx8, 15 ns, Corner Vcc/GND Pins, 0.3”SOJ28 93 1 U14 Am29F010-90 DIP32(0.6” )(SOCKET ) AMD Am29F010-90PC 94 1 U15 74F04 SO14 SIGNETICS 74F04D PULSE ENGR. PE-68515 Notes: An asterisk (*) indicates parts that are not populated. Am486® Microprocessor PCI Customer Development Platform B-7 Item Qty. Reference Part Package Description 95 1 U17 IMI SC464 SSOP28 INTL. MICROCKTS. INC. IMISC464AYB 96 1 U21 M1487 PQFP160 ALi M1487 97 1 U22 DS1685-5 DIP24(0.65 0”) DALLAS SEMI. DS1685-5 98 2 U24, U82 74F08 SO14 SIGNETICS 74F08D 99 1 U25 Am486 Microprocessor, PGA PGA169 AMD (AMP SOCKET1 916504-2) 100 11 U26, U28, U30, U31, U32, U36, U38, U40, U47, U49, U70 74ABT16244 SSOP48 SIGNETICS 74ABT16244ADL 101 1 U42 74ABT244 SOL20 SIGNETICS 74ABT244D 102 1 U43 M5113A PQFP100 ALi M5113A 103 1 U44 TFDS6000 SMT TEMIC TFDS6000D 104 2 U46, U45 RS232-5V SSOP28 LINEAR TECH LTC1349CG 105 1 U51 Am79C972 (PQR160) PQR160 AMD Am79C972KC 106 1 U52 LXT970QC MQFP64 LEVEL ONE LXT970QC 107 1 U53 MC33269DT-3.3 DPAK MOTOROLA MC33269DT-3.3 108 1 U54 NM93C46N DIP8 NATIONAL NM93C46N 109 1 U55 MACH221 PQFP-100 AMD MACH221SP-7 110 9 U56, U61, U62, U63, U64, U65, U66, U67, U68 29F800-55 TSOP48 TSOP48 AMD AM29F800BT-55EC 111 2 U60, U80 PALCE22V10_PLCC (5ns) PLCC28 AMD PALCE22V10H-5JC 112 1 U69 74ABT373 SOL20 SIGNETICS 74ABT373AD 113 1 U71 74ABT16245 SSOP48 SIGNETICS 74ABT16245BDL 114 4 U72, U73, U74, U75 Hex Display TH TI TIL311 Notes: An asterisk (*) indicates parts that are not populated. B-8 Am486® Microprocessor PCI Customer Development Platform User’s Manual Item Qty. Reference Part Package Description 115 1 U77 74F32 SO14 SIGNETICS 74F032D 116 1 U78 74F06 SO14 SIGNETICS 74F06D 117 1 U79 M5042 PLCC44 ALi M5042 118 1 U81 NM93C66M8 SO8 NATIONAL NM93C66M8 119 1 U83 74F14 SO14 SIGNETICS 74F14D 120 1 U84 74ABT125 SO14 Signetics 74ABT125D 121 1 Y1 24 MHz_SMD ECLIPTEK ECSMA-24.00MTR 122 1 Y2 14.318 MHz_SMD ECLIPTEK ECSMAT-14.318MTR 123 2 Y4, Y6 32.768 KHz_SMD ECLIPTEK ECPSM29T-32.768KTR 124 1 Y5 25 MHz_SMD ECLIPTEK ECSMA-25.000MTR 127 1 XU14 DIP32(0.6”) SOCKET SAMTEC ICA-632-SGG 128 1 XBT1 3.3 V LITHIUM COINCELL TOSHIBA CR2032 129 1 U25-HS FANSINK FOR CPU THERMALLOY 2321BTCM-42S-PF17 130 5 XXX JUMPERS (0.1”) FOR 0.025” SQ. POSTS Notes: An asterisk (*) indicates parts that are not populated. Am486® Microprocessor PCI Customer Development Platform B-9 Schematics The schematics that follow are the actual CAD schematics used to build the PCI CDP. These schematics are useful for understanding and modifying the PCI CDP. Because the development platform is based on a particular chipset and incorporates many different possible design options, actual Am486 microprocessor-based designs might be considerably different. B-10 Am486® Microprocessor PCI Customer Development Platform User’s Manual 1 2 3 4 5 Table of Contents A B Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Am486 Microprocessor PCI Customer Development Platform 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: 13: 14: 15: 16: 17: 18: 19: 20: 21: 22: 23: 24: 25: 26: COVER.SCH CPU.SCH CPU_POWER.SCH CPU_VIS1.SCH CPU_VIS2.SCH M1489.SCH L2_CACHE.SCH SIMM_SKTS.SCH EIP_MEM1.SCH EIP_MEM2.SCH PCI_CONN.SCH PCI_VIS.SCH ENET1.SCH ENET2.SCH IDE.SCH M1487.SCH ROM_MISC.SCH CLOCK.SCH ISA_CONN.SCH SUPER_I/O.SCH SERIAL_PARALLEL.SCH ISA_MEM1.SCH ISA_MEM2.SCH RTC_TIP.SCH KEYBOARD.SCH CPU_PINOUT.SCH A B Am486 Microprocessor Development System With PCI Expansion and On-Board Am79C972 100MB/s Ethernet Controller Rev 2.0 (continued): Rev 1.0: Original design Rev 1.1: Minor modifications after Design Review Rev 1.2: Added External 8042 Style Keyboard Controller (SH24) Removed Support for M1487 Internal KBC (SH15) Removed Keyboard Interface From Clock Page (SH17) Changed design name to Am486PCI C.D.P. C SH17: Added jumpers to allow mulitple BIOS images in a single Flash ROM device Removed 1 diode from VBAT generation circuit Added new NMI generation circuit and spare ’F14 gates Added jumper for external RESET# pushbutton SH18: Fixed wiring error on crystal Removed MCLK1 net (16MHz) and rewired MCLK2 to drive all 33MHz clock nets Removed CLKCNTL signal from DOZE# pin of U17 Rev 1.3: Added Extra Bypass Capacitors (SH5 & SH14 & SH15 & SH17) Swapped Around Some Signals Within Resistor Networks (SH6 & SH20) Renamed MCLK1 net to M_CLK1 (SH24) Added 0-ohm resistor to make pin 10 & 11 pullup work (SH17) Added Pin to HS1 for NetLister (SH3) Fixed Error in 3.3V Regulator Circuit (SH12) SH20: Removed unneeded 0-ohm resistors from Super I/O chip Fixed wiring error on crystal Added ’ABT125 buffer to drive serial port LEDs C SH22: MACH device outputs changed for new ISA Flash support SH23: Changed ISA Flash to 1MByte (512Kx16) Rev 1.4: Rearranged Clock Nets to Facilitate Routing (SH17) Changed Some Components to Standard Values (50ohm to 49.9ohm, 1% on SH 13 and 40pF to 39pF, 5% on SH19) SH24: Removed unneeded logic from RTC interface Added inverter to generate proper CS# for RTC chip Fixed wiring error on crystal Grounded U22-pin 22 Removed 1 unused OR gate for use on SH17 Rev 2.0: Changed SIP resistor packs to 10-pin (SH2, SH3, SH11, SH15, SH16, SH17, SH19, SH20 & SH21) Changed 330ohm SIP Resistor Pack to 8-pin (SH19) SH3: Added diagram to correct Power Connector Footprint SH25: Switched mouse connector to verticle type Changed ’F06 symbol to show o/c SH4 & 5: Broke CPU Logic Analyzer Headers into 2 pages Added PAL to gnerate CPU A0 and A1 and also generate a Logic Analyzer Qualify signal Buffered BE[0..3], RDY#, BRDY#, and ADS# through the new PAL D D SH9: Added better explanation of EIP Flash memory operation SH11: Added configuration information for PCI slots Removed circuit to generate PCI PERR# to cause M1487 to assert NMI to Am486 microprocessor Rev 2.1: Updated revision level and prototype warning on all sheets SH17: Modified ROM jumpers to allow mulitple BIOS images in a single Flash ROM device and support 256K or 512K BIOS for non-PC applications SH22: Added XBUSCSJ signal to Mach device so it does not respond when Am486 fetches the reset vector at FFFF FFF0 SH14 &15 &20: Connected pins 1 and 2 on all LEDs for greater purchasing/manufacturing flexibility SH13: Added a 4K serial EEPROM for user parameters and mux. circuit to daisy chain it off the 1K device. ’972 E/net device loads its configuration from 1K SEEPROM. CLKCNTL signal from M1487 used to select 1K or 4K SEEPROM. SH14: Swapped R107 and R109; R109 is 49.9ohm, 1% Fixed wiring error on crystal SH15: Added 5 more 0.1uF bypass capacitors for new chips (’F14, ’ABT125, 22V10, ’F08, ’C66) SH16: Fixed wiring error on crystal Fixed wiring error in generation of low-active reset signal RSTDRV# Removed unused inverter (used on SH24) Changed net on NMI pin to 1487NMI for use in new circuit Changed R58 to be a populated component (C) Advanced Micro Devices, Inc. (800) 222-9323 E E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Note: Unless otherwise noted all logic operates off a 5V power supply Size Date: Friday, December 04, 1998 Note: Unless otherwise stated the capacitors are a 0805 package and 10% Tol. 2 Rev 2.1 COVER.SCH Note: Unless otherwise stated the resistors are a 0805 package and 5% Tol. 1 Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number 3 4 Sheet 5 1 of 26 1 2 3 4 5 Am486 MICROPROCESSOR, PULLUPS, AND JTAG INTERFACE STPCLKJ PCD_CACH CPURST HITMJ INV A A VCC RP1 1 C K2VCC K2VCC GD31 GD30 GD29 GD28 GD27 GD26 GD25 GD24 GD23 GD22 GD21 GD20 GD19 GD18 GD17 GD16 GD15 GD14 GD13 GD12 GD11 GD10 GD9 GD8 GD7 GD6 GD5 GD4 GD3 GD2 GD1 GD0 C DP0 DP1 DP2 DP3 13 47 83 10 12 44 29 74 INV(DX2INC) HITM#(DX2INC) SRESET CACHE#(DX2INC) STPCLK# M/IO# D/C# W/R# LOCK# PLOCK# ADS# BLAST# BREQ HLDA PWT PCD FERR# A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Enhanced Am486 Microprocessor (SOCKET1-PGA169) DP0 DP1 DP2 DP3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 7 9 11 20 21 22 59 64 71 76 77 82 89 94 95 100 101 106 118 120 139 158 160 161 162 163 164 166 3 14 33 31 DP[0..3] HITMJ PULLHI1 111 104 112 110 134 169 151 133 116 98 88 48 MIOJ DCJ WRJ LOCKJ PLOCK# ADSJ BLAST# BREQ PCHK# SMI# WB/WT#(DX2INC) UP# SMIACT# CLKMUL(DX2INC) PWT PCD FERRJ 70 86 87 92 BEJ3 BEJ2 BEJ1 BEJ0 119 115 114 136 153 154 137 124 155 125 123 126 122 140 121 127 142 157 128 159 147 165 129 148 131 167 130 168 150 132 GA31 GA30 GA29 GA28 GA27 GA26 GA25 GA24 GA23 GA22 GA21 GA20 GA19 GA18 GA17 GA16 GA15 GA14 GA13 GA12 GA11 GA10 GA9 GA8 GA7 GA6 GA5 GA4 GA3 GA2 SKT1_NC 135 27 30 45 46 152 B HDLA BEJ[0..3] GD[0..31] GD[0..31] DP[0..3] 109 65 79 5 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TCK TDI TDO TMS D 25 43 8 42 40 41 23 6 4 2 19 1 18 36 54 85 67 91 53 73 35 61 52 66 97 96 84 103 78 107 108 113 2 3 4 5 6 7 8 9 10 10K-10P BE3# BE2# BE1# BE0# VOLDET(DX2NC) BOFFJ AHOLD EADSJ KENOJ FLUSHJ IGNNEJ BS16J BS8J A20MJ RDYOJ BRDYOJ C40 1000pF B CLK RESET INTR NMI HOLD BOFF# AHOLD EADS# KEN# FLUSH# IGNNE# BS16# BS8# A20M# RDY# BRDY# U25 BEJ[0..3] GA[2..31] GA[2..31] RP8 1 C O2 O3 O4 O5 O6 O7 O8 O9 O10 2 GA31 3 GA30 4 GA29 5 GA28 6 GA27 7 GA26 8 GA25 9 GA24 10 C 4.7K-10P VCC R91 10K PCHKJ SMIJ WB-WT# PULLHI1 SMIACKJ D VCC 55 R11 *10K Am486-PGA 156 INTR INC INC(DX2NC) 37 50 16 32 62 58 17 34 68 49 15 51 57 56 69 80 ZRSTDRV INC(DX4VCC5) CPUCLK NMI VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 24 26 28 38 39 60 63 72 75 81 90 93 99 102 105 117 138 141 143 144 145 146 149 CPUVCC3 O2 O3 O4 O5 O6 O7 O8 O9 O10 Tie CLKMUL pin to GND for AMD DX2-66 and AMD DX5-133; use 10K pullup for AMD DX4-100 CLKMUL VCC R148 0 R13 10K P24T5 P35 TDO TDI TMS TCK E 1 3 5 7 9 JTAG Connector 2 4 6 8 10 1 2 (C) Advanced Micro Devices, Inc. E HEADER2X5; SHRD Title JTAG Connector 9 10 Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Date: Friday, December 04, 1998 2 3 Rev 2.1 CPU.SCH Top View 1 (800) 222-9323 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 4 Sheet 5 2 of 26 1 2 3 4 5 POWER CONNECTOR, CPU PULLUPS, CPU POWER SUPPLY, CPU BYPASS CAPACITORS VCC CPUVCC3 HS1 C162 C163 C164 C165 C166 C167 C168 C169 0.015uF 0.015uF 0.015uF 0.015uF 0.1uF 0.1uF 0.1uF 0.1uF R30 K2VCC VCC 1 1 + HEATSINK (TO-220) THERMALLOY C39 0.1uF 10uF A ML32 VCC VCC Q5 TIP127 3 JP2 E C 2 HEADER 3X1 JP3 1 DP[0..3] RP2 10 9 8 7 6 5 4 3 2 DP1 DP2 DP3 DP0 B MIOJ RDYOJ BRDYOJ BOFFJ U6 U6O/P VCC 1 2 3 4 C37 O/P SEN SD GND VIN FB TAP ERR 8 7 6 5 R23 27.4K, 1% 1/8W 0.1uF R26 15.8K, 1% 1/8W R25 25.5K, 1% 1/8W 1% 1% 10K-10P 1% + JP4 1 3 5 R27 33 VCC B HEADER 3X1 COLLECTOR U6VIN U6FB LP2951 1 1 2 3 CPUVCC3 BASE O10 O9 O8 O7 O6 O5 O4 O3 O2 C 1-2: 5V CPU 2-3: OTHERS 1 2 3 CPUVCC3 B R28 330 DP[0..3] K2VCC TC9 100 A TC8 100uF CPUV1 CPUV2 CPUV3 2 4 6 HEADER 3X2 R3 10K C R5 10K R4 10K R29 15.0K, 1% 1/8W 1% R61 10K 1-2: 3-4: 5-6: 3.45V 3.3V 2.5V V(out)= 1.235(1+ R/15.0K) FLUSHJ BS16J BS8J IGNNEJ C + TC4 47uF + TC7 47uF TC1 47uF + TC10 47uF + PWG -12V +12V VCC -5V J2 1 2 3 4 5 6 -5V -12V C5 0.1uF +12V CPUVCC3 TC6 + 10uF MT1 + + 1 2 3 4 5 6 TC19 10uF + TC5 10uF PWR-CN6 J3 TC20 + 10uF TC21 10uF 1 MT8 1 C6 C4 C36 C3 C8 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF D MountingHole MountingHole MT2 MT7 MountingHole MountingHole 1 TC18 10uF PWR-CN6 1 TC3 10uF + + D C7 0.1uF MT3 C11 0.01uF C34 0.01uF C9 0.01uF C12 0.01uF C10 0.01uF C13 0.01uF MT6 MT9 1 C35 0.01uF 1 1 MountingHole MountingHole MountingHole MT4 J3 J2 1 MountingHole E 6 5 4 3 2 1 6 5 4 3 2 1 MT5 1 MountingHole MT10 1 (C) Advanced Micro Devices, Inc. MountingHole (800) 222-9323 E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Overlap To Make An Oval Title Power Connector(s) = Connector Polarizing Key Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 CPU_POWER.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 3 of 26 1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR CPU SIGNALS A A VCC U26 1 48 25 24 GD31 GD30 GD29 GD28 GD27 GD26 GD25 GD24 GD23 GD22 GD21 GD20 GD19 GD18 GD17 GD16 B 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 21 4 10 15 1OE# 2OE# 3OE# 4OE# VCC VCC VCC VCC 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND P36 7 18 31 42 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VGD31 VGD30 VGD29 VGD28 VGD27 VGD26 VGD25 VGD24 VGD23 VGD22 VGD21 VGD20 VGD19 VGD18 VGD17 VGD16 28 34 39 45 VGD30 VGD28 VGD26 VGD24 VGD22 VGD20 VGD18 VGD16 1 3 5 7 9 11 13 15 17 19 GD15 GD14 GD13 GD12 GD11 GD10 GD9 GD8 GD7 GD6 GD5 GD4 GD3 GD2 GD1 GD0 C GD[0..31] GD[0..31] 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 21 4 10 15 1OE# 2OE# 3OE# 4OE# P38 VGD14 VGD12 VGD10 VGD8 VGD6 VGD4 VGD2 VGD0 1 3 5 7 9 11 13 15 17 19 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 2 4 6 8 10 12 14 16 18 20 VGD15 VGD13 VGD11 VGD9 VGD7 VGD5 VGD3 VGD1 POD 3 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND B VGD[0..31] 7 18 31 42 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VGD31 VGD29 VGD27 VGD25 VGD23 VGD21 VGD19 VGD17 HP CONN 3M:2520-6003UB VCC VCC VCC VCC VCC CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND 2 4 6 8 10 12 14 16 18 20 HP CONN 3M:2520-6003UB 74ABT16244 U28 1 48 25 24 +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 POD 4 VGD15 VGD14 VGD13 VGD12 VGD11 VGD10 VGD9 VGD8 VGD7 VGD6 VGD5 VGD4 VGD3 VGD2 VGD1 VGD0 VCC U47 1 48 25 24 PCHKJ SMIJ WB-WT# SMIACKJ FERRJ 28 34 39 45 AHOLD NMI IGNNEJ 74ABT16244 STPCLKJ PCD_CACH CPURST HITMJ INV PLOCK# 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 21 4 10 15 D 1OE# 2OE# 3OE# 4OE# SIGNALS NOT NEEDED BY HP DISASSEMBLER VCC VCC VCC VCC 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND 7 18 31 42 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 P47 1 3 5 7 9 11 13 15 17 19 VPCHKJ VSMIJ VWB-WT# VSMIACKJ VFERRJ VAHOLD VNMI VIGNNEJ VSTPCLKJ VCACHE# VSRESET VHITMJ VINV VPLOCK# +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 POD 7 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND C 2 4 6 8 10 12 14 16 18 20 HP CONN 3M:2520-6003UB 28 34 39 45 D 74ABT16244 HP Conn. 1 Using Logic Analyzer Headers: 2 Clock the analyzer off the clock signal on P41 (POD1) Qualify the clock using the LA_QUAL signal on P39 (POD2) This qualification signal is asserted (1) when ADS#, RDY# or BRDY# is asserted on the Am486 Microprocessor bus. Thus cycles where valid address or data information is not transferred can be filtered out when needed Signals are arranged on the LA Headers to work with the HP Disassembler for the 16500 analyzer (C) Advanced Micro Devices, Inc. (800) 222-9323 E E 19 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 20 Top View Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 CPU_VIS1.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 4 of 26 1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR CPU SIGNALS, AND PAL TO AID LOGIC ANALYZER USE VCC U49 1 48 25 24 A BEJ[0..3] BEJ[0..3] 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 PWT A20MJ BREQ U80 BEJ0 BEJ1 BEJ2 BEJ3 ADSJ BRDYOJ RDYOJ 3 4 5 6 7 9 10 11 12 13 16 2 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 ZRSTDRV I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 27 26 25 24 23 21 20 19 18 17 VBRDYOJ VADSJ VRDYOJ LA_QUAL VGA0 VGA1 VBEJ0 VBEJ1 VBEJ2 VBEJ3 VCC INTR FLUSHJ R94 330 CPUCLK3 PLACE THEVENIN TERMINATOR NEAR ’ABT16244 BUFFER CLK/I0 PALCE22V10_PLCC (5ns) 5nsec LACNTL.JED B 21 4 10 15 R95 470 1OE# 2OE# 3OE# 4OE# VCC VCC VCC VCC 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND P39 7 18 31 42 LA_QUAL VRDYOJ VPWT VA20MJ VBREQ VZRSTDRV 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1 3 5 7 9 11 13 15 17 19 POD 2 +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND 2 4 6 8 10 12 14 16 18 20 A VBRDYOJ VADSJ VHOLD VFLUSHJ VINTR HP CONN 3M:2520-6003UB VCPUCLK1 VCPUCLK 28 34 39 45 VCPUCLK1 VCC 74ABT16244 R156 330 B PLACE THEVENIN TERMINATOR NEAR HP LOGIC ANALYZER CONNECTOR R157 470 VCC U31 1 48 25 24 VCC U30 1 48 25 24 GA31 GA30 GA29 GA28 GA27 GA26 GA25 GA24 GA23 GA22 GA21 GA20 GA19 GA18 GA17 GA16 C 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 21 4 10 15 1OE# 2OE# 3OE# 4OE# VCC VCC VCC VCC 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND 7 18 31 42 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 LOCKJ KENOJ BS16J 28 34 39 45 VCC U32 1 48 25 24 GA15 GA14 GA13 GA12 GA11 GA10 GA9 GA8 GA7 GA6 GA5 GA4 GA3 GA2 E GA[2..31] GA[2..31] 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 21 4 10 15 1OE# 2OE# 3OE# 4OE# VCC VCC VCC VCC 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND BLAST# HDLA VGA31 VGA30 VGA29 VGA28 VGA27 VGA26 VGA25 VGA24 VGA23 VGA22 VGA21 VGA20 VGA19 VGA18 VGA17 VGA16 74ABT16244 D MIOJ WRJ BS8J PCD BOFFJ DCJ EADSJ P40 VGA30 VGA28 VGA26 VGA24 VGA22 VGA20 VGA18 VGA16 1 3 5 7 9 11 13 15 17 19 7 18 31 42 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 21 4 10 15 POD 6 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2 4 6 8 10 12 14 16 18 20 1OE# 2OE# 3OE# 4OE# VCC VCC VCC VCC 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND 7 18 31 42 P41 VCPUCLK 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 VMIOJ VWRJ VBEJ2 VBEJ0 VLOCKJ VKENOJ VBS16J VBLAST# 1 3 5 7 9 11 13 15 17 19 +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 POD 1 2 4 6 8 10 12 14 16 18 20 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND C HP CONN 3M:2520-6003UB VHLDA VBS8J VPCD VBOFFJ VBEJ1 VBEJ3 VDCJ VEADSJ 28 34 39 45 74ABT16244 VGA31 VGA29 VGA27 VGA25 VGA23 VGA21 VGA19 VGA17 HP Conn. 1 2 D HP CONN 3M:2520-6003UB VGA15 VGA14 VGA13 VGA12 VGA11 VGA10 VGA9 VGA8 VGA7 VGA6 VGA5 VGA4 VGA3 VGA2 P42 VGA14 VGA12 VGA10 VGA8 VGA6 VGA4 VGA2 VGA0 1 3 5 7 9 11 13 15 17 19 +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 POD 5 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND 2 4 6 8 10 12 14 16 18 20 VGA15 VGA13 VGA11 VGA9 VGA7 VGA5 VGA3 VGA1 19 HP CONN 3M:2520-6003UB 20 Top View VGA[2..31] 28 34 39 45 (C) Advanced Micro Devices, Inc. VGA[2..31] (800) 222-9323 E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 74ABT16244 VADSJ VRDYOJ VBRDYOJ VWRJ VADSJ VRDYOJ VBRDYOJ VWRJ Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 CPU_VIS2.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 5 of 26 1 2 3 4 5 FINALi M1489 INTERFACE PARITY HDCSJ3 HDCSJ2 HDCSJ1 HDCSJ0 HDIO16J HDIORDY HDA2 HDA1 HDA0 HDIORJ HDIOWJ A HDD[0..15] R162 *0 R166 *0 R164 *0 R168 *0 PD0 PD1 PD2 PD3 R163 R167 0 R165 0 R169 MDP0 MDP1 MDP2 MDP3 0 0 FOR IDE MASTER: DO NOT POPULATE A VCC HDD0 HDD1 HDD2 HDD3 HDD4 HDD5 HDD6 HDD7 HDD8 HDD9 HDD10 HDD11 HDD12 HDD13 HDD14 HDD15 HDD[0..15] DEVSELJ PAR STOPJ IRDYJ TRDYJ C_BEJ0 C_BEJ1 C_BEJ2 C_BEJ3 FRAMEJ HDRQ1 HDACK1 HDRQ0 HDACK0 HDRQ1 HDACK1 HDRQ0 HDACK0 GA[2..31] + C38 0.1uF HDD0 HDD1 HDD2 HDD3 HDD4 HDD5 HDD6 HDD7 HDD8 HDD9 HDD10 HDD11 HDD12 HDD13 HDD14 HDD15 HDIOWJ HDIORJ HDA0 HDA1 HDA2 HDIORDY HDIO16J HDCSJ0 HDCSJ1 HDCSJ2 HDCSJ3 DEVSELJ PAR STOPJ IRDYJ TRDYJ C/BEJ0 C/BEJ1 C/BEJ2 C/BEJ3 FRAMEJ VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND 87 89 92 94 96 98 100 101 99 97 95 93 91 88 86 85 84 83 77 80 79 82 81 74 73 76 75 139 114 113 140 112 123 137 141 147 111 22 52 78 130 144 182 34 53 72 90 104 128 156 168 208 TC11 10uF GA[2..31] 157 158 173 172 171 170 167 165 163 162 164 169 166 161 160 159 174 175 176 177 178 179 180 183 184 181 47 46 48 45 186 187 188 189 39 40 185 190 191 42 41 44 43 131 127 129 192 155 152 154 153 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GA17 GA18 GA19 GA20 GA21 GA22 GA23 GA24 GA25 GA26 GA31 B BEJ0 BEJ1 BEJ2 BEJ3 ADSJ MIOJ DCJ WRJ RDYOJ BRDYOJ LOCKJ PCD_CACH HITMJ AHOLD BOFFJ KENOJ EADSJ RSTDRV PCICLK CPUCLK1 SMIACKJ IBCSTJ CMPSTJ CMPGNTJ CLEAROKJ C D GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GA17 GA18 GA19 GA20 GA21 GA22 GA23 GA24 GA25 GA26 GA31 BEJ0 BEJ1 BEJ2 BEJ3 ADSJ MIOJ DCJ WRJ RDYOJ BRDYJ LOCKJ PCD HITMJ AHOLD BOFFJ KENOJ EADSJ RSTDRV PCICLK CPUCLK1 SMIACKJ IBCSTJ CMPSTJ CMPGNTJ CLEAROKJ C171 0.1uF C172 0.1uF U5 PAD[0..31] PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 COEJ0 COEJ1 CWEJ0 CWEJ1 CCSJ0 CCSJ1 CCSJ2 CCSJ3 TAG0 TAG1 TAG2 TAG3 TAG4 TAG5 TAG6 TAG7 PERRJ TAGWEJ CA2 CA3 122 132 120 133 119 125 121 124 126 118 134 117 135 116 136 115 110 142 109 143 108 145 107 146 106 148 105 149 103 150 102 151 201 194 200 196 193 195 198 202 203 204 205 3 2 1 207 206 138 4 197 199 PAD[0..31] PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 B C COEJ0 CWEJ0 PD0 PD1 PD2 PD3 TAG0 TAG1 TAG2 TAG3 TAG4 TAG5 TAG6 TAG7 TAG[0..7] TAG[0..7] PERRJ TAGWEJ A3II A3I D GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 GD16 GD17 GD18 GD19 GD20 GD21 GD22 GD23 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 5 6 7 8 9 10 12 11 13 14 15 16 17 18 20 19 21 23 24 25 26 27 29 28 30 31 32 33 35 36 37 38 58 57 56 55 54 51 50 49 62 61 60 59 66 65 64 63 71 70 69 68 67 GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 GD16 GD17 GD18 GD19 GD20 GD21 GD22 GD23 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 CASJ0 CASJ1 CASJ2 CASJ3 RASJ0 RASJ1 RASJ2 RASJ3 WEJ R85 1K GD[0..31] M1489 WEJ RASJ3 RASJ2 RASJ1 RASJ0 CASJ3 CASJ2 CASJ1 CASJ0 GD[0..31] (C) Advanced Micro Devices, Inc. E MA[0..11] (800) 222-9323 E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved MA[0..11] Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 M1489.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 6 of 26 1 2 3 4 5 L2 CACHE TAG AND DATA SRAMS AND BYTE CONTROL; DRAM SERIES TERMINATION AND WE* FANOUT GD[0..31] GA[4..18] A3II A A3I GD[0..31] GA[4..18] A3II A3I A VCC VCC U10 VCC GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GA17 GA18 VCC 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC VCC 13 14 15 17 18 19 20 21 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 30 22 29 24 CE2 CE1# WE# OE# GA17 GA18 VCC B GND 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC 16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 CE2 CE1# WE# OE# 13 14 15 17 18 19 20 21 VCC U8 U7 32 VCC 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 1 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 30 22 29 24 GA17 GA18 VCC GND 128Kx8-15 COEJ0 CWEJ0 VCC U9 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 CE2 CE1# WE# OE# 13 14 15 17 18 19 20 21 VCC 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 1 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GD16 GD17 GD18 GD19 GD20 GD21 GD22 GD23 30 22 29 24 GA17 GA18 VCC 16 GND 128Kx8-15 32 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 CE2 CE1# WE# OE# 16 GND 128Kx8-15 32 13 14 15 17 18 19 20 21 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 30 22 29 24 B 16 128Kx8-15 COEJ0 CWEJ0 CSJ0 CSJ1 CSJ2 CSJ3 MA[0..11] C GA[2..19] AMA[0..11] MA[0..11] AMA[0..11] TAG[0..7] TAG[0..7] RN4 GA[2..19] VCC U11 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GA17 GA18 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 27 20 22 TAGWEJ VCC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 RN2 28 11 12 13 15 16 17 18 19 2 4 6 8 RASJ0 RASJ1 RASJ2 RASJ3 TAG0 TAG1 TAG2 TAG3 TAG4 TAG5 TAG6 TAG7 1 3 5 7 MRASJ0 MRASJ1 MRASJ2 MRASJ3 1 3 5 7 MCASJ0 MCASJ1 MCASJ2 MCASJ3 MA0 MA2 MA4 MA6 2 4 6 8 MA1 MA3 MA5 MA7 2 4 6 8 MA8 MA9 MA10 MA11 2 4 6 8 1 3 5 7 AMA0 AMA2 AMA4 AMA6 1 3 5 7 AMA1 AMA3 AMA5 AMA7 C 33-8B RN3 33-8B RN9 2 4 6 8 CASJ0 CASJ1 CASJ2 CASJ3 33-8B RN1 33-8B 1 3 5 7 AMA8 AMA9 AMA10 AMA11 33-8B WE# CE# OE# GND 14 32Kx8-15 D D U1 VCC U1PD U24A WRJ 1 BEJ3 2 3 R19 10K CSJ3 74F08 U24B WEJ 4 6 BEJ2 5 2 3 4 5 6 7 8 9 19 1 CSJ2 R96 470 74F08 U24C VCC A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 ZMWEJ2 ZMWEJ1 ZMWEJ0 R124 R8 R7 33 33 33 MWEJ2 MWEJ1 MWEJ0 G DIR 74F245 9 BEJ1 8 CSJ1 11 CSJ0 10 74F08 U24D 12 E (C) Advanced Micro Devices, Inc. 13 BEJ0 (800) 222-9323 E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 74F08 Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 L2_CACHE.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 7 of 26 1 2 3 4 5 DRAM 72-PIN SIMM SOCKETS VCC 66 48 46 11 70 69 68 67 MRASJ1 B A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IO34 IO33 IO32 IO31 IO30 IO29 IO28 IO27 IO25 IO24 IO23 IO22 IO21 IO20 IO19 IO18 IO16 IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 NC4 NC3 NC2 NC1 PRD3 PRD2 PRD1 PRD0 MRASJ0 MCASJ3 MCASJ2 MCASJ1 MCASJ0 42 41 43 40 47 MWEJ0 CAS3 CAS2 CAS1 CAS0 WE SIMM72 GND GND GND MCASJ[0..3] RAS3 RAS2 RAS1 RAS0 IO35 IO26 IO17 IO8 38 35 37 36 GD31 GD30 GD29 GD28 GD27 GD26 GD25 GD24 GD23 GD22 GD21 GD20 GD19 GD18 GD17 GD16 GD15 GD14 GD13 GD12 GD11 GD10 GD9 GD8 GD7 GD6 GD5 GD4 GD3 GD2 GD1 GD0 AMA11 AMA10 AMA9 AMA8 AMA7 AMA6 AMA5 AMA4 AMA3 AMA2 AMA1 AMA0 71 29 19 32 31 28 18 17 16 15 14 13 12 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 66 48 46 11 70 69 68 67 MRASJ0 PRD3 PRD2 PRD1 PRD0 MRASJ2 MCASJ[0..3] 33 34 45 44 MCASJ[0..3] MCASJ3 MCASJ2 MCASJ1 MCASJ0 MDP3 MDP2 MDP1 MDP0 MWEJ2 MDP[0..3] GD[0..31] IO34 IO33 IO32 IO31 IO30 IO29 IO28 IO27 IO25 IO24 IO23 IO22 IO21 IO20 IO19 IO18 IO16 IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 NC4 NC3 NC2 NC1 RAS3 RAS2 RAS1 RAS0 42 41 43 40 CAS3 CAS2 CAS1 CAS0 47 WE MDP[0..3] SIMM72 1 39 72 33 34 45 44 64 62 60 58 56 54 52 50 27 25 23 21 9 7 5 3 65 63 61 57 55 53 51 49 26 24 22 20 8 6 4 2 GND GND GND 71 29 19 32 31 28 18 17 16 15 14 13 12 AMA[0..11] GD[0..31] IO35 IO26 IO17 IO8 64 62 60 58 56 54 52 50 27 25 23 21 9 7 5 3 65 63 61 57 55 53 51 49 26 24 22 20 8 6 4 2 38 35 37 36 GD[0..31] GD31 GD30 GD29 GD28 GD27 GD26 GD25 GD24 GD23 GD22 GD21 GD20 GD19 GD18 GD17 GD16 GD15 GD14 GD13 GD12 GD11 GD10 GD9 GD8 GD7 GD6 GD5 GD4 GD3 GD2 GD1 GD0 A B MDP3 MDP2 MDP1 MDP0 MDP[0..3] MDP[0..3] 1 39 72 AMA11 AMA10 AMA9 AMA8 AMA7 AMA6 AMA5 AMA4 AMA3 AMA2 AMA1 AMA0 GD[0..31] VCC VCC VCC A MCASJ[0..3] AMA[0..11] AMA[0..11] VCC VCC VCC 10 30 59 SIMM2 SIMM0 AMA[0..11] 10 30 59 VCC C C AMA[0..11] AMA11 AMA10 AMA9 AMA8 AMA7 AMA6 AMA5 AMA4 AMA3 AMA2 AMA1 AMA0 71 29 19 32 31 28 18 17 16 15 14 13 12 D 66 48 46 11 70 69 68 67 MRASJ2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IO34 IO33 IO32 IO31 IO30 IO29 IO28 IO27 IO25 IO24 IO23 IO22 IO21 IO20 IO19 IO18 IO16 IO15 IO14 IO13 IO12 IO11 IO10 IO9 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 NC4 NC3 NC2 NC1 PRD3 PRD2 PRD1 PRD0 MRASJ1 MCASJ3 MCASJ2 MCASJ1 MCASJ0 MWEJ1 E 42 41 43 40 47 RAS3 RAS2 RAS1 RAS0 CAS3 CAS2 CAS1 CAS0 WE SIMM72 GND GND GND 33 34 45 44 MCASJ[0..3] IO35 IO26 IO17 IO8 64 62 60 58 56 54 52 50 27 25 23 21 9 7 5 3 65 63 61 57 55 53 51 49 26 24 22 20 8 6 4 2 38 35 37 36 SIMM SOCKET POPULATION CHART GD[0..31] GD31 GD30 GD29 GD28 GD27 GD26 GD25 GD24 GD23 GD22 GD21 GD20 GD19 GD18 GD17 GD16 GD15 GD14 GD13 GD12 GD11 GD10 GD9 GD8 GD7 GD6 GD5 GD4 GD3 GD2 GD1 GD0 SIMM0 SIMM1 SINGLE BANK SINGLE BANK DOUBLE BANK SINGLE BANK SIMM2 SINGLE BANK D SIMMS CAN BE SINGLE BANK OR DOUBLE BANK, USING 1Mbit, 4Mbit, or 16Mbit DRAM CHIPS. POPULATE SIMM SOCKETS AS SHOWN IN THIS CHART. MDP3 MDP2 MDP1 MDP0 (C) Advanced Micro Devices, Inc. MDP[0..3] (800) 222-9323 E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved MDP[0..3] 1 39 72 MCASJ[0..3] GD[0..31] VCC VCC VCC SIMM1 AMA[0..11] 10 30 59 VCC Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 SIMM_SKTS.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 8 of 26 1 2 3 4 5 EIP FLASH MEMORY CONTROLLER VA(2:21) A A Am486 MICROPROCESSOR A(2:22) A(22)=0 U60 Bank1 Cntl. VA(22) VCC R158 330 RSTDRV VGA22 AMA8 VWRJ MRASJ3 MCASJ3 MCASJ2 MCASJ1 MCASJ0 VCPUCLK1 3 4 5 6 7 9 10 11 12 13 16 2 R159 470 B I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 ’ABT244 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 27 26 25 24 23 21 20 19 18 17 REFCIP WRCIP Bank2 Cntl. EIPCE1# EIPCE2# EIPOE1# EIPOE2# 4 ea. 1Mx8 Flash ROM Chips A(22)=1 PAL 4 ea. 1Mx8 Flash ROM Chips CPU Address Bit A(22) Used As Flash Bank Select EIPWE1# EIPWE2# CLK/I0 PALCE22V10_PLCC (5ns) EIPCNTL.JED REV. 0.9 B PLACE THEVENIN TERMINATOR NEAR 22V10 PAL Makes 2 banks of 1Mx32 Flash ROM appear as 1 bank of 2Mx32 DRAM (70ns, FPM) to M1489 Memory Controller. Program M1489 for 2Mx8 (11/10) DRAM chips. MA8 (CPU A22) used as Flash ROM Bank Select when RAS3# asserted by M1489 Memory Controller. Limitations and Operation of the EIP Interface: Access as 32-bits wide always Supports burst Read Cycles or single-beat Read Cycles Supports single-beat Write Cycles only; no back-to-back Write Cycles Compatible with CAS-before-RAS Refresh Cycles only C C Set M1489 Memory Controller to "Fast" for proper operation, even if installed DRAM is 60ns and can run at the "Fastest" setting Flash chip A0 pin tied to Am486 Microprocessor A2 pin, so multiply desired Flash chip address by 4h to find Am486 Microprocessor address needed to access the desired memory cell (ex: Flash Chip AAAh accessed by Am486 Microprocessor at 2AA8h) EIP Flash Array start address moves, depending on how much DRAM is installed (ex: 48MByte DRAM puts EIP start address at 48MB or 3000000h for first bank of Flash ROMs and 3400000h start address for second bank of Flash ROMs Uses 29F800T, 55ns devices in "Byte" mode Accessable from Am486 Microprocessor only; not accessable from PCI Bus Masters Uses fourth DRAM bank of M1489 Memory Controller D D (C) Advanced Micro Devices, Inc. (800) 222-9323 E E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 EIP_MEM1.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 9 of 26 1 2 3 4 5 EIP FLASH MEMORY ARRAY GD[0..31] VGA[2..31] A A U61 VGA3 VGA4 VGA5 VGA6 VGA7 VGA8 VGA9 VGA10 VGA11 VGA12 VGA13 VGA14 VGA15 VGA16 VGA17 VGA18 VGA19 VGA20 VGA21 B 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 U62 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY# 29 31 33 35 38 40 42 44 GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 30 32 34 36 39 41 43 45 VGA3 VGA4 VGA5 VGA6 VGA7 VGA8 VGA9 VGA10 VGA11 VGA12 VGA13 VGA14 VGA15 VGA16 VGA17 VGA18 VGA19 VGA20 VGA21 VGA2 15 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 U63 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY# 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 VGA2 15 VCC RSTDRV# RSTDRV# 47 12 26 28 11 EIPCE1# EIPOE1# EIPWE1# BYTE# RESET# VCC CE# OE# WE# GND GND 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY# 29 31 33 35 38 40 42 44 GD16 GD17 GD18 GD19 GD20 GD21 GD22 GD23 30 32 34 36 39 41 43 45 C122 C123 0.1uF EIPCE1# 0.1uF EIPOE1# EIPWE1# 47 12 26 28 11 BYTE# RESET# VGA2 VCC CE# OE# WE# GND GND C124 C125 0.1uF EIPCE1# 0.1uF EIPOE1# EIPWE1# 46 27 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY# GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 VGA2 15 B VCC RSTDRV# 37 VGA3 VGA4 VGA5 VGA6 VGA7 VGA8 VGA9 VGA10 VGA11 VGA12 VGA13 VGA14 VGA15 VGA16 VGA17 VGA18 VGA19 VGA20 VGA21 15 VCC RSTDRV# 37 46 27 VGA3 VGA4 VGA5 VGA6 VGA7 VGA8 VGA9 VGA10 VGA11 VGA12 VGA13 VGA14 VGA15 VGA16 VGA17 VGA18 VGA19 VGA20 VGA21 U64 47 12 26 28 11 BYTE# RESET# VCC CE# OE# WE# GND GND VCC RSTDRV# 37 C126 C127 0.1uF EIPCE1# 0.1uF EIPOE1# EIPWE1# 46 27 47 12 26 28 11 BYTE# RESET# VCC CE# OE# WE# GND GND 29F800-55 TSOP48 29F800-55 TSOP48 29F800-55 TSOP48 29F800-55 TSOP48 U65 U66 U67 U68 37 C128 C129 0.1uF 0.1uF 46 27 GD[0..31] C C VGA[2..31] VGA3 VGA4 VGA5 VGA6 VGA7 VGA8 VGA9 VGA10 VGA11 VGA12 VGA13 VGA14 VGA15 VGA16 VGA17 VGA18 VGA19 VGA20 VGA21 D 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY# 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 VGA3 VGA4 VGA5 VGA6 VGA7 VGA8 VGA9 VGA10 VGA11 VGA12 VGA13 VGA14 VGA15 VGA16 VGA17 VGA18 VGA19 VGA20 VGA21 VGA2 15 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY# 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 VGA2 15 VCC RSTDRV# 47 12 26 28 11 EIPCE2# EIPOE2# EIPWE2# BYTE# RESET# CE# OE# WE# VCC GND GND 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY# 29 31 33 35 38 40 42 44 GD16 GD17 GD18 GD19 GD20 GD21 GD22 GD23 30 32 34 36 39 41 43 45 RSTDRV# C130 C131 0.1uF EIPCE2# 0.1uF EIPOE2# EIPWE2# 29F800-55 TSOP48 47 12 26 28 11 BYTE# RESET# CE# OE# WE# VCC VGA2 GND GND C132 C133 0.1uF EIPCE2# 0.1uF EIPOE2# EIPWE2# 46 27 29F800-55 TSOP48 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 VGA2 D RY/BY# 15 VCC RSTDRV# 37 VGA3 VGA4 VGA5 VGA6 VGA7 VGA8 VGA9 VGA10 VGA11 VGA12 VGA13 VGA14 VGA15 VGA16 VGA17 VGA18 VGA19 VGA20 VGA21 15 VCC 37 46 27 VGA3 VGA4 VGA5 VGA6 VGA7 VGA8 VGA9 VGA10 VGA11 VGA12 VGA13 VGA14 VGA15 VGA16 VGA17 VGA18 VGA19 VGA20 VGA21 47 12 26 28 11 BYTE# RESET# CE# OE# WE# VCC GND GND VCC RSTDRV# 37 46 27 C134 C135 0.1uF EIPCE2# 0.1uF EIPOE2# EIPWE2# 29F800-55 TSOP48 47 12 26 28 11 BYTE# RESET# VCC CE# OE# WE# GND GND 37 C136 C137 0.1uF 0.1uF 46 27 29F800-55 TSOP48 (C) Advanced Micro Devices, Inc. (800) 222-9323 E E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 EIP_MEM2.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 10 of 26 1 2 3 4 5 PCI PULLUPS AND SLOT CONNECTORS; PCI IDSEL GENERATION VCC VCC VCC RP10 A 2 3 4 5 6 7 8 9 10 FRAMEJ TRDYJ DEVSELJ STOPJ PLOCKJ PAR SERRJ C_BEJ0 C42 15pF O2 C O3 O4 O5 O6 O7 O8 O9 O10 RP11 1 INT0J INT2J INT1J INT3J PREQJ1 PGNTJ2 PREQJ2 2 3 4 5 6 7 8 9 10 4.7K-10P RP9 O2 C O3 O4 O5 O6 O7 O8 O9 O10 1 PGNTJ0 PGNTJ1 PREQJ0 C_BEJ1 C_BEJ2 IRDYJ C_BEJ3 4.7K-10P 2 3 4 5 6 7 8 9 10 1 O2 C O3 O4 O5 O6 O7 O8 O9 O10 RN8 7 5 3 1 PCIID1 PCIID3 PCIID2 A 8 6 4 2 PAD19 PAD21 PAD20 PCIBus INT 33-8B 4.7K-10P VCC Slot1 Slot2 INT0# INTA# INTD# INT1# INTB# INTA# INT2# INTC# INTB# INT3# INTC# INTC# Ethernet INTA# VCC B B -12V 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 INT1J INT3J PCICLK1 PREQJ0 C PAD31 PAD29 PAD27 PAD25 C_BEJ3 PAD23 PAD21 PAD19 PAD17 C_BEJ2 IRDYJ DEVSELJ PLOCKJ PERRJ SERRJ D SLT1 C_BEJ1 PAD14 PAD12 PAD10 110 111 112 113 114 115 116 117 118 119 120 PAD8 PAD7 PAD5 PAD3 PAD1 +12V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSRVD PRSNT2# GND GND RSRVD GND CLK GND REQ# +5V(I/O) AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND TRST# +12V TMS TDI +5V INTA# INTC# +5V RSRVD +5V(I/O) RSRVD GND GND RSRVD RST# +5V(I/O) GNT# GND RSVRD AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V(I/O) ACK64# +5V +5V C/BE0# +3.3V AD6 AD4 GND AD2 AD0 +5V(I/O) REQ64# +5V +5V -12V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 INT0J INT2J 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 INT2J INT0J PCIRSTJ PCICLK2 PGNTJ0 PREQJ1 PAD30 PAD28 PAD26 PAD24 PCIID1 PAD22 PAD20 PAD18 PAD16 FRAMEJ PAD31 PAD29 PAD27 PAD25 C_BEJ3 PAD23 PAD21 PAD19 PAD17 C_BEJ2 IRDYJ TRDYJ DEVSELJ STOPJ PLOCKJ PERRJ SERRJ PAR PAD15 PAD13 PAD11 C_BEJ1 PAD14 PAD12 PAD10 PAD9 50 51 52 53 54 55 56 57 58 59 60 C_BEJ0 PAD6 PAD4 PAD2 PAD0 SLT2 110 111 112 113 114 115 116 117 118 119 120 PAD8 PAD7 PAD5 PAD3 PAD1 +12V -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSRVD PRSNT2# GND GND RSRVD GND CLK GND REQ# +5V(I/O) AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND TRST# +12V TMS TDI +5V INTA# INTC# +5V RSRVD +5V(I/O) RSRVD GND GND RSRVD RST# +5V(I/O) GNT# GND RSVRD AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD15 +3.3V AD13 AD11 GND AD9 AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V(I/O) ACK64# +5V +5V C/BE0# +3.3V AD6 AD4 GND AD2 AD0 +5V(I/O) REQ64# +5V +5V PCI Slot PCI Slot IDSEL = AD19 Device #3 IDSEL = AD20 Device #4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 INT1J INT3J PCIRSTJ PGNTJ1 PAD30 C PAD28 PAD26 PAD24 PCIID2 PAD22 PAD20 PAD18 PAD16 FRAMEJ TRDYJ STOPJ PAR PAD15 D PAD13 PAD11 PAD9 50 51 52 53 54 55 56 57 58 59 60 C_BEJ0 PAD6 PAD4 PAD2 PAD0 (C) Advanced Micro Devices, Inc. (800) 222-9323 E E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 PCI_CONN.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 11 of 26 1 2 3 4 5 BUFFERS AND LOGIC ANALYZER HEADERS FOR PCI BUS VCC U36 1 48 25 24 PAD[0..31] JP29 1 2 3 PREQJ0 PGNTJ0 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 A 21 4 10 15 HEADER 3X1 PLACE NEAR PCI0 CONNECTOR 1OE# 2OE# 3OE# 4OE# VPAD[0..31] 7 18 31 42 VCC VCC VCC VCC 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND VPAD0 VPAD1 VPAD2 VPAD3 VPAD4 VPAD5 VPAD6 VPAD7 VPAD8 VPAD9 VPAD10 VPAD11 VPAD12 VPAD13 VPAD14 VPAD15 VCC PLACE THEVENIN TERMINATOR NEAR HP LOGIC ANALYZER CONNECTOR R160 330 P43 VPCICLK R161 470 28 34 39 45 VPAD30 VPAD28 VPAD26 VPAD24 VPAD22 VPAD20 VPAD18 VPAD16 1 3 5 7 9 11 13 15 17 19 JP30 PREQJ1 PGNTJ1 1 48 25 24 HEADER 3X1 PLACE NEAR PCI1 CONNECTOR JP31 PREQJ2 PGNTJ2 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 1 2 3 HEADER 3X1 PLACE NEAR Am79C972 E/NET CHIP 21 4 10 15 C 1OE# 2OE# 3OE# 4OE# 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND VPAD14 VPAD12 VPAD10 VPAD8 VPAD6 VPAD4 VPAD2 VPAD0 VPAD16 VPAD17 VPAD18 VPAD19 VPAD20 VPAD21 VPAD22 VPAD23 VPAD24 VPAD25 VPAD26 VPAD27 VPAD28 VPAD29 VPAD30 VPAD31 R97 330 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 C_BEJ3 C_BEJ2 C_BEJ1 C_BEJ0 FRAMEJ IRDYJ TRDYJ DEVSELJ PCICLK D PLACE THEVENIN TERMINATOR NEAR ’ABT16244 BUFFER R98 470 INT0J INT1J INT2J INT3J PCIRSTJ STOPJ PAR 21 4 10 15 HP Conn. 1 1 3 5 7 9 11 13 15 17 19 +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND 2 4 6 8 10 12 14 16 18 20 VPAD15 VPAD13 VPAD11 VPAD9 VPAD7 VPAD5 VPAD3 VPAD1 2 19 20 Top View HP CONN 3M:2520-6003UB 28 34 39 45 C P45 VCC VCC VPAD31 VPAD29 VPAD27 VPAD25 VPAD23 VPAD21 VPAD19 VPAD17 P44 7 18 31 42 VCC VCC VCC VCC 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND 1 3 5 7 9 11 13 15 17 19 VC_BEJ2 VC_BEJ0 VIRDYJ VTRDYJ U40 1OE# 2OE# 3OE# 4OE# 2 4 6 8 10 12 14 16 18 20 B 7 18 31 42 VCC VCC VCC VCC 74ABT16244 1 48 25 24 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND VCC U38 1 2 3 +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 HP CONN 3M:2520-6003UB 74ABT16244 B A VC_BEJ3 VC_BEJ2 VC_BEJ1 VC_BEJ0 VFRAMEJ VIRDYJ VTRDYJ VDEVSELJ VPCICLK VINT0J VINT1J VINT2J VINT3J VPCIRSTJ VSTOPJ VPAR +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND 2 4 6 8 10 12 14 16 18 20 VC_BEJ3 VC_BEJ1 VFRAMEJ VDEVSELJ VSTOPJ HP CONN 3M:2520-6003UB P46 1 3 5 7 9 11 13 15 17 19 VINT2J VINT0J VPAR VSERRJ 28 34 39 45 +5V CLK1 D14 D12 D10 D8 D6 D4 D2 D0 CLK2 D15 D13 D11 D9 D7 D5 D3 D1 GND 2 4 6 8 10 12 14 16 18 20 VINT3J VINT1J VPCIRSTJ VPERRJ VPLOCKJ D HP CONN 3M:2520-6003UB 74ABT16244 U42 2 4 6 8 11 13 15 17 PLOCKJ PERRJ SERRJ E 1 19 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 18 16 14 12 9 7 5 3 VPLOCKJ VPERRJ VSERRJ (C) Advanced Micro Devices, Inc. (800) 222-9323 E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 1G 2G 74ABT244 Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 PCI_VIS.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 12 of 26 1 2 3 4 5 ETHERNET CONTROLLER, BYPASS CAPACITORS AND POWER SUPPLY FOR ETHERNET CONTROLLER, VCC3 AND SERIAL EEPROMS VCC3 VCC VCC3 EECS_1K ENETPG R105 1K C_BEJ0 C_BEJ1 C_BEJ2 C_BEJ3 PCIID3 FRAMEJ IRDYJ TRDYJ DEVSELJ STOPJ PERRJ SERRJ PAR INT2J PCIRSTJ PREQJ2 PGNTJ2 1 17 18 20 22 23 25 26 28 142 143 146 145 PCICLK3 144 131 132 133 141 5 13 21 29 38 45 53 147 155 65 77 88 101 113 124 136 VDDB VDDB VDDB VDDB VDDB VDDB VDDB PME# WUMI# RWU PG VCC3 EBDA15 EBDA14 EBDA13 EBDA12 EBDA11 EBDA10 EBDA9 EBDA8 EBD7 EBD6 EBD5 EBD4 EBD3 EBD2 EBD1 EBD0 PCICLK VSS VSS VSS VSS VSS VSS VSS VSS 16 32 56 72 90 110 130 150 DO NC GND 4 3 5 7 8 VCC 6 ORG CS SK DI DO NC GND 4 A 5 NM93C66M8 VCC3 EBUA_EBA7 EBUA_EBA6 EBUA_EBA5 EBUA_EBA4 EBUA_EBA3 EBUA_EBA2 EBUA_EBA1 EBUA_EBA0 IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR INTA# PCIRST# PCIREQ# PCIGNT# DI 1 2 NM93C46N For ’972 E/net Config. For User NV Data R104 10K 129 EAR# 122 TBC_IN 123 TBC_EN 125 LED2#/SRDCLK/MIIRXFRTGE 120 EEDO/LED3#/SRD/MIIRXFRTGD 121 EEDI/LED0# 126 EESK/LED1#/SFBD 128 EECS C_BE0# C_BE1# C_BE2# C_BE3# U81 EECS_4K 8 VCC 6 ORG CS SK 7 PHY_RST MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK/RXCLK RX_ER/RXDAT TX_ER TX_CLK/TXCLK TX_EN/TXEN TXD3 TXD2 TXD1 TXD0/TXDAT COL/CLSN CRS/RXEN 134 TCK 135 TMS 139 TDI 137 TDO C 42 30 15 160 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 1 2 3 EEDO EEDI EESK EECS 119 118 116 115 114 112 111 109 108 107 105 104 103 97 98 99 102 96 94 PHY_RST MDIO MDC ERXD3 ERXD2 ERXD1 ERXD0 RX_DV RX_CLK_RXCLK RX_ER_RXDAT TX_ER TX_CLK_TXCLK TX_EN_TXEN ETXD3 ETXD2 ETXD1 ETXD0_TXDAT COL_CLSN CRS_RXEN 71 70 69 68 67 66 63 61 B U82A EECS 1 3 EECS_1K 6 EECS_4K 2 74F08 82 81 80 79 78 76 75 73 C U82B U83A CLKCTR 1 4 2 CLKCTR# 5 Defaults to "1" 74F08 VCC3 83 85 86 87 89 91 92 93 74F14 R106 4.7K 60 EBCLK 59 AS_EBOE# 58 EBWE# 57 EROMCS# VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB VSSB B 55 54 52 50 49 47 46 44 41 40 39 37 36 34 33 31 14 12 10 9 7 6 4 2 159 158 156 154 153 152 151 148 3 11 19 27 35 43 51 62 74 84 95 106 117 127 138 149 157 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 VDD VDD VDD VDD VDD VDD U51 VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI VDD_PCI 8 24 48 64 100 140 A PAD[0..31] VCC U54 R103 1K ENETEBCLK Am79C972 (PQR160) D D IDSEL = AD21 Device #5 Set CSR116 bit 0 to "1" for proper PHY_RST operation Spare "AND" Gates VCC3 U82C 9 8 10 VCC U53 3 1 C85 VIN GND_ADJ VCC3 VOUT + C78 2.2uF C79 C80 C81 C82 C83 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 74F08 U82D VCC 12 11 4 13 74F08 + C84 10uF VCC3 1uF MC33269DT-3.3 (C) Advanced Micro Devices, Inc. (800) 222-9323 E E PLACE INPUT AND OUTPUT FILTER CAPS AS CLOSE AS POSSIBLE TO REGULATOR + C86 2.2uF + C87 10uF C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 ENET1.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 13 of 26 1 2 3 4 5 ETHERNET PHY CHIP, ETHERNET CONNECTOR, AND LEDS Y5 A A 1 2 4 3 C98 C99 33pF 25MHz_SMD ECLIPTEK ECSMA-25.00MTR ETXD3 ETXD2 ETXD1 ETXD0_TXDAT TX_CLK_TXCLK TX_EN_TXEN COL_CLSN RX_DV RX_ER_RXDAT RX_CLK_RXCLK ERXD3 ERXD2 ERXD1 ERXD0 CRS_RXEN MDIO VCC MDC 13 15 3 4 5 6 7 8 33 14 34 16 R114 1.00K, 1% MFV0 R115 1.00K, 1% PHY_RST LEDS# R117NET C 38 39 40 41 42 LEDT# LEDR# 32 35 36 R117 1.00K, 1% 11 XO TPIP ENET_RD+ 29 TPIN TPOP ENET_TD+ 21 ENET _RES TREF FDE MDDIS TRSTE MF4 MF3 MF2 MF1 MF0 CFG1 CFG0 PWRDWN RESET# VCCT VCCA RBIAS C111 0.1uF RD+ RDRD_CT RX+ RXRX_CT TD_CT TD+ TD- 12 TX_CT 11 TX+ 10 TX- 1 2 3 4 5 6 7 8 ENET_ R1 TXCT ENET_ R2 1 2 3 4 5 6 7 8 11 12 PE68515 R110 75, 1% R111 75, 1% R112 75, 1% B GND1 GND2 AMP RJ45A R113 75, 1% 555153-1 ENET_TD- 23 ENET _CAP ENET_TREF 20 C101 0.001uF, 2KV (MIN.) 19 24 25 RBIAS C102 0.01uF C103 0.01uF VCC R116 22K, 1% LEDS# LEDC# LEDL# LEDT# LEDR# 7 6 5 C100 0.1uF R109 49.9, 1% L4 C104 0.01uF C105 0.1uF AVCC 1 2 C FB GNDT GNDA NC1 NC2 NC3 + C106 10uF 22 AGND 26 + C107 10uF L5 1 2 FB L6 VCCR + C110 10uF 14 15 16 R108 49.9, 1% TPON ENET_TX+ ENET_TXENET_RX+ ENET_RXRXCT T1 1 2 3 ENET_RD- 30 37 AAVCC 1 2 FB C109 0.01uF VCC3 53 J10 R107 100, 1% VCCIO GNDR VCC 31 AAGND + C108 10uF L7 1 2 FB 9 VCCD 17 FIBOP 18 FIBON C112 0.1uF GNDIO TEST FIBIP FIBIN 12 27 28 D 10 8 VCC LXT970QC 7 6 5 52 10 43 GNDD D EDGE OF BOARD B TX_ER TXD4 TXD3 TXD2 TXD1 TXD0 TX_CLK TX_EN COL RX_DV RX_ER RX_CLK RXD4 RXD3 RXD2 RXD1 RXD0 CRS MDIO FDS/MDINT MDC RD_CT 56 63 62 61 60 59 57 58 64 51 55 54 46 47 48 49 50 1 44 2 45 XI U52 TX_ER 33pF PHY_ XO 12 PHY _XI 4 3 R149 270 R150 270 R151 270 2 1 9 2 E 4 3 ECLIPTEK ECSMA-25.00MTR RLEDR# RJ45 PINOUT, COMPONENT SIDE VIEW PINS: 1-8 NP MOUNTING HOLES: 9, 10 SHIELD MOUNTING HOLES: 11, 12 2 1 D12 LED (SOT23) LED (SOT23) LED (SOT23) 3 1 D11 3 2 D10 3 1 2 1 2 1 RLEDT# RLEDS# 11 (C) Advanced Micro Devices, Inc. (800) 222-9323 E 3 LEDS# LEDT# LINK SPEED Red TX DATA Green 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved LEDR# LUMEX SOT23 LED RX DATA Green Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 ENET2.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 14 of 26 1 2 3 4 5 IDE INTERFACE AND BOARD BYPASS CAPACITORS HDD[0..15] VCC Byass Capacitors For The Board VCC RP6 BC3 BC4 BC5 BC6 BC7 BC1 BC2 BC8 BC9 BC10 BC11 BC12 BC13 BC14 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF BC15 BC16 BC17 BC18 BC19 BC20 BC21 BC22 BC23 BC24 BC25 BC26 BC27 BC28 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 2 3 4 5 6 7 8 9 10 HDD7 HDD6 HDD5 HDD4 HDD3 HDD2 HDD13 HDD1 A VCC O2 C O3 O4 O5 O6 O7 O8 O9 O10 RP5 1 1 10K-10P BC30 BC31 BC32 BC33 BC34 BC35 BC36 BC37 BC38 BC39 BC40 BC41 BC42 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF HDRQ0 HDIOWJ HDIORJ HDIORDY HDACK0 IRQ14 HDA1 HDA0 HDCSJ0 Place one bypass capacitor near each chip Vcc pin, except: ’ABT chips get one on each side near end Vcc pins QFP chips get one on each side by central Vcc pin VCC TC12 10uF + TC2 10uF + TC24 10uF + J5LED VCC + TC25 10uF BC43 0.1uF BC44 0.1uF BC45 0.1uF BC46 0.1uF VCC BC47 O2 O3 O4 O5 O6 O7 O8 O9 O10 2 3 4 5 6 7 8 9 10 HDD8 HDD9 HDD10 HDD11 HDD12 HDD15 HDD14 HDD0 A 10K-10P 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 HDD7 HDD6 HDD5 HDD4 HDD3 HDD2 HDD1 HDD0 VCC BC29 C J5 SYSRSTJ B HDD[0..15] 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 HDD8 HDD9 HDD10 HDD11 HDD12 HDD13 HDD14 HDD15 B HDIO16J HDA2 HDCSJ1 CNN-40C HD ACTIVE LED R62 0.1uF J5LEDR 1 2 3 D13 LED (SOT23) 270 IDE HARD DISK 1 Distribute Tantalum capacitors around the board C C J7 SYSRSTJ HDD7 HDD6 HDD5 HDD4 HDD3 HDD2 HDD1 HDD0 J7LED HDRQ1 HDIOWJ HDIORJ HDIORDY HDACK1 IRQ15 HDA1 HDA0 HDCSJ2 D 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 HDD8 HDD9 HDD10 HDD11 HDD12 HDD13 HDD14 HDD15 RP7 HDIO16J HDA2 HDCSJ3 HDCSJ1 HDCSJ0 HDCSJ3 HDCSJ2 HDA0 HDA2 HDA1 HDIO16J 10 9 8 7 6 5 4 3 2 O10 O9 O8 O7 O6 O5 O4 O3 O2 C VCC 1 10K-10P D R21 CNN-40C HDIORJ VCC 1K R20 HD ACTIVE LED R63 HDIOWJ J7LEDR 1 2 3 D14 LED (SOT23) 270 1K R90 IDE HARD DISK 2 HDIORDY 4.7k (C) Advanced Micro Devices, Inc. E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 1 3 CATH 2 Top View (800) 222-9323 E LUMEX LED (SOT23) Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 IDE.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 15 of 26 1 2 3 4 5 FINALi M1487 INTERFACE VCC A RP12 1 C 2 3 4 5 6 7 8 9 10 O2 O3 O4 O5 O6 O7 O8 O9 O10 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 DACK7 DACK6 DACK5 DACK3 DACK2 DACK1 DACK0 IRQ15 IRQ14 IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ1 IRQ8J XBUSCSJ CLEAROKJ CMPGNTJ CMPSTJ ENRTC A VCC TC17 10K-10P C50 C173 C174 0.1uF 0.1uF 0.1uF 3 11 93 92 90 89 88 83 96 97 99 101 100 102 86 94 84 104 106 108 103 87 91 85 105 107 109 1 40 60 80 120 144 10 41 62 98 128 138 160 + 10uF IRQ8J IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DACKJ0 DACKJ1 DACKJ2 DACKJ3 DACKJ5 DACKJ6 DACKJ7 DREQ0 DREQ1 DREQ2 DREQ3 DREQ5 DREQ6 DREQ7 VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND U21 U15A B 2 PCIRSTJ CPUCLK2 CPURST 1 SYSRST A20MJ INTR FERRJ IGNNEJ M1487NMI SMIJ STPCLKJ PCICLK 74F04 U15B 4 SYSRSTJ 61 20 63 22 23 16 17 18 19 21 46 81 49 70 13 50 53 54 52 51 55 47 48 57 59 56 58 73 78 14 15 65 64 74 75 72 71 5 6 12 3 74F04 JRESET U15D 8 ZRSTDRV OSC ATCLK PWG PREQJ0 PREQJ1 PREQJ2 PGNTJ0 PGNTJ1 PGNTJ2 FRAMEJ IRDYJ INT0J INT1J INT2J INT3J XBUSCSJ RTCAS 9 74F04 U15C R147 6 RRDRV# RSTDRV# 5 74F04 22 C OSCI OSCO R79 10M SPEAK TURBO EXTSMI Y4 4 3 CLKCTR ENRTC 1 2 VBAT CLEAROKJ CMPGNTJ CMPSTJ IBCSTJ HA2 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 IOCS16J MEMCS16J MEMRJ MEMWJ SMEMRJ SMEMWJ IOCHRDY OWAITJ BALE IORJ IOWJ MASTERJ TC IOCHCKJ REFRESHJ SBHEJ AEN C54 10pF 32.768KHz_SMD ECLIPTEK ECPSM29T-32.768KTR 44 43 45 42 39 38 24 25 26 27 29 31 33 34 32 28 30 35 36 37 110 111 67 79 66 76 139 2 68 69 77 82 95 129 158 159 140 C53 10pF CPUCLK CPURST SYSRST A20MJ INTR FERRJ IGNNEJ NMI SMIJ STPCLKJ PCICLK SYSRSTJ OSC ATCLK PWG PREQJ0 PREQJ1 PREQJ2 PGNTJ0 PGNTJ1 PGNTJ2 FARMEJ IRDYJ INT0J INT1J INT2J INT3J XBUSCSJ RTCAS OSC1 OSC2 SPEAKER TURBO EXTSMI SPLED CLKCTR ENRTC KBCLK KBDATA VBAT R58 ENRTC D 1K OFF: ENABLE INTERNAL RTC ON: DISABLE INTERNAL RTC 137 136 135 134 133 132 131 130 119 121 127 126 125 124 123 122 7 4 157 156 155 154 152 151 150 149 148 147 146 9 8 153 145 143 142 141 118 117 116 115 114 113 112 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SA[0..19] C LA[17..23] LA[17..23] ZAEN ZSBHEJ ZREFSHJ IOCHKJ TC MASTERJ ZIOWJ ZIORJ ZBALE N0WSJ IOCHRDYJ ZSMEMWJ ZSMEMRJ ZMWJ ZMRJ MEM16J IO16J CMPSTJ GA[2..17] R170 IBCSTJ DISABLES INTERNAL KBC 1K SA[0..19] M1487 *1K GA[2..17] B LA17 LA18 LA19 LA20 LA21 LA22 LA23 R59 OFF: 1X CPU-TO-PCI BUS FREQUENCY ON: 2X CPU-TO-PCI BUS FREQUENCY SD[0..15] SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 GA10 GA11 GA12 GA13 GA14 GA15 GA16 GA17 CLEAROKJ CMPGNTJ CMPSTJ IBCSTJ SD[0..15] SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 LA17 LA18 LA19 LA20 LA21 LA22 LA23 D *=Do Not Populate (C) Advanced Micro Devices, Inc. E 1 (800) 222-9323 E 2 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title 4 3 ECLIPTEK ECPSM29T-32.768KTR (COMPONENT SIDE VIEW) Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 M1487.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 16 of 26 1 2 3 4 5 BIOS ROM, ISA SIGNAL SERIES TERMINATION; BATTERY AND SPEAKER CIRCUITS; RESET, SMI, AND NMI PUSHBUTTONS VCC A VCC SA[0..19] SA[0..19] 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 XBUSCSJ MRDJ B GA[2..9] 22 24 31 SMEMWJ VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 13 14 15 17 18 19 20 21 ROM Data Transferred on FINALi LinkBus GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 1 3 5 7 AEN SBHEJ RSTDRV ZBALE GND ZAEN ZSBHEJ ZRSTDRV BALE RN10 SMEMWJ ZSMEMRJ ZIORJ IOWJ R178 1K ROM_A17 ROM_A18 1 3 5 7 1 2 3 SA17 VCC 16 1 2 3 SA18 Am29F010-90 ZSMEMWJ SMEMRJ IORJ ZIOWJ VCC 33-8B R71 470 Jumpers to allow multiple 128K BIOS images in the same Flash ROM chip and/or non-PC applications that can use more than 128Kx8 BIOS ROM B TURBO SWITCH FUNCTION RN11 1 3 5 7 REFRESHJ ZMRJ MWTJ ATCLKO HEADER 3X1 FINALi only supports 1MBit Flash ROM chip (128Kx8 worth of address space) for legacy, desktop PC applications 2 4 6 8 R68 10K HEADER 3X1 JP33 CE OE WR 2 4 6 8 VCC JP32 A17 A18 A RN12 33-8B CTS 743 08-3 330 J TR VCC R177 1K 30 1 R76 10K GA[2..9] U14 32 O10 O9 O8 O7 O6 O5 O4 O3 O2 C VCC 10 9 8 7 6 5 4 3 2 VCC R77 10K 1 RP18 10K-10P 2 4 6 8 ZREFSHJ MRDJ ZMWJ ATCLK TURBO R70 *2.2K 33-8B VCC 1 1 BT1P 3 D1 3 VBAT D8 MMBD4148 (SOT23) MMBD4148 (SOT23) R34 1K 2 BT1 3V Coincell (socket) KEYSTONE 103 or 106 1 3 R139 100 U83B 1 Press Switch To Assert NMI U77A EXTNMI# SW2NET 3 EXTNMI 4 1 3 C SW2 PBNO VCC Q1 MMBT3906 (SOT23) 2 3 (TO Am486 CPU) 74F14 + R47 TC22 10uF C NMI 2 74F32 M1487NMI Q1R (FROM M1487) 0 1 VCC VCC D5 MMBD4148 (SOT23) Press Switch To Assert SMI 1 Q2RR 3 Q2 2MMBT3904 (SOT23) 1 3 R140 100 R52 10K Press Switch To Assert RESET 1 3 1 Q2RQ D9 MMBD4148 (SOT23) RREXTSMI R65 100 RRPWG PWG SW1 PBNO EXTSMI JP34 SW3 PBNO 1 2 D R49 10K + R64 10K 1 R50 10K 3 R48 51K TC13 10uF 3 Q1RQ + TC23 10uF + TC16 10uF D HEADER 2X1 Jumper for external RESET# pushbutton VCC SPARE ’F14 GATES U83C LS1 R81 RRSPEAK Battery Socket 5 RCSPEAK 33 C52 3 4 1 SPEAK 3 CSPEAK CRSPEAK 0.1uF 2 E 1 MMBD4148 MMBT3904 MMBT3906 2 (SOT23) (SOT23) (SOT23) 9 8 C55 22pF 470 74F14 U83E D6 MMBD4148 (SOT23) 11 1 C&K SWITCH 1 1 74F14 U83D 3 Q4 2MMBT3904 (SOT23) 3 2 R80 6 SPEAKER Reset, SMI Switches (C) Advanced Micro Devices, Inc. E Title 74F14 U83F 13 (800) 222-9323 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 10 12 Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 ROM_MISC.SCH 74F14 1 2 3 4 Date: Friday, December 04, 1998 Sheet 5 17 of 26 1 2 3 4 5 CLOCK GENERATOR A A Y2 1 2 C161 VCC 4 3 C155 B VCC INSTALL PULLUP RESISTOR AND REMOVE 0-OHM RESISTOR FOR 25MHz CPU AND PCI BUS 14.318MHz_SMD VCC OSC U17 R92 R93 4.7K 1 *4.7K 2 CLKOSCOUT 11 10 17 CLKPU2 CLKPU1 R176 18 0 15 U15E 14.318 OSCout S0 S1 S2 DOZE# 10 TC14 + 14 AVDD 28 24 MCLK1 25 MCLK2 B2in B1in ST# R42 CLKAVDD1 R41 OSCin VCC C B R39 4.7K 10pF CLKOSCIN 10pF R54 ROSCC B1OUT1 20 B2out1 21 B2out2 22 B2out3 23 B2out4 B2OUT1 B2OUT2 B2OUT3 B2OUT4 R31 10 R33 B1OUT2 B1OUT3 B1OUT4 R36 R38 10 R22 R57 0 R35 R99 C65 0.1uF CLKLF1 13 LF1 VSS1 VSS2 VSS3 CPUCLK1 CPUCLK2 CPUCLK3 10 10 CLKAVDD2 + TC15 10uF PCICLK1 PCICLK2 10 C CPUCLK VCC AVSS PCICLK3 PCICLK 0 10 L3 7 16 OSC1 C60 15pF PLACE SERIES TERMINATORS AS CLOSE TO U17 AS POSSIBLE 27 3 5 B1out1 6 B1out2 8 B1out3 9 B1out4 VDD1 VDD2 RROSC1 10 10uF 12 10 74F04 MCLK2 C47 0.1uF CLKAVSS 11 RROSC 10 C41 C43 15pF 15pF C46 C154 15pF 15pF C33 15pF C56 C57 C66 15pF 15pF 15pF FB C48 0.1uF 4 19 26 C170 0.1uF PCICLK AND CPUCLK3 HAVE MULTIPLE LOADS AND ARE THEVENIN TERMINATED AT THE END OF THE NET IMI SC464 D D 1 E (C) Advanced Micro Devices, Inc. 2 (800) 222-9323 E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title 4 3 ECLIPTEK ECSMAT-14.318MTR (COMPONENT SIDE VIEW) Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 CLOCK.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 18 of 26 1 2 3 4 5 ISA BUS CONNECTORS AND PULLUPS VCC -5V VCC R75 4.7K SL2 RSTDRV A IRQ9 DRQ2 N0WSJ B SMEMWJ SMEMRJ IOWJ IORJ DACK3 DRQ3 DACK1 DRQ1 REFRESHJ ATCLKO IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE OSC1 MEM16J IO16J IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 MASTERJ 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 -IOCHCK D7 D6 D5 D4 D3 D2 D1 D0 IOCHRDY AEN A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 -MEMCS16 -IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 -DACK0 DREQ0 -DACK5 DREQ5 -DACK6 DREQ6 -DACK7 DREQ7 +5V -MASTER GND -SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 -MEMR -MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VCC 1 RP19 10K-10P DRQ2 IOCHRDYJ AEN VCC 1 RP17 10K-10P SBHEJ D VCC 1 N0WSJ SMEMWJ SMEMRJ IOWJ IORJ DACK3 DRQ3 DACK1 DRQ1 REFRESHJ ATCLKO IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE GND RESDRV +5V IRQ9 -5V DREQ2 -12V -0WS +12V GND -SMEMW -SMEMR -IOW -IOR -DACK3 DREQ3 -DACK1 DREQ1 -REFSH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 -DACK2 TC ALE +5V 14.3MHZ GND 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 MEM16J IO16J IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 MRDJ MWTJ SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 O10 O9 O8 O7 O6 O5 O4 O3 C O2 D7 MMBD4148 (SOT23) OSC1 LA23 LA22 LA21 LA20 LA19 LA18 LA17 O10 O9 O8 O7 O6 O5 O4 O3 C O2 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 IRQ9 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 O10 O9 O8 O7 O6 O5 O4 O3 C O2 IOCHKJ VCC RSTDRV MASTERJ AMP 645169-3 RP16 10K-10P -5V IOCHKJ ISA AT Connector C -12V SL1 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 +12V SA[0..19] 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 GND RESDRV +5V IRQ9 -5V DREQ2 -12V -0WS +12V GND -SMEMW -SMEMR -IOW -IOR -DACK3 DREQ3 -DACK1 DREQ1 -REFSH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 -DACK2 TC ALE +5V 14.3MHZ GND R78 1K 3 -12V 1 +12V SD[0..15] -IOCHCK D7 D6 D5 D4 D3 D2 D1 D0 IOCHRDY AEN A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 -MEMCS16 -IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 -DACK0 DREQ0 -DACK5 DREQ5 -DACK6 DREQ6 -DACK7 DREQ7 +5V -MASTER GND -SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 -MEMR -MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 A IOCHRDYJ AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 B SBHEJ LA23 LA22 LA21 LA20 LA19 LA18 LA17 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 MRDJ MWTJ ISA AT Connector C58 47pF C64 47pF 10 9 SA12 8 SA13 7 SA14 6 SA15 5 SA16 4 SA17 3 SA18 2 SA19 C AMP 645169-3 RP15 VCC 10 9 SA4 8 SA5 7 SA6 6 SA7 5 SA8 4 SA9 3 SA10 2 SA11 RP21 O10 O9 O8 O7 O6 O5 O4 O3 C O2 1 10 9 SD0 8 SD1 7 SD2 6 SD3 5 SD4 4 SD5 3 SD6 2 SD7 VCC 1 4.7K-10P O10 O9 O8 O7 O6 O5 O4 O3 C O2 10 9 SD15 8 SD14 7 SD13 6 SD12 5 SD11 4 SD10 3 SD9 2 SD8 4.7K-10P SD[0..15] SD[0..15] VCC VCC RP14 10 9 SA1 8 SA2 7 SA3 6 SA0 5 4 3 2 2 3 4 5 6 7 8 9 10 IRQ9 IRQ8J IRQ7 IRQ15 IRQ14 IRQ10 IRQ11 IRQ12 IRQ3 IRQ4 IRQ5 IRQ6 O2 C O3 O4 O5 O6 O7 O8 O9 O10 RP20 1 1 10K-10P C O2 O3 O4 O5 O6 O7 O8 O9 O10 2 3 4 5 6 7 8 9 10 LA23 LA22 LA21 LA20 LA19 LA18 LA17 D 10K-10P LA[17..23] LA[17..23] SA[0..19] VCC RP13 MEM16J IO16J N0WSJ REFRESHJ MASTERJ E 2 3 4 5 6 7 8 O2 O3 O4 O5 O6 O7 O8 C 1 (C) Advanced Micro Devices, Inc. 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Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 330-8P Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 ISA_CONN.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 19 of 26 1 2 3 4 5 SUPER I/O CHIP, IrDA INTERFACE, FLOPPY DISK INTERFACE, SERIAL PORT ACTIVITY LEDS Y1 VCC C44 39pF R152 1.5K SD[0..7] SD[0..7] VCC R153 1.5K B PWG DACK1 DACK2 DACK3 28 36 96 PWG RSTDRV 58 57 RXD1 CTS1J DSR1J DCD1J RI1J 78 82 80 85 84 RXD2 CTS2J DSR2J DCD2J RI2J 88 92 90 87 86 D15 D16 LED (2mA, SOT23) LED (2mA, SOT23) TXD2 2 3 6 47 67 95 15 72 20 37 IRQ3 38 IRQ4 94 IRQ5/ADRx#/PP_MODE1 40 IRQ6 39 IRQ7 AEN IOR# IOW# TC IOCHRDY SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 3 48 49 50 51 53 54 55 56 1 46 44 45 35 100 U43 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 A TXD1_LED 3 U84A 74ABT125 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 4 AEN IORJ IOWJ TC IOCHRDYJ SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 GND GND GND GND 27 29 30 31 32 33 34 41 42 43 97 VCC VCC SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 OSC1 SA[0..10] OSC2 SA[0..10] 21 1 2 SIOOSC1 SIOOSC2 A RRRXD1 24MHz_SMD RRTXD1 C45 39pF 4 3 1 2 1 2 RXD2 5 RXD1_LED 6 U84B 74ABT125 B VCC 23 DRQ1/UR1_ADD1 52 DRQ2 98 DRQ3 DACK1# DACK2# DACK3# DRQ1 DRQ2 DRQ3 PWRGD MR R154 1.5K R155 1.5K TXD2 RTS2J DTR2J TXD1 IRQ9 R130 IIRQ9 SIO_IRQIN DENSEL MOT0 MOT1 DRV0 DRV1 DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK0# WP# RDATA# DSKCHG# IDE_OE#/IRQ10 NCSJ IDE_CS1#/IRQ11 IDE_CS0#/IRQ9/UR1_ADD0 PDIR/IRQIN 1K COMPONENT SIDE VIEW IRTX IRRX 5 25 26 IRTX/CFG_PORT IRRX/FDC_ADD R118 1K 61 62 60 59 75 73 74 76 77 3 RPM MTR0J MTR1J DR0J DR1J FDIR STEPJ WDATAJ WGATEJ HDSEL INDEXJ TRK0J WRTPRTJ RDATAJ DSKCHG 9 RXD1 12 J6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 SuperI/O IrDA Port PP[0..7] R100 10 R101 10 R102 47 C67 0.1uF 8 1 VCCIR1 VCC GND 5 GP1 GP2 TXD RXD NC SD 3 C68 6.8uF + PP[0..7] PSTROBJ PAUTOFDJ PINITJ PSLCTINJ PERRORJ PSLCT PPE PACKJ PBUSY IR1LEDA LEDA C69 0.1uF RP4 1K-10P D RPM 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 INDEXJ MTR0J DR1J DR0J MTR1J FDIR STEPJ WDATAJ WGATEJ TRK0J WRTPRTJ RDATAJ HDSEL DSKCHG CNN-34C FLOPY-CON 4 (C) Advanced Micro Devices, Inc. 7 2 IRTX IRRX 6 (800) 222-9323 E 1 2 2 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 1 Title IR1SD 4 3 ECLIPTEK ECSMA-25.00MTR (COMPONENT SIDE VIEW) U44 TFDS6000 3 KINGBRIGHT SOT23 LED (COMPONENT SIDE VIEW) Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number 2 3 Rev 2.1 SUPER_I/O.SCH Date: Friday, December 04, 1998 1 3 VCC PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 VCC 9 10 RXD2_LED 11 U84D 74ABT125 M5113A TFDS6000 E C 4 D LEDC TXD2_LED 8 U84C 74ABT125 2 3 4 5 6 7 8 9 10 2 1 1 2 5 4 3 7 8 9 10 11 12 13 14 16 17 1 10 9 LED (2mA, SOT23) PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 6 71 70 69 68 66 65 64 63 7 BUSY ACK# PE SLCT ERROR# SLCTIN# INIT# AUTOFD# STROB# 8 D18 LED (2mA, SOT23) O2 C O3 O4 O5 O6 O7 O8 O9 O10 18 19 22 24 99 IIRQ11 D17 3 IIRQ10 SIO_NCSJ IRQ11 C RRRXD2 89 TxD2/FDC_EN 91 RTS2#/UR2_ADD0 93 DTR2#/UR2_ADD1 10 RxD2 CTS2# DSR2# DCD2# RI2#/IDE_ADD 1 2 TXD1 RTS1J DTR1J 1 2 79 TxD1/PP_ADD0 81 RTS1#/PP_ADD1 83 DTR1#/PP_MODE0 13 R127 0 RxD1 CTS1# DSR1# DCD1# RI1#/IDE_EN RRTXD2 IRQ10 4 Sheet 5 20 of 26 1 2 3 4 5 SERIAL AND PARALLEL PORT INTERFACES VCC RP3 2 3 4 5 6 7 8 9 10 A PP[0..7] PP[0..7] O2 C O3 O4 O5 O6 O7 O8 O9 O10 PP0 PP1 1 3 5 7 PP2 PP3 1 3 5 7 PAUTOFDJ R6 1K A J4 1K-10P RN5 PSTROBJ 1 PPSTROBJ PPAUTOFDJ PPP0 PPERRORJ PPP1 PPINTJ PPP2 PPSLCTINJ PPP3 2 4 6 8 22-8B RN6 PINITJ PSLCTINJ 2 4 6 8 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 PPP4 PPP5 22-8B PPP6 RN7 PP4 PP5 PP6 PP7 2 4 6 8 PPP7 1 3 5 7 PPACKJ PPBUSY B 22-8B R14 PPPE 22 PERRORJ R17 22 R15 22 R16 22 R18 22 PPSLCT PACKJ B Parallel Port AMP 745967-7 PBUSY PPE PSLCT C C26 C24 C21 C18 C16 C32 C27 C25 C23 C20 C17 C15 C31 C22 C19 C29 C30 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF Serial Connector (Component Side View) VCC U45 SIO1C1P 21 22 20 23 19 24 25 18 13 3 C70 RO3 RO2 RO4 DI2 DI3 RO1 DI1 RO5 ON/OFF C1+ RI3 RI2 RI4 DO2 DO3 RI1 DO1 RI5 C2+ 9 8 10 7 11 6 5 12 27 DCD1P# DSR1P# RXD1P RTS1P# TXD1P CTS1P# DTR1P# RIN1P# SIO1C2P C71 SIO1C1M SIO1VP 4 1 2 C72 C1V+ VCC C2VGND 26 28 17 1 3 5 7 2 4 6 8 C73 5 1 6 2 7 3 8 4 9 5 4 3 2 C138 C139 C140 C141 C142 C143 C144 C145 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 9 8 7 6 1 SERIAL PORT AMP 745410-1 22-8B SIO1C2M SIO1VM RS232-5V LTC1349CG 0.1uF RDCD1P# RDSR1P# RRXD1P# RRTS1P# RTXD1P# RCTS1P# RDTR1P# RRIN1P# 2 4 6 8 22-8B RN14 0.1uF 0.1uF VCC 1 3 5 7 C J9 RN13 DCD1J DSR1J RXD1 RTS1J TXD1 CTS1J DTR1J RI1J Parallel Connector 1 14 0.1uF 2 15 3 D D 16 4 17 5 VCC 18 U46 SIO2C1P 21 22 20 23 19 24 25 18 13 3 C74 RO3 RO2 RO4 DI2 DI3 RO1 DI1 RO5 ON/OFF C1+ RI3 RI2 RI4 DO2 DO3 RI1 DO1 RI5 C2+ 9 8 10 7 11 6 5 12 27 DCD2P# DSR2P# RXD2P RTS2P# TXD2P CTS2P# DTR2P# RIN2P# SIO2C2P C75 0.1uF 0.1uF SIO2C1M SIO2VP C76 E VCC 0.1uF 4 1 2 C1V+ VCC RS232-5V LTC1349CG C2VGND 26 28 17 1 3 5 7 RDCD2P# RDSR2P# RRXD2P# RRTS2P# RTXD2P# RCTS2P# RDTR2P# RRIN2P# 2 4 6 8 22-8B RN16 1 3 5 7 2 4 6 8 C77 19 1 6 2 7 3 8 4 9 5 7 20 8 21 9 22 10 23 11 24 12 SERIAL PORT AMP 745410-1 22-8B SIO2C2M SIO2VM 6 J8 RN15 DCD2J DSR2J RXD2 RTS2J TXD2 CTS2J DTR2J RI2J C146 C147 C148 C149 C150 C151 C152 C153 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 25 13 (Component Side View) (C) Advanced Micro Devices, Inc. (800) 222-9323 E 0.1uF 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 SERIAL_PARALLEL.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 21 of 26 1 2 3 4 5 INTERFACE FOR ISA BUS MEMORY AND HEX DISPLAYS LA[17..23] ISAA[1..23] U69 3 4 7 8 13 14 17 18 LA23 LA22 LA21 LA20 LA19 LA18 LA17 A 1 11 BALE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 2 5 6 9 12 15 16 19 RSTDRV IORJ ISAA23 ISAA22 ISAA21 ISAA20 ISAA19 ISAA18 ISAA17 BALE ATCLKO REFRESHJ U55 OE# E VCC SA[0..16] ISAA1 ISAA2 ISAA3 ISAA4 ISAA5 ISAA6 ISAA7 ISAA8 ISAA9 ISAA10 ISAA11 ISAA12 ISAA13 ISAA14 ISAA15 ISAA16 ISAA17 ISAA18 ISAA19 ISAA20 ISAA21 ISAA22 ISAA23 U70 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 B 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 21 4 10 15 1OE# 2OE# 3OE# 4OE# VCC VCC VCC VCC 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND 7 18 31 42 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 ISAA1 ISAA2 ISAA3 ISAA4 ISAA5 ISAA6 ISAA7 ISAA8 ISAA9 ISAA10 ISAA11 ISAA12 ISAA13 ISAA14 ISAA15 ISAA16 93 94 95 96 97 99 6 8 9 10 11 12 19 20 21 22 23 25 32 34 35 36 37 38 43 44 45 46 47 49 SMEMWJ SMEMRJ IOWJ AEN MRDJ MWTJ 74ABT373 1 48 25 24 A XBUSCSJ SA0 28 34 39 45 3 28 53 78 74ABT16244 SD[0..15] 1 2 16 17 29 30 40 41 51 52 66 67 79 80 90 91 ISAD[0..15] P48 VCC MACH_TCK MACH_TMS MACH_TDI MACH_TDO U71 C DIR245 1 24 EN245# 48 25 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 21 4 10 15 D 1DIR 2DIR VCC VCC VCC VCC 1G# 2G# 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 GND GND GND GND GND GND GND GND 7 18 31 42 1 3 5 7 9 VCC 2 4 6 8 10 LOW R134 1K HEADER2X5; SHRD 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 ISAD0 ISAD1 ISAD2 ISAD3 ISAD4 ISAD5 ISAD6 ISAD7 ISAD8 ISAD9 ISAD10 ISAD11 ISAD12 ISAD13 ISAD14 ISAD15 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I0/CLK0 I1/CLK1 I2 I3 I4/CLK2 I5/CLK3 I6 I7 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C TDI TCK TMS TDO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC 56 58 59 60 61 62 69 70 71 72 73 75 82 84 85 86 87 88 13 18 26 54 63 68 76 4 XBUSCSJ N0WSJ MEM16J IOCHRDYJ ROMCE# ROMOE# ROMWE# EN245# DIR245 P80CS# P680CS# B ATCLKO ATCLKO BALE IORJ RSTDRV 5 7 24 27 31 33 48 50 55 57 74 77 81 83 98 100 VCC C 14 15 39 42 64 65 89 92 MACH221SP-7Y ISACNTL.J1 Rev. 1.6 VCC U72 3 2 13 12 ISAD4 ISAD5 ISAD6 ISAD7 28 34 39 45 P80CS# 74ABT16245 P80HD 5 8 4 10 R135 330 DA DB DC DD STRB BLNK LDC RDC VCC LED NC NC NC GND 14 1 VCC U73 3 2 13 12 ISAD0 ISAD1 ISAD2 ISAD3 6 9 11 7 P80LD Hex Display TI - TIL311 5 8 4 10 DA DB DC DD STRB BLNK LDC RDC VCC LED NC NC NC GND 14 1 PORT 80 6 9 11 D 7 Hex Display TI - TIL311 R136 330 MACH221SP 100 99 82 81 VCC U74 1 80 2 79 78 ISAD4 ISAD5 ISAD6 ISAD7 JTAG Connector P680CS# 3 2 13 12 53 5 8 P680HD 4 10 29 52 R137 330 30 51 1 2 E 9 DA DB DC DD STRB BLNK LDC RDC VCC LED NC NC NC GND Hex Display TI - TIL311 14 1 6 9 11 7 VCC U75 3 2 13 12 ISAD0 ISAD1 ISAD2 ISAD3 P680LD R138 330 5 8 4 10 DA DB DC DD STRB BLNK LDC RDC VCC LED NC NC NC GND 14 1 PORT 680 6 9 11 (C) Advanced Micro Devices, Inc. 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Hex Display TI - TIL311 Title 10 Size 31 32 49 50 Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 ISA_MEM1.SCH Top View Date: Friday, December 04, 1998 1 (800) 222-9323 E 7 2 3 4 Sheet 5 22 of 26 1 2 3 4 5 ISA BUS FLASH MEMORY A A ISAD[0..15] ISAA[1..21] U56 B VCC R131 ISAA1 ISAA2 ISAA3 ISAA4 ISAA5 ISAA6 ISAA7 ISAA8 ISAA9 ISAA10 ISAA11 ISAA12 ISAA13 ISAA14 ISAA15 ISAA16 ISAA17 ISAA18 ISAA19 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RY/BY# 29 31 33 35 38 40 42 44 ISAD0 ISAD1 ISAD2 ISAD3 ISAD4 ISAD5 ISAD6 ISAD7 30 32 34 36 39 41 43 45 ISAD8 ISAD9 ISAD10 ISAD11 ISAD12 ISAD13 ISAD14 ISAD15 15 10K RSTDRV# C ROMCE# ROMOE# ROMWE# B VCC WORD RSTDRV# 47 12 ROMCE# ROMOE# ROMWE# 26 28 11 BYTE# RESET# CE# OE# WE# VCC GND GND 37 C114 C115 0.1uF 0.1uF C 46 27 29F800-55 TSOP48 1MByte ISA Flash Memory Configured as 512Kx16bit (29F800T device in "word" mode) Access at even ISA Memory addresses between 15MB and 16MB-1 Use CSR 12h bit 3 to access 0f00000-0ffffffh as ISA Memory (instead of DRAM, if installed) Flash chip A0 pin tied to ISA Address Bit 1; mulitply desired Flash chip address by 2h to find correct ISA address for access (ex: Flash chip address 555h is accessed at ISA address AAAh) D D (C) Advanced Micro Devices, Inc. (800) 222-9323 E E 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 ISA_MEM2.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 23 of 26 1 2 3 4 5 OPTIONAL Y2K RTC AND TEST INTERFACE PORT CONNECTOR VCC GA[2..9] RTC Address/Data Transferred on FINALi LinkBus A R142 10K RSTDRV# Set RAMCLR Bit in CR 4B to enable RAM_Clear Function VCC U22 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 VCC 4 5 6 7 8 9 10 11 18 21 RTCKS# VCC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VBAT VBAUX SQW IRQ# PWR# R141 10K 24 A 20 VBAT 22 23 19 1 IRQ8J RTCPWR# Y6 KS# RCLR# X1 2 4 3 RTCX1 1 2 U15F 13 PWG 12 RTCCS# 13 14 15 17 74F04 CS# ALE WR# RD# X2 GND GND 3 RTCX2 32.768KHz_SMD 12 16 12.5pF Set CS Bit in CR 4B for 12.5pF Xtal DS1685-5 RTCAS U77B 4 ZIOWJ B 6 RTCWR# 8 RTCRD# B 5 74F32 U77C ENRTC (RTCSJ) 9 U77D 10 ZIORJ 12 11 74F32 13 74F32 1 4 3 ECLIPTEK ECPSM29T-32.768KTR (COMPONENT SIDE VIEW) OPTIONAL Y2K COMPLIANT RTC C 2 C T.I.P. CONNECTOR SD[0..15] SA[0..19] P31 SA0 SA2 SA4 SA6 SA8 D SA10 SA12 SA14 SA16 SA18 SD0 SD2 SD4 SD6 TIP TEST IRQ R122 0 AEN IORJ IOWJ SWIRQ IRQ14 PWG RSTDRV E 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 SA1 SA3 SA5 SA7 SA9 EDGE OF BOARD D T.I.P. CONNECTOR SA11 SA13 SA15 SA17 SA19 1 SD1 SD3 SD5 SD7 R119 0 ETHERNET IRQ R120 0 PARALLEL PORT IRQ R121 0 SERIAL PORT1 IRQ R123 0 SERIAL PORT0 IRQ 2 IRQ15 IRQ12 ENETIRQ PARIRQ SERIRQ1 SERIRQ0 PLASTIC SHROUD NOTCH ON TOP IRQ11 IRQ10 IOCHRDYJ VCC (C) Advanced Micro Devices, Inc. E COND60 + C113 10uF 16V C-CASE Title 59 60 Top View 1 2 (800) 222-9323 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved 3 4 Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 RTC_TIP.SCH Date: Friday, December 04, 1998 Sheet 5 24 of 26 1 2 3 4 5 PC KEYBOARD AND MOUSE INTERFACE VCC R145 470 KEYBOARD INHIBIT FUNCTION A A KBINHIBIT R146 *2.2K VCC VCC R171 4.7K U78A R172 4.7K F2 FUSE--0.5A 1 B 2 L8 VCC FB 3 R174 1K C157 0.1uF RSTDRV# 5 IORJ XBUSCSJ IOWJ IORJ XBUSCSJ IOWJ 9 7 11 SA2 8 10 28 6 GA2 GA3 GA4 GA5 GA6 GA7 GA8 GA9 14 15 16 17 18 19 20 21 74F06 7 8 C159 47pF C160 0.1uF OSC T0 T1 P10 P11 P12 P13 P14 P15 P16 P17 RESET# RD# CS# WR# P20 P21 P22 P23 P24 P25 P26 P27 EA A0 PROG SS# D0 D1 D2 D3 D4 D5 D6 D7 NC1 NC2 NC3 NC4 NC5 GA[2..9] M5042 SYNC KKDATA MMDATA 30 31 32 33 35 36 37 38 24 25 26 27 39 40 41 42 1 3 12 23 34 GND GND MOUSE_CON AMP 750329-2 44 29 VCC VCC 2 43 GND 4 RSTDRV# GA[2..9] M_CLK1 1 2 3 4 5 6 VCC VCC KBINHIBIT MDATA MCLK IRQ1 IRQ12 KCLK KDATA C VCC R44 4.7K R45 4.7K IRQ1 IRQ12 F1 U78C 5 6 KKCLK L2 FB FUSE--0.5A 74F06 U78D 9 J1 8 KKDATA KCLK1 KDATA1 FB L1 1 2 3 4 5 KBVCC 74F06 13 C28 47pF C14 47pF 6 7 C1 22 KBSS# U79 ATCLK SA2 MVCC MMCLK 4 C158 47pF KKCLK MMCLK C 1 2 3 4 5 6 R175 10K C156 0.1uF ATCLK MDATA1 L9 U78B VCC R173 1K B J11 FB MMDATA 74F06 0.1uF KYBD CONN AMP 212044-1 D EDGE OF BOARD (COMPONENT SIDE) 1 4 (COMPONENT SIDE) 7 6 2 5 3 7 5-Pin Din (PINS 6 AND 7 GROUND THE METAL SHELL) 5 3 6-Pin Mini-Din 1 2 6 8 4 U78E 11 E KEYBOARD CONNECTOR 3 5 D EDGE OF BOARD 10 74F06 U78F MOUSE CONNECTOR 13 6 1 5 4 4 2 74F06 3 2 (C) Advanced Micro Devices, Inc. 1 (800) 222-9323 E 12 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 KEYBOARD.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 25 of 26 1 2 3 4 5 SOCKET1 Am486 MICROPROCESSOR (PIN #)-PIN DESIGNATION (PIN SIDE VIEW) (1)-D20 (18)-D19 (35)-D11 (52)-D9 (59)-GND (65)-DP1 (71)-GND (77)-GND (83)-INC (89)-GND (95)-GND (101)-GND (107)-D2 (113)-D0 (119)-A31 (136)-A28 (153)-A27 (2)-D22 (19)-D21 (36)-D18 (53)-D13 (60)-VCC (66)-D8 (72)-VCC (78)-D3 (84)-D5 (90)-VCC (96)-D6 (102)-VCC (108)-D1 (114)-A29 (120)-GND (137)-A25 (154)-A26 (3)-TCK (20)-GND (37)-CLK (54)-D17 (61)-D10 (67)-D15 (73)-D12 (79)-DP2 (85)-D16 (91)-D14 (97)-D7 (103)-D4 (109)-DP0 (115)-A30 (121)-A17 (138)-VCC (155)-A23 (4)-D23 (21)-GND (38)-VCC (55)-SKT1_NC (122)-A19 (139)-GND (156)-VOLDET (5)-DP3 (22)-GND (39)-VCC (123)-A21 (140)-A18 (157)-A14 (6)-D24 (23)-D25 (40)-D27 (124)-A24 (141)-VCC (158)-GND (7)-GND (24)-VCC (41)-D26 (125)-A22 (142)-A15 (159)-A12 (8)-D29 (25)-D31 (42)-D28 (126)-A20 (143)-VCC (160)-GND (9)-GND (26)-VCC (43)-D30 (127)-A16 (144)-VCC (161)-GND (10)-INV (27)-SMI# (44)-SRESET (128)-A13 (145)-VCC (162)-GND (11)-GND (28)-VCC (45)-UP# (129)-A9 (146)-VCC (163)-GND (12)-HITM# (29)-CACHE# (46)-SMIACT# (130)-A5 (147)-A11 (164)-GND (13)-INC (30)-WB/WT# (47)-INC (131)-A7 (148)-A8 (165)-A10 (14)-TDI (31)-TMS (48)-FERR# (132)-A2 (149)-VCC (166)-GND (15)-IGNEE# (32)-NMI (49)-FLUSH# (56)-A20M# (62)-HOLD (68)-KEN# (74)-STPCLK# (80)-BRDY# (86)-BE2# (92)-BE0# (98)-PWT (104)-D/C# (110)-LOCK# (116)-HLDA (133)-BREQ (150)-A3 (167)-A6 (16)-INTR (33)-TDO (50)-RESET (57)-BS8# (63)-VCC (69)-RDY# (75)-VCC (81)-VCC (87)-BE1# (93)-VCC (99)-VCC (105)-VCC (111)-M/IO# (117)-VCC (134)-PLOCK# (151)-BLAST# (168)-A4 (17)-AHOLD (34)-EADS# (51)-BS16# (58)-BOFF# (64)-GND (70)-BE3# (76)-GND (82)-GND (88)-PCD (94)-GND (100)-GND (106)-GND (112)-W/R# (118)-GND (135)-PCHK# (152)-CLKMUL (169)-ADS# A A Am486 MICROPROCESSOR PIN SIDE VIEW B B C C SOCKET 1 1 153 153 1 D D 169 17 17 COMPONENT SIDE VIEW 169 SOLDER SIDE VIEW (C) Advanced Micro Devices, Inc. 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Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Title Size Am486 MICROPROCESSOR PCI CUSTOMER DEVELOPMENT PLATFORM Document Number Rev 2.1 CPU_PINOUT.SCH Date: Friday, December 04, 1998 1 2 3 4 Sheet 5 26 of 26 Index Numerics 25-MHz system clock, 33-MHz system clock, B 2-35 2-36 A A17, boot address, 2-6, 2-21, A-1 A18, boot address, 2-6, 2-21, A-1 Am486 microprocessor block diagram, 2-10 overview, 2-8 Am486 microprocessor PCI customer development platform analyzer headers, 2-15 block diagram, 2-4 damage, avoiding, 1-2 default settings, A-1 documentation, xvii features overview, xiii installation requirements, 1-3 installing, 1-4 jumper summary, 2-6, A-1 layout diagram, 2-5 overview diagram, xi, 2-3 purpose, xi restrictions, 2-7 troubleshooting, 1-8 Am486DX2-66 microprocessor, 2-35 Am486DX4-100 microprocessor, 2-36 Am486DX5-133 microprocessor, 2-36 analyzer headers, 2-15 bill of materials, B-2 BOM See bill of materials. boot ROM limitations, 2-7 socket, 2-21 C cable, diskette drive, 1-4 cache memory and EIP Flash memory, 2-25 Level-2 cache, 2-20 chipset description, 2-11 limitations, 2-7 CLKCTL signal, 2-14 CLKMUL signal, 2-35, 2-36 CLKPU2 signal, 2-35, 2-36 clock multiplier, 2-35, 2-36 CMOS, problems, 1-8 CMPSTJ signal, 2-35 CodeKit software, iii configuration, PCI, 2-11 conventions, notational, xix core logic chipset, 2-11 CPU power, adjusting, 2-32 CPUV1 signal, 2-6, A-1 CPUV2 signal, 2-6, A-1 Am486® Microprocessor PCI Customer Development Platform Index-1 CPUV3 signal, 2-6, A-1 CPUVCC3, 2-6, A-1 F D debugging monitor, 2-34 support, 2-15 defaults for jumpers and switches, A-1 development support, 2-15 diskette connecting drive, 1-4 starting from, 1-6 DMA controller, 2-12 documentation conventions, xix description of, xvii manual contents, xvii reference material, xviii support, iii DRAM limit without buffering, 2-7 speed limit with EIP, 2-7 using, 2-20 drive See IDE hard drive or floppy disk drive. DS1685 real-time clock, 2-27 G GND connectors, 2-33 ground wire, 2-33 H hard drive, IDE See IDE hard drive. headers, analyzer, 2-15 heat sink, CPU, 1-5, 1-6 hexadecimal display, 2-17 I E EEPROM, serial, 2-13, 2-14 ENRTC signal, 2-35 errors, 1-8 Ethernet controller, 2-13 execute-in-place (EIP) Flash memory, EXTSMI signal, 2-34 Index-2 fan heat sink, 1-5, 1-6 Flash memory in DRAM space, 2-25 ISA, 2-23 limitations, 2-7 floppy disk drive, 2-30 starting from, 1-6 frequency multiplier, 2-35 2-25 IBCSTJ signal, 2-36 IDE hard drive connection for, 2-31 starting from, 1-7 IDSEL signal, 2-11 in-circuit emulator compatibility, infrared support See IrDA interface. 2-17 Am486® Microprocessor PCI Customer Development Platform User’s Manual installing customer development platform, 1-4 requirements, 1-3 troubleshooting, 1-8 interrupt controller, chipset function, 2-12 interrupt signals DMA channel limitations, 2-7 PCI, 2-19 TIP interface, 2-18 IrDA interface Super I/O, 2-29 ISA bus, 2-28 J J1 connector, 1-5 J2 connector, 1-5 J3 connector, 1-5 J4 connector, 2-30 J5 connector, 1-5, 2-31 J6 connector, 1-4, 2-30 J7 connector, 2-31 J8 connector, 2-29 J9 connector, 2-29 JP2 jumper, 2-6, A-1 JP29 test header, 2-17 JP3 jumper, 2-6, A-1 JP30 test header, 2-17 JP31 test header, 2-17 JP32 jumper, 2-6, 2-21, JP33 jumper, 2-6, 2-21, JP34 connector, 2-34 JP4 jumper, 2-6, A-1 JTAG port, 2-15 jumpers defaults, A-1 summary, 2-6, A-1 K KBINHIBIT signal, 2-36 keyboard connecting, 1-5 connector, 2-31 controller enable, 2-36 error, 1-9 L LEDs, problems with, 1-8 Level-2 cache memory, 2-20 limitations, 2-7 LinkBus, 2-12 literature support, iii locations, part, 2-5 logic analyzer headers, 2-15 M 2-22, A-1 2-22, A-1 M1487 southbridge chip, 2-12 M1489 northbridge chip, 2-11 MACH device, 2-15 memory boot ROM, 2-21 cache, 2-20 DRAM, 2-20 EIP Flash memory, 2-25 Flash memory, 2-23 map, 2-24 problems, 1-8 serial EEPROM, 2-13, 2-14 monitor, debugging, 2-34 mouse, 2-31 Am486® Microprocessor PCI Customer Development Platform Index-3 N NMI signal, 2-34 nonvolatile data, 2-14 northbridge chip, 2-11 P P36 analyzer header, 2-16 P38 analyzer header, 2-16 P39 analyzer header, 2-16 P40 analyzer header, 2-16 P41 analyzer header, 2-16 P42 analyzer header, 2-16 P43 analyzer header, 2-16 P44 analyzer header, 2-16 P45 analyzer header, 2-16 P46 analyzer header, 2-16 P47 analyzer header, 2-16 parallel port, 2-30 part locations, 2-5 PCI bus arbiter, 2-12 configuration addressing, 2-11 description, 2-19 interrupt signals, 2-19 limitations, 2-7 peripherals needed to use board, 1-3 PGNTJ0 signal, 2-17 PGNTJ1 signal, 2-17 PGNTJ2 signal, 2-17 pin-grid-array (PGA) socket, 2-17 port 680h display, 2-17 port 80h display, 1-6, 1-7, 2-17 ports See serial ports or parallel port. POST (Power-On Self-Test codes), 1-6, 1-7 power management not implemented, 2-7, 2-14 Index-4 power supply connecting, 1-5 using, 2-33 PREQJ0 signal, 2-17 PREQJ1 signal, 2-17 PREQJ2 signal, 2-17 programmable interval timer, PWG signal, 2-34 2-12 R R11 resistor, 2-35 R145 resistor, 2-36 R146 resistor, 2-36 R148 resistor, 2-36 R170 resistor, 2-36 R176 resistor, 2-36 R58 resistor, 2-35 R59 resistor, 2-35 R70 resistor, 2-35 R71 resistor, 2-35 R93 resistor, 2-35 real-time clock (RTC), 2-27 RESET signal, 2-34 resistor options, 2-35 ROM boot, 2-21 EIP Flash memory, 2-25 ISA Flash memory, 2-23 S schematics, B-10 serial EEPROM, 2-13, 2-14 serial ports connector, 2-29 Super I/O, 2-29 SL1 ISA slot, 1-5, 2-28 SL2 ISA slot, 1-5, 2-28 SLT1 PCI slot, 1-5 SLT2 PCI slot, 1-5 Am486® Microprocessor PCI Customer Development Platform User’s Manual SMI signal, 2-34 southbridge chip, 2-12 super I/O IrDA interface, 2-29 overview, 2-28 serial ports, 2-29 support, iii SW1 switch, 2-34 SW2 switch, 2-34 SW3 switch, 2-34 switch summary, 2-34 system clock speed, 2-35, W WWW support, iii Y year-2000 (Y2K), 2-36 2-27 Z zero-insertion-force (ZIF) socket, T 2-17 technical support, iii test interface port (TIP), 2-18 test points, PCI, 2-17 third-party support, iii timer, chipset function, 2-12 TIP board, 2-18 TURBO signal, 2-35 U U25 ZIF socket, 2-8 U44 IrDA module, 2-29 U54 serial EEPROM, 2-13 U81 serial EEPROM, 2-14 V VGA cable, connecting, 1-5 card, connecting, 1-5 monitor problems, 1-8 voltage limitations, 2-7 Am486® Microprocessor PCI Customer Development Platform Index-5 Index-6 Am486® Microprocessor PCI Customer Development Platform User’s Manual