Download TPU TIME PROCESSOR UNIT REFERENCE MANUAL

4.1 TPU Control Store Organization
The TPU control store consists of a contiguous 2-Kbyte block of micro-ROM arranged
as 512 long words. Refer to Figure 4-2.
The TPU2 includes a 4-Kbyte block of micro-ROM and up to eight Kbytes of additional
address space. Three configurations of address space are possible. Refer to Figure
4-3.
Emulation mode memory is partitioned into a microcode segment and an entry point
segment. Each TPU function has 16 word-sized entry points associated with it; there
are a total of 128 long words for all 16 possible functions. TPU2 memory can contain
multiple entry point segments. Entry point segments are arranged in order by function
number (0 to 15). Function numbers are assigned to functions as part of the assembly
process. Each entry point includes a vector that forces function execution to begin at
a known address. The entry point used at the start of each channel service depends
on several conditions.
It is often neither possible nor necessary to fit 16 functions into the control store. When
this is the case, the memory area occupied by entry points of unused function numbers
is available for extra microcode space. Begin function number assignment with 15 and
work down, so that any unused entry point segment is contiguous with the normal microcode segment. This is the most efficient use of the available space. Figure 4-4
shows unused entry points being used for additional opcode space.
All operations, timing, and conditions that apply to the ROM control store also apply to
the RAM when used for emulation.
4.2 Emulation Mode Memory Map
When the TPU enters emulation mode, the TPURAM is dedicated to the TPU and replaces the control store ROM. Most microcontrollers currently available with a TPU
have a full two Kbytes of TPURAM, which allows complete emulation of the control
store. Figure 4-2 shows the equivalent host CPU byte addresses that are used to load
TPURAM with TPU microcode before invoking emulation mode.
Some Motorola MCUs contain only one Kbyte of TPURAM. With these devices, it is
only possible to emulate half the TPU control store. Figure 4-5 shows emulation memory map and equivalent TPURAM addresses for these devices.
Some Motorola microcontrollers contain TPURAM modules that are larger than the
TPU microcode control store. In these devices, only a portion of the TPURAM will be
used for TPU emulation, but the entire TPURAM will be removed from the CPU memory map during emulation. The emulation mode memory map will never be larger than
the control store map.
MOTOROLA
4-2
TPU EMULATION MODE
TPU
REFERENCE MANUAL