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User’s Manual SuperH™ Family E10A Emulator Additional Document for User’s Manual SH7294 E10A HS7294KCM02HE Renesas Microcomputer Development Environment System SuperH™ Family / SH7200 Series Specific Guide for the SH7294 E10A Emulator Rev.1.0 2003.07 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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Contents Section 1 Connecting the Emulator with the User System ................................1 1.1 1.2 1.3 1.4 1.5 Components of the Emulator ............................................................................................ 1 Connecting the E10A Emulator with the User System ..................................................... 4 Installing the H-UDI Port Connector on the User System ................................................ 5 Pin Arrangement of the H-UDI Port Connector................................................................ 5 Recommended Circuit between the H-UDI Port Connector and the MPU ....................... 8 1.5.1 Recommended Circuit (36-Pin Type) .................................................................. 8 1.5.2 Recommended Circuit (14-Pin Type) .................................................................. 10 Section 2 Specifications of the SH7294 E10A Emulator’s Software ................13 2.1 2.2 Differences between the SH7294 and the Emulator ......................................................... 13 Specific Functions for the SH7294 E10A Emulator ......................................................... 17 2.2.1 Emulator Driver Selection ................................................................................... 17 2.2.2 Break Condition Functions .................................................................................. 18 2.2.3 Trace Functions.................................................................................................... 19 2.2.4 Notes on Using the JTAG Clock (TCK) and AUD Clock (AUDCK) ................. 25 2.2.5 Notes on Setting the [Breakpoint] Dialog Box .................................................... 25 2.2.6 Notes on Setting the [Break Condition] Dialog Box and the BREAKCONDITION_ SET Command ........................................................ 27 2.2.7 Notes on Setting the UBC_MODE Command..................................................... 27 2.2.8 Performance Measurement Function ................................................................... 28 2.2.9 Notes on U Standby State .................................................................................... 33 i ii Section 1 Connecting the Emulator with the User System 1.1 Components of the Emulator The SH7294 E10A emulator supports the SH7294. Table 1.1 lists the components of the emulator. 1 Table 1.1 Components of the Emulator (HS7294KCM01H, HS7294KCM02H, HS7294KCI01H, or HS7294KCI02H) Classification Component Hardware Card emulator Appearance Quantity 1 PC PC Card (PCMCIA) or (PCI) Software User system interface cable 1 Ferrite core (connected with the user interface cable) 1 Remarks HS7294KCM01H (PCMCIA: 14-pin type): Depth: 85.6 mm, Width: 54.0 mm, Height: 5.0 mm, Mass: 27.0 g HS7294KCM02H (PCMCIA: 36-pin type): Depth: 85.6 mm, Width: 54.0 mm, Height: 5.0 mm, Mass: 28.0 g HS7294KCI01H (PCI: 14-pin type): Depth: 122.0 mm, Width: 96.0 mm, Mass: 80.0 g HS7294KCI02H (PCI: 36-pin type): Depth: 122.0 mm, Width: 96.0 mm, Mass: 90.0 g HS7294KCM01H (PCMCIA: 14-pin type): Length: 80 cm, Mass: 45.0 g HS7294KCM02H (PCMCIA: 36-pin type): Length: 30 cm, Mass: 55.0 g HS7294KCI01H (PCI: 14-pin type): Length: 150 cm, Mass: 86.0 g HS7294KCI02H (PCI: 36-pin type): Length: 80 cm, Mass: 69.0 g Countermeasure for EMI* (only for HS7294KCM02H and HS7294KCI02H) SH7294 E10A 1 HS7294KCM01SR, emulator setup program, SH Family E10A HS0005KCM01HJ, Emulator User’s HS0005KCM01HE, Manual, and Specific Guide to the HS7294KCM02HJ, and SH7294 E10A HS7294KCM02HE Emulator (provided on a CD-R) Note: The EMI is an abbreviation of the Electrical Magnetic Interference. 2 For EMI countermeasure, use the ferrite core by connecting the user interface cable. When the user interface cable is connected with the emulator or user system, connect the ferrite core in the user system as shown in figure 1.1. Host computer (PC with PC card slot) User system E10A emulator Insert PC Card Emulator H-UDI Micro Computer Development System PC Card HITACHI User system connector Ferrite core PC card slot User interface cable Figure 1.1 Connecting Ferrite Core 3 1.2 Connecting the E10A Emulator with the User System To connect the E10A emulator (hereinafter referred to as the emulator), the H-UDI port connector must be installed on the user system to connect the user system interface cable. When designing the user system, refer to the recommended circuit between the H-UDI port connector and the MCU. In addition, read the E10A emulator user's manual and hardware manual for the related device. Table 1.2 shows the type number of the E10A emulator, the corresponding connector type, and the use of AUD function. Table 1.2 Type Number, AUD Function, and Connector Type Type Number Connector AUD Function HS7294KCM02H, HS7294KCI02H 36-pin connector Available HS7294KCM01H, HS7294KCI01H 14-pin connector Not available The H-UDI port connector has the 36-pin and 14-pin types as described below. Use them according to the purpose of the usage. 1. 36-pin type (with AUD function) The AUD trace function is supported. A large amount of trace information can be acquired in realtime. The window trace function is also supported for acquiring memory access in the specified range (memory access address or memory access data) by tracing. 2. 14-pin type (without AUD function) The AUD trace function cannot be used because only the H-UDI function is supported. For tracing, only the internal trace function is supported. Since the 14-pin type connector is smaller than the 36-pin type (1/2.5), the area where the connector is installed on the user system can be reduced. 4 1.3 Installing the H-UDI Port Connector on the User System Table 1.3 shows the recommended H-UDI port connectors for the emulator. Table 1.3 Recommended H-UDI Port Connectors Connector Type Number Manufacturer Specifications 36-pin connector DX10M-36S Hirose Electric Co., Ltd. Screw type Lock-pin type DX10M-36SE, DX10G1M-36SE 14-pin connector 2514-6002 Minnesota Mining & Manufacturing Ltd. 14-pin straight type Note: When the 36-pin connector is used, do not connect any components under the H-UDI connector. When the 14-pin connector is used, do not install any components within 3 mm of the H-UDI port connector. 1.4 Pin Arrangement of the H-UDI Port Connector Figures 1.2 and 1.3 show the pin arrangement of the 36-pin and 14-pin H-UDI port connectors, respectively. Note: Note that the pin number assignment of the H-UDI port connector shown below differs from that of the connector manufacturer. 5 Pin No. Signal Input/ Output *1 1 AUDCK Output 2 GND 3 AUDATA 0 4 GND 5 AUDATA 1 6 GND 7 AUDATA 2 8 GND 9 AUDATA 3 10 GND Output Output Output Output 11*2 /AUDSYNC Output Note SH7294 Pin No . M18 J16 K18 K16 Pin No. Signal Input/ Output *1 19 TMS Input F4 20 GND 21*2 /TRST Input E2 22 GND 23 TDI Input D2 24 GND 25 TDO Output E1 26 GND Output G4 Output H18 U-standby detection Output H15 User reset 27*2 /ASEBRKAK L18 J18 28 GND 29*2 /CA 12 GND 30 GND 13 NC 31*2 /RESETP 14 GND 32 GND 15 NC 33*3 GND 16 GND 34 17 TCK 18 Input C2 GND SH7294 Pin No . Note Output GND 35 NC 36 GND Notes: 1. Input to or output from the user system. 2. The slash (/) means that the signal is active-low. 3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected. H-UDI port connector (top view) Edge of the board (connected to the connector) 4 +0.2 0 +0.1 0 2 0.7 36 1 3 9.0 1.905 1.1 4.5 2.8 (Pin 1 mark) 35 1.27 4.09 M2.6 x 0.45 H-UDI port connector (front view) 4.8 H-UDI port connector (top view) 3.9 37.61 43.51 : Pattern inhibited area 0.3 9.0 21.59 Unit: mm Figure 1.2 Pin Arrangement of the H-UDI Port Connector (36 Pins) 6 Pin No. Signal Input/ Output* 1 SH7294 Pin No. 1 TCK Input C2 2*2 /TRST Input E2 3 TDO Output E1 4*2 /ASEBRKAK Output G4 5 TMS Input F4 6 TDI Input D2 7* 2 /RESETP Output H15 11 /CA Output H18 Note 8 to 10 GND 12 to 13 14* 3 GND Output Notes: 1. Input to or output from the user system. 2. The slash (/) means that the signal is active-low. 3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected. Pin 1 mark H-UDI port connector (top view) 25.0 23.0 6 x 2.54 = 15.24 (2.54) H-UDI port connector (top view) 0.45 Pin 1 mark Unit: mm Figure 1.3 Pin Arrangement of the H-UDI Port Connector (14 Pins) 7 1.5 Recommended Circuit between the H-UDI Port Connector and the MPU 1.5.1 Recommended Circuit (36-Pin Type) Figure 1.4 shows a recommended circuit for connection between the H-UDI port connector (36 pins) and the MPU. Notes: 1. Do not connect anything to the N.C. pin of the H-UDI port connector. 8 2. Note that the processing of the /ASEMD0 pin differs depending on whether the emulator is used or not. In addition, the /ASEMD0 pin must be switched on the board because it is not controlled by the emulator. (1) When the emulator is used: /ASEMD0 = low (ASE mode) (2) When the emulator is not used: /ASEMD0 = high (normal mode) 3. The /CA and reset signals in the user system are input to the /CA and /RESETP pins of the MPU. Connect these signals to the H-UDI port connector as the output from the user system. 4. When a joined resistance is used for pull-up, it may be affected by a noise. Separate TCK from other resistances. 5. When the emulator is used, the /CA pin must be pulled up by a resistance of several kilo-ohms whether the U-standby function is used or not. 6. The /TRST pin must be at the low level for a certain period when the power is supplied whether the H-UDI is used or not. Reduce the power supplied to the /TRST pin by pulling the pin up by a resistance of several kilo-ohms and setting HIZB9=0 in the HIZCRB register after a reset. 7. The pattern between the H-UDI connector and the MPU must be as short as possible. Do not connect the signal lines to other components on the board. 8. The resistance values shown in figure 1.4 are recommended. 9. For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related device. VccQ (3.3 V) VccQ (3.3 V) H-UDI port connector (36-pin type) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 GND GND AUDCK AUDATA0 GND AUDATA1 GND AUDATA2 GND AUDATA3 GND AUDSYNC GND N.C. GND N.C. GND TCK GND TMS GND TRST GND TDI GND TDO GND ASEBRKAK GND CA GND RESET GND GND GND N.C. SH7294 4.7 kΩ 4.7 kΩ 1 AUDCK 3 AUDATA0 5 AUDATA1 7 AUDATA2 9 AUDATA3 11 AUDSYNC 13 15 17 TCK 19 TMS 21 TRST 23 TDI 25 TDO 27 ASEBRKAK 29 CA 31 33 35 RESETP /CA signal Reset signal 1 kΩ ASEMD0 Figure 1.4 Recommended Circuit for Connection between the H-UDI Port Connector and MPU (36-Pin Type) 9 1.5.2 Recommended Circuit (14-Pin Type) Figure 1.5 shows a recommended circuit for connection between the H-UDI port connector (14 pins) and the MPU. Notes: 1. Do not connect anything to the N.C. pin of the H-UDI port connector. 10 2. Note that the processing of the /ASEMD0 pin differs depending on whether the emulator is used or not. In addition, the /ASEMD0 pin must be switched on the board because it is not controlled by the emulator. (1) When the emulator is used: /ASEMD0 = low (ASE mode) (2) When the emulator is not used: /ASEMD0 = high (normal mode) 3. The /CA and reset signals in the user system are input to the /CA and /RESETP pins of the MPU. Connect these signals to the H-UDI port connector as the output from the user system. 4. When a joined resistance is used for pull-up, it may be affected by a noise. Separate TCK from other resistances. 5. When the emulator is used, the /CA pin must be pulled up by a resistance of several kilo-ohms whether the U-standby function is used or not. 6. The /TRST pin must be at the low level for a certain period when the power is supplied whether the H-UDI is used or not. Reduce the power supplied to the /TRST pin by pulling the pin up by a resistance of several kilo-ohms and setting HIZB9=0 in the HIZCRB register after a reset. 7. The pattern between the H-UDI connector and the MPU must be as short as possible. Do not connect the signal lines to other components on the board. 8. The resistance values shown in figure 1.5 are recommended. 9. For the pin processing in cases where the emulator is not used, refer to the hardware manual of the related device. VccQ (3.3 V) VccQ (3.3 V) 4.7 kΩ H-UDI port connector (14-pin type) 8 9 GND GND 10 GND TCK TRST 13 GND GND 14 GND 1 TRST TDO TDO TMS TDI RESET SH7294 TCK 2 3 ASEBRKAK 12 4.7 kΩ 4 ASEBRKAK 5 TMS 6 TDI 7 RESETP 11 CA CA Reset signal /CA signal 1 kΩ ASEMD0 Figure 1.5 Recommended Circuit for Connection between the H-UDI Port Connector and MPU (14-Pin Type) 11 12 Section 2 Specifications of the SH7294 E10A Emulator’s Software 2.1 Differences between the SH7294 and the Emulator 1. When the emulator system is initiated, it initializes the general registers and part of the control registers as shown in table 2.1. The initial values of the actual SH7294 registers are undefined. Table 2.1 Register Initial Values at Emulator Power-On Register Emulator at Power-on R0 to R14 H'00000000 R15 (SP) H'A0000000 R0_BANK to R7_BANK H'00000000 PC H'A0000000 SR H'700000F0 GBR H'00000000 VBR H'00000000 MACH H'00000000 MACL H'00000000 PR H'00000000 SPC H'00000000 SSR H'000000F0 RS H'00000000 RE H'00000000 MOD H'00000000 A0G, A1G H'00000000 A0, A1 H'00000000 X0, X1 H'00000000 Y0, Y1 H'00000000 M0, M1 H'00000000 DSR H'00000000 2. The emulator uses the H-UDI; do not access the H-UDI. 13 3. Low-Power States (Sleep, Software Standby, Module Standby, and U Standby) For low-power consumption, the SH7294 has sleep, software standby, module standby, and U standby states. The sleep, software standby, and module standby states are switched using the SLEEP instruction. When the emulator is used, only the sleep state can be cleared with either the normal clearing function or with the [Stop] button, and a break will occur. For the U standby state, refer to section 2.2.9, Notes on U Standby State. Note: The memory must not be accessed or modified in sleep state. 4. Reset Signals The SH7294 reset signals are only valid during emulation started with clicking the GO or STEP-type button. If these signals are input from the user system in command input wait state, they are not sent to the SH7294. Note: Do not break the user program when the /RESETP and /WAIT signals are being low. A TIMEOUT error will occur. If the /WAIT signal is fixed to low during break, a TIMEOUT error will occur at memory access. 5. Direct Memory Access Controller (DMAC) The DMAC operates even when the emulator is used. When a data transfer request is generated, the DMAC executes DMA transfer. 6. Memory Access during User Program Execution When a memory is accessed from the memory window, etc. during user program execution, the user program is resumed after it has stopped in the E10A emulator to access the memory. Therefore, realtime emulation cannot be performed. The stopping time of the user program is as follows: Environment: ® Host computer: 650 MHz (Pentium III) SH7294: 60 MHz (CPU clock) JTAG clock: 3.75 MHz When a one-byte memory is read from the command-line window, the stopping time will be about 20 ms. 7. Memory Access during User Program Break The emulator can download the program for the flash memory area. Other memory write operations are enabled for the RAM area. Therefore, an operation such as memory write or BREAKPOINT should be set only for the RAM area. 14 8. Cache Operation during User Program Break When cache is enabled, the emulator accesses the memory by the following methods: • At memory write: Writes through the cache, then writes to the memory. • At memory read: Does not change the cache write mode that has been set. Therefore, when memory read or write is performed during user program break, the cache state will be changed. 9. Port G The AUD and H-UDI pins are multiplexed as shown in table 2.2. Table 2.2 Multiplexed Functions Port Function 1 G Function 2 1 /ASEBRKAK (H-UDI) 2 /AUDSYNC (AUD) 2 AUDATA3 (AUD) 2 AUDATA2 (AUD) 2 AUDATA1 (AUD) 2 AUDATA0 (AUD) PTG5 input/output (port) * G PTG4 input/output (port) * G PTG3 input/output (port) * G PTG2 input/output (port) * G PTG1 input/output (port) * G PTG0 input/output (port) * Notes: 1. PTG5 cannot be used when the E10A emulator is used. 2. Function 1 can be used when the AUD pins of the device are not connected to the SH7294 E10A emulator. Note that the SH7294 E10A setting should be made so that function 2 would be forcibly used during activation. If function 1 is to be used, the setting should be made by the pin function controller. 10. UBC When [User] is specified in the [UBC mode] list box in the [Configuration] dialog box, the UBC can be used in the user program. Do not use the UBC in the user program as it is used by the E10A emulator when [EML] is specified in the [UBC mode] list box in the [Configuration] dialog box. 11. MFI Boot Mode When the MFI boot mode is used, be sure to allocate the boot program from the top of MFRAM. 12. Using RWDT At power-on reset, the operation of RWDT is enabled. When RWDT is not used, be sure to disable the operation of RWDT at the top of the user-reset program. 15 13. Memory Access during Break In the enabled MMU, when a memory is accessed and a TLB error occurs during break, it can be selected whether the TLB exception is controlled or the program jumps to the user exception handler in [TLB Mode] in the [Configuration] dialog box. When [TLB miss exception is enable] is selected, a Communication Timeout error will occur if the TLB exception handler does not operate correctly. When [TLB miss exception is disable] is selected, the program does not jump to the TLB exception handler even if a TLB exception occurs. Therefore, if the TLB exception handler does not operate correctly, a Communication Timeout error will not occur but the memory contents may not be correctly displayed. 14. Loading Sessions Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading sessions. Thus the TCK value will be as follows: • When HS7294KCI01H or HS7294KCI02H is used: TCK = 1.031 MHz • When HS7294KCM01H or HS7294KCM02H is used: TCK = 0.937 MHz 15. [IO] window • Display and modification Do not change values of the User Break Controller because it is used by the emulator. For each watchdog timer and RCLK watchdog timer register, there are two registers to be separately used for write and read operations. Table 2.3 Watchdog Timer Register Register Name Usage Register WTCSR(W) Write Watchdog timer control/status register WTCNT(W) Write Watchdog timer counter WTCSR(R) Read Watchdog timer control/status register WTCNT(R) Read Watchdog timer counter RWTCSR(W) Write RCLK watchdog timer control/status register RWTCNT(W) Write RCLK watchdog timer counter RWTCSR(R) Read RCLK watchdog timer control/status register RWTCNT(R) Read RCLK watchdog timer counter • The watchdog timer operates only when the user program is executed. Do not change the value of the frequency change register in the [IO] window or [Memory] window. 16 • The internal I/O registers can be accessed from the [IO] window. However, note the following when accessing the SDMR register of the bus-state controller. Before accessing the SDMR register, specify addresses to be accessed in the I/O-register definition file (SH7294.IO) and then activate the HEW. For details on I/O-register definition file, refer to the Hitachi Debugging Interface User's Manual. Note that, however, the E10A emulator does not support the bit-field function described in the Hitachi Debugging Interface User's Manual. • Verify In the [IO] window, the verify function of the input value is disabled. 16. Illegal Instructions If illegal instructions are executed by STEP-type commands, the emulator cannot go to the next program counter. 2.2 Specific Functions for the SH7294 E10A Emulator The SH7294 E10A emulator does not support the following function: • Profiler function 2.2.1 Emulator Driver Selection Table 2.4 shows drivers which are selected in the [E10A Driver Details] dialog box. Table 2.4 Type Number and Driver Type Number Driver HS7294KCM01H E10A PC Card Driver 7 HS7294KCM02H E10A PC Card Driver 8 HS7294KCI01H E10A PCI Card Driver 7 HS7294KCI02H E10A PCI Card Driver 8 17 2.2.2 Break Condition Functions In addition to BREAKPOINT functions, the emulator has Break Condition functions. Three types of conditions can be set under Break Condition 1, 2, 3. Table 2.5 lists these conditions of Break Condition. Table 2.5 Types of Break Conditions Break Condition Type Description Address bus condition (Address) Breaks when the SH7294 address bus value or the program counter value matches the specified value. Data bus condition (Data) Breaks when the SH7294 data bus value matches the specified value. Byte, word, or longword can be specified as the access data size. X-Bus or Y-Bus condition (Address and data) Breaks when the X-Bus or Y-Bus address bus or data bus matches the specified value. Bus state condition (Bus State) There are two bus state condition settings: Read/Write condition: Breaks when the SH7294 RD or RDWR signal level matches the specified condition. Bus state condition: Breaks when the operating state in an SH7294 bus cycle matches the specified condition. Types of buses that can be specified are listed below. • L-bus (CPU-ALL): Indicates an instruction fetch and data access, including a hit to the cache memory. • L-bus (CPU-Data): Indicates a data access by the CPU, including a hit to the cache memory. • I-bus (CPU.DMA): Indicates a CPU cycle when the cache memory is not hit, and a data access by the DMA. Internal I/O break condition Breaks when the SH7294 accesses the internal I/O. LDTLB instruction break condition Breaks when the SH7294 executes the LDTLB instruction. Count Breaks when the conditions set are satisfied the specified number of times. Note: When U-RAM or X/Y-RAM is accessed from the P0 space, the I-bus must be selected, and when accessed from the P2 space, the L-bus must be selected. When cache fill cycle is acquired, the I-bus must be selected. 18 Table 2.6 lists the combinations of conditions that can be set under Break Condition 1, 2, 3. Table 2.6 Dialog Boxes for Setting Break Conditions Type Dialog Box Address Bus Condition (Address) Data Bus ASID Condition Condition (Data) (ASID) Bus State Condition Count Internal LDTLB (Bus Condition I/O Instruction Status) (Count) Break Break [Break Condition 1] dialog box O O O O O X X [Break Condition 2] dialog box O X O O X X X [Break Condition 3] dialog box X X X X X O O Note: O: Can be set in the dialog box. X: Cannot be set in the dialog box. 2.2.3 Trace Functions The SH7294 E10A emulator supports the trace functions listed in table 2.7. Table 2.7 Trace Functions Function Internal Trace AUD Trace Branch trace Supported (eight branches) Supported Range memory access trace Not supported Supported Software trace Not supported Supported Table 2.8 shows the type numbers that the AUD function can be used. Table 2.8 Type Number and AUD Function Type Number AUD Function HS7294KCM01H, HS7294KCI01H Not supported HS7294KCM02H, HS7294KCI02H Supported 19 AUD Trace Functions: This function is operational when the AUD pin of the device is connected to the emulator. Table 2.9 shows the AUD trace acquisition mode that can be set in each trace function. Table 2.9 AUD Trace Acquisition Mode Type Mode Description Continuous trace occurs Realtime trace When the next branch occurs while the trace information is being output, the trace information being output is output but the next trace information is not output. The user program can be executed in realtime, but some trace information may be lost. Non realtime trace When the next branch occurs while the trace information is being output, the CPU stops operations until the information is output. The user program is not executed in realtime. Trace continue This function overwrites the oldest trace information to store the latest trace information. Trace stop After the trace buffer becomes full, the trace information is no longer acquired. (The user program is continuously executed.) Trace buffer full 20 To set the AUD trace acquisition mode, click the [Trace] window with the right mouse button and select [Setting] from the pop-up menu to display the [Acquisition] dialog box. The AUD trace acquisition mode can be set in the [AUD mode1] or [AUD mode2] group box in the [Trace mode] page of the [Acquisition] dialog box. Figure 2.1 [Trace mode] Page When the AUD trace function is used, select the [AUD function] radio button in the [Trace type] group box of the [Trace mode] page. 21 (a) Branch Trace Function The branch source and destination addresses and their source lines are displayed. Branch trace can be acquired by selecting the [Branch trace] check box in the [AUD function] group box of the [Trace mode] page. The branch type can be selected in the [AUD Branch trace] page. Figure 2.2 [AUD Branch trace] Page (b) Window Trace Function Memory access in the specified range can be acquired by trace. Two memory ranges can be specified for channels A and B. The read, write, or read/write cycle can be selected as the bus cycle for trace acquisition. [Setting Method] (i) Select the [Channel A] and [Channel B] check boxes in the [AUD function] group box of the [Trace mode] page. Each channel will become valid. (ii) Open the [Window trace] page and specify the bus cycle and memory range that are to be set for each channel. 22 Figure 2.3 [Window trace] Page Notes: 1. When the [L-bus] or [I-bus] radio button is selected, the following bus cycles will be traced. • L-bus: A bus cycle generated by the CPU is acquired. A bus cycle is also acquired when the cache has been hit. • I-bus: A bus cycle generated by the CPU or DMA is acquired. A bus cycle is not acquired when the cache has been hit. The address information acquired by the Ibus is 28 bits and the upper 4 bits are displayed as ‘*’. The source cannot be displayed in the [Trace] window. When U-RAM or X/Y-RAM is accessed from the P0 space, the I-bus must be selected, and when accessed from the P2 space, the L-bus must be selected. When a cache fill cycle is acquired, I-bus must be selected. 2. Address setting when X/Y-bus is selected To trace both the X/Y-bus when the X/Y-bus is accessed at the same time, the X-bus condition must be set in channel A, and the Y-bus condition must be set in channel B. 23 (c) Software Trace Function Note: This function can be supported with SHC compiler V7.0 and later. When a specific instruction is executed, the PC value at execution and the contents of one general register are acquired by trace. Describe the Trace(x) function (x is a variable name) to be compiled and linked beforehand. For details, refer to the SHC manual. When the load module is loaded on the emulator and a valid software trace function is executed, the PC value that has executed the Trace(x) function, the general register value for x, and the source lines are displayed. To activate the software trace function, select the [Software trace] check box in the [AUD function] group box of the [Trace mode] page. Notes on AUD Trace: 1. When the trace display is performed during user program execution, the mnemonics, operands, or source is not displayed. 2. The AUD trace function outputs the differences between newly output branch source addresses and previously output branch source addresses. The window trace function outputs the differences between newly output addresses and previously output addresses. If the previous branch source address is the same as the upper 16 bits, the lower 16 bits are output. If it matches the upper 24 bits, the lower 8 bits are output. If it matches the upper 28 bits, the lower 4 bits are output. The emulator regenerates the 32-bit address from these differences and displays it in the [Trace] window. If the emulator cannot display the 32-bit address, it displays the difference from the previously displayed 32-bit address. 3. If the 32-bit address cannot be displayed, the source line is not displayed. 4. In the SH7294 E10A emulator, when multiple loops are performed to reduce the number of AUD trace displays, only the IP counts up. 5. In the SH7294 E10A emulator, the maximum number of trace display pointers is as follows: When HS7294KCM02H is used: D'8191 to -0 When HS7294KCI02H is used: D'32767 to -0 However, the maximum number of trace display pointers differs according to the AUD trace information to be output. Therefore, the above pointers cannot be always acquired. 6. The AUD trace acquisition is not available when [User] is selected in the [UBC mode] list box of the [Configuration] dialog box. In this case, close the [Trace] window. 7. Do not use the AUD full-trace mode for the VIO function. 8. If a completion-type exception occurs during exception branch acquisition, the next address to the address in which an exception occurs is acquired. 24 Internal Trace Function: This function is activated by selecting the [Internal trace] radio button in the [Trace type] group box of the [Trace mode] page. This function traces and displays the branch instructions. The branch source address and branch destination address for the eight latest branch instructions are displayed. See figure 2.1, [Trace mode] Page. Notes: 1. If an interrupt is generated at the program execution start or end, including a step execution, the emulator address may be acquired. In such a case, the following message will be displayed. Ignore this address because it is not a user program address. *** EML *** 2. If a completion-type exception occurs during exception branch acquisition, the next address to the address in which an exception occurs is acquired. 3. Trace information cannot be acquired for the following branch instructions: • The BF and BT instructions whose displacement value is 0 • Branch to H'A0000000 by reset 4. The internal trace acquisition is not available when [User] is selected in the [UBC mode] list box of the [Configuration] dialog box. In this case, close the [Trace] window. 2.2.4 Notes on Using the JTAG Clock (TCK) and AUD Clock (AUDCK) 1. Set the JTAG clock (TCK) frequency to less than the frequency of the SH7294 peripheral module clock (CKP). 2. Set the AUD clock (AUDCK) frequency to 50 MHz or below for PCMCIA and PCI cards. 2.2.5 Notes on Setting the [Breakpoint] Dialog Box 1. When an odd address is set, the next lowest even address is used. 2. A BREAKPOINT is accomplished by replacing instructions of the specified address. Accordingly, it can be set only to the internal RAM area. However, a BREAKPOINT cannot be set to the following addresses: • An area other than CS0 to CS6 and the internal RAM • An instruction in which Break Condition 2 is satisfied • A slot instruction of a delayed branch instruction • An area that can be only read by MMU 3. During step execution, a BREAKPOINT is disabled. 4. Conditions set at Break Condition 2 are disabled when an instruction to which a BREAKPOINT has been set is executed. Do not set a BREAKPOINT to an instruction in which Break Condition 2 is satisfied. 5. When execution resumes from the address where a BREAKPOINT is specified, single-step execution is performed at the address before execution resumes. Therefore, realtime operation cannot be performed. 25 6. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot instruction of a delayed branch instruction. 7. When a BREAKPOINT is set to the cacheable area, the cache block containing the BREAKPOINT address is filled immediately before and after user program execution. 8. Note on DSP repeat loop: A BREAKPOINT is equal to a branch instruction. In some DSP repeat loops, branch instructions cannot be set. For these cases, do not set BREAKPOINTs. Refer to the hardware manual for details. 9. When the [Normal] option is selected in the [Memory area] group box in the [General] page of the [Configuration] dialog box, a BREAKPOINT is set to a physical address or a virtual address according to the SH7294 MMU status during command input when the VPMAP_SET command setting is disabled. The ASID value of the SH7294 PTEH register during command input is used. When VPMAP_SET command setting is enabled, a BREAKPOINT is set to a physical address into which address translation is made according to the VP_MAP table. However, for addresses out of the range of the VP_MAP table, the address to which a BREAKPOINT is set depends on the SH7294 MMU status during command input. Even when the VP_MAP table is modified after BREAKPOINT setting, the address translated when the BREAKPOINT is set valid. 10. When the [Physical] option is selected in the [Memory area] group box in the [General] page of the [Configuration] dialog box, a BREAKPOINT is set to a physical address. A BREAKPOINT is set after disabling the SH7294 MMU upon program execution. After setting, the MMU is returned to the original state. When a break occurs at the corresponding virtual address, the cause of termination displayed in the status bar and the [Output] window is ILLEGAL INSTRUCTION, not BREAKPOINT. 11. When the [Virtual] option is selected in the [Memory area] group box in the [General] page of the [Configuration] dialog box, a BREAKPOINT is set to a virtual address. A BREAKPOINT is set after enabling the SH7294 MMU upon program execution. After setting, the MMU is returned to the original state. When an ASID value is specified, the BREAKPOINT is set to the virtual address corresponding to the ASID value. The emulator sets the BREAKPOINT after rewriting the ASID value to the specified value, and returns the ASID value to its original value after setting. When no ASID value is specified, the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input. 12. An address (physical address) to which a BREAKPOINT is set is determined when the BREAKPOINT is set. Accordingly, even if the VP_MAP table is modified after BREAKPOINT setting, the BREAKPOINT address remains unchanged. When a BREAKPOINT is satisfied with the modified address in the VP_MAP table, the cause of termination displayed in the status bar and the [Output] window is ILLEGAL INSTRUCTION, not BREAKPOINT. 13. If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area, a mark ! will be displayed in the [BP] area of the address on the [Editor] or [Disassembly] 26 window by refreshing the [Memory] window, etc. after Go execution. However, no break will occur at this address. When the program halts with the break condition, the mark ! disappears. 2.2.6 Notes on Setting the [Break Condition] Dialog Box and the BREAKCONDITION_ SET Command 1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Break Condition 2 are disabled. 2. Break Condition 2 is disabled when an instruction to which a BREAKPOINT has been set is executed. Accordingly, do not set a BREAKPOINT to an instruction which satisfies Break Condition 2. 3. When a Break Condition is satisfied, emulation may stop after two or more instructions have been executed. 4. If a PC break address condition is set to the slot instruction after a delayed branch instruction, user program execution cannot be terminated before the slot instruction execution; execution stops before the branch destination instruction. 5. Break Condition 1,2 is used as the measurement range in the performance measurement function when [PA-1 start point] and [PA-1 end point] are displayed on the [Action] part in the [Break condition] sheet of the [Event] window. This applies when the Break Condition is displayed with the BREAKCONDITION_DISPLAY command in the command-line function. In this case, a break does not occur when Break Condition 1,2 is satisfied. 6. A break will not occur with the execution counts specified on the execution of the multi-step instruction. 2.2.7 Notes on Setting the UBC_MODE Command In the [Configuration] window, if [User] is set while the [UBC mode] list box has been set, the STEP-type commands that use Break Condition 2 for implementation cannot be used. 27 2.2.8 Performance Measurement Function The SH7294 E10A emulator supports the performance measurement function. 1. Setting the performance measurement conditions To set the performance measurement conditions, use the [Performance Analysis] dialog box and the PERFORMANCE_SET command. When any line on the [Performance Analysis] window is clicked with the right mouse button, the popup menu is displayed and the [Performance Analysis] dialog box is displayed by selecting [Setting]. Note: For the command line syntax, refer to the online help. (a) Specifying the measurement start/end conditions The measurement start/end conditions are specified in the [Mode] drop-down list box in the [Performance Analysis] dialog box. Three conditions can be set as shown in table 2.10. Table 2.10 Conditions Specified in [Mode] Item Description Normal break Measurement is started by executing a program and ended when a break condition is satisfied. Break Condition 1 -> 2 Measurement is started from the satisfaction of the condition set in Break Condition 1 and ended with the satisfaction of the condition set in Break Condition 2. Break Condition 2 -> 1 Measurement is started from the satisfaction of the condition set in Break Condition 2 and ended with the satisfaction of the condition set in Break Condition 1. 28 Figure 2.4 [Performance Analysis] Dialog Box (b) Measurement range One of the following ranges can be specified. This depends on the item selected for [Mode] in the [Performance Analysis] dialog box. 1. From the start to the end of the user program execution (When Normal Break is selected for [Mode]) 2. From the satisfaction of the condition set in Break Condition 1 to the satisfaction of the condition set in Break Condition 2 (When Break condition 1->2 is selected for [Mode]) 3. From the satisfaction of the condition set in Break Condition 2 to the satisfaction of the condition set in Break Condition 1 (When Break condition 2->1 is selected for [Mode]) (In the second and third ranges, [PA-1 start point] and [PA-1 end point] are displayed on the [Action] part in the [Break condition] sheet of the [Event] window.) For measurement errors, • The measured value includes errors. • Error will occur before or after a break. 29 Notes: 1. When the second and third ranges are specified, execute the user program after the measurement start condition is set to Break Condition 1 (or Break Condition 2) and the measurement end condition to Break Condition 2 (or Break Condition 1). 2. Step execution is not possible when Break condition 1->2 or Break condition 2->1 is selected for the PERFORMANCE_SET command or in [Mode] of the [Performance Analysis] dialog box. 3. When Break condition 1->2 or Break condition 2->1 is selected in [Mode] of the [Performance Analysis] dialog box, specify one or more items for measurement. When there is no item, the error message “Measurement item does not have specification. Please set up a measurement item.” will be displayed. When no item is specified for the PERFORMANCE_SET command, the settings of Break condition 1 ->2 or Break condition 2->1 will be an error. (c) Measurement item Items are measured with [Channel 1 to 4] in the [Performance Analysis] dialog box. Maximum four conditions can be specified at the same time. Table 2.11 shows the measurement items (Options in table 2.11 are parameters for <mode> of the PERFORMANCE_SET command. They are displayed for CONDITION in the [Performance Analysis] window). 30 Table 2.11 Measurement Item Selected Name Option Disabled None Elapsed time AC Number of execution states VS Branch instruction counts BT Number of execution instructions I DSP-instruction execution counts DI (Devices incorporating the DSP function can only be measured.) Instruction/data conflict cycle MAC Other conflict cycles than instruction/data OC Exception/interrupt counts EA Data-TLB miss cycle MTS (Devices incorporating the MMU function can only be measured.) Instruction-TLB miss cycle ITS (Devices incorporating the MMU function can only be measured.) Interrupt counts INT Number of BL=1 instructions BL1 Number of MD=1 instructions MD1 Instruction cache-miss counts IC Data cache-miss counts DC Instruction fetch stall IF Data access stall DA Instruction cache-miss stall ICS Data cache-miss stall DCS Cacheable access stall CS X/Y-RAM access stall XYS (Devices incorporating the X/Y memory can only be measured.) URAM access stall US (Devices incorporating the U memory can only be measured.) Instruction/data access stall cycle MA Other access cycles than instruction/data NMA Non-cacheable area access cycle NCC Non-cacheable area instruction access cycle NCI Non-cacheable area data access cycle NCD Cacheable area access cycle CC 31 Table 2.11 Measurement Item (cont) Selected Name Option Cacheable area instruction access cycle CIC Cacheable area data access cycle CDC Access counts other than instruction/data NAM Non-cacheable area access counts NCN Non-cacheable area instruction access counts NCIN Non-cacheable area data access counts NCDN Cacheable area access counts CN Cacheable area instruction access counts CIN Cacheable area data access counts CDN Each measurement condition is also counted when conditions in table 2.12 are generated. Table 2.12 Performance Measurement Conditions to be Counted Measurement Condition Notes No caching due to the settings of TLB cacheable bit Counted for accessing the cacheable area. Cache-on counting Accessing the non-cacheable area is counted less than the actual number of cycles and counts. Accessing the cacheable, X/Y RAM, and U RAM areas is counted more than the actual number of cycles and counts. Branch count The counter value is incremented by 2. This means that two cycles are valid for one branch. Notes: 1. In the non realtime trace mode of the AUD trace, normal counting cannot be performed because the generation state of the stall or the execution cycle is changed. 2. Since the clock source of the counter is the CPU clock, counting also stops when the clock halts in the sleep mode. 32 2. Displaying the measured result The measured result is displayed in the [Performance Analysis] window or the PERFORMANCE_ANALYSIS command with hexadecimal (32 bits). Note: If a performance counter overflows as a result of measurement, “********” will be displayed. 3. Initializing the measured result To initialize the measured result, select [Initialize] from the popup menu in the [Performance Analysis] window or specify INIT with the PERFORMANCE_ANALYSIS command. 2.2.9 Notes on U Standby State Controlling Vcc (main) in the U standby state clears settings for peripheral modules in the SH7294 which the emulator uses for debugging. Thus the appropriate function must be selected in the [Recovery Information] page of the [Configuration] dialog box so that debugging can be continued after recovering from the U standby state. Note: When using the U standby state, be sure to connect the /CA pin to the emulator. Table 2.13 lists the items to be selected in the [Recovery Information] page of the [Configuration] dialog box. Table 2.13 Selected Items in the [Recovery Information] Page Selected Item Description Configuration dialog information Resets the information on the [General] page in the [Configuration] dialog box. Break Condition (UBC) Resets the conditions of Break Condition. Trace Acquisition Condition (AUD) Resets the AUD trace conditions. Performance Analysis Condition (PPC) Resets the performance conditions. 33 Figure 2.5 [Recovery Information] Page 34 The following shows the procedures recovered from the U standby state. 1. In the software standby mode, when the /CA pin is asserted, the emulator enters the U standby state and the message box shown in figure 2.6 is displayed. To cancel the U standby state, be sure to end the message box before asserting /RESETP from the user system. 2. Turn Vcc (main) off. Figure 2.6 Message Box for Entering the U Standby State 3. Assert /RESETP and turn Vcc (main) on. 4. After the power has been stable, negate the /CA pin. 5. Negate /RESETP, and the U standby state is cancelled. 6. Before the program execution is restarted from the reset vector, the E10A debugging function, which has been set in the [Recovery Information] page in the [Configuration] dialog box, is recovered. During this period, the HEW cannot operate. Notes: 1. For entering or canceling the U standby state, refer to the section of low power mode in the SH7294 Series Hardware Manual. 2. When Vcc (main) is turned on in the U standby state, set the TCK value to less than the number of peripheral module clocks and select [Configuration dialog information] in the [Recovery Information] page. If this is not selected, the TCK value will be as follows: When HS7294KCI01H or HS7294KCI02H is used: TCK = 1.031 MHz When HS7294KCM01H or HS7294KCM02H is used: TCK = 0.937 MHz 3. After the /CA pin has been negated, if /RESETP is not input for about 30 seconds, a timeout error will occur. 4. Software breakpoints that have recovered from the U standby state remain to be set on the memory. However, the contents displayed in the [Breakpoints] window may be different from the actual points when the contents of memory is initialized by the control of Vcc (main). In this case, clear all the breakpoints and set them again. 5. In functions for which conditions were not recovered by a selection in [Recovery information], the settings made will not be the same as the contents displayed in a dialog box or command after the recovery from the U standby state until when the user program is halted. 35 36 6. If [User] is set in the [UBC mode] list box in the [Configuration] dialog box, Break Condition (UBC) and Trace Acquisition Condition (AUD) cannot be selected. 7. A noise filter is provided in the emulator to prevent malfunction due to noises of the /CA pin. It takes about 70 ns from assertion (negation) of /CA to reflection to the emulator. Therefore, set 70 ns or more periods during assertion to negation of /CA. 8. When the U standby state has been cancelled, before the program execution is restarted from the reset vector, the E10A debugging function, which has been set in the [Recovery Information] page in the [Configuration] dialog box, is recovered. During this period, the HEW cannot operate. When the debugging functions except for [Configuration dialog information] are not recovered in the [Recovery Information] page, the following waiting time will be generated before the user program is reexecuted: ® Frequency: 833 MHz (Pentium III) OS: Windows 2000 Operating state of SH7294: Operating mode 3, 20-MHz input clock, 1.87-MHz TCK value Waiting time: Approximately 24 ms TM SuperH Family E10A Emulator Additional Document for User's Manual Specific Guide for the SH7294 E10A Emulator Publication Date: Rev.1.00, July 3, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2003 Renesas Technology Corp. All rights reserved. Printed in Japan. SuperH™ Family E10A Emulator Additional Document for User’s Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ10B0013-0100H