Download m68mpb916x1 mcu personality board user`s manual

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M68MPB916X1UM/D
Freescale Semiconductor, Inc...
October 1998
M68MPB916X1
MCU PERSONALITY BOARD
USER’S MANUAL
© MOTOROLA, INC., 1993, 1998; All Rights Reserved
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Motorola reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. Motorola does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of
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Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part.
Motorola and the Motorola logo are registered trademarks of Motorola Inc. SDI is a trademark of
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Motorola Inc. is an Equal Opportunity/Affirmative Action Employer.
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CONTENTS
CONTENTS
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CHAPTER 1
1.1
1.2
1.3
1.4
GENERAL INFORMATION
INTRODUCTION............................................................................................................. 1-1
SPECIFICATIONS ........................................................................................................... 1-2
EQUIPMENT REQUIRED............................................................................................... 1-2
CUSTOMER SUPPORT .................................................................................................. 1-3
CHAPTER 2
HARDWARE PREPARATION AND INSTALLATION
2.1
2.2
INTRODUCTION............................................................................................................. 2-1
HARDWARE PREPARATION ....................................................................................... 2-1
2.2.1 Clock Select Header (W1) ......................................................................................... 2-4
2.2.2 VDDA Select Header (W2) ....................................................................................... 2-5
2.2.3 Voltage Reference High Select Header (W3)............................................................ 2-6
2.2.4 Voltage Reference Low Select Header (W4)............................................................. 2-7
2.2.5 VSSA Insertion Point (E1) ........................................................................................ 2-7
2.3 ANALOG/DIGITAL CIRCUITS.......................................................................................... 2-8
2.4 MEVB CONFIGURATION.............................................................................................. 2-9
2.5 ACTIVE PROBE CONFIGURATION........................................................................... 2-11
CHAPTER 3
MEVB QUICK START GUIDE
3.1
3.2
INTRODUCTION............................................................................................................. 3-1
CONFIGURING THE MPFB........................................................................................... 3-1
3.2.1 MPFB Memory Devices ............................................................................................ 3-1
3.2.2 MPFB Jumper Headers.............................................................................................. 3-2
3.3 MEVB INSTALLATION INSTRUCTIONS.................................................................... 3-3
3.3.1 Power Supply – MPFB Connection........................................................................... 3-4
3.3.2 Personal Computer – BDM Connection .................................................................... 3-5
3.4 SOFTWARE INSTALLATION ....................................................................................... 3-6
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CONTENTS
CHAPTER 4
4.1
4.2
INTRODUCTION............................................................................................................. 4-1
LOGIC ANALYZER CONNECTOR SIGNALS............................................................. 4-1
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CHAPTER 5
5.1
5.2
MAPI SUPPORT INFORMATION
INTRODUCTION............................................................................................................. 5-1
MAPI BUS CONNECTORS ............................................................................................ 5-1
CHAPTER 6
6.1
MEVB SUPPORT INFORMATION
SCHEMATIC DIAGRAMS
INTRODUCTION............................................................................................................. 6-1
FIGURES
2-1.
2-2.
2-3.
2-4.
5-1.
5-2.
5-3.
5-4.
5-5.
MPB Parts Location Diagram (top view).......................................................................... 2-2
A/D Signal Filtering.......................................................................................................... 2-8
MPB – MPFB Interconnection (with serial interface) .................................................... 2-10
Active Probe Interconnection (with Active Probe Box) ................................................. 2-12
MAPI Interface Connector Layout.................................................................................... 5-1
MAPI Interface Connector P1 Pin Assignments............................................................... 5-2
MAPI Interface Connector P2 Pin Assignments............................................................... 5-3
MAPI Interface Connector P3 Pin Assignments............................................................... 5-4
MAPI Interface Connector P4 Pin Assignments............................................................... 5-5
TABLES
1-1.
2-1.
2-2.
3-1.
4-1.
4-2.
4-3.
4-4.
4-5.
iv
MPB Specifications........................................................................................................... 1-2
Jumper Header Types........................................................................................................ 2-3
MPB Jumper Header Descriptions.................................................................................... 2-3
MPFB Quick Start Jumper Header Configuration ............................................................ 3-2
Logic Analyzer Connector J7 Pin Assignments................................................................ 4-2
Logic Analyzer Connector J8 Pin Assignments................................................................ 4-2
Logic Analyzer Connector J9 Pin Assignments................................................................ 4-3
Logic Analyzer Connector J10 Pin Assignments.............................................................. 4-3
Logic Analyzer Connector J11 Pin Assignments.............................................................. 4-4
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CONTENTS
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TABLES (CONTINUED)
4-6.
4-7.
4-8.
4-9.
4-10.
4-11.
4-12.
4-13.
4-14.
Logic Analyzer Connector J12 Pin Assignments.............................................................. 4-4
Logic Analyzer Connector J13 Pin Assignments.............................................................. 4-6
Logic Analyzer Connector J14 Pin Assignments.............................................................. 4-8
Logic Analyzer Connector J15 Pin Assignments.............................................................. 4-8
Logic Analyzer Connector J16 Pin Assignments.............................................................. 4-9
Logic Analyzer Connector J17 Pin Assignments.............................................................. 4-9
Logic Analyzer Connector J18 Pin Assignments............................................................ 4-10
Logic Analyzer Connector J19 Pin Assignments............................................................ 4-10
Logic Analyzer Connector J20 Pin Assignments............................................................ 4-11
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CONTENTS
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GENERAL INFORMATION
CHAPTER 1
GENERAL INFORMATION
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1.1 INTRODUCTION
This manual provides general information, hardware preparation, installation
instructions, a quick start guide, and support information for the M68MPB916X1
MCU Personality Board (MPB). The MPB is one component of Motorola’s
modular approach to MC68HC916X1 Microcontroller Unit-based product
development. This modular approach lets you easily configure our development
systems to fit your requirements.
The MPB may be used in either the MMDS1632 Motorola Modular Development
System (MMDS) or the modular evaluation board (MEVB). The MEVB consists
of the M68MPFB1632 Modular Platform Board (MPFB) and an MPB.
Alternately, you may install the MPB directly in your target system if the target
system includes a modular active probe interconnect (MAPI) interface. The MCU
device on the MPB defines which MCU is emulated/evaluated by the MMDS or
evaluated by the MEVB. Both systems are invaluable tools for designing,
debugging, and evaluating MCU operation of the M68HC16 and M68300 MCU
families. By providing the essential MCU timing and I/O circuitry, these systems
simplify user evaluation of prototype hardware/software products.
The MPB product includes:
• M68MPB916X1 MCU Personality Board (MPB)
• Plastic overlay for use with the MEVB – pin outs for the logic analyzer
connectors on the MPFB (specifically for the MC68HC916X1 MCU)
• Documentation (this manual)
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GENERAL INFORMATION
1.2 SPECIFICATIONS
Table 1-1 lists MPB specifications.
Table 1-1. MPB Specifications
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Characteristic
Specifications
On-Board Clock
Case style: 14 or 8-pin hybrid crystal clock oscillator
(frequency as required by MCU).
External Clock
32 KHz – 16.78 MHz (or maximum MCU allows).
MCU I/O ports
HCMOS compatible
Temperature
Operating
Storage
0° to +40° C
-40° to +85° C
Relative humidity
0 to 90% (non-condensing)
Power requirements
+5 Vdc ± 5% @ 500 mA (max.)
Dimensions
Size
Weight
3.25 x 3.25 in. (82.6 x 82.6 mm)
2.9 oz. (82.2 grams)
1.3 EQUIPMENT REQUIRED
The external requirements for MPB operation are either an MPFB or MMDS
system. For MMDS operation requirements, see the MMDS1632 Motorola
Modular Development System User’s Manual, MMDS1632UM/D. For operation
requirements for the MEVB, see this manual and the M68MPFB1632 Modular
Platform Board User’s Manual, M68MPFB1632/D. To use the MPB in an MEVB
you must also have background debug mode (BDM) software and hardware
(purchased separately) that communicates via BDM interface.
1-2
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GENERAL INFORMATION
1.4 CUSTOMER SUPPORT
For information about a Motorola distributor or sales office near you call:
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AUSTRALIA, Melbourne – (61-3)887-0711
Sydney – 61(2)906-3855
BRAZIL, Sao Paulo – 55(11)815-4200
CANADA, B. C., Vancouver – (604)606-8502
ONTARIO, Toronto – (416)497-8181
ONTARIO, Ottawa – (613)226-3491
QUEBEC, Montreal – (514)333-3300
JAPAN, Fukuoka – 81-92-725-7583
Gotanda – 81-3-5487-8311
Nagoya – 81-52-232-3500
Osaka – 81-6-305-1802
Sendai – 81-22-268-4333
Takamatsu – 81-878-37-9972
Tokyo – 81-3-3440-3311
KOREA, Pusan – 82(51)4635-035
Seoul – 82(2)554-5118
CHINA, Beijing – 86-10-68437222
MALAYSIA, Penang – 60(4)2282514
DENMARK – (45)43488393
FINLAND, Helsinki – 358-9-6824-400
MEXICO, Mexico City – 52(5)282-0230
Guadalajara – 52(36)21-8977
FRANCE, Paris – 33134 635900
PUERTO RICO, San Juan – (809)282-2300
GERMANY,
Langenhagen/Hannover – 49(511)786880
Munich – 49 89 92103-0
Nuremberg – 49 911 96-3190
Sindelfingen – 49 7031 79 710
Wiesbaden – 49 611 973050
SINGAPORE – (65)4818188
HONG KONG, Kwai Fong – 852-6106888
Tai Po – 852-6668333
SPAIN, Madrid – 34(1)457-8204
SWEDEN, Solna – 46(8)734-8800
SWITZERLAND, Geneva – 41(22)799 11 11
Zurich – 41(1)730-4074
TAIWAN, Taipei – 886(2)717-7089
INDIA, Bangalore – (91-80)5598615
THAILAND, Bangkok – 66(2)254-4910
ISRAEL, Herzlia – 972-9-590222
UNITED KINGDOM, Aylesbury – 441(296)395-252
ITALY, Milan – 39(2)82201
UNITED STATES, Phoenix, AZ – 1-800-521-6274
For a list of the Motorola sales offices and distributors:
http://www.mcu.motsps.com/sales/soffice.html
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GENERAL INFORMATION
1-4
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HARDWARE PREPARATION AND INSTALLATION
CHAPTER 2
HARDWARE PREPARATION AND INSTALLATION
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2.1 INTRODUCTION
This chapter provides unpacking instructions, hardware preparation information,
and installation instructions for the MPB.
When you unpack the MPB from its shipping carton, verify that all items are in
good condition. Save packing material for storing and shipping the MPB.
NOTE
Should the MPB arrive damaged, save all packing material, and
contact the carrier’s agent.
2.2 HARDWARE PREPARATION
This portion of the manual explains how to prepare the MPB before use, as well
as how to configure the MPB for system operation. This section also explains
MPB installation in the MMDS and MEVB.
The MPB has been factory tested and is shipped with installed jumpers. A jumper
installed on a jumper header provides a connection between two points in the
MPB circuit. The MPB has two types of jumper headers: three-pin and two-pin
with a cut-trace short. A cut-trace short has a copper trace between the feedthrough holes (bottom or solder side of the MPB). Table 2-1 describes each type
of jumper header.
The MPB has four jumper headers (for which Table 2-2 is a quick reference
guide). You may re-configured these jumper headers to customize MPB
functionality. The following paragraphs explain each jumper header function.
There is also an insertion point (E1) for connecting an external ground. Figure 2-1
shows the location of the MPB jumper headers and the insertion point.
NOTE
Verify that all socketed parts are seated in their sockets.
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HARDWARE PREPARATION AND INSTALLATION
CAUTION
Depending on your application, it may be necessary to cut the W2
wiring trace short (cut-trace short). Be careful not to cut adjacent
PCB traces, nor cut too deep into the multi-layer circuit board.
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If the cut-trace short on a jumper header is already cut, you can
return the MPB to its default setting by installing a user-supplied
fabricated jumper.
Figure 2-1. MPB Parts Location Diagram (top view)
2-2
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Table 2-1. Jumper Header Types
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Jumper Header
Type
Symbol
Description
two-pin with cut-trace
short
Two-pin jumper header with cut-trace short, designated WX,
where X = the jumper header number. If you cut the short, use a
fabricated jumper to return the jumper header to its factory default
state.
three-pin
Three-pin jumper header, designated WX, where X = the jumper
header number. Use a fabricated jumper to create a connection
between two of the three pins of the jumper header.
Table 2-2. MPB Jumper Header Descriptions
Jumper
Header
W1
W2
Type
Description
1
2
3
Jumper between pins 1 and 2 (factory default); selects the MPB on-board
crystal clock source.
1
2
Jumper installed or cut-trace short intact (factory default); selects the on-board
VDDA power source.
Jumper between pins 2 and 3; selects an external clock source to be the MCU
EXTAL input signal.
No jumper or cut-trace short; enables use of an external power source
connected to W2 pin 2.
NOTE
Jumper header W2 is not populated by the factory.
W3
W4
1
2
3
Jumper installed on pins 1 and 2 (factory default); selects the MPB on-board
VRH power source.
1
2
3
Jumper installed on pins 1 and 2 (factory default); selects the MPB on-board
VRL power source.
M68MPB916X1UM/D
Jumper installed on pins 2 and 3; selects an external VRH power source.
Jumper installed on pins 2 and 3; selects an external VRL power source.
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2.2.1
Clock Select Header (W1)
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Jumper header W1 connects the MCU external clock (EXTAL) pin to either an
on-board or external (target-system) clock source. The drawing below shows the
factory configuration: a fabricated jumper on pins 1 and 2. This configuration
selects the MPB on-board clock source; crystal oscillator in the Y1 socket. (This
crystal provides for operation at the maximum rate the MCU allows via the
internal phase-locked loop or direct clock input.)
If you install the MPB in the active probe or directly on a target system, and use
the target system clock as the MPB clock, move the fabricated jumper to W1 pins
2 and 3. This connects the MCU EXTAL pin to the MAPI bus input pin. The
frequency of the external clock signal can be from 32 KHz to 16.78 MHz (or to
the maximum the MCU allows).
Clock Source
Selection
1
2
W1
3
Fabricated
Jumper
NOTE
You cannot drive the MPB clock circuit from an external source
(target system) with a discrete crystal. If you use a target system
clock source to drive the MPB clock circuit, always use a logicdriven clock such as a hybrid oscillator.
2-4
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2.2.2
VDDA Select Header (W2)
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Jumper header W2 selects the MPB VDDA power source: either MPB power
(VDDI) or an external source. The drawing below shows the factory
configuration: a cut-trace short between pins 1 and 2. This configuration connects
filtered VDDI to VDDA.
To use an external power source, remove the cut-trace short from W2 pins 1 and
2, then connect the external power source to W2 pin 2. Removal of the cut-trace
short isolates the MCU VDDA pin from the other MPB circuitry. Isolation lets
you connect a precision VDDA source for accurate 10-bit analog/digital (A/D)
generation. When connecting an external VDDA power supply to the MPB,
connect the power supply ground to insertion point E1. For more information on
A/D generation refer to the Analog-To-Digital Converter Reference Manual,
ADCRM/AD.
VDDA Source
Selection
1
2
W2
Cut-Trace
Short
NOTES
If the cut-trace short has been cut, you must install a fabricated
jumper on W2 to return it to the factory configuration.
Jumper header W2 is not populated by the factory.
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HARDWARE PREPARATION AND INSTALLATION
2.2.3
Voltage Reference High Select Header (W3)
Jumper header W3 selects the voltage reference high (VRH) source: either MPB
power (VDDA) or an external VRH source. The drawing below shows the factory
configuration: a fabricated jumper on pins 1 and 2. This configuration selects
VDDA as the VRH source.
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To use an external VRH source, first place the fabricated jumper on W3 pins 2
and 3. Then connect the MCU VRH pin to the external VRH source. Each
configuration defines the best method for connecting the MCU VRH pin to the
external VRH source:
• MPB/MPFB – connect via the MPFB logic analyzer connector (refer to
Chapter 4 for the appropriate logic analyzer pin).
• MPB/MMDS1632 – connect via the VRH pin of the target MCU socket
• MPB/Target System – connect via the VRH pin of the target system
MAPI bus
Alternately, you may remove the jumper and wire-wrap directly to W3 pin 2.
Connecting directly to pin 2 is an option regardless of the configuration.
VRH Source
Selection
1
2
Fabricated
Jumper
3
W3
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HARDWARE PREPARATION AND INSTALLATION
2.2.4
Voltage Reference Low Select Header (W4)
Jumper header W4 selects the voltage reference low (VRL) source: either MPB
power (VSSA) or an external VRL source. The drawing below shows the factory
configuration: a fabricated jumper on pins 1 and 2. This configuration selects
VSSA as the VRL source.
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To use an external VRL source, first place the fabricated jumper on W4 pins 2 and
3. Then connect the MCU VRL pin to the external VRL source. Each
configuration defines the best method for connecting the MCU VRL pin to the
external VRL source:
• MPB/MPFB – connect via the MPFB logic analyzer connector (refer to
Chapter 4 for the appropriate logic analyzer pin).
• MPB/MMDS1632 – connect via the VRL pin of the target MCU socket
• MPB/Target System – connect via the VRL pin of the target system MAPI
bus
Alternately, you may remove the jumper and wire-wrap directly to W4 pin 2.
Connecting directly to pin 2 is an option regardless of the configuration.
VRL Source
Selection
1
2
Fabricated
Jumper
3
W4
2.2.5
VSSA Insertion Point (E1)
Insertion point E1 is a plate through hole that lets you connect an external ground
to the MPB VSSA pin (refer to paragraph 2.2.2). Insert an external ground wire in
E1 and solder it into the plate through hole.
NOTE
Insertion point E1 is not populated by the factory.
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HARDWARE PREPARATION AND INSTALLATION
2.3 ANALOG/DIGITAL CIRCUITS
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Analog-to-digital (A/D) signals on the MPB are filtered via an installed capacitor
(Figure 2-2 is a representative diagram). If your target board also has A/D filter
capacitors you must remove either the capacitors on your board or on MPB. Refer
to the table below when removing MPB filter capacitors from its associated A/D
signal.
ANALOG
SIGNAL
ADAn
VSSA
MCU
Figure 2-2. A/D Signal Filtering
2-8
Signal
Capacitor
AN0
C7
AN1
C5
AN2
C3
AN3
C6
AN4
C4
AN5
C2
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HARDWARE PREPARATION AND INSTALLATION
2.4 MEVB CONFIGURATION
The MEVB contains:
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• MPB – MCU-device-specific board that defines the MCU to be evaluated.
• M68MPFB1632 Modular Platform Board (MPFB) – which provides the
interface connections to the host computer, logic analyzer connections, and
the platform for installing the MPB. For more information about the MPFB
and MEVB system connections refer to the M68MPFB1632 Modular
Platform Board User's Manual, M68MPFB1632/D. Chapter 3 contains
information to help you get started using your MEVB.
CAUTION
Turn OFF MPFB power when installing the MPB on the MPFB or
removing the MPB from the MPFB. Sudden power surges could
damage MEVB integrated circuits.
To install the MPB on the MPFB (refer to Figure 2-3):
1. Inspect all connectors for bent or damaged pins.
2. Align the MPB reference mark with the MPFB reference mark.
3. Rotate the MPB until the four MAPI bus connectors on its bottom mate
with the MAPI bus connectors on the top of the MPFB. (There is only one
way to connect the MPB and the MPFB.)
4. Firmly press the MPB onto the MPFB.
5. Follow the instructions in the appropriate manual when connecting your
debugger hardware to the background debug mode connector.
CAUTION
Support the bottom side of MPFB when installing the MPB on the
MPFB. Excessive flexing of the MPFB could damage the printed
circuit.
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HARDWARE PREPARATION AND INSTALLATION
Figure 2-3. MPB – MPFB Interconnection (with serial interface)
After you have installed the MPB, install the plastic overlay on the MPFB: place
the overlay over logic analyzer connectors J12 through J20 and press down. Holes
in the overlay slide down over plastic clips on the MPFB. These clips hold the
overlay in place.
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HARDWARE PREPARATION AND INSTALLATION
2.5 ACTIVE PROBE CONFIGURATION
The MMDS1632 Motorola Modular Development System (MMDS) consists of
the station module and an active probe. The active probe consists of a three board
set, two cables, and a box:
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• MPB – MCU-device-specific board that defines the MCU to be evaluated.
• Target Control Board (TCB) – the interface between the MPB, target
system, and the station module. The TCB comes with the MMDS. For more
information about the TCB refer to the MMDS1632 Motorola Modular
Development System User's Manual, MMDS1632UM/D.
• Package Personality Board (PPB) – the board that connects the active probe
to the target system. The PPB must be purchased separately. For more
information about the PPB refer to the appropriate PPB configuration
guide.
• Active probe cables (2) – the interface between the active probe and the
station module. 01-RE90340W01 REV 0 and 01-RE90341W01 REV 0 are
printed on the active probe cables. The active probe cables come with the
TCBe. For more information about the active probe cables refer to the
MMDS1632 Motorola Modular Development System User's Manual,
MMDS1632UM/D.
• Active probe box – the protective enclosure for the TCB.
CAUTION
Turn off MMDS and target system power when installing or
removing MMDS components. Sudden power surges could
damage MMDS and target system integrated circuits.
To configure an active probe (refer to Figure 2-4):
1. Inspect all connectors for bent or damaged pins.
2. Rotate the MPB until the four MAPI bus connectors on its bottom mate
with the MAPI bus connectors on the top of the TCB. (There is only one
way to connect the MPB and the TCB.)
3. Firmly press the MPB and the TCB together.
Rotate the PPB until the four MAPI bus connectors on its top mate with
the MAPI bus connectors on the bottom of the TCB. (There is only one
way to connect the PPB and the TCB.)
4. Firmly press the PPB and the TCB together.
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HARDWARE PREPARATION AND INSTALLATION
5. Connect one end of the 01-RE90341W01 REV 0 active probe cable to
connector P6 on the MMDS control board; connect the other end to
connector J6 on the TCB. Connect one end of the 01-RE90340W01 REV
0 active probe cable to connector P5 on the MMDS control board; connect
the other end to connector J5 on the TCB. Secure the connector clamps on
TCB connectors J5 and J6.
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The active probe is now ready to connect to the target system (refer to the PPB configuration
guide for information on connecting the active probe to the target system.)
Figure 2-4. Active Probe Interconnection (with Active Probe Box)
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MEVB QUICK START GUIDE
CHAPTER 3
MEVB QUICK START GUIDE
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3.1 INTRODUCTION
This quick start guide is intended for the user who may not be familiar with
Motorola’s development tools. This chapter explains the MEVB hardware and
software setup for M68MEVB916X1 operation. Hardware setup consists of
configuring the MPB and MPFB jumper headers; software setup consists of
running the appropriate initialization code within the debugger.
For the purpose of this quick start guide the MPB jumper headers should be
configured in their default positions. Chapter 2 of this manual contains the default
jumper header settings for the MPB.
3.2 CONFIGURING THE MPFB
The MPFB includes jumper-selectable options such as chip select usage, memory
type selection and memory size selection for the pseudo ROM sockets, and reset
data control.
NOTE
The MPFB must be configured for the specific MPB. Paragraph
3.2.2 provides a configuration for basic MPFB operation. For a
detailed description of the MPFB jumper header selections refer to
the M68MPFB1632 Modular Platform Board User’s Manual,
M68MPFB1632/D.
3.2.1
MPFB Memory Devices
Pseudo ROM refers to memory locations U2 & U4. The two pseudo ROM sockets
are generic memory sockets that accept a variety of RAM, EPROM, or EEPROM
devices. The pseudo ROM sockets, as shipped from the factory, contain two 32K
x 8 RAM devices. These memories are 28-pin package devices.
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MEVB QUICK START GUIDE
3.2.2
MPFB Jumper Headers
Configure your MPFB jumper headers per the instructions in Table 3-1. Table 3-1
contains information exclusively intended for quick start and ignores the other
jumper headers.
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Table 3-1. MPFB Quick Start Jumper Header Configuration
Jumper
Header
Type
Description
W2
123
Install a jumper on pins 1 and 2 to configure pin 1 of the memory devices in the
pseudo ROM sockets (U2 & U4) as a standard address line.
W3
123
Install a jumper on pins 1 and 2 to indicate that the memory devices in the
pseudo ROM sockets (U2 & U4) have 28 pins.
W4
123
Install a jumper on pins 1 and 2 to set the pseudo ROM port size (memory data
width) as word.
W5
123
Install a jumper on pins 2 and 3 to enable the PRU.
W6
123
W6 selects the MCU operation mode. Each 3-pin jumper header set
corresponds to an MCU data line. While the reset pin is low, the reset data
values are driven on the data bus (D0 – D15). (The MEVB reset data circuit is
open drain; a high state is provided via a pull-up resistor.) Each reset data line
may be set high (H) or low (L). Consult the appropriate MCU user's manual,
data book, or technical summary for reset data information.
W10
1
3
5
2
4
6
Install a jumper on pins 1 and 2 to indicate that RAM is installed in the pseudo
ROM sockets (U2 & U4).
W12
1
3
5
7
9
2
4
6
8
10
Install a jumper on pins 3 and 4 to indicate that the two devices installed in the
pseudo ROM sockets (U2 & U4) are 32K x 8.
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Table 3-1. MPFB Quick Start Jumper Header Configuration (continued)
Jumper
Header
Type
Description
W14
123
Jumper header W14 selects the MCU signal for the memory devices in the fast
RAM sockets (U9 & U10) and pseudo ROM sockets (U2 & U4). Pins 1 and 2
select the MCU chip select for the memory devices in the fast RAM sockets.
Pins 2 and 3 of jumper header W14 select the chip select for the memory
devices in the pseudo ROM sockets.
Jumper installed on CSBOOT pins 2 and 3 (factory default); use CSBOOT as
the memory device chip enable for memory devices in the pseudo ROM
sockets.
W16
12
No jumper installed; the MCU MODCLK signal is pulled high (logic 1) via a
resistor during reset.
W17
12
No jumper installed; the BERR signal is pulled high (logic 1) via a resistor
during reset.
W18
123
Install a jumper on pins 1 and 2 for unrestricted writes to the memory devices
in the pseudo ROM sockets (U2 & U4).
W19
123
Install a jumper on pins 1 and 2 to ground the A19 signal to the MPFB memory
arrays.
W22
123
Install a jumper on pins 2 and 3 to select the evaluation MCU (on the MPB) as
an M68HC16 MCU device.
3.3 MEVB INSTALLATION INSTRUCTIONS
MEVB installation requires a user-supplied power supply and host computer. The
host computer must have the appropriate I/O port (serial or parallel) as required by
your debugger hardware; as well as the appropriate operating system as required
by your debugger software (refer to the appropriate debugger documentation for
these requirements). The following paragraphs explain MPFB connections. Refer
to Chapter 2 for instructions to connect the MPB and MPFB.
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3.3.1
Power Supply – MPFB Connection
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Use MPFB connector J5 to connect a user-supplied power supply to the MEVB.
Contact 1 is ground; black lever. Contact 2 is VDD (+5 volts); red lever. Use 20
or 22 AWG wire for power connections. For each wire, trim back the insulation
1/4 in. (.635 cm), lift the appropriate lever of J5 to release tension on the contacts,
then insert the bare wire into J5 and close the lever. The MEVB requires a +5Vdc
@ 1.0 amp power supply for operation. A 1.5 amp fuse is installed on the MPFB
+5Vdc power supply input line.
BLK
RED
GND
J5
+5V
CAUTIONS
Do not use wire larger than 20 AWG in connector J5. Such wire
could damage the connector.
Turn off MEVB power when installing or removing the MPB from
the MPFB. Sudden power surges could damage MEVB integrated
circuits.
3-4
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3.3.2
Personal Computer – BDM Connection
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Personal computer communication with the MEVB requires background debug
mode (BDM) hardware. Connect your BDM hardware between your computer’s
I/O port and the BDM header on the MPFB (MPFB connector J6). The drawing
below shows signal assignments for connector J6. For additional information
about your BDM software/hardware, including debugging and assembly
information, see the appropriate user's manual.
J6
M68MPB916X1UM/D
DS
1
GND
3
GND
5
RESET
7
+5 Vdc
9
•
•
•
•
•
•
•
•
•
•
2
BERR*
4
BKPT*
6
FREEZE
8
DSI
10
DSO
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3.4 SOFTWARE INSTALLATION
After you have set up the MEVB hardware you must install ICD16 in your
computer. To install the software and initialize your MEVB:
1. Insert the software diskette into the 3.5-inch drive of your computer.
2. Type the drive letter, followed by the word install. For example, if
your 3.5-inch drive is drive B, type: b install
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3. The install program automatically loads the software. Follow the
instructions that appear on the screen. This completes software loading.
4. After you have configured the MEVB hardware and installed ICD16 on
your hard drive, turn on the MEVB power supply.
5. To start ICD type:
C:/>ICD16 [option] [option]
[option]
bw
lpt1
lpt2
lpt3
-orpath
Use the correct pathname to access ICD16
ICD optional parameters are:
Set display to black and white
Use lpt1 (default)
Use lpt2
Use lpt3
A DOS path to directory containing the source code
for source level debug.
Example: ICD16 bw lpt2
If more than one option is given, they must
be separated by spaces.
6. To install macros from the ICD16 debugger, type at the ICD16 debug
window prompt:
>macs
This command opens a window containing a list of macros with the .ICD
extension. Use the arrow keys to highlight and the <return> key to select
the initialization macro: MPBX1.ICD. MPBX1.ICD sets up the MEVB for
basic operation. The macro file enables the maximum system clock
frequency and disables the software watchdog while enabling the bus
monitor. CSBOOT is set to zero-wait state and the block size set to 64K
starting at $00000. The SRAM is enabled to reside at $10000 with the
stack pointer initialized at $103FE and the instruction pointer (IP)
initialized to $00200 (PK=0, IP=200).
7. Load your program at address $00200.
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Below is the MPBX1.ICD initialization macro program listing.
symbol SCIMCR FFA00
symbol SYNCR FFA04
symbol SYPCR FFA21
symbol CSBARBT FFA48
symbol CSORBT FFA4A
symbol START 00200
dmmw SCIMCR 40CF
dmmb SYNCR 7F
dmmb SYPCR 04
dmmw CSBARBT 0003
dmmw CSORBT 7830
mdf6 START
pk=0
a=AA
b=BB
e=0000
ix=0000
iy=0000
iz=0000
hr=0000
ir=0000
k=0000
sp=03fe
sk=1
symbol TRAMBAR FFB04
symbol TRAMMCR FFB00
dmmb TRAMBAR 01
dmmb TRAMMCR 00
dmml 10000 4D6F746F
dmml 10004 726F6C61
dmml 10008 20363848
dmml 1000C 43313620
dmml 10010 41647661
dmml 10014 6E636564
dmml 10018 20204D43
dmml 1001C 55732020
dmml 10020 36384843
mdf3 10000
ip=START
M68MPB916X1UM/D
Set module mapping to $FFF000-$FFFFFF
Set system clock frequency to 16.78 MHz
Turn off software watchdog timer
Change CSBOOT block size to 64K
Change wait state to zero
Display program in PMM window
Initialize CPU registers
Initialize the stack pointer
Set SRAM base address
Enable SRAM array
Check SRAM: write Motorola 68HC16 advanced MCUs
Display SRAM in DMM window
Start entering your program here
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MEVB QUICK START GUIDE
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MEVB SUPPORT INFORMATION
CHAPTER 4
MEVB SUPPORT INFORMATION
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4.1 INTRODUCTION
This chapter’s information is pertains to using the MPB in an MEVB (the MPB
installed on a MPFB). Signals on the MPFB logic analyzer connectors are defined
by the MPB type.
4.2 LOGIC ANALYZER CONNECTOR SIGNALS
The tables of this chapter describe MPFB logic analyzer connector signals if you
install an M68MPB916X1 on the MPFB. The signal descriptions on J12 – J20 are
the logic analyzer pin-outs on the plastic overlay supplied with the MPB.
NOTE
The signal descriptions in the following tables are for quick
reference only. The MC68HC916X1 User's Manual,
MC68HC916X1UM/AD, contains a complete description of the
MC68HC916X1 MCU signals.
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Table 4-1. Logic Analyzer Connector J7 Pin Assignments
PIN
MNEMONIC
SIGNAL
1, 2
SPARE
No connection
3
OE(ALL)
I/O PRU OUTPUT ENABLE – Input, active high; when
low disables all PRU outputs.
4 – 11
PEPAR7 –
PEPAR0
PEPAR OUTPUTS – Output signals that show the
complement (negated contents) of the PEPAR register.
12 – 19
PE7 – PE0
PORT E I/O SIGNALS – PRU replacement of the port
E function.
20
GND
GROUND
Table 4-2. Logic Analyzer Connector J8 Pin Assignments
4-2
PIN
MNEMONIC
SIGNAL
1, 2
SPARE
3
OE(ABG)
I/O PRU OUTPUT ENABLE – Input, active high; when
low disables port A, port B, and port G outputs.
4 – 11
PA7 – PA0
PORT A I/O SIGNALS – PRU replacement of the port
A function.
12 – 19
PB7 – PB0
PORT B I/O SIGNALS – PRU replacement of the port
B function.
20
GND
No connection
GROUND
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Table 4-3. Logic Analyzer Connector J9 Pin Assignments
PIN
MNEMONIC
SIGNAL
1, 2
SPARE
No connection
3
OE(H)
I/O PRU OUTPUT ENABLE – Input, active high; when
low disables the port H outputs.
4 – 11
PH7 – PH0
PORT H I/O SIGNALS – PRU replacement of the port
H function.
12 – 19
PG7 – PG0
PORT G I/O SIGNALS – PRU replacement of the port
G function.
20
GND
GROUND
Table 4-4. Logic Analyzer Connector J10 Pin Assignments
PIN
MNEMONIC
SIGNAL
1
+5V
+5 VDC POWER – Input voltage (+5 Vdc @ 1.0 A)
used by the MEVB logic circuits. (To make this pin no
connection, remove the jumper from the header on the
MPFB.)
2
SPARE
3
AS
4 – 19
20
M68MPB916X1UM/D
A15 – A0
GND
No connection
ADDRESS STROBE – Active-low output signal that
indicates whether a valid address is on the address
bus.
ADDRESS BUS BITS 15 – 0 – Sixteen bits of the 24-bit
address bus.
GROUND
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Table 4-5. Logic Analyzer Connector J11 Pin Assignments
PIN
MNEMONIC
SIGNAL
1
+5V
+5 VDC POWER – Input voltage (+5 Vdc @ 1.0 A)
used by the MEVB logic circuits. (To make this pin no
connection, remove the jumper from the header on the
MPFB.)
2
SPARE
3
DS
DATA STROBE – Active-low output signal. During a
read cycle, indicates that an external device should
place valid data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
4 – 19
D15 – D0
DATA BUS 15 – 0 – 16 bits of the MCU bi-directional
data bus lines.
20
GND
No connection
GROUND
Table 4-6. Logic Analyzer Connector J12 Pin Assignments
PIN
MNEMONIC
1, 2
SPARE
3
CLKOUT
4
BERR
BUS ERROR – Active-low signal that indicates a
memory access error has occurred.
5
BKPT /
BREAKPOINT – Active-low input signal that signals a
hardware breakpoint to the CPU.
DSCLK
Development Serial Clock – Clock input signal for
background debug mode.
6
FREEZE
QUOT
7
4-4
LAT-DSO /
(Latched
IPIPE0)
SIGNAL
No connection
SYSTEM CLOCK OUT – Output signal that is the MCU
internal system clock.
FREEZE – Output signal that indicates the CPU has
acknowledged a breakpoint.
QUOTIENT OUT – Output signal that furnishes the
quotient bit of the polynomial divider for test purposes.
LATCHED INSTRUCTION PIPE 0 – Latched output
signal of the first state of IPIPE0 for CPU16-based
MCUs; indicates instruction pipeline activity.
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Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued)
PIN
8
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9
MNEMONIC
LAT-DSI
LATCHED INSTRUCTION PIPE 1 – Latched output
(Latched IPIPE1) signal of the first state of IPIPE1 for CPU16-based
MCUs; indicates instruction pipeline activity.
DSO /
(IPIPE0)
10
SIGNAL
DSI /
DEVELOPMENT SERIAL OUT – Serial data output
signal for background debug mode.
INSTRUCTION PIPE 0 for CPU16-based MCUs.
DEVELOPMENT SERIAL IN – Serial data input signal
for background debug mode.
(IPIPE1)
INSTRUCTION PIPE 1 for CPU16-based MCUs.
11
DSACK1
DATA AND SIZE ACKNOWLEDGE 1 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and external
devices.
12
PULL-UP
Not connected; pulled high through a resistor on the
MPB.
13
FC2 /
FUNCTION CODE 2 – Output signal that identifies the
processor state and address space of the current bus
cycle.
CS5
CHIP SELECT 5 – Output signal that selects peripheral
or memory devices at programmed addresses.
14
FC1
FUNCTION CODE 1 – Output signal that identifies the
processor state and address space of the current bus
cycle.
15
FC0 /
FUNCTION CODE 0 – Output signal that identifies the
processor state and address space of the current bus
cycle.
CS3
CHIP SELECT 3 – Output signal that selects peripheral
or memory devices at programmed addresses.
SIZ1
TRANSFER SIZE – Active-high output signals that
Indicates the number of bytes to be transferred during
a bus cycle.
16
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Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued)
PIN
MNEMONIC
SIGNAL
17
SIZ0
TRANSFER SIZE – Active-high output signals that
indicates the number of bytes to be transferred during a
bus cycle.
18
R/W
READ/WRITE – Active-high output signal that indicates
the direction of data transfer on the bus.
19
BGACK /
20
BUS GRANT ACKNOWLEDGE – Active-low input
signal that indicates an external device has assumed
bus mastership.
CSE
EMULATOR CHIP SELECT – Active-low output signal
that selects external emulation devices at internallymapped addresses. CSE is used to emulate I/O ports.
GND
GROUND
Table 4-7. Logic Analyzer Connector J13 Pin Assignments
4-6
PIN
MNEMONIC
SIGNAL
1
+5V
+5 VDC POWER – Input voltage (+5 Vdc @ 1.0 A)
used by the MEVB logic circuits. (To make this pin no
connection, remove the jumper from the header on the
MPFB.)
2
SPARE
3
DSACK1
DATA AND SIZE ACKNOWLEDGE 1 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and external
devices.
4, 5
PULL-UP
Not connected; pulled high through a resistor on the
MPB.
6
AS
ADDRESS STROBE – Active-low output signal that
indicates a valid address is on the address bus.
7
DS
DATA STROBE – Active-low output signal. During a
read cycle, indicates that an external device should
place valid data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
No connection
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Table 4-7. Logic Analyzer Connector J13 Pin Assignments (continued)
PIN
MNEMONIC
SIGNAL
8
BR /
BUS REQUEST – Active-low input signal that indicates
an external device requires bus mastership.
CS0
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9
CHIP SELECT 0 – Output signal that selects peripheral
or memory devices at programmed addresses.
BG /
BUS GRANT – Active-low output signal that indicates
the MCU has relinquished the bus.
CSM
INTERNAL MODULE CHIP SELECT – CSM is not
supported on the M68HC916X1 MCU.
10
PULL-UP
Not connected; pulled high through a resistor on the
MPB.
11
CLKOUT
SYSTEM CLOCK OUTPUT – MCU internal clock
output signal.
12
A23 /
ADDRESS BUS BIT 23 – One bit of the 24-bit address
bus.
CS10
CHIP SELECT 10 – Output signal that selects
peripheral or memory devices at programmed
addresses.
13 – 15
PULL-UP
16
A19 /
ADDRESS BUS BIT 19 – One bit of the 24-bit address
bus.
CS6
CHIP SELECT 6 – Output signal that selects peripheral
or memory devices at programmed addresses.
17 – 19
A18 – A16
20
GND
M68MPB916X1UM/D
Not connected; pulled high through a resistor on the
MPB.
ADDRESS BUS 18 – 16 – Three bits of the 24-bit
address bus.
GROUND
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Table 4-8. Logic Analyzer Connector J14 Pin Assignments
PIN
MNEMONIC
SIGNAL
1, 2
SPARE
3
PULL-UP
Not connected; pulled high through a resistor on the
MPB.
4
MODCLK
CLOCK MODE SELECT – Input signal that configures
the MCU internal clock at reset.
5
TSC
THREE STATE CONTROL – When TSC is logic high,
this input signal forces all output drivers to a highimpedance state.
6
RESET
RESET – Active-low, bi-directional signal that starts a
system reset.
7
PULL-UP
8
SPARE
9, 10
IRQ6, IRQ7
11 – 15
GND
16 – 19
SPARE
20
GND
No connection
Not connected; pulled high through a resistor on the
MPB.
No connection
TARGET INTERRUPT REQUEST 6, 7 - Active-low
input signals from the target that asynchronously
provides an interrupt priority level to the CPU. IRQ1
has the lowest priority, IRQ7 has the highest.
GROUND
No connection
GROUND
Table 4-9. Logic Analyzer Connector J15 Pin Assignments
4-8
PIN
MNEMONIC
1–3
SPARE
4 – 17
GND
18, 19
SPARE
20
GND
SIGNAL
No connection
GROUND
No connection
GROUND
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Table 4-10. Logic Analyzer Connector J16 Pin Assignments
PIN
MNEMONIC
1–4
SPARE
5 – 12
VSSA
13 – 19
SPARE
20
VSSA
SIGNAL
No connection
A/D GROUND – A/D ground reference.
No connection
A/D GROUND – A/D ground reference.
Table 4-11. Logic Analyzer Connector J17 Pin Assignments
PIN
MNEMONIC
1–4
SPARE
5–8
VSSA
A/D GROUND – A/D ground reference.
9
VRH
VOLTAGE REFERENCE HIGH – Input reference
supply voltage (high) line (must set jumper on the
MPB).
10
VRL
VOLTAGE REFERENCE LOW – Input reference
supply voltage (low) line (must set jumper on the MPB).
11
AN0
ANALOG INPUT 0 – Analog input line to the MCU
device.
12
AN1 – AN5
17 – 19
SPARE
20
VSSA
M68MPB916X1UM/D
SIGNAL
No connection
ANALOG INPUT 1 - 5 – Analog input lines to the MCU
device.
No connection
A/D GROUND – A/D ground reference.
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Table 4-12. Logic Analyzer Connector J18 Pin Assignments
PIN
MNEMONIC
1–4
SPARE
5 – 13
GND
14 – 16
IC1 – IC3
17 – 19
SPARE
20
GND
SIGNAL
No connection
GROUND
INPUT CAPTURE 1 - 3 – Input signals that latch the
contents of the GPT timer counter (TCNT) into the
input capture registers TIC1 - TIC3 when a selected
edge occurs at the pin.
No connection
GROUND
Table 4-13. Logic Analyzer Connector J19 Pin Assignments
4-10
PIN
MNEMONIC
1–4
SPARE
5–8
OC1 – OC4
9
IC4 /
INPUT CAPTURE 4 – Input signal that latches the
contents of the GPT timer counter (TCNT) into the
input capture register TI4O5 when a selected edge
occurs at the pin.
OC5
OUTPUT COMPARE 5 – Output signal that is
generated when the GPT timer counter (TCNT) and
TI4O5 comparator register contain the same value.
10, 11
PWMA,
PWMB
12
PAI
13 – 19
SPARE
20
GND
SIGNAL
No connection
OUTPUT COMPARE 1 - 4 – Output signals that are
generated when the GPT timer counter (TCNT) and
TOC1 - TOC4 comparator registers contain the same
value.
PULSE WIDTH MODULATION A and B – Repetitive
output signals whose high time to low time ratio can be
controlled by the CPU.
PULSE ACCUMULATOR INPUT – Input signal that
increments an 8-bit counter.
No connection
GROUND
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Table 4-14. Logic Analyzer Connector J20 Pin Assignments
PIN
MNEMONIC
1–4
SPARE
5–8
GND
GROUND
9
MISO
MASTER-IN, SLAVE-OUT – Serial input to SPI in
master mode; serial output from SPI in slave mode.
10
MOSI
MASTER-OUT, SLAVE-IN – Serial output from SPI in
master mode; serial input to SPI in slave mode.
11
SCK
SPI SERIAL CLOCK – In master mode, the clock
signal from the SPI; in slave mode the clock signal to
the SPI.
12
PCS0 /
SS
SIGNAL
No connection
PERIPHERAL CHIP SELECT 0 – Active-low output
SPI peripheral chip select signal.
SLAVE SELECT – Bi-directional, active-low signal that
initiates serial transmission when SPI is in slave mode;
causes mode fault in master mode.
13 – 15
PCS1 – PCS3
PERIPHERAL CHIP SELECT 1 – 3 – Active-low
output SPI peripheral chip select signal.
16
RXD
RECEIVE DATA – RS-232C serial data input line.
17
TXD
TRANSMIT DATA – Serial data output line.
18
PCLK
19
SPARE
20
GND
M68MPB916X1UM/D
AUXILIARY TIMER CLOCK INPUT – External input
clock source to the GPT.
No connection
GROUND
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MEVB SUPPORT INFORMATION
4-12
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M68MPB916X1UM/D
Freescale Semiconductor, Inc.
MAPI SUPPORT INFORMATION
CHAPTER 5
MAPI SUPPORT INFORMATION
Freescale Semiconductor, Inc...
5.1 INTRODUCTION
This chapter information pertains to installing the MPB on a target system. The
figures in this chapter show the MAPI interface connector layout and pin
assignments for MPB connectors P1, P2, P3, and P4 (Figures 5-1 through 5-5).
5.2 MAPI BUS CONNECTORS
The connectors required to interface to the MAPI bus are:
2
Robinson Nugent
2 X30 plugs
P50L-060P-AS-TGF
2
Robinson Nugent
2 X40 plugs
P50L-080P-AS-TGF
CL
1
1
1
2.500
CL
1.250
CL
1
CL
CL
CL
1.250
2.500
Figure 5-1. MAPI Interface Connector Layout
M68MPB16X1UM/D
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5-1
Freescale Semiconductor, Inc.
MAPI SUPPORT INFORMATION
Freescale Semiconductor, Inc...
AN1
AN2
AN3
AN4
AN5
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CS10*
CS9*
CS8*
CS7*
CS6*
CS5*
CS4*
CS3*
CS2*
CS1*
CS0*
CSBOOT*
+5Vdc
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
Figure 5-2. MAPI Interface Connector P1 Pin Assignments
5-2
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Freescale Semiconductor, Inc.
MAPI SUPPORT INFORMATION
Freescale Semiconductor, Inc...
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
GND
NC
GND
A1
A3
A5
A7
A9
A10
A12
A14
A16
A18
VPP
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
AN0
MAPI-VRL
MAPI-VRH
VSSA
VSSA
VSSA
VSSA
GND
+5 Vdc
GND
A2
A4
A6
A8
GND
A11
A13
A15
A17
GND
+5 Vdc
GND
GND
GND
GND
GND
GND
GND
GND
GND
Figure 5-3. MAPI Interface Connector P2 Pin Assignments
M68MPB16X1UM/D
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MAPI SUPPORT INFORMATION
Freescale Semiconductor, Inc...
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MAPI-EXTAL
GND
GND
+5 Vdc
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
GND
IC1
IC2
IC3
OC1
OC2
OC3
OC4
IC4/OC5
PWMA
PWMB
PAI
PCLK
TXD
RXD
PCS3*
PCS2*
PCS1*
PCS0*/SS*
SCK
MOSI
MISO
GND
GND
GND
GND
VSTBY
DSO
DSI
HALT*
RESET*
BERR*
BKPT*
TSC
FREEZE
GND
GND
CLKOUT
GND
+5 Vdc
Figure 5-4. MAPI Interface Connector P3 Pin Assignments
5-4
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M68MPB16X1UM/D
Freescale Semiconductor, Inc.
MAPI SUPPORT INFORMATION
Freescale Semiconductor, Inc...
+5 Vdc
GND
D1
D3
D5
D7
D8
D10
D12
D14
GND
A0
DSACK0*
DSACK1*
AVEC*
PMC*
DS*
AS*
SIZ0
SIZ1
R/W*
MODCLK
IRQ6*
IRQ7*
GND
GND
GND
GND
GND
+5 Vdc
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
n n
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
+5 Vdc
D0
D2
D4
D6
GND
D9
D11
D13
D15
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
Figure 5-5. MAPI Interface Connector P4 Pin Assignments
M68MPB16X1UM/D
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Freescale Semiconductor, Inc...
MAPI SUPPORT INFORMATION
5-6
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M68MPB16X1UM/D
Freescale Semiconductor, Inc.
SCHEMATIC DIAGRAMS
CHAPTER 6
SCHEMATIC DIAGRAMS
Freescale Semiconductor, Inc...
6.1 INTRODUCTION
This chapter contains the M68MPB16Y1 MCU Personality Board (MPB)
schematic diagrams. These schematic diagrams are for reference only and may
deviate slightly from the circuits on your MPB.
M68MPB916X1UM/D
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6-1
D
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4
ZONE
O
A
REV
DATE:
10/05/92
R.E.
PROJECT LEADER:
R.E.
3
10/05/92
DATE:
10/05/92
R.E.
GEDABV: MPB916X1C
GEDTTL: BOARD
2
AUSTIN, TEXAS 78735
9 11:29:14 1994
1
A
REV:
USA
R.E.
APPROVED
SHEET 1 OF 8
63ASE90344W
DWG. NO.
SCHEMATIC MPB916X1C
LAST_MODIFIED=Fri Sep
A
SIZE
TITLE:
6501 WILLIAM CANNON DRIVE WEST
MICROPROCESSOR AND MEMORY
TECHNOLOGIES GROUP
10/05/92
09/09/94
DATE
1
C
D
A
A
DESIGN ENGINEER:
DATE:
INDUCTOR SIZE, TANTALUM CAP VOLTAGES.
REMOVED RC FILTER FROM A/D, CHANGED
ORIGINAL RELEASE
DESCRIPTION
REVISIONS
63ASE90344W
DRAWN BY:
MOTOROLA RESERVES THE RIGHT TO MAKE
CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN.
MOTOROLA DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN.
TITLE & REVISION STATUS
NOTES
BYPASS CAPACITORS, CLEAN POWER & SIGNAL FILTERS
MODULAR ACTIVE PROBE INTERCONNECT P1 & P3
MODULAR ACTIVE PROBE INTERCONNECT P2 & P4
MCU & CLOCK
PULLUPS/PULLDOWNS/PERSONALITY ID
SIGNAL CROSS REFERENCES
TABLE OF CONTENTS
Freescale
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2
DWG. NO.
A
B
C
1
2
3
4
5
6
7
8
4
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4
GEDABV: MPB916X1C
GEDTTL: BOARD
2
LAST_MODIFIED=Fri Sep
A
9 10:44:58 1994
1
A
REV:
SHEET 2 OF 8
63ASE90344W
DWG. NO.
NOTES
C
D
A
A
SIZE
DEVICE TYPE NUMBER IS FOR REFERENCE
ONLY. THE NUMBER VARIES WITH THE
MANUFACTURER.
SPECIAL SYMBOL USAGE:
* DENOTES - ACTIVE LOW SIGNAL.
<> DENOTES - VECTORED SIGNALS.
INTERPRET DIAGRAM IN ACCORDANCE
WITH AMERICAN NATIONAL STANDARDS
INSTITUTE SPECIFICATIONS, CURRENT
REVISION, WITH THE EXCEPTION OF
LOGIC BLOCK SYMBOLOGY.
CODE FOR SHEET TO SHEET REFERENCES
IS AS FOLLOWS:
5 C7 < >
OUTPUT
SHEET
INPUT
ZONE
VCC LOCATIONS
UNLESS OTHERWISE SPECIFIED, VCC IS APPLIED TO:
PIN 8 OF ALL 8-PIN ICS
PIN 14 OF ALL 14-PIN ICS
PIN 16 OF ALL 16-PIN ICS
PIN 20 OF ALL 20-PIN ICS, ETC.
GROUND LOCATIONS
UNLESS OTHERWISE SPECIFIED, GROUND IS APPLIED TO:
PIN 4 OF ALL 8-PIN ICS
PIN 7 OF ALL 14-PIN ICS
PIN 8 OF ALL 16-PIN ICS
PIN 10 OF ALL 20-PIN ICS, ETC.
1
63ASE90344W
3
8.
7.
6.
5.
4.
3.
NOTES:
1.
UNLESS OTHERWISE SPECIFIED:
ALL RESISTORS ARE IN OHMS, 5%, 1/8 WATT.
ALL CAPACITORS ARE IN UF. 50V.
ALL VOLTAGES ARE DC.
2.
INTERRUPTED LINES CODED WITH THE
SAME LETTER OR LETTER COMBINATIONS
ARE ELECTRICALLY CONNECTED.
Freescale
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2
DWG. NO.
A
B
C
4
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REV:
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VRL
MAPI-VRL
5C1>
MAPI-VRH
5C1>
6B4<
VRH
6B4<
GND
ADC MODULE
GND
C64
1 0.1UF
2
GND
C59
1 0.1UF
2
4
C9
C10
0.1UF
C65
VSSA
VDDA
GND
W4
1
2
3
W3
1
2
3
1 0.1UF
2
GND
C60
1 0.1UF
2
C66
GND
3
1 0.1UF
2
VSSA
1 0.1UF
VSSA
2
1 0.1UF
C5
1
1
L3
1UH
L4
2
2
VSSA
ADC MODULE
TANT
+ 1 C55
10UF
2 25V
E1
ADC MODULE
1
1 2
W2
(CUT TRACE ON BOARD)
C53
1 0.1UF
2
TANT
+ 1 C8
10UF
2 25V
C3
C6
C4
VSSA
1 0.1UF
2
C2
VSSA
1 0.1UF
2
C11
1 0.1UF
2
C54
VSSA
VDDA
VSSI
1 0.1UF
2
VDDI
AN<5..0>
GEDABV: MPB916X1C
GEDTTL: BOARD
2
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A
SIZE
9 11:23:46 1994
1
SHEET 3 OF 8
63ASE90344W
DWG. NO.
A
REV:
4C4> 5C1> 6B4<
C
D
A
A
BYPASS CAPACITORS, CLEAN POWER & SIGNAL FILTERS
VSSA
1 0.1UF
2
AN<5>
AN<4>
AN<3>
AN<2>
AN<1>
AN<0>
ANALOG SIGNAL FILTERS
1 0.1UF
2
2
FERRITE BEAD
1
L1
1UH
2
VDDA/VSSA GENERATION
TANT
C12
10UF
25V
1
L5
VDDI/VSSI GENERATION
FERRITE BEAD
2
C7
VSSI
VDDI
GND
+ 1 C1
+ 1
10UF
2 25V
2
TANT
+5V
1
63ASE90344W
VSSA
2
1
VSSA
1 0.1UF
2
VRH & VRL SELECTION
GND
1 0.1UF
1 0.1UF
C62
2
2
C61
GND
C58
1 0.1UF
C56
1 0.1UF
GND
2
2
FOR VDDE OF MCU AND OSCILLATOR
+5V AND GND DECOUPLING
Freescale
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2
DWG. NO.
A
B
C
+5V
4
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7C1>
CSBOOT*
CS<10..0>*
AN<5..0>
4
+5V
CS<10>*
CS<9>*
CS<8>*
CS<7>*
CS<6>*
CS<5>*
CS<4>*
CS<3>*
CS<2>*
CS<1>*
CS<0>*
VSSA
AN<1>
AN<2>
AN<3>
AN<4>
AN<5>
GND
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
11
13
15
17
19
21
23
25
1
3
5
7
9
A
N
A
L
O
G
#
1
A
N
A#
L2
O
G
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND2
GND2
GND2
GND2
GND2
3
RN P50L-080S-BS-TGF
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
CS10
GND
CS9
GND
CS8
GND
CS7
GND
CS6
GND
CS5
GND
CS4
GND
CS3
GND
CSE/2
GND
CSM/1
GND
CS0
CSBOOT GND
VDD
VPP1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
12
14
16
18
20
22
24
26
2
4
6
8
10
GND
MAPI BUS P1
NC
VSSA
VSSA
GND
+5V
GND
GND
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
9
11
13
15
17
19
21
23
1
3
5
7
A
N
A
L
O
G
#
4
A
N
A#
L3
O
G
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
10
12
14
16
18
20
22
24
2
4
6
8
GND
+5V
OC4
OC3
OC2
OC1
IC3
IC2
IC1
6D1>
6C4>
6A1<
CLKOUT
MAPI-EXTAL
6D1<
6D1<
6C4<
BKPT*
FREEZE
6C4<>
BERR*
TSC
7C4<
RESET*
6D1<>
HALT*
6D1>
DSI
GEDABV: MPB916X1C
GEDTTL: BOARD
2
LAST_MODIFIED=Fri Sep
A
9 11:33:36 1994
1
A
REV:
SHEET 4 OF 8
63ASE90344W
DWG. NO.
7B1<
7B1<
7B1<
7C1<
7C1<
7B4<
7B4<
7B4<
7B4<
7B4<
7A4<
7C4<
7C4<
7C4<
7B4<
7B4<
7B4<
7B4<
7B4<
C
D
A
A
SIZE
6C1<>
6C1<>
6B1<>
6B1<>
6B1<>
6B1<>
6B1<>
6B1<>
6B1>
6B1>
6B1<
6B1<
6B4<>
6B4<
6B4<>
6B4<>
6B4<>
6B4<>
6B4<>
6C4<>
6C4<>
6C1<
DSO
VSTBY
MISO
MOSI
SCK
PCS0/SS*
PCS1*
PCS2*
PCS3*
RXD
TXD
PCLK
PAI
PWMB
PWMA
IC4/OC5
1
63ASE90344W
MODULAR ACTIVE PROBE INTERCONNECT P1 & P3
RN P50L-080S-BS-TGF
GND
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
VSTBY
GND
DSO
GND
DSI
GND
HALT
GND
RESET
GND
BERR
GND
BKPT
GND
TSC
GND
GND FREEZE
GND
GND
GND
EXTAL
GND CLKOUT
GND
GND
VDD
VDD
GND4
GND4
GND4
GND4
GND4
GND4
GND4
GND4
GND3
GND3
GND3
GND3
P3
MAPI BUS P3
Freescale
Semiconductor,
Inc...
3
2
DWG. NO.
A
B
C
6D1<>
5C1> 3B1>
6B4<
4
Freescale Semiconductor, Inc.
REV:
D
For More Information On This Product,
Go to: www.freescale.com
SIZ0
SIZ1
6D4<>
6C4<>
MODCLK
IRQ<6>*
IRQ<7>*
6D4<>
7C4<
6D4<>
7A4<
6D4<>
7A4<
R/W*
AS*
6D4<>
6C4>
DS*
6D4<>
4
A<0>
D<1>
D<3>
D<5>
D<7>
D<8>
D<10>
D<12>
D<14>
GND
+5V
45
47
49
51
53
55
57
59
23
25
27
29
31
33
35
37
39
41
43
1
3
5
7
9
11
13
15
17
19
21
GND
GND
GND
GND
GND
GND
GND
VPP4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
D0
D2
D4
D6
GND
D9
D11
D13
D15
GND
3
RN P50L-060S-BS-TGF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
A0
DSACK0
DSACK1
AVEC
RMC
DS
AS
SIZ0
SIZ1
R/W
MODCLK
VDD
GND
D1
D3
D5
D7
D8
D10
D12
D14
GND
P4
46
48
50
52
54
56
58
60
24
26
28
30
32
34
36
38
40
42
44
2
4
6
8
10
12
14
16
18
20
22
GND
NC
D<9>
D<11>
D<13>
D<15>
D<0>
D<2>
D<4>
D<6>
+5V
MAPI BUS P4
GND
VSSA
A<1>
A<3>
A<5>
A<7>
A<9>
A<10>
A<12>
A<14>
A<16>
A<18>
GND
NC
45
47
49
51
53
55
57
59
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
1
3
5
7
9
11
13
A
N
A
L
O
G
#
3
A
N
A
L
O
G
#
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VDD
GND
A2
A4
A6
A8
GND
A11
A13
A15
A17
GND
VDD
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
46
48
50
52
54
56
58
60
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
2
4
6
8
10
12
14
GND
A<11>
A<13>
A<15>
A<17>
A<2>
A<4>
A<6>
A<8>
VSSA
AN<0>
VPP
MAPI-VRH
MAPI-VRL
AN<5..0>
1
6B1<
3B4<
3B4<
GEDABV: MPB916X1C
GEDTTL: BOARD
2
LAST_MODIFIED=Fri Sep
A
9 11:23:57 1994
1
SHEET 5 OF 8
63ASE90344W
DWG. NO.
A
C
A
A
SIZE
REV:
3B1> 4C4> 6B4<
D
63ASE90344W
MODULAR ACTIVE PROBE INTERCONNECT P2 & P4
RN P50L-060S-BS-TGF
GND3
GND3
GND3
GND3
GND3
GND3
GND3
GND3
GND
VPP2
GND
A1
A3
A5
A7
A9
A10
A12
A14
A16
A18
VPP3
GND
GND2
GND2
GND2
GND2
GND2
GND2
GND2
P2
+5V
MAPI BUS P2
Freescale
Semiconductor,
Inc...
3
2
DWG. NO.
A
B
C
RMC*
DSACK1*
6D4<>
7C4<
DSACK0*
7C4<
AVEC*
D<15..0>
6D4<>
7C4<
A<18..0>
7D1> 6D1>
4
Freescale Semiconductor, Inc.
REV:
D
For More Information On This Product,
Go to: www.freescale.com
3B1>
4C4>
5C1>
3B4>
3B4>
4B1<>
7A4<
4B1<>
7B4<
4B1<>
7B4<
4C1<>
7B4<
4C1<>
7B4<
4C1<>
7B4<
4C1<>
7C1<
4C1<>
7B1<
4C1>
4B1<>
DS*
5C4<>
5C4<>
5C4<>
5C4<>
5C4<
4A1<
4B1>
AN<5..0>
VRL
VRH
RXD
TXD
PCS3*
PCS2*
PCS1*
PCS0/SS*
SCK
MOSI
MISO
RESET*
BERR*
CLKOUT
R/W*
SIZ1
SIZ0
AS*
DSACK1*
5C4<>
4
1
1UH
L2
2
VSSI
C63
2 X.XUF
C51
1 0.1UF
VSSI
1
2
XFC
45
49
47
16
75
101
VSSI
VSSA
3
4
1
120
2
119
118
117
116
115
55
62
61
60
59
58
57
56
54
63
VSSI
VSSI
VSSI
VDDSYN
XFC
VSSI
VDDA
VRH
VRL
AN0/PADA0
AN1/PADA1
AN2/PADA2
AN3/PADA3
AN4/PADA4
AN5/PADA5
---/-------/----VSSA
RXD
M
O
D
U
L
E
A
D
C
MISO
/PQS0
MOSI
/PQS1
SCK
/PQS2
PCS0*/SS*/PQS3
PCS1*
/PQS4
PCS2*
/PQS5
PCS3*
/PQS6
TXD
/PQS7
RESET*
Q
S G
M P
T
M
O M
D O
U D
L U
E L
E
3
2) THE CAP BETWEEN XFC & VSSI IS OPTIONAL.
A0
A1
A2
PB0/ A3
PB1/ A4
PB2/ A5
PB3/ A6
PB4/ A7
PB5/ A8
PB6/ A9
PB7/A10
PA0/A11
PA1/A12
PA2/A13
PA3/A14
PA4/A15
PA5/A16
PA6/A17
PA7/A18
VDDI
VDDE
VDDE
VDDE
VDDE
VSSE
VSSE
VSSE
VSSE
VSSE
VSSE
VSSE
VSSE
XTAL
EXTAL
VFPE 2K
VFPE32K
PGP0/
IC1
PGP1/
IC2
PGP2/
IC3
PGP3/
OC1
PGP4/
OC2
PGP5/
OC3
PGP6/
OC4
PGP7/IC4/OC5
PAI
PWMA
PWMB
PCLK
VSTBY
IPIPE1/DSI
IPIPE0/DSO
DSCLK/BKPT
FREEZE
TSC
-------
BR*/ CS0*
BG*/ CSM*
BGACK*/ CSE*
PC0/FC0/ CS3*
PC1/FC1/ ---PC2/FC2/ CS5*
PC3/A19/ CS6*
---/---/-------/---/-------/---/----E/A23/CS10*
SCIM INTERFACE
MC68HC916X1
FOR THE
SOCKET
CLAM SHELL
-------/--DSACK1*/PE1
-------/---------/--DS*
/PE4
AS*
/PE5
SIZ0
/PE6
SIZ1
/PE7
R/W*
CLKOUT
BERR*
U1
YAMAICHI
MODCLK/PF0
------/--------/--------/--------/--------/--IRQ6* /PF6
IRQ7* /PF7
D0 /PH0
D1 /PH1
D2 /PH2
D3 /PH3
D4 /PH4
D5 /PH5
D6 /PH6
D7 /PH7
D8 /PG0
D9 /PG1
D10/PG2
D11/PG3
D12/PG4
D13/PG5
D14/PG6
D15/PG7
VDDI
VDDE
VDDE
VDDE
VDDE
+5V
GEDABV: MPB916X1C
GEDTTL: BOARD
2
Y1
8 OUT14
11 OUT8
SMT-SO
9 11:38:12 1994
4A1>
5B1>
4D1<> 7C4<
4D1<> 7C4<
4C1<> 7C4<
4C1<> 7B4<
4C1<> 7B4<
4C1<> 7B4<
4C1<> 7B4<
4C1<> 7B4<
4C1>
4C1< 7B1<
4C1< 7B1<
4C1>
4B1<>
4B1<
4B1>
4A1<
4B1>
4B1>
4B4< 7C4<
5D4< 7D1>
8 OR 14 PIN CANS / DIPS.
14 PIN DIP SOCKET FOR
MAPI-EXTAL
VPP
PCLK
PWMB
PWMA
PAI
IC4/OC5
OC4
OC3
OC2
OC1
IC3
IC2
IC1
VSTBY
TSC
FREEZE
BKPT*
DSO
DSI
CS<10..0>*
A<18..0>
1
A
REV:
SHEET 6 OF 8
63ASE90344W
DWG. NO.
C68
0.1UF
XTALOSC
GND
1
2
MCU & CLOCK
2
W1
C67
0.1UF
MCUEXTAL 3
1
GND
1
2
LAST_MODIFIED=Fri Sep
A
SIZE
GND
107
94
81
66
51
36
23
5
44 NC
46
28
114
29
30
31
32
33
35
37
38
39
40
41
42
43
112
113
111
53
65
CS<10>*
CS<0>*
CS<1>*
CS<2>*
CS<3>*
CS<4>*
CS<5>*
CS<6>*
99
102
103
104
105
106
108
110
A<0>
A<1>
A<2>
A<3>
A<4>
A<5>
A<6>
A<7>
A<8>
A<9>
A<10>
A<11>
A<12>
A<13>
A<14>
A<15>
A<16>
A<17>
A<18>
VDDI
78
6
8
9
10
11
12
13
14
15
17
18
19
20
22
24
25
26
27
100
21
50
83
109
C
D
A
A
VSSI
TANT
+ 1 C52
1UF
2 25V
C57
2 0.1UF
1
VDDA
AN<0>
AN<1>
AN<2>
AN<3>
AN<4>
AN<5>
VDDSYN
33
1
71
52
64
76
74
73
72
77
69
67
70
98
97
96
95
93
91
90
89
88
87
86
85
84
82
80
79
48
7
34
68
92
1
63ASE90344W
NOTE: 1) PLACE THE CAP BETWEEN VDDSYN & XFC AS CLOSE TO MCU PINS AS POSSIBLE.
VDDI
2
R51
IRQ <6>*
IRQ <7>*
D<0>
D<1>
D<2>
D<3>
D<4>
D<5>
D<6>
D<7>
D<8>
D<9>
D<10>
D<11>
D<12>
D<13>
D<14>
D<15>
VDDI +5V
Freescale
Semiconductor,
Inc...
3
2
DWG. NO.
A
B
C
MODCLK
5B4<>
7C4<
5B4<>
7A4<
IRQ<7..6>*
D<15..0>
5C4<>
4
Freescale Semiconductor, Inc.
REV:
D
For More Information On This Product,
Go to: www.freescale.com
IC1
6D1<>
4D1<>
6C1<>
4D1<>
6C1<>
4C1<>
6B1<>
4C1<>
6B1<>
4C1<>
6B1<>
4C1<>
6B1<>
4C1<>
6B1<>
4C1<>
6B1<>
IRQ<7..6>*
MISO
MOSI
SCK
PCS0/SS*
PCS1*
PCS2*
IC4/OC5
OC4
OC3
OC2
OC1
IC3
4
3
IRQ<6>*
IRQ<7>*
CS<7>*
CS<8>*
CS<9>*
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
1
2
3
4
5
7
8
9
10
9
8
7
6
4
5
14
RN2
1M
RN3
1M
RN1
220K
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
6
16
11
12
1
13
2
15
3
NC
NC
NC
NC
NC
NC
NC
+5V
+5V
NC
NC
NC
NC
+5V
GND
NC
A<9>
A<1>
A<8>
A<10>
A<2>
A<3>
A<4>
A<5>
A<6>
A<7>
4C1>
6B1>
6B1>
PAI
PWMB
PWMA
GEDABV: MPB916X1C
GEDTTL: BOARD
2
LAST_MODIFIED=Fri Sep
A
9 11:24:04 1994
1
A
REV:
SHEET 7 OF 8
63ASE90344W
DWG. NO.
C
D
A
A
SIZE
PULL-UPS / PULL-DOWNS / PERSONALITY ID
4C1>
4C1<> 6B4<>
4C1>
4C1<> 6B4<>
4B4<
5D4< 6D1>
PCLK
TXD
RXD
PCS3*
CSBOOT*
A<18..0>
1
63ASE90344W
5B4<>
6D4<>
4C1<>
6B4<>
4C1<>
6B4<>
4C1<>
6B4<>
4B1<>
6B4<>
4B1<>
6C4<>
4B1<>
6C4<>
CS<10..0>*
5C4<>
IC2
DSACK0*
RMC*
5C4<>
NC
NC
NC
NC
NC
NC
RN4
220K
MC68HC916X1 MCU PERSONALITY CODE = 101HEX
(USING A<10..1>)
Freescale
Semiconductor,
Inc...
3
2
DWG. NO.
A
B
C
AVEC*
HALT*
5C4<>
5B4<>
6D4<>
4B1<>
MODCLK
4
Freescale Semiconductor, Inc.
REV:
D
For More Information On This Product,
Go to: www.freescale.com
4
A <18..0>
AN <5..0>
AS *
AVEC *
BERR *
BKPT *
CLKOUT
CS <10..0> *
CSBOOT *
D <15..0>
DS *
DSACK0 *
DSACK1 *
DSI
DSO
FREEZE
HALT *
IC1
IC2
IC3
IC4/OC5
IRQ <7..6> *
MAPI-EXTAL
MAPI-VRH
MAPI-VRL
MISO
MODCLK
MOSI
OC1
OC2
OC3
OC4
PAI
PCLK
PCS0/SS *
PCS1 *
PCS2 *
PCS3 *
PWMA
PWMB
R/W *
RESET *
RMC *
RXD
SCK
SIZ0
SIZ1
TSC
TXD
VPP
VRH
5D4< 6D1> 7D1>
3B1> 4C4> 5C1> 6B4<
5C4<> 6D4<>
5C4<> 7C4<
4B1> 6C4<
4B1> 6D1<
4A1< 6C4>
4B4< 6D1<> 7C4<
4B4< 7C1>
5C4<> 6D4<>
5C4<> 6D4<>
5C4<> 7C4<
5C4<> 6D4<>
4B1<> 6D1<>
4B1< 6D1>
4A1< 6D1>
4B1<> 7C4<
4D1<> 6C1<> 7C4<
4D1<> 6C1<> 7C4<
4C1<> 6B1<> 7C4<
4C1<> 6B1<> 7B4<
5B4<> 6D4<> 7A4<
4A1> 6A1<
3B4< 5C1>
3B4< 5C1>
4B1<> 6C4<> 7A4<
5B4<> 6D4<> 7C4<
4B1<> 6C4<> 7B4<
4C1<> 6B1<> 7B4<
4C1<> 6B1<> 7B4<
4C1<> 6B1<> 7B4<
4C1<> 6B1<> 7B4<
4C1> 6B1< 7B1<
4C1> 6B1< 7B1<
4C1<> 6B4<> 7B4<
4C1<> 6B4<> 7B4<
4C1<> 6B4<> 7B4<
4C1<> 6B4<> 7C1<
4C1< 6B1> 7B1<
4C1< 6B1> 7B1<
5C4< 6C4>
4B1<> 6C4<>
5C4<> 7C4<
4C1> 6B4< 7C1<
4B1<> 6B4<> 7B4<
5C4<> 6D4<>
5C4<> 6C4<>
4B1> 6D1<
4C1<> 6B4<> 7B1<
5B1> 6B1<
3B4> 6B4<
*** Signal Cross-Reference ***
--- for the entire design --
3
VRL
VSTBY
3B4> 6B4<
4B1> 6C1<
2
LAST_MODIFIED=Fri Sep
9 11:31:48 1994
1
A
REV:
SHEET 8 OF 8
63ASE90344W
DWG. NO.
C
D
A
A
GEDABV: MPB916X1C
GEDTTL: BOARD
SIGNAL CROSS REFERENCES
1
63ASE90344W
A
SIZE
Freescale
Semiconductor,
Inc...
3
2
DWG. NO.
A
B
C
4
Freescale Semiconductor, Inc.
REV:
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
SCHEMATIC DIAGRAMS
6-10
For More Information On This Product,
Go to: www.freescale.com
M68MPB916X1UM/D