Download ^1 USER MANUAL ^2 Accessory 34DD

^1 USER MANUAL
^2 Accessory 34DD
^3 64-Bit OPTO I/O Interface Board (20 in 12 out)
^4 4Ax-603433-xUxx
^5 October 16, 2003
Single Source Machine Control
Power // Flexibility // Ease of Use
21314 Lassen Street Chatsworth, CA 91311 // Tel. (818) 998-2095 Fax. (818) 998-7807 // www.deltatau.com
Copyright Information
© 2003 Delta Tau Data Systems, Inc. All rights reserved.
This document is furnished for the customers of Delta Tau Data Systems, Inc. Other uses are
unauthorized without written permission of Delta Tau Data Systems, Inc. Information contained in
this manual may be updated from time-to-time due to product improvements, etc., and may not
conform in every respect to former issues.
To report errors or inconsistencies, call or email:
Delta Tau Data Systems, Inc. Technical Support
Phone: (818) 717-5656
Fax: (818) 998-7807
Email: [email protected]
Website: http://www.deltatau.com
Operating Conditions
All Delta Tau Data Systems, Inc. motion controller products, accessories, and amplifiers contain
static sensitive components that can be damaged by incorrect handling. When installing or handling
Delta Tau Data Systems, Inc. products, avoid contact with highly insulated materials. Only
qualified personnel should be allowed to handle this equipment.
In the case of industrial applications, we expect our products to be protected from hazardous or
conductive materials and/or environments that could cause harm to the controller by damaging
components or causing electrical shorts. When our products are used in an industrial environment,
install them into an industrial electrical cabinet or industrial PC to protect them from excessive or
corrosive moisture, abnormal ambient temperatures, and conductive materials. If Delta Tau Data
Systems, Inc. products are directly exposed to hazardous or conductive materials and/or
environments, we cannot guarantee their operation.
Accessory 34DD
Table of Contents
INTRODUCTION .......................................................................................................................................................1
CONNECTORS ...........................................................................................................................................................3
J2 - 34D .....................................................................................................................................................................3
J2 - 34DD ..................................................................................................................................................................3
J3 - 34D .....................................................................................................................................................................3
J3 - 34DD ..................................................................................................................................................................3
J4A (JTHW) ..............................................................................................................................................................3
J4B ............................................................................................................................................................................3
TB1 - pins 1 & 2........................................................................................................................................................3
TB1 - pins 3 & 4........................................................................................................................................................3
MULTIPLEX ADDRESS MAP .................................................................................................................................5
SW1 DIP Switch Setting ...........................................................................................................................................5
M-Variable Assignments...........................................................................................................................................6
PROCESSING ACC-34DX INPUTS & OUTPUTS .................................................................................................7
When to Access ACC-34Dx......................................................................................................................................7
Image Word Variables...............................................................................................................................................7
Location of Image Words..........................................................................................................................................7
Preventing Conflicts in Output Image Words ...........................................................................................................8
Example.....................................................................................................................................................................9
POWER SUPPLY AND OPTO-ISOLATION CONSIDERATIONS...................................................................11
WATCHDOG TIMER (ROLE OF JUMPER E2)..................................................................................................13
BOARD LAYOUT AND CONNECTOR PINOUTS..............................................................................................15
ACC-34D and ACC-34DD Board Layout...............................................................................................................15
ACC-34D - J2 (50 Pin Header) ...............................................................................................................................16
ACC-34D – J3 (50 Pin Header)...............................................................................................................................17
ACC-34D – J3 (50 Pin Header)...............................................................................................................................18
ACC-34DD - J2 (50 Pin Header) ............................................................................................................................18
J4A & J4B (26-PIN Header) ...................................................................................................................................20
TB1 (4-pin Terminal Block)....................................................................................................................................21
SCHEMATICS ..........................................................................................................................................................23
Table of Contents
i
Accessory 34DD
ii
Table of Contents
Accessory 34DD
INTRODUCTION
PMAC's Accessory 34D (ACC-34D) and Accessory 34DD (ACC-34DD) are discrete input/output (I/O)
boards designed for easy connection to Opto-22 and compatible mounting racks. The board interfaces
with several third party opto modules (e.g. Opto-22 Models G4PB32, 70GRQ432 and all PB8, 16, and 24
boards) via standard 50-pin flat cables (see ACC-21 cables). In addition to the third party I/O boards the
ACC-34DD interfaces directly to the I/O Pack board (Delta Tau part number 603052). ACC-34 D and
DD provide 32 lines of optically isolated inputs and 32 lines of optically isolated outputs. Both the inputs
and the outputs are TTL compatible negative logic (low true) types. The actual I/O Reads and Writes are
carried out using a special form of M-variables which will be described later.
The ACC-34D differs from the ACC-34DD in only one aspect, the input and output layout on the
connectors J2 and J3. The D has 32 inputs on connector J2, while the DD has 20 inputs and 12 outputs.
The D has 32 outputs on J3, while the DD has 12 inputs and 20 outputs. If the application only requires 1
I/O board or the I/O boards being used are the I/O Pack (Delta Tau #603052) then the ACC-34DD should
be used, otherwise the ACC-34D should be used.
From this point on this document will refer to the ACC-34D and the ACC-34DD as ACC-34DDX when
they could be used interchangeably.
ACC-34DDX is part of a series of I/O accessories for PMAC that use the JTHW connector. Others are:
•
•
•
•
•
•
ACC-34A The Opto 32 Bit Input/32 Bit Output board
ACC-34B The Opto 32 Bit Input/32 Bit Output board
ACC-34C The Opto 64 Bit Input/32 Bit Output board
ACC-18 The Thumbwheel Multiplexer board
ACC-8D-Opt.7 The Resolver to Digital Converter board
ACC-8D-Opt.8 The Absolute Encoder Interface board
All of the above accessories use the JTHW multiplex address scheme and several of them may be daisychained to a single PMAC. In addition for enhanced noise reduction and long distance installation,
accessories 35A and 35B provide differential buffer capability for the JTHW signals. The use of the long
distance buffer pair (ACC-35A and ACC-35B) is recommended whenever the required cable length
between PMAC and ACC-34Dx is beyond 3 meters (10 feet).
Up to 32 ACC-34Dxs may be connected to a single PMAC, giving the possible total number of 1024
input and 1024 output lines in addition to those available on the PMAC board and those available on the
parallel I/O expansion board(s) (ACC-14). Accessory 34Dx communicates to PMAC via its JTHW
connector through the supplied flat cable. In situations where the I/O modules are a long distance away
from PMAC, ACC-35A & ACC-35B may be used as local and remote buffers between PMAC and ACC34Dx.
ACC-34Dx also supports a local watchdog timer feature independent of that of PMAC's. The mode of
operation of this function is explained at the end of this manual (see also the enclosed schematic).
Introduction
1
Accessory 34DD
2
Introduction
Accessory 34DD
CONNECTORS
Please refer to the layout diagram of ACC-34Dx for the location of the connectors on the board. A pin
definition listing for each connector is provided at the end of this Manual.
J2 - 34D
This is a 50-pin header which provides the connection for the input lines numbered 0 to 31. In addition,
this connector has a 5 volt (maximum 0.5 A) power supply outlet is provided for external logic circuits.
J2 - 34DD
This is a 50-pin header which provides the connection for the input lines numbered 0 to 11, 24 to 31 and
output lines numbered 0 to 11. In addition, this connector has a 5V (maximum 0.5 A) power supply outlet
is provided for external logic circuits.
J3 - 34D
This is a 50-pin header which provides the connection for the output lines numbered 0 to 31. In addition,
this connector has a 5V (maximum 0.5 A) power supply outlet is provided for external logic circuits.
J3 - 34DD
This is a 50-pin header which provides the connection for the output lines numbered 12 to 31 and input
lines numbered 12 to 23. In addition, this connector has a 5V (maximum 0.5 A) power supply outlet is
provided for external logic circuits.
J4A (JTHW)
This is a 26-pin header which provides the link between PMAC's JTHW (J3) and this board. Using the
supplied flat cable PMAC's J3 should be connected to J4A. Through this connector PMAC sets the
outputs and reads the inputs. In addition, the power for the processor side of the opto-isolation circuitry is
provided from the PMAC board through this connector.
J4B
This is a 26-pin header which brings out the JTHW signals for the next accessory board on the JTHW
multiplex memory map. This connector is pin-to-pin compatible with J4A.
TB1 - pins 1 & 2
Terminal block through which a 5V power supply may be brought in for the optically isolated side of the
digital circuitry on ACC-34Dx (50 mA is required). Remove jumper E1 if the power is supplied to the
board via TB1 - pins 1 & 2. Note that with jumper E1 is installed, whenever a 12 to 24V supply is
brought in from TB1 - pins 3 & 4, then TB1 - pins 1 & 2 can be used as a 5-volt power source for the
logic circuits on the external opto boards (see the enclosed schematic).
TB1 - pins 3 & 4
Terminal block through which a 12 to 24V unregulated power supply may be brought for the optically
isolated side of the digital circuitry on ACC-34Dx. The voltage is reduced to 5V via the on board
regulator. Install jumper E1 if the required power is supplied via TB1 - pins 3 & 4. Do not supply power
through both 1 & 2 and 3 & 4.
Connectors
3
Accessory 34DD
4
Connectors
Accessory 34DD
MULTIPLEX ADDRESS MAP
Each ACC-34Dx occupies eight bytes of address space on the PMAC JTHW MULTIPLEX memory
space. This memory space is 8-bit wide, providing the ability to daisy-chain 32 (256/8) ACC-34Dxs
together (or a combination of ACC-34Dxs, ACC-34As, ACC-18s and ACC-8D OPT7s). The 5-bit DIP
switch, SW1, determines the address of each ACC-34D board on the allocated memory space. Port A, the
input port, occupies the base address (i.e. bytes 0, 8, 16 etc.) and Port B, the output port, occupies the base
address plus 4 (i.e. bytes 4, 12, 20 etc.). The table below shows how SW1 should be set for one or more
ACC-34D boards connected to the same PMAC.
SW1 DIP Switch Setting
Board #
Port A &
Port B
Byte #
SW1 DIP Switch Setting
5
4
3
2
1
#1
0&4
ON
ON
ON
ON
ON
#2
8 & 12
ON
ON
ON
ON
OFF
#3
16 & 20
ON
ON
ON
OFF
ON
#4
24 & 28
ON
ON
ON
OFF
OFF
#5
32 & 36
ON
ON
OFF
ON
ON
#6
40 & 44
ON
ON
OFF
ON
OFF
#7
48 & 52
ON
ON
OFF
OFF
ON
#8
56 & 60
ON
ON
OFF
OFF
OFF
#9
64 &68
ON
OFF
ON
ON
ON
#10
72 & 76
ON
OFF
ON
ON
OFF
#11
80 & 84
ON
OFF
ON
OFF
ON
#12
88 &92
ON
OFF
ON
OFF
OFF
#13
96 & 100
ON
OFF
OFF
ON
ON
#14
104 & 108
ON
OFF
OFF
ON
OFF
#15
112 & 116
ON
OFF
OFF
OFF
ON
#16
120 & 124
ON
OFF
OFF
OFF
OFF
#17
128 & 132
OFF
ON
ON
ON
ON
#18
136 & 140
OFF
ON
ON
ON
OFF
#19
144 & 148
OFF
ON
ON
OFF
ON
#20
152 & 156
OFF
ON
ON
OFF
OFF
#21
160 & 164
OFF
ON
OFF
ON
ON
#22
168 & 172
OFF
ON
OFF
ON
OFF
#23
176 & 180
OFF
ON
OFF
OFF
ON
#24
184 &188
OFF
ON
OFF
OFF
OFF
#25
192 & 196
OFF
OFF
ON
ON
ON
#26
200 & 204
OFF
OFF
ON
ON
OFF
#27
208 & 212
OFF
OFF
ON
OFF
ON
#28
216 & 220
OFF
OFF
ON
OFF
OFF
#29
224 & 228
OFF
OFF
OFF
ON
ON
#30
232 & 236
OFF
OFF
OFF
ON
OFF
#31
240 & 244
OFF
OFF
OFF
OFF
ON
#32
248 & 252
OFF
OFF
OFF
OFF
OFF
The daisy-chain board address relationship with respect to the 5-bit (SW1) dip position setting.
Note: on=closed, off=open. To turn "off" a switch, push down on the "open" side. To turn "on"
a switch, push down on the "numbered" side.
Multiplex Address Map
5
Accessory 34DD
M-Variable Assignments
Port A is always configured as a negative logic input port which can be read through TWS type Mvariables (see below). The output lines are driven by writing to port B.
There is a special format 32-bit wide M-variable for reading the data from, and writing the data to, an
ACC-34Dx cards, TWS. NOTE: This special M-variable definition is implemented in PMAC’s firmware
with a version number equal to or higher than 1.13. In version 1.14D, the TWS format was modified in
its address designation field to prevent un-intentional reads from an output port or un-intentional writes to
an input port. If your PROM version is between 1.13 to 1.14C, you may request for a free PROM update
to version 1.14D or above.
The definition format is of the form:
M{constant}->TWS:{m-plex}
For an input port, {m-plex} is a legal byte number (from column 2 of Table 1) plus 1. Any attempt to
write to a TWS type M-variable defined with bit zero of its address set to 1, is prevented by PMAC’s
firmware automatically. For an output port, {m-plex} is a legal byte number (from column 2 of Table
1) plus 2. An attempt to read a TWS type M-variable defined with bit one of its address set to 1, returns
zero and the actual read is prevented by PMAC's firmware (no error is reported). Note that individual bits
cannot be directly assigned to an M-variable of this type. Rather banks of 32 bits (ports) can be assigned
to M-variables. For example to address Port A (bits 0 to 31) of board #1 as an input using M100, we
would use the following definition:
M100->TWS:1
;Port A (AIO 0-31) of an ACC-34Dx with SW1 switches
all ON
;assigned for read only (1=0+1)
Similarly to address Port B of the same board #1 as an output using M101, we would use the following
definition:
M101->TWS:6
;Port B (BIO 0-31) of an ACC-34Dx with SW1 switches
all ON
;assigned for write only (6=4+2)
Yet another example: to address Port A of board #6 as an input using M300, we would use the following
definition:
M300->TWS:41
;Port A (AIO 0-31) of an ACC-34Dx with SW1 switches
;ON,ON,OFF,ON,OFF
;assigned for read only (41=40+1)
Note
1. A 32-bit Read or a 32-bit Write to an individual port takes approximately 64
microseconds of time in the PMAC’s background time slot. As a result excessive
and unnecessary references to TWS type M-variables is not recommended (see below
for efficient ACC-34Dx I/O processing).
2. TWS type M-variable definition addresses which point to the base address directly
(e.g. M300->TWS:40) are still valid (i.e. they do not generate error). However their
use is very strongly discouraged. This because both reads and writes are enabled
when the least significant and the next least significant addresses bits are both zero
(e.g. decimal 40 = 01000000 in binary). In this situation, any accidental read of an
output port (say via the Executive programs watch window) will cause all the output
to be turned on! It is therefore safer and more predictable when bits 0 & 1 of the Mvariable definition are intentionally used to disable either the read function or the
write function.
6
Multiplex Address Map
Accessory 34DD
PROCESSING ACC-34DX INPUTS & OUTPUTS
Because the PMAC interface to the Accessory 34 family of I/O boards (ACC-34Dx) is by full 32-bit
words transmitted serially, even when access to only a single bit is desired, the user must consider
carefully how the interface is done and how frequently. Care must also be taken to work efficiently with
the data so that PMAC is not bogged down with slow serial reads and writes, and time-consuming logic to
assemble and disassemble I/O words.
The recommended strategy is to keep "images" of each input or output word in PMAC’s internal memory,
or in the dual-ported RAM. The input words are copied into their image words, and the output words are
copied from their image words. Most program operations deal with these image words; much less
frequently is the slow transfer to or from an ACC-34Dx board performed. During the act of copying, bit
inversion can also be performed with the exclusive-or function.
When to Access ACC-34Dx
The actual reads and writes for an ACC-34Dx board can only be done in a background PLC program
(PLC 1-31) or through on-line commands, which are executed between PLC programs. Motion programs
and PLC 0 cannot directly access this I/O -- they can work only with the image words. Reading an input
word from an ACC-34Dx is simply a question of using the TWS-form M-variable for that word on the
right side of an equation. Usually this operation simply copies the input word into its internal image
variable. Similarly, writing an output word to an ACC-34Dx just involves using the M-variable for that
word on the left side of an equation, typically just copying it from its internal image word.
Most users will treat ACC-34Dx I/O the same way that a traditional PLC treats its I/O; all of the inputs
are read at the beginning of a PLC software scan, and all of the outputs are written to at the end of the
scan. In between, all the processing of the variables is done working with the internal image words. It is
possible to make the write operation to the output word conditional on a change in the image word for the
output from the previous scan, but the time involved in making the decision and storing each scan's value
is about the same as the actual writing to the output.
Image Word Variables
It is best to use fixed-point M-variables as the internal image variables for the I/O words. When this is
done, a single M-variable representing the entire I/O word can be used for the copying operation. Then
separate M-variables can be used to access individual bits or segments of the image word. Use of these
smaller M-variables allows PMAC's efficient firmware to do the masking and logic necessary to pick out
portions of the I/O word, rather than slower user program code.
Location of Image Words
Where should these internal image variables reside in PMAC's memory? If the system has dual-ported
RAM, it is probably best to use a 32-bit register in DPRAM. This way, the host computer always has
immediate access to the I/O. In fact, it is possible to use PMAC just as a pass-through between the host
computer and the ACC-34Dx boards, letting the host computer do all the processing. A 32-bit fixed-point
register in DPRAM is defined by the DP format of M-variable (e.g. M60->DP:$DF00). This type of
variable occupies the low 16 bits (bits 0 to 15) of PMAC Y-memory, and the low 16 bits of PMAC Xmemory at the same address, with the less significant bits in Y-memory. It appears to the host computer
as 2 16-bit registers at consecutive even addresses, with the less significant bits at the lower address.
If there is no DPRAM, the image word will be in an otherwise unused double register in PMAC's own
memory. There are several places to find unused registers. There are sixteen open registers that are
automatically set to zero on power-up at PMAC addresses $0770 to $077F. There are sixteen more open
registers whose values are held when power is off at PMAC addresses $07F0 to $07FF. Also, it is
possible to use the registers of otherwise unused P and Q-variables for this purpose.
Processing ACC-34Dx Inputs & Outputs
7
Accessory 34DD
These registers should be accessed with fixed-point M-variables, not floating-point P or Q-variables! A
double fixed-point register in PMAC's internal memory is defined by the D format of M-variable (e.g.
M61->D:$07F0). This is a 48-bit register -- only the low 32 bits will be used. The low 24 bits of the
I/O will be in Y-memory, and the high 8 bits of the I/O will be in the low 8 bits of X-memory.
When working with the ACC-34Dx I/O with this method of using fixed-point image variables, the only
software overhead is the actual copying between image and I/O. Including program interpretation time,
this amounts to about 100 microseconds per 32-bit word. Aside from this, working with the I/O through
the image words is at least as fast as direct (parallel) PMAC I/O. Of course, there is a potential latency of
a full PLC scan on the actual I/O which must be respected. Many systems will have a few critical I/O
points that cannot tolerate this latency; these typically use PMAC's JOPTO port or ACC-14 I/O for these
time-critical points, then use ACC-34Dx for I/O that do not need to be so fast.
Preventing Conflicts in Output Image Words
Care must be taken if tasks of different priority levels are trying to write to the same output image word,
or if both the host computer and PMAC are trying to write to the same DPRAM output image word. If
the proper techniques are not used, occasional output changes will not be executed, and because of the
intermittent nature of the problem will make it very difficult to diagnose. If the application has two
priority levels or two computers that write to the same ACC-34Dx output word, separate partial image
words must be used, then these words combined as the output word is sent. Note that there is no conflict
in having different tasks or different processors read from the same input word.
Remember that a computer cannot actually write to less than a word of memory at a time, even if it only
wants to change one bit. In PMAC the word length is 24 bits; for the DPRAM, it is 16 bits. If a computer
wants to change less than a full word, it must read the full word, modify the bits it wants with mask
words, and then write back the full word.
There are two priority levels in PMAC that can write to these image words: the foreground level, which
includes all of the motion programs and PLC 0; and the background level, which includes PLCs 1-31 and
on-line commands. The problem can occur when a higher priority task interrupts a lower priority task
that is in the middle of changing the image word with a read-modify-write operation. When the lower
priority task resumes, it will undo the changes made by the higher priority task. Similarly, if the image
word is in the DPRAM, and one side starts its read-modify-write cycle on the word but does not finish it
before the other side starts its own cycle, the side that starts later can undo the changes made by the side
that starts first.
Note
Two tasks at the same priority level cannot interrupt each other; one will always finish an
operation before the other starts. Therefore, there is no need to worry about two motion
programs writing to the same image word; or a motion program and PLC 0; because
these tasks are at the same priority level. Similarly, there is no need to worry about two
background PLC programs writing to the same image word, or a background PLC and
on-line commands.
To prevent this possible conflict, the different priority levels or different processors must use different
image words, even if they each represent only a part of the same total output word. These partial words
are then combined in the act of writing to the actual output word.
The simplest way to split an image word is to use the natural X-memory vs. Y-memory split in PMAC’s
memory. If you are using a double word in PMAC’s internal memory, you can reserve the 24 bits in Ymemory for one priority level, and the 8 bits in X-memory for the other. If you are using the DPRAM,
you can reserve the 16 bits in Y-memory for one processor or priority level, and the 16 bits in X-memory
for another. If you do this, no special techniques need to be used. On PMAC, simply write to the partial
8
Processing ACC-34Dx Inputs & Outputs
Accessory 34DD
words with a X or Y format M-variable; PMAC will automatically do the read-modify-write cycle
without touching the other part of the word. On the host computer, access the DPRAM register with the
short (16-bit) integer format, not the long.
However, if you cannot arrange your split in this fashion, you must create separate "overlapping" image
words and explicitly combine them. As an example, take a system where the low 12 bits will be written
to by background PLCs and the high 20 bits will be written to by motion programs. We create two
separate image words, one for each priority level, and the actual output word:
M101->D:$0770
M102->D:$0771
M103->TWS:6
; Image word for PLC programs (background)
; Image word for motion programs (foreground)
; ACC-34x output word; write-only
We also define single-bit M-variables to parts of these same internal addresses: at Y:$0770, bits 0 to 11
for the PLCs; then at Y:$0771, bits 12 to 23, and X:$0771, bits 0 to 7 for the motion programs. At the
end of a PLC scan, to create the actual output word on an ACC-34Dx from the image words, we would
use the program statement:
M103 = (M101 & $00000FFF) | (M102 & $FFFFF000)
The bit-by-bit AND (&) operations make sure no falsely set bits in unused portions of the image words
get into the output word. They are not strictly necessary if the unused bits can be guaranteed to be zero.
The bit-by-bit OR (|) operation combines the word, and the assignment of the resulting value to M103
causes it to be written to the ACC-34Dx.
If you want to be able to write to the same bit of an output image word with two different priority levels
or processors, one of the tasks must do so indirectly by writing into a holding register. The other task
must take this holding register and transfer the bit value into the image word. This task must decide what
to do in case of any conflict (i.e. one task wants to clear the bit, and the other wants to set it).
Example
The following example should illustrate the concept of this method of working with ACC-34Dx I/O. It is
a bit unrealistic, because it shows the image variables both in DPRAM and several places in internal
memory. In a real application, a single location range would probably be chosen.
Set-up and Definitions:
; Actual ACC-34 I/O Words
M1000->TWS:1
M1002->TWS:6
M1004->TWS:9
M1006->TWS:14
;
;
;
;
;
;
;
;
First side of first ACC-34Dx board; an input here
Location is at port address 0; added 1 for read only
Second side of first ACC-34Dx board; an output here
Location is at port address 4; added 2 for write ; only
First side of second ACC-34Dx board; an input here
Location is at port address 8; added 1 for read only
Second side of second ACC-34Dx board; an output here
Location is at port address 12; added 2 for write only
;
;
;
;
32-bit fixed-point DPRAM register
48-bit fixed-point register, set to zero on power-up
48-bit fixed-point register, value held thru power-down
Register for P1023, treated as 48-bit fixed-point value
; Image Words
M1001->DP:$D800
M1003->D:$0770
M1005->D:$07F0
M1007->D:$13FF
; Individual Pieces of Image Words
M100->Y:$D800,0
M101->Y:$D800,1
...
M115->Y:$D800,15
M116->X:$D800,0
M117->X:$D800,1
...
M131->X:$D800,15
; Least significant bit (bit 0) of first image word
; Second bit (bit 1) of first image word
; Bit 15 of first image word
; Bit 16 of first image word
; Most significant bit (bit 31) of first image word
Processing ACC-34Dx Inputs & Outputs
9
Accessory 34DD
M300->Y:$0770,0
M301->Y:$0770,1
...
M323->Y:$0770,23
M324->X:$0770,0
M325->X:$0770,1
...
M331->X:$0770,7
M500->Y:$07F0,0
...
M523->Y:$07F0,23
M524->X:$07F0,0
...
M531->X:$07F0,7
M700->Y:$13FF,0
...
M724->X:$13FF,0,8
; Least significant bit (bit 0) of second image word
; Second bit (bit 1) of second image word
; Bit 23 of second image word
; Bit 24 of second image word
; Bit 25 of second image word
; Most significant bit (bit 31) of second image word
; Least significant bit (bit 0) of third image word
; Bit 23 of third image word
; Bit 24 of third image word
; Most significant bit (bit 31) of third image word
; Least significant bit (bit 0) of fourth image word
; Top eight bits (bits 24-31) of fourth image word
Programs:
; "Reset" PLC program that only runs once on power-up or reset
OPEN PLC 1 CLEAR
M1003=0
M1007=0
...
DISABLE PLC 1
CLOSE
; Clear output image word to make sure all outputs off
; Ditto
; To make sure this only runs once on power-up/reset
; PLC program to copy the inputs into image words at beginning of each scan
OPEN PLC 2 CLEAR
M1001=M1000
; Copy first input word into its image register
M1005=M1004^$FFFFFFFF
; inverting
; Copy second input word into its image register,
...
CLOSE
; PLC program that works with individual bits of image words
OPEN PLC 3 CLEAR
IF (M100=1 AND M101=0 AND P43>50)
M301=1
ELSE
M301=0
ENDIF
...
CLOSE
; PLC program that copies image words to outputs at end of scan
OPEN PLC 31 CLEAR
M1002=M1003
; Copy first output image word to ACC-34Dx
M1004=M1005^$FFFFFFFF
; Copy second output image word to ACC-34Dx, inverting
10
Processing ACC-34Dx Inputs & Outputs
Accessory 34DD
POWER SUPPLY AND OPTO-ISOLATION CONSIDERATIONS
The power for the PMAC processor side of the opto-isolation circuitry is brought in directly from J1
(JTHW). The power for the external side of the opto-isolation circuitry should be from a separate supply
brought in through TB1 (5V or 12-24 volts). Note either 5V or 12-24V should be used. Do not supply
power through both. E1 should be installed when +12 to 24V supply is brought in through TB1. It
should be removed if +5V supply is brought in through TB1. The current requirement for on board logic
circuit on the external side of the opto isolation is approximately 50 mA. However, if the power is also
supplied for the external opto boards digital circuits, then up to 550 mA may be required.
Power Supply And Opto-Isolation Considerations
11
Accessory 34DD
12
Power Supply And Opto-Isolation Considerations
Accessory 34DD
WATCHDOG TIMER (ROLE OF JUMPER E2)
Acc-34Dx has a local watchdog timer that is disabled when the jumper E2 is installed. In the factory
default setup, this jumper is installed (the watchdog timer is disabled).
When jumper E2 is removed, the 1.5-second watchdog timer circuit is enabled on ACC-34Dx. With the
watchdog circuit enabled, PMAC must read from or write to the board at least once every 1.5 seconds. If
the board is not accessed within the 1.5-second period, then the watchdog circuit switches off the output
circuits of the opto board(s) connected to the ACC-34Dx. A single read or write cycle will re-establish
control over the outputs.
Watchdog Timer (Role of Jumper E2)
13
Accessory 34DD
14
Watchdog Timer (Role of Jumper E2)
Accessory 34DD
BOARD LAYOUT AND CONNECTOR PINOUTS
ACC-34D and ACC-34DD Board Layout
Board Layout and Connector Pinouts
15
Accessory 34DD
ACC-34D - J2 (50 Pin Header)
Pin #
Symbol
Function
Description
Notes
1
IN23
Input
Port A Bit 23
2
IN24
Input
Port A Bit 24
3
IN22
Input
Port A Bit 22
4
IN25
Input
Port A Bit 25
5
IN21
Input
Port A Bit 21
6
IN26
Input
Port A Bit 26
7
IN20
Input
Port A Bit 20
8
IN27
Input
Port A Bit 27
9
IN19
Input
Port A Bit 19
10
IN28
Input
Port A Bit 28
11
IN18
Input
Port A Bit 18
12
IN29
Input
Port A Bit 29
13
IN17
Input
Port A Bit 17
14
IN30
Input
Port A Bit 30
15
IN16
Input
Port A Bit 16
16
IN31
Input
Port A Bit 31
17
IN15
Input
Port A Bit 15
18
GND
Common
Opto Common
19
IN14
Input
Port A Bit 14
20
GND
Common
Opto Common
21
IN13
Input
Port A Bit 13
22
GND
Common
Opto Common
23
IN12
Input
Port A Bit 12
24
GND
Common
Opto Common
25
IN11
Input
Port A Bit 11
26
GND
Common
Opto Common
27
IN10
Input
Port A Bit 10
28
GND
Common
Opto Common
29
IN9
Input
Port A Bit 9
30
GND
Common
Opto Common
31
IN8
Input
Port A Bit 8
32
GND
Common
Opto Common
33
IN7
Input
Port A Bit 7
34
GND
Common
Opto Common
35
IN6
Input
Port A Bit 6
36
GND
Common
Opto Common
37
IN5
Input
Port A Bit 5
38
GND
Common
Opto Common
39
IN4
Input
Port A Bit 4
40
GND
Common
Opto Common
41
IN3
Input
Port A Bit 3
42
GND
Common
Opto Common
43
IN2
Input
Port A Bit 2
44
GND
Common
Opto Common
45
IN1
Input
Port A Bit 1
46
GND
Common
Opto Common
47
IN0
Input
Port A Bit 0
48
GND
Common
Opto Common
49
A +5V
Output
+5 V supply
50
GND
Common
Opto Common
This 50-pin header provides the connection for the input lines numbered 0 to 31. In addition, this connector
has a 5-volt (maximum 0.5 A) power supply outlet for external logic circuits.
16
Board Layout and Connector Pinouts
Accessory 34DD
ACC-34D – J3 (50 Pin Header)
Pin #
Symbol
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
OUT23
OUT24
OUT22
OUT25
OUT21
OUT26
OUT20
OUT27
OUT19
OUT28
OUT18
OUT29
OUT17
OUT30
OUT16
OUT31
OUT15
GND
OUT14
GND
OUT13
GND
OUT12
GND
OUT11
GND
OUT10
GND
OUT9
GND
OUT8
GND
OUT7
GND
OUT6
GND
OUT5
GND
OUT4
GND
OUT3
GND
OUT2
GND
OUT1
GND
OUT0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Common
Output
Board Layout and Connector Pinouts
Description
Notes
Port B Bit 23
Port B Bit 24
Port B Bit 22
Port B Bit 25
Port B Bit 21
Port B Bit 26
Port B Bit 20
Port B Bit 27
Port B Bit 19
Port B Bit 28
Port B Bit 18
Port B Bit 29
Port B Bit 17
Port B Bit 30
Port B Bit 16
Port B Bit 31
Port B Bit 15
Opto Common
Port B Bit 14
Opto Common
Port B Bit 13
Opto Common
Port B Bit 12
Opto Common
Port B Bit 11
Opto Common
Port B Bit 10
Opto Common
Port B Bit 9
Opto Common
Port B Bit 8
Opto Common
Port B Bit 7
Opto Common
Port B Bit 6
Opto Common
Port B Bit 5
Opto Common
Port B Bit 4
Opto Common
Port B Bit 3
Opto Common
Port B Bit 2
Opto Common
Port B Bit 1
Opto Common
Port B Bit 0
17
Accessory 34DD
ACC-34D – J3 (50 Pin Header)
(Continued)
Pin #
Symbol
Function
Description
Notes
Opto Common
48
GND
Common
+5 V supply
49
A +5V
Output
Opto Common
50
GND
Common
This 50-pin header provides the connection for the output lines numbered 0 to 31. In addition, this connector
has a 5-volt (maximum 0.5 A) power supply outlet for external logic circuits.
ACC-34DD - J2 (50 Pin Header)
18
Pin #
Symbol
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
OUT11
IN24
OUT10
IN25
OUT09
IN26
OUT08
IN27
OUT07
IN28
OUT06
IN29
OUT05
IN30
OUT04
IN31
OUT03
GND
OUT02
GND
OUT01
GND
OUT00
GND
IN11
GND
IN10
GND
IN9
GND
IN8
GND
IN7
GND
IN6
GND
IN5
GND
IN4
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Common
Output
Common
Output
Common
Output
Common
Input
Common
Input
Common
Input
Common
Input
Common
Input
Common
Input
Common
Input
Common
Input
Description
Notes
Port B Bit 11
Port A Bit 24
Port B Bit 10
Port A Bit 25
Port B Bit 9
Port A Bit 26
Port B Bit 8
Port A Bit 27
Port B Bit 7
Port A Bit 28
Port B Bit 6
Port A Bit 29
Port B Bit 5
Port A Bit 30
Port B Bit 4
Port A Bit 31
Port B Bit 3
Opto Common
Port B Bit 2
Opto Common
Port B Bit 1
Opto Common
Port B Bit 0
Opto Common
Port A Bit 11
Opto Common
Port A Bit 10
Opto Common
Port A Bit 9
Opto Common
Port A Bit 8
Opto Common
Port A Bit 7
Opto Common
Port A Bit 6
Opto Common
Port A Bit 5
Opto Common
Port A Bit 4
Board Layout and Connector Pinouts
Accessory 34DD
ACC-34DD - J2 (50 Pin Header)
(Continued)
Pin #
Symbol
Function
Description
Notes
40
GND
Common
Opto Common
41
IN3
Input
Port A Bit 3
42
GND
Common
Opto Common
43
IN2
Input
Port A Bit 2
44
GND
Common
Opto Common
45
IN1
Input
Port A Bit 1
46
GND
Common
Opto Common
47
IN0
Input
Port A Bit 0
48
GND
Common
Opto Common
49
A +5V
Output
+5 V supply
50
GND
Common
Opto Common
This 50-pin header provides the connection for the output lines numbered 12 to 31 and input lines numbered
12 to 23. In addition, this connector has a 5V (maximum 0.5A) power supply outlet for external logic
circuits.
ACC-34DD – J3 (50 Pin Header)
Pin #
Symbol
Function
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
OUT23
OUT24
OUT22
OUT25
OUT21
OUT26
OUT20
OUT27
OUT19
OUT28
OUT18
OUT29
OUT17
OUT30
OUT16
OUT31
OUT15
GND
OUT14
GND
OUT13
GND
OUT12
GND
IN23
GND
IN22
GND
IN21
GND
IN20
GND
IN19
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Common
Output
Common
Output
Common
Output
Common
Input
Common
Input
Common
Input
Common
Input
Common
Input
Port B Bit 23
Port B Bit 24
Port B Bit 22
Port B Bit 25
Port B Bit 21
Port B Bit 26
Port B Bit 20
Port B Bit 27
Port B Bit 19
Port B Bit 28
Port B Bit 18
Port B Bit 29
Port B Bit 17
Port B Bit 30
Port B Bit 16
Port B Bit 31
Port B Bit 15
Opto Common
Port B Bit 14
Opto Common
Port B Bit 13
Opto Common
Port B Bit 12
Opto Common
Port A Bit 23
Opto Common
Port A Bit 22
Opto Common
Port A Bit 21
Opto Common
Port A Bit 20
Opto Common
Port A Bit 19
Board Layout and Connector Pinouts
Notes
19
Accessory 34DD
34
35
GND
IN18
Common
Input
Opto Common
Port A Bit 18
ACC-34DD – J3 (50 Pin Header)
(Continued)
Pin #
Symbol
Function
Description
Notes
34
GND
Common
Opto Common
35
IN18
Input
Port A Bit 18
35
36
GND
Common
Opto Common
37
IN17
Input
Port A Bit 17
38
GND
Common
Opto Common
39
IN16
Input
Port A Bit 16
40
GND
Common
Opto Common
41
IN15
Input
Port A Bit 15
42
GND
Common
Opto Common
43
IN14
Input
Port A Bit 14
44
GND
Common
Opto Common
45
IN13
Input
Port A Bit 13
46
GND
Common
Opto Common
47
IN12
Input
Port A Bit 12
48
GND
Common
Opto Common
49
A +5V
Output
+5 V supply
50
GND
Common
Opto Common
This 50-pin header provides the connection for the output lines numbered 12 to 31 and input lines numbered
12 to 23. In addition, this connector has a 5-volt (maximum 0.5 A) power supply outlet for external logic
circuits.
J4A & J4B (26-PIN Header)
Top View
20
Pin #
Symbol
Function
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
GND
DAT0
SEL0
DAT1
SEL 1
DAT2
SEL2
DAT3
SEL3
DAT4
SEL 4
DAT5
SEL5
DAT6
SEL6
DAT7
SEL7
N.C.
GND
N.C.
GND
N.C.
GND
Common
Common
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
PMAC Common
PMAC Common
Data Bit 0
Address Line 0
Data Bit 1
Address Line 1
Data Bit 2
Address Line 2
Data Bit 3
Address Line 3
Data Bit 4
Address Line 4
Data Bit 5
Address Line 5
Data Bit 5
Address Line 6
Data Bit 6
Data Bit 7
Common
PMAC Common
Common
PMAC Common
Notes
Common
Board Layout and Connector Pinouts
Accessory 34DD
25
+5V
Input
+5V DC Supply
26
N.C.
J4A (JTHW) is a 26-pin header that provides the link between PMAC’s JTHW (J3) and this board.
Using the supplied flat cable, PMAC's J3 should be connected to J4A. Through this connector PMAC
sets the outputs and reads the inputs. In addition, the power for the processor side of the opto-isolation
circuitry is provided from the PMAC board through this connector.
J4B is a 26-pin header that brings out the JTHW signals for the next accessory board on the JTHW
multiplex memory map. This connector is pin-to-pin compatible with J4A
TB1 (4-pin Terminal Block)
Pin #
Symbol
Function
1
A+24V
Power Supply
Description
Notes
External Supply for Optically
12V to 24 V
Isolated Part of Circuitry
Unregulated
2
AGND
Common
External Supply Ground
3
AGND
Common
External Supply Ground
4
A+5V
Power Supply External Supply for Optically
Regulated +5 volts.
Isolated Part of Circuitry
This a 4-pin terminal block through which a 5V regulated, or, a 12 to 24 volt unregulated power supply
may be brought in for the optically isolated side of the circuitry on ACC-34DDX (50 mA is required).
Remove jumper E1 if the power is supplied to the board via TB1-3, 4. Note that with jumper E1 installed,
whenever a 12 to 24V supply is brought in from TB1-1, 2, then TB1-3, 4 can be used as a 5V power
source for the logic circuits on the external opto boards (see the enclosed schematic). Do not supply power
through both TB1-1, 2and TB1-3, 4.
Board Layout and Connector Pinouts
21
Accessory 34DD
22
Board Layout and Connector Pinouts
Accessory 34DD
SCHEMATICS
LOGIC GND-PLANE
OPTO GND-PLANE
+5V
U1
VDD
1
1OE1
1Y
2
2OE2
2Y
5
3OE3
3Y
9
J4B
4OE4
4Y
12
DAT0
SEL0
DAT1
SEL1
DAT2
SEL2
DAT3
SEL3
DAT4
SEL4
DAT5
SEL5
DAT6
SEL6
DAT7
SEL7
11
4A
7
VSS
A+5V
74HC125P
(SO14)
U8
C4
1
.1UF
2
U2
2
4
6
8
11
13
15
17
+5V
3
5
7
9
12
14
16
18
SW1
10
9
8
7
6
HEADER 26
1
2
3
4
5
6
5
4
3
2
SW DIP-5
19
5
10
1
2
ANODE#1
2
RP3B
3
4
CATHODE#1
VO1
CATHODE#2
VO2
GND
12
8
7
7
1
1
C6
.1UF
4
1
2
RP3D
5
4
ANODE#1
VCC
CATHODE#1
VO1
CATHODE#2
VO2
ANODE#2
330
1
5
6
11 74HC30
12 (SO14)
RP2
RP3E
6
330
1
2
3
4
RP3F
7
GND
1
N.C.
VCC
ANO
VE
CAT
VOUT
N.C.
6N137
330
.1UF
D7
LED
ORN
+5PWR
2Y
SCLK
6
SDO
SDO
SDI_1
SDI_1
SDI_0
SDI_0
2A
3OE3
8
3Y
3A
4OE4
11
4Y
4A
VSS
7
6
U9
5
C10
1
2
3
(DIP8)
HCPL-2630
1
U3
8
2
3
4
5
6
7
8
9
10
1N5908
TP1
GND
2OE2
8
A
B
C
U6
C7
SCLK
C9
.1UF
D6
3
U5
RP3C
3
1
R5
330
.1UF
1Y
1A
.1UF
+5V
1
2
3
4
VDD
1OE1
74HC125P
(SO14)
6
5
C12
14
(DIP8)
HCPL-2630
G
VCC
C5
22UF
35V
VCC
ANODE#2
330
330
+
1
3
1
330
U4
RP3A
330
74HC688
(SOL20)
10K
9
13
RP4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
RP1
4
P=Q
P0
P1
P2
P3
P4
P5
P6
P7
10
9
8
7
6
5
4
3
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
HEADER 26
(JTHW)
GND
GND
DAT0
SEL0
DAT1
SEL1
DAT2
SEL2
DAT3
SEL3
DAT4
SEL4
DAT5
SEL5
DAT6
SEL6
DAT7
SEL7
N.C.
GND
BFLD/
GND
IPLD/
GND
+5V
INIT/
8
3A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
6
2A
10
J4A
3
1A
4
(JTHW)
GND
GND
DAT0
SEL0
DAT1
SEL1
DAT2
SEL2
DAT3
SEL3
DAT4
SEL4
DAT5
SEL5
DAT6
SEL6
DAT7
SEL7
N.C.
GND
BFLD/
GND
IPLD/
GND
+5V
INIT/
14
GND
6
4
5
8
7
5
ENA_0ENA_1-
ENA_0ENA_1-
C13
AGND
A+5V
.1UF
74HC138A
(SO16)
6
(DIP8)
G1
G2A
G2B
15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
C11
.1UF
AGND
RP3G
8
330
C14
100pf
U7
47K
8
7
1
6
C8
GND
5
.1UF
VCC
N.C.
VE
ANO
VOUT
GND
6N137
CAT
N.C.
1
7
2
RP5D
RESET-
RESET-
8
A+5V
1K
3
C15
4
1
RP5A
.1UF
(DIP8)
2
3
RP5B
1K
4
1K
GND
D8
1N6263
5
LOGIC GND-PLANE
RP5C
OPTO GND-PLANE
1K
Q1
2N3906
U10
6
1
2
3
R6
1M
E2
+ C16
1UF
4
IN
VCC
MODE
NMI
TOL
RST
GND
RST
8
D9
7
6
1N6263
C17
.1UF
5
DS1231-20
(DIP8)
TP2
AGND
12-24V
UNREGULATED
DC INPUT
TB2
F2
H1,H2 =
STRAP HOLE FOR `L1'
D1
1N5822
A+5V
+VIN
GND
100 UF
63V
OUTPUT
H1
2AMP
4
HOLE
L1
2
R1
330
E1
100 uH
(ON HEATSINK)
D3
5
C1
3
P6KE33A
+
FEEDBACK
ON/OFF
D2
U1
H2
+
1000 UF
16V
AGND
USE SAME COIL(L1) AS ACC34B `602375-101'
Board Layout and Connector Pinouts
23
C2
1N5822
HOLE
AGND
A+24V
TB1
F1
LM2576-5.0
1
1
2
2AMP
D4
LED
GRN
D5
1N5908
1
2
AGND
A+5V
Accessory 34DD
1
2
3
4
5
SDO
SDO
6
7
8
A+5V
U47A
SCLK
SCLK
1
C35
.1UF
RESET-
RESET-
2
A+5V
OPTO GND-PLANE
CLR
U26A
74HC393A
(S014)
AGND
ENA_1-
ENA_1-
3
4
5
6
QA
QB
QC
QD
A
1
2
3
4
5
3
2 (S014)
U47B
ENA_0A+5V
2
SDI_1
Q
12
11
CLK
Q
A+5V
ODD
A+5V
1
8
9
10
11
12
13
1
2
4
2
4
6
74HC280A
(S014)
RP23
3.3K
2
3
4
5
6
7
8
9
10
A+5V
12
SER
A
B
C
D
E
F
G
H
2
15
1
10
A+5V
U20
10
11
12
13
14
3
4
5
6
8
AGND
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6
1
1
CLK
INH
SH/LDSH/
QH
FOR GRAYHILL 70GRCM32
32 MODULE RACK
24, 16, OR 8 MODULE RACK
ADAPTER AVAILABLE FOR
DEC Q-BUS 32 MODULE RACKS
SDI_1
.1UF
A+5V
13
11
3
11
1
2
7
A
B
(S014)
8
9
9
CLK
CLR
QA
QB
QC
QD
QE
QF
QG
QH
AGND
74HC00A
(S014)
4
1KSIP8I
U28
13
VSS
RP31B
U34
2
3
4
5
6
7
8
9
3
4
5
6
10
11
12
13
74HC164A
7
A
AGND
.1UF
U26D
D1
D2
D3
D4
D5
D6
D7
D8
11
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
19
18
17
16
15
14
13
12
A+5V
C
OC
A+5V
C18
74AC563A
(SOL20)
.1UF
A+5V
5
U35
RP31C
C36
6
1KSIP8I
RP31D
7
8
9
10
11
12
13
1
2
4
.1UF
8
1KSIP8I
AGND
D9
LED
RED
WDO
C26
100PF
C27
A
B
C
D
E
F
G
H
I
EVEN
ODD
5
AGND
EVEN1
J3
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
6
A+5V
C19
.1UF
74HC280A
(S014)
100PF
AGND
A+5V
AGND
U26C
RP24
9
3.3K
10
11
12
13
14
3
4
5
6
10
U29
SER
A
B
C
D
E
F
G
H
2
15
1
8
A+5V
U21
2
3
4
5
6
7
8
9
10
OR ANY INDUSTRY STANDARD
SDI_1
C41
12
1
NOTE:
B
13
C43
2
9
74HC14P
(S014)
J2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RP31A
5
74HC165A
(S016)
GND
A+5V
GND
IN00GND
IN01GND
IN02GND
IN03GND
IN04GND
IN05GND
IN06GND
IN07GND
IN08GND
IN09GND
IN10GND
IN11GND
IN12GND
IN13GND
IN14GND
IN15GND/IN31IN16GND/IN30IN17GND/IN29IN18GND/IN28IN19GND/IN27IN20GND/IN26IN21GND/IN25IN22GND/IN24IN23-
.1UF
1
A+5V
74HC00A
EVEN1
EVEN2
EVEN3EVEN4-
1KSIP8I
3
AGND
QH
8
6
5 (S014)
74HC393A
(S014)
AGND
VDD
C30
.1UF
CLR
U33
9 (S014)
10
11
74HC4078A
12
4
.1UF
U25
14
Q
13
1
C28
A
B
C
D
E
F
G
H
I
EVEN
6
12
9
74HC00A
U26B
11
10
9
8
QA
QB
QC
QD
A
C42
74HC74A
(S014)
U19
5
A
Q
CLK
6
(S014)
74HC74A
D
CL
CL
AGND
5
PR
3
.1UF
D
PR
C29
U27B
4
U27A
10
A+5V
13
ENA-0-
74HC00A
(S014)
C31
1
2
.1UF
CLK
INH
SH/LDSH/
QH
A
B
(S014)
8
AGND
QH
U36
9
9
CLK
CLR
QA
QB
QC
QD
QE
QF
QG
QH
3
4
5
6
10
11
12
13
2
3
4
5
6
7
8
9
74HC164A
7
D1
D2
D3
D4
D5
D6
D7
D8
11
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
19
18
17
16
15
14
13
12
A+5V
C
OC
C20
74AC563A
(SOL20)
74HC165A
(S016)
.1UF
A+5V
U37
C37
8
9
10
11
12
13
1
2
4
.1UF
AGND
A
B
C
D
E
F
G
H
I
EVEN
ODD
5
AGND
EVEN2
6
A+5V
C21
.1UF
74HC280A
(S014)
AGND
HEADER 50
GND
A+5V
GND
OUT00GND
OUT01GND
OUT02GND
OUT03GND
OUT04GND
OUT05GND
OUT06GND
OUT07GND
OUT08GND
OUT09GND
OUT10GND
OUT11GND
OUT12GND
OUT13GND
OUT14GND
OUT15GND/OUT31OUT16GND/OUT30OUT17GND/OUT29OUT18GND/OUT28OUT19GND/OUT27OUT20GND/OUT26OUT21GND/OUT25OUT22GND/OUT24OUT23-
NOTE:
B
FOR GRAYHILL 70GRCM32
32 MODULE RACK
OR ANY INDUSTRY STANDARD
24, 16, OR 8 MODULE RACK
ADAPTER AVAILABLE FOR
DEC Q-BUS 32 MODULE RACKS
HEADER 50
A+5V
1
RP25
3.3K
AGND
A+5V
U22
2
3
4
5
6
7
8
9
10
10
11
12
13
14
3
4
5
6
C
2
15
1
AGND
U30
SER
A
B
C
D
E
F
G
H
1
2
C32
.1UF
(S014)
8
AGND
QH
CLK
INH
SH/LDSH/
QH
U38
A
B
9
9
CLK
CLR
QA
QB
QC
QD
QE
QF
QG
QH
3
4
5
6
10
11
12
13
2
3
4
5
6
7
8
9
74HC164A
7
D1
D2
D3
D4
D5
D6
D7
D8
11
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
19
18
17
16
15
14
13
12
C
OC
C22
74AC563A
(SOL20)
74HC165A
(S016)
C
A+5V
.1UF
A+5V
U39
C38
8
9
10
11
12
13
1
2
4
.1UF
AGND
A
B
C
D
E
F
G
H
I
EVEN
ODD
AGND
5
EVEN3-
6
A+5V
C23
.1UF
74HC280A
(S014)
AGND
A+5V
1
RP26
3.3K
A+5V
U23
2
3
4
5
6
7
8
9
10
10
11
12
13
14
3
4
5
6
U31
SER
A
B
C
D
E
F
G
H
2
15
1
1
2
C33
.1UF
8
AGND
QH
CLK
INH
SH/LDSH/
QH
9
9
CLK
CLR
QA
QB
QC
QD
QE
QF
QG
QH
3
4
5
6
10
11
12
13
2
3
4
5
6
7
8
9
74HC164A
7
D1
D2
D3
D4
D5
D6
D7
D8
11
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
19
18
17
16
15
14
13
12
C
OC
74AC563A
(SOL20)
74HC165A
(S016)
D
U40
A
B
(S014)
A+5V
C24
A+5V
D
.1UF
U41
C39
8
9
10
11
12
13
1
2
4
.1UF
A+5V
AGND
C34
6
11
SDI_0
SDI_0
Board Layout and Connector Pinouts
Q
1
2
CLK
A
B
(S014)
8
8
9
CLK
CLR
QA
QB
QC
QD
QE
QF
QG
QH
3
4
5
6
10
11
12
13
A+5V
EVEN
74HC280A
(S014)
ODD
5
AGND
EVEN4-
6
A+5V
C25
.1UF
DELTA TAU DATA SYSTEMS
AGND
C40
.1UF
Title
OPTO GND-PLANE
74HC164A
A+5V
3
Q
9
13
74HC74A
(S014)
D
CL
AGND
CLK
U32
PR
24
2
12
10
1
Q
U24B
5
1
A+5V
Q
CL
74HC74A
(S014)
D
PR
3
.1UF
4
U24A
2
A
B
C
D
E
F
G
H
I
AGND
4
AGND
5
6
7
ACC34D 32IN/32OUT OPTO I/O PCB, PANEL MOUNT
Size
D
Document Number
602xxx375-322
Date:
Tuesday, January 20, 1998
Rev
B
Sheet
8
3
of
3