Download F 19 SERVICE MANUAL

F 19 SERVICE MANUAL
THIS DOCUMENT IS A PROPERTY
OF INDUSTRIE FORMENTI ITALIA
NO AUTHORIZED MODIFICATIONS
ARE PERMITTED.
CREATED BY E.G.
There are two different types of F19 chassis that are equipped with two
different microcontroller.
These microcontroller are known as ETT having a code SAA5297A and
PAINTER with a code number SAA5553.
From the point of view of the application on the F19 chassis the two type of
microcontroller are substantially having the same performances, the same pinout , the same firmware but they are not interchangeable as the power supply
are different.
In case of SAA5297A the power supply is 5 V for the SAA5553 is 3.3 V.
Even if the two devices are non interchangeable the two chassis
can be interchanged as the in/out interface are exactly the same.
As the specifications of the two devices are the same and the first version of
the chassis was equipped with the SAA5297A , in this document
the
characteristics of it are very much detailed meanwhile there is a very short
description (as an addendum at the end) for the SAA5553.
F19 CHASSIS DESCRIPTION
Summary
The F19 is a chassis suitable to drive CRT having both 4 by 3 and 16 to 9 aspect
ratio and dimension from 25" up to 34".
As we can see from the block diagram the chassis is equipped with the most recent
Integrated Circuit like the one chip TV processor TDA884x that does include all the low
level signal processing including Video, Audio,
synchronisation process, and chroma
decoder . (see more detail at the "TDA884x FAMILY SPECIFICATION" paragraph), and
the Sound Processor TDA9875A that perform all sound function including digital decoding
of NICAM signals. (see more detail at the " TDA9870A & tda9875A MAIN
CHARACTERISTICS" paragraph).
The above mentioned devices are driven by an Integrated Circuit that does include
the microcontroller function with 64 K ROM and the TELETEXT acquisition and 8 pages
RAM. (SAA5297A)
In the F19 chassis there are, besides the stereo one, two possible module that are
performing "FEATURES" like
PIP (picture in picture) and / or CTI (colour transients
improvement) and 4 by 3 to 16 by 9 signal processing. One further module is dedicated to
the so called "Zero Power Stand By"
A 26 Key Remote Control is performing the full control for the end- used but can
also be used in " SERVICE MODE" to control and adjust, without open the back cover of
the TV set all the necessary functions.
With the 5 "LOCAL KEY BOARD" button all the end user function can also be
performed
When the TV set is equipped with a PLL tuner the microcontroller recognise it and
the tuning method became a frequency synthesis system if not it work as a voltage tuning
system (provided all necessary components are mounted)
The TV make use of a multilevel MENU (activated both by the Remote Control and
Local Keyboard) using five selectable languages ( Italian, German, English, France, end
Spanish) with which it is possible to control sequentially all video and sound value, to
adjust several parameter like picture format, sound response, sleep timer etc., and to set
others important parameter like standard, select country for automatic tuning and sort etc.
Here below a list of the characteristics of the TV se
E.G.Data creazione 31/10/99 15.38
1/7
f19intro
TV SET CHARACTERISTICS (MONO & STEREO )
PICTURE TUBE SIZE :
• 4 : 3 ASPECT RATIO
• 16 : 9 ASPECT RATIO
• STANDARD
• R.F. (ANTENNA) (FOR FREQ. SYNTH.)
• VIDEO (SCART & CINCH)
• COLOUR (MAX. THREE STANDARDS)
• SOUND STANDARD:
∗ MONO
∗ STEREO
TUNING SYSTEM SELECTABLE :
FREQUENCY SYTHETIZER
• TOTAL AVAILABLE CHANNEL NUMBER
• CHANNEL IN ONE RF STANDARD UP TO
• NUMBER OF PROGRAM
• DIRECT PROGRAM & CHANNEL CALL WITH
• PROGRAM & CHANNEL STEP UP AND DOWN
• VOLTAGE SYNTHESISER
• CABLE & HYPERBAND CHANNEL
• SWITCHABLE AFC
• AUTOMATIC SEARCH TUNING
• A S T WITH AUTO SORT
21” / 25” / 28” / 29” / 34”
28 “ / 32”
CCIR ( B / G/ L / L’ / D / K / I )
B / G/ L / L’ / D / K / I / M / N
PAL / SECAM / NTSC
B / G/ L / L’ / D / K / I
AM & FM
A2 OR NICAM
FACTORY OPTION
200
100
100
1, OR 2 OR 3 DIGIT
YES
YES
YES
YES
YES
AUDIO SECTION
POWER
• MONO
• STEREO
EXTERNAL CONNECTION
• HEADPHONE
• LOUDSPEAKERS
A / V INPUT / OUTPUT
• FRONT PANEL CINCH
• I FULL SCART (CVBS, STEREO, RBA)
• SCART (CVBS & STEREO IN / OUT)
• SCART A TO SCART B LOOP THROUGH
TXT
• LEVEL 1
• LEVEL 1,5 (FASTEXT)
FEATURES
• CTI (COLOUR TRANSIENT IMPROVEMENT)
• 16:9 TO 4:3 VIDEO COMPRESSION
• VERTICAL ZOOM OUT
• MENU DRIVEN SYSTEM
• EASY TO USE REMOTE CONTROL
• REMOTE CONTROL WITH “SERVICE” USE
• PIP
E.G.Data creazione 31/10/99 15.38
2/7
6 W RMS.
2 x 6 W RMS.
STEREO SET ONLY
INTERNAL L.S. SWITCHED
A / V INPUT
MULTIMEDIA INPUT OUTPUT
VCR, HI.FI, SATELLITE, ETC
FOR PROGRAMS DUBBING
PANEUROPEAN CHARACTER SET
8 PAGES
7 PAGES
OPTION
ONLY FOR 16:9 TV SET
3 LEVEL
NOT ACCESSIBLE TO END USER
OPTION
f19intro
TD
A9
87
5
AUDIO
AUDIO
TDA1521
THIS MODULE IS PRESENT ONLY FOR STEREO SET
AUDIO
AUDIO
TUNER
2ND SCART
A/V IN/OUT
SAW
FILTER
PLL
SCART INTER.
A /V OUT
A/V IN
FULL SCART
RGB
VIDEO PROCESSOR
TD
A
84
4X
EEPROM
PCF8582
VIDEO
&
AUDIO
RGB
VIDEO AMPL.
TDA 8362A
IIC bus
MICRO
SECAM
TDA8395
SA
A
52
97
A
PCA84C841/210
D.L. CROMA
TDA4661
TXT
SAA5281/....
H. DRIVER
BC 639
POWER SUPPLY
5
TDA 460
& STH7N80F
PIP (RGB)
F16 UPDATED F19
TDA5112
CUT-OFF
VERTICAL
TDA3654
E.W. GEN.
TDA4950
TXT & OSD
RBG
T.O.P.
PHILIPS
PIP
SIEMENS
RGB
(OSD)
L.O.T.
BU 508 D
V.
RGB
110°
H.
EHT
TRAFO
EAT
140 V
26 V
15 V
12 V
8V
F16UPF19.DRW
E.G.
2/02/99
BLOCK DIAGRAM
2x7W
AUDIO STEREO (NICAM) PROCESSOR
TDA 9811 (nicam)
V
I
D
E
O
F 19
TDA 9870A (TDA9875A (nicam)
I.
F.
AUDIO
AUDIO
AUDIO SCART SWITCH HEF4053
VIDEO & AUDIO
2ND SCART
A/V IN/OUT
A /V OUT
TUNER
VIDEOSCART
SWITCH LA7955
HEADPHONE
LINE OUT
(OPTION)
FULL SCART
A/V/ CINCH
(OPTION)
A/V IN
RGB
RGB
IIC BUS ONE CHIP VIDEO PROCESSOR
PLL
IIC bus
SAW
FILTER
IIC bus
LOCAL KEY BOARD
*IF VIDEO & PLL DEM
*AGC & AFC, MUTE
*AUDIO PLL DEM
*PAL/NTSC (SECAM) DEC.
*B.B CHROMA DELAY LINE
*FULL SCART INTERFACE.
ETT
4
SAA5297A
MICROCONTROLLER
& TELETEX 8 PAGES
PIP
OPTION
TXT
& OSD
RBG
CUT-OFF
RGB
VERTICAL
FEEDBACK
CRT
E-W-
FEATURES MODULE
E-W POWER
TDA4566 (CTI)
SAA4981 (16:9 TO 4:3)
BUK474200A
VERTICAL
TDA8351
H DRIVE
E-W DRIVE COIL
OPTION
H. DRIVER
I.R. INPUT
F19 BLOCK DIAGRAM
E-W LOAD COIL
*H & V SYNC PROCESSIG
*FULL IIC BUS CONTROLL FOR:
*AUTO CUT-OFF
*ALL ANALOGUE FUCTIONS
*GEOMETRY CORRECTION
*FEATURES INTERFACE
BC 338
PIP (RGB)
VIDEO AMPL.
TDA5112
TDA 8843 (4)
UV
IIC bus
TDA1521
THIS MODULE IS PRESENT ONLY FOR STEREO SET
I
N
T
E
R
C
A
R
R
I
E
R
A
U
D
I
O
EEPROM
PCF8584 /
ST2404CB
AUDIO POWER
POWER SUPPLY
TDA 4605 & STH7N90F1
DRIVER
TRAFO
150 V
26 V
12 V
8V
5V
L.O.T.
BU 508 D
V.
110°
H.
H. DEFL.
&EHT
TRAFO EAT
F19BLDIA.DRW
E.G.
17 / 7 / 99
2x7W
AUDIO STEREO (NICAM) PROCESSOR
AUDIO POWER
TDA 9811 (nicam)
F 19.1
EEPROM
PCF8584 /
ST2404CB
V
I
D
E
O
A
U
D
I
O
I.
F.
AUDIO
IIC bus
LOCAL KEY BOARD
2ND SCART
A/V IN/OUT
A /V OUT
VIDEOSCART
SWITCH LA7955
HEADPHONE
LINE OUT
(OPTION)
FULL SCART
A/V/ CINCH
(OPTION)
A/V IN
RGB
RGB
*IF VIDEO & PLL DEM
*AGC & AFC, MUTE
*AUDIO PLL DEM
*PAL/NTSC (SECAM) DEC.
*B.B CHROMA DELAY LINE
*FULL SCART INTERFACE.
UV
4
SAA5297A or
SAA5553M3
MICROCONTROLLER
& 8 PAGES TELETEXT
TXT
& OSD
RBG
CUT-OFF
E-W LOAD COIL
*H & V SYNC PROCESSIG
*FULL IIC BUS CONTROLL FOR:
*AUTO CUT-OFF
*ALL ANALOGUE FUCTIONS
*GEOMETRY CORRECTION
*FEATURES INTERFACE
E-W-
FEATURES MODULE
RGB
VERTICAL
FEEDBACK
CRT
VERTICAL
TDA8351
E-W POWER
BUK474200A
TDA4566 (CTI)
SAA4981 (16:9 TO 4:3)
VIDEO AMPL.
TDA5112
TDA 8843 (4)
ETT
OPTION
AUDIO SCART SWITCH HEF4053
IIC BUS ONE CHIP VIDEO PROCESSOR
SAW
FILTER
PIP
AUDIO
VIDEO & AUDIO
PLL
IIC bus
TDA1521
THIS MODULE IS PRESENT ONLY FOR STEREO SET
I
N
T
E
R
C
A
R
R
I
E
R
TUNER
IIC bus
TDA 9870A (TDA9875A (nicam)
H DRIVE
V.
110°
H.
E-W DRIVE COIL
OPTION
H. DRIVER
BC 338
DRIVER
TRAFO
I.R. INPUT
L.O.T.
BU 508 D
H. DEFL.
&EHT
TRAFO EAT
150 V
PIP (RGB)
POWER SUPPLY
26 V
12 V
F19.1 BLOCK DIAGRAM
TDA 4605 & STH7N90F1
8V
5V
F19BDE&P.DRW
E.G. 22/04/2000
F19
TUNING
&
TELETEXT
SAA529XA FAMILY MAIN CHARACTERISTICS
FEATURES
General
•
Single chip microcontroller with integrated teletext decoder
•
Single +5 V power supply
•
Single crystal oscillator for teletext decoder, display and microcontroller
•
Teletext function can be powered-down independent of microcontroller function for
reduced power consumption in standby
•
Pin compatibility throughout family.
Microcontroller
•
80C51 microcontroller core
•
16/32/64 kbyte mask programmed ROM
•
256/768/1280 bytes of microcontroller RAM
•
Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals
•
One 14-bit PWM for Voltage Synthesis Tuner control
•
Four 8-bit Analog-to-Digital converters
•
2 high current open-drain outputs for directly driving LEDs etc.
•
I 2 C-bus interface
•
External ROM and RAM capability on QFP80 package version.
Teletext acquisition
•
1 page and 10 page Teletext version
•
Acquisition of 525-line and 625-line World System Teletext, with automatic selection
•
Acquisition and decoding of VPS data (PDC system A)
•
Page clearing in under 64
•
Separate storage of extension packets (SAA5296/7, SAA5296/7A and SAA5496/7)
•
Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT)
s (1 TV line)
end Subtitle Page Table (SPT) (SAA5296/7, SAA5296/7A and SAA5496/7)
•
Automatic detection of FASTEXT transmission
E.G.Data creazione 01/11/99 17.27
8 / 30
F19MANU.doc
SAA5297A
FRANCE STD. SWITCH
CTI DETECTOR
16 : 9 DETECTOR
SCART1 / SCART2 SWITCH
SCART 1 / TV
TO SCART 2 SWITCH
FRONT CINCH / SCART1
SWITCH
SCART 1 INPUT DETECTOR
SCART 2 INPUT DETECTOR
HEAD PHONES DETECTOR
STANDARD SWITCH
UHF SUPPLY
(VOLTAGE SINTESYS ONLY)
TV / AV SWITCH
MENU V - V + P -
P+
LOCAL KEY BOARD
TV ON / OFF SWITCH
TUNER SUPPLY (V.S. ONLY)
TUNER SUPPLY(V.S. ONLY)
CVBS FROM ANTENNA
CVBS FROM SCART
SAA5297A.DRW
E.G . 17 / 10 / 99
DATA
SLICER
REF.PIN
V TUN.
DSC
SWT. L/L'
CTI STS.
16:9 STS
SWT. S1/S2
COPY SWT.
SWT. CI/S1
AV1 STS.
AV2 STS.
H.P. STS.
SYSTEM
VSS M+T
UHF
TV / AV
P0.3
P0.4
P0.5
ON / OFF
VHF H
VHF L
VSSA
CVBS0
CVBS1
BLACK
IREF
ROM
RAM
P
O
R
T
2
P
O
R
T
3
P
O
R
T
0
A/ D
PWM
B
U
S
TXT
INT
PAGE
RAM
T X T DATA
SLICER &
ACQUISITION
SWT 16:9
P OSC. SWT.
O
MSDA
R
MSCL
T
SDA 1
1
INTO
SCL 1
AM/FM
8051
VDDM
CORE
RESET
OSCOUT
R
O
OSCIN
AT
L
L
CI
OSCGND
OS
VDDT
VDDA
VSYNC
HSYNC
BLK
R
G
B
RGBREF
PIP STS
INT. TEST
FRAME
TIMER
D
TI ISP
M LA
IN Y
G
TO X13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DI
SP
LA
Y
TO CURRENT INTEGRATOR
VOLTAGE SINTESYS ONLY
MICRO & TXT Block Diagram
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TO CHANGE
ASPECT RATIO
TO SWITCH S.C.
FROM 4.43
TO 3.58 MHz
MAIN
IIC BUS
I.R.
IIC BUS
FOR
EEPROM
SOUND STANDARD
SWITCH
5 V from ST-BY
FROM
RESESET CIRCUIT
QZ100
12 MHz
5V
VERTICAL
FLYBACK
HORIZONTAL
FLYBACK PULSE
TO
TDA884X
RGB REFERENCE
2,5 VVOLTAGE
PIP DETECTOR
NOT CONNECTED
NOT CONNECTED
SAA5553M3
FRANCE STD. SWITCH
CTI DETECTOR
16 : 9 DETECTOR
SCART1 / SCART2 SWITCH
SCART 1 / TV
TO SCART 2 SWITCH
FRONT CINCH / SCART1
SWITCH
SCART 1 INPUT DETECTOR
SCART 2 INPUT DETECTOR
HEAD PHONES DETECTOR
STANDARD SWITCH
UHF SUPPLY
(VOLTAGE SINTESYS ONLY)
TV / AV SWITCH
MENU V - V + P -
P+
LOCAL KEY BOARD
TV ON / OFF SWITCH
TUNER SUPPLY (V.S. ONLY)
TUNER SUPPLY(V.S. ONLY)
CVBS FROM ANTENNA
CVBS FROM SCART
SAA5553.DRW
E.G 22/ 04 / 2000
DATA
SLICER
REF.PIN
V TUN.
DSC
SWT. L/L'
CTI STS.
16:9 STS
SWT. S1/S2
COPY SWT.
SWT. CI/S1
AV1 STS.
AV2 STS.
H.P. STS.
SYSTEM
VSS M+T
UHF
TV / AV
P0.3
P0.4
P0.5
ON / OFF
VHF H
VHF L
VSSA
CVBS0
CVBS1
BLACK
IREF
ROM
RAM
TIMER
P
O
R
T
2
P
O
R
T
3
P
O
R
T
0
P
O
R
T
1
A/ D
PWM
B
U
S
TXT
INT
PAGE
RAM
T X T DATA
SLICER &
ACQUISITION
8051
CORE
R
TO
A
LL
CI
S
O
DI
TI SP
M LA
IN Y
G
TO X13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DI
SP
LA
Y
TO CURRENT INTEGRATOR
VOLTAGE SINTESYS ONLY
MICRO & TXT Block Diagram
SWT 16:9
OSC. SWT.
MSDA
MSCL
SDA 1
INTO
SCL 1
AM/FM
VDDM
RESET
OSCOUT
OSCIN
OSCGND
VDDT
VDDA
VSYNC
HSYNC
BLK
R
G
B
RGBREF
PIP STS
INT. TEST
FRAME
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TO CHANGE
ASPECT RATIO
TO SWITCH S.C.
FROM 4.43
TO 3.58 MHz
MAIN
IIC BUS
I.R.
IIC BUS
FOR
EEPROM
SOUND STANDARD
SWITCH
5 V from ST-BY
FROM
RESESET CIRCUIT
QZ100
12 MHz
3V
VERTICAL
FLYBACK
HORIZONTAL
FLYBACK PULSE
TO
TDA884X
RGB REFERENCE
2,5 V VOLTAGE
PIP DETECTOR
NOT CONNECTED
NOT CONNECTED
•
Real-time packet 26 engine for processing accented (and other) characters
•
Comprehensive Teletext language coverage
•
Video signal quality detector.
Teletext Display
•
525-line and 625-line display
•
12
•
Double height, width and size On-Screen Display (OSD)
•
Definable border colour
•
Enhanced display features including meshing and shadowing
•
260 characters in mask programmed ROM
•
Automatic FRAME output control with manual override
•
RGB push-pull output to standard decoder ICs
•
Stable display via slave synchronisation to horizontal sync and vertical sync.
10 character matrix
Additional features of SAA529xA devices
•
Wide Screen Signalling (WSS) bit decoding (line 23).
2 GENERAL DESCRIPTION
The SAA529x, SAA529xA and SAA549x family of microcontrollers are a derivative of the
Philips’ industry-standard 80C51 microcontroller and are intended for use as the central
control mechanism in a television receiver. They provide control functions for the television
system and include an integrated teletext function.
The teletext hardware has the capability of decoding and displaying both 525-line and 625line World System Teletext. The same display hardware is used both for Teletext and OnScreen Display, which means that the display features give greater flexibility to
differentiate the TV set.
The family offers both 1 page and 10 page Teletext capability, in a range of ROM sizes.
Increasing display capability is offered from the SAA5290 to the SAA5497.
TELETEXT DECODER
Data slicer
E.G.Data creazione 01/11/99 17.27
9 / 30
F19MANU.doc
The data slicer extracts the digital teletext data from the incoming analog waveform. This
is performed by sampling the CVBS waveform and processing the samples to extract the
teletext data and clock.
Acquisition timing
The acquisition timing is generated from a logic level positive-going composite sync signal
VCS. This signal is generated by a sync separator circuit which adaptively slices the sync
pulses. The acquisition clocking and timing are locked to the VCS signal using a digital
phase-locked-loop. The phase error in the acquisition phase-locked-loop is detected by a
signal quality circuit which disables acquisition if poor signal quality is detected.
Teletext acquisition
This family is capable of acquiring 625-line and 525-line World System Teletext see “World
System Teletext and Data Broadcasting System”. Teletext pages are identified by seven
numbers: magazine (page hundreds), page tens, page units, hours tens, hours units,
minutes tens and minutes units. The last four digits, hours and minutes, are known as the
subcode, and were originally intended to be time related, hence their names.
For the ten page device, each packet can only be written into one place in the teletext
RAM so if a page matches more than one of the page requests the data is written into
the area of memory corresponding to the lowest numbered matching page request.
At power-up each page request defaults to any page, hold on and error check Mode 0.
Rolling headers and time
When a new page has been requested it is conventional for the decoder to turn the header
row of the display green and to display each page header as it arrives until the correct
page has been found.
Error checking
Before teletext packets are written into the page memory they are error checked. The error
checking carried out depends on the packet number, the byte number, the error check
mode bits in the page request data and the TXT1.8 BIT bit. If an uncorrectable error
occurs in one of the Hamming checked addressing and control bytes in the page header
or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory
is set, to act as an error flag to the software. If uncorrectable errors are detected in any
other Hamming checked data the byte is not written into the memory.
E.G.Data creazione 01/11/99 17.27
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F19MANU.doc
Packet 26 processing
One of the uses of packet 26 is to transmit characters which are not in the basic teletext
character set. The family automatically decodes packet 26 data and, if a character
corresponding to that being transmitted is available in the character set, automatically
writes the appropriate character code into the correct location in the teletext memory. This
is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and
so is often referred to as level 1.5.
By convention, the packets 26 for a page are transmitted before the normal packets. To
prevent the default character data overwriting the packet 26 data the device incorporates a
mechanism which prevents packet 26 data from being overwritten.
Fastext detection
When a packet 27, designation code 0 is detected, whether or not it is acquired, the
TXT13.FASTEXT bit is set. If the device is receiving 525-line teletext, a packet X/0/27/0 is
required to set the flag. The flag can be reset by writing a logic 0 into the SFR bit.
When a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525-line
transmission, the TXT13.Pkt 8/30 is set. The flag can be reset by writing a logic 0 into the
SFR bit.
THE DISPLAY
Introduction
The capabilities of the display are based on the requirements of level 1 teletext, with some
enhancements for use with locally generated on screen displays. The display consists of
25 rows each of 40 characters, with the characters displayed being those from rows 0 to
24 of the basic page memory. If the TXT7.STATUS ROW TOP bit is set row 24 is
displayed at the top of the screen, followed by row 0, but normally memory rows are
displayed in numerical order. The teletext memory stores 8 bit character codes which
correspond to a number of displayable characters and control characters, which are
normally displayed as spaces. The character set of the device is described in more detail
below.
E.G.Data creazione 01/11/99 17.27
11 / 30
F19MANU.doc
(OPTION BYTE 1
BIT 3 SETTED TO 0
EAST EUROPE
CHARACTER SET
NATIONAL OPTION FOR:
POLISH
GERMAN
ESTONIAN
SERBO-CROAT
CZECH
SLOVAKIA
RUMANIAN
WEST EUROPE
CHARACTER SET
NATIONAL OPTION FOR:
WEST
ENGLISH
GERMAN
SWEDISH
ITALIAN
FREANCH
SPANISH
TURKISH
(OPTION BYTE 1
BIT 6 SETTED TO 1
EAST
PL
D
CZ
A
H
Y
F19 E&WCS.DRW
E.G.
7/11/99
R
Character matrix
Each character is defined by a matrix 12 pixels wide and 10 pixels high. When displayed,
each pixel is 1
12
s wide and 1 TV line, in each field, high.
East/West selection
In common with their predecessors, these devices store teletext pages as a series of 8 bit
character codes which are interpreted as either control codes (to change colour, invoke
flashing etc.) or displayable characters. When the control characters are excluded, this
gives an addressable set of 212 characters at any given time.
National option characters
The meanings of some character codes between 20H and 7FH depend on the C12 to C14
language control bits from the teletext page header.
The interpretation of the C12 to C14 language control bits is dependent on the East/West
bit.
On-Screen Display characters
Character codes 80H to 9FH are not addressed by the teletext decoding hardware. An
editor is available to allow these characters to be redefined by the customer.
The
alternative character shapes in columns 8a and 9a (SAA549x only) can be displayed when
the ‘graphics’ serial attribute is set. This increases the number of customer definable
characters to 64.
Clock generator
The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration.
The circuitry between XTALIN and XTALOUT is basically an inverter biased to the transfer
point. A crystal must be used as the feedback element to complete the oscillator circuitry.
It is operated in parallel resonance. XTALIN is the high gain amplifier input and XTALOUT
is the output. To drive the device externally XTALIN is driven from an external source and
XTALOUT is left open-circuit.
E.G.Data creazione 01/11/99 17.27
12 / 30
F19MANU.doc
12 V
SOUND I.F.
TUNUNG
VOLTAGE
TO PIN 2
TR500
TUNER
AM
SOUND
FILTER
TO X13
F204
TR219
12V
TR218
CVBS PIN 6
IC 204
TR200
SAA5297A
5V
TO PIN 4 IC 201
TO PIN
10, 11
IC 200
R174
TO PIN 8 IC 201
R128
R140
R141
TR110
TR201
FRON PIN 8 SCART 1
FROM PIN 8 SCART 2
F575
5V
TO PIN 1
IC 204
F576
R146
TR209
TR210
TR111
TR107
TO SWITC INT/EX SOUND
TO STEREO
NICAM
MODULE
TO PIN 4
IC 10
MENU V - V + P -
TR2
TV ON / OFF
TR 502
PIN 5
T
O
CVBS FROM
ANTENNA
TR 501
TR203
PIN 3
T
U
N
E
R PIN 4
CVBS
FROM SCART TR211
TR503
5V
P+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MICRO & TXT PERIPHERALS
V TUN. SWT 16:9
OSC. SWT.
DSC
SWT. L/L' MSDA
MSCL
CTI STS.
SDA 1
16:9 STS
SWT. S1/S2 INTO
COPY SWT. SCL 1
SWT. CI/S1 AM/FM
VDDM
AV1 STS.
AV2 STS. RESET
H.P. STS. OSCOUT
OSCIN
SYSTEM
VSS M+T OSCGND
VDDT
UHF
VDDA
TV / AV
VSYNC
P0.3
HSYNC
P0.4
BLK
P0.5
R
ON / OFF
G
VHF H
B
VHF L
RGBREF
VSSA
PIP STS
CVBS0
COR
CVBS1
BLACK INT. TEST
FRAME
IREF
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TO CTI &
16:9 MOULE
TR 208
TR 109
4.43 MHz
TR206
3.58MHz
IIC BUS
TR 205
EEPROM
IC 101
IIC BUS
IRR100
SOUND STDANDARD SWITCH
TR 108
TO PIN 10
IC 102
5V ST-BY
TR 105
D 105
QZ100
12 MHz
R 106
5V
D 102
FLYBACK PULSE
FROM EHT
D 108
TO
PIN 35
IC 204
VERTICAL
BLANKING
FROM PIN 8
IC 5
TO PIN
23, 24, 25
IC 204
TR 101
TR 102
TR 103
5V
R167
F19MTPER.DRW
E.G.
24 /10 /99
FOR VOLTAGE
SISTETIZER ONLY
12 V
SOUND I.F.
TUNUNG
VOLTAGE
TO PIN 2
TUNER
AM
SOUND
FILTER
TR500
TO X13
F204
TR219
12V
TR218
CVBSPIN 6
IC 204
TR200
SAA 5553 MICRO
R174
5V
R128
TO PIN 4 IC 201
TO PIN
10, 11
IC 200
TO PIN 8 IC 201
R140
R141
TR110
TR201
FRON PIN 8 SCART 1
FROM PIN 8 SCART 2
F575
5V
TO PIN 1
IC 204
F576
R146
TR209
TR210
TR111
TR107
TO SWITC INT/EX SOUND
TO STEREO
NICAM
MODULE
TO PIN 4
IC 10
MENU V - V + P -
TR2
TV ON / OFF
TR 502
PIN 5
T
O
TR 501
CVBS FROM
ANTENNA
TR203
PIN 3
T
U
N
E
R PIN 4
TR503
CVBS
FROM SCART TR211
5V
P+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V TUN. SWT 16:9
DSC
OSC. SWT.
SWT. L/L' MSDA
MSCL
CTI STS.
SDA 1
16:9 STS
SWT. S1/S2 INTO
COPY SWT. SCL 1
SWT. CI/S1AM/FM
AV1 STS. VDDM
AV2 STS. RESET
H.P. STS. OSCOUT
SYSTEM OSCIN
VSS M+T OSCGND
VDDT
UHF
VSSA
TV / AV
VSYNC
P0.3
HSYNC
P0.4
BLK
P0.5
R
ON / OFF
G
VHF H
B
VHF L
RGBREF
VSSA
PIP STS
CVBS0
COR
CVBS1
BLACK INT. TEST
FRAME
IREF
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
& TXT PERIPHERALS
TO CTI &
16:9 MOULE
TR 208
TR 109
4.43 MHz
TR206
3.58MHz
IIC BUS
TR 205
EEPROM
IC 101
IIC BUS
IRR100
TO
PIN 35
IC 204
SOUND STDANDARD SWITCH
TO PIN 10
IC 102
3,3 V
TR 108
TR 105
TR8
5V
R39
D 105
QZ100
12 MHz
R40
3,3 V
TR7
5V
D5
D 108
2,5V
FLYBACK
FROM EHT
D 102
VERTICAL
BLANKING
FROM PIN 8
IC 5
TO PIN
23, 24, 25
IC 204
TR 101
TR 102
TR 103
5V
R167
F19PAPER.DRW
E.G. 22 / 04 /2000
FOR VOLTAGE
SISTETIZER ONLY
PAINTER
VIDEO
SIGNAL
PROCESSING
FOR VOLTAGE SINTHESIS ONLY
F 19
EF
EF
TR201
TR200
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IIC
TR202
TO PIN 33
IC100
CVBS
EF
FOR TXT
TR203
TO PIN 24
IC 100
(CVBS FOR TXT)
TO PIN 9
IC 100
AV1
STATUS
SCART 1
EF
VIDEO IN
CINCH
EF
19
8
TR204
15
11
7
16
20
SIF
AUDEXT
NC
NC
PLLIF
IFVIDEO OUT
SCL
SDA
DECOUPLING
TDA884X
I.F.
VIDEO
AGC
AFC
DEM.
IDENT
MSD
PAL
(SECAM)
NTSC
CHR.IN
EX.CVBS/Y IN
VP1
INT CVBS IN
GND
AUDIO OUT
DECOUPLING
C.D. &
RGB
MATRIX
VIDEO
CONTROL
SOUND
PROCES.
(MONO)
EX. CVBS IN
BLKIN
B OUT
G OUT
R OUT
BCL/VG
R IN
SYNC
PROCES.
V. & H.
TIME
BASE
EXT RGB
SWITCH
& RGB
DRIVE
G IN
B IN
RGB INSERT.
Y IN
Y OUT
IIC
TRANSRECEIVER
DECOUPLING
DEENPHASIS
AGC OUT
DECOPLING
I REF
VERT. RAMP
EHT PROTEC.
IF IN 2
IF IN 1
V. DRIVE A
V. DRIVE B
E - W OUT
GND 2
PH. 1 FILTER
PH. 2 FILTER
H. IN, S.C. OUT
HOR. OUT
DECOUPLING
CVBS 1 OUT
VP2
DET FILTER
X TAL 2
X TAL 1
S.C. REF OUT
R - Y IN
B - Y IN
R - Y OUT
B - Y OUT
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TR500
IIC
FROM PIN 6
IC100
AV1 / AV2
SWITCH
1
3.58MHz
TV
CVBS
FROM PIN 7
IC100
AV1 / TV
SWITCH
TO AV2
9
3
2
7
8
SCART 2
1/3 0F IC201
LA7955
CVBS IN
TO PIN 10
IC 100
AV2 STATUS
EF
TR206
8V
RGB AMPLIFIER
MODULE
TR212
CVBS OUT
FROM IC 100
PIN 14, 20, 21
BAND SWITCHING
TR105
FROM
PIN 51
IC 100
4.43MHz
3,57MHz
A10
1
2
3
4
5
5V
5
TR503
VHF H
VHF LTR502
TR208
6
CVBS IN
UHF
10
11
12 V
4
2
3
4
5
6
5V
7
8
9
EF
EF
TR501
1
12 V
TR211
FROM PIN 1
IC 100
∫
UV
6
7
8
9
10
11
12
TR205
CTI
&
4:3
TO
16 : 9
FROM PIN 52
IC 100 4:3 TO 16:9
SWITCH
8
20
19
TO CRT
FROM EHT
8V
VIDEO SIGNAL PATH
F19VIDEP.DRW
E.G.
14 / 11 / 99
Reset signal
The externally applied RESET signal (active HIGH) is used to initialize the microcontroller
core, in addition to the teletext decoder. However, the teletext decoder incorporates a
separate internal reset function which is activated on the rising edge of the analog supply
pin, VDDA . The purpose of this internal reset circuit is to initialize the teletext decoder when
returning from the “text standby mode”.
TDA884X FAMILY SPECIFICATION
FEATURES
The following features are available in all IC’s:
• Multi-standard vision IF circuit with an alignment-freePLL demodulator without external
components
• Alignment-free multi-standard FM sound demodulator(4.5 MHz to 6.5 MHz)
• Audio switch
• Flexible source selection with CVBS switch andY(CVBS)/C input so that a comb filter can
be applied
• Integrated chrominance trap circuit
• Integrated luminance delay line
• Asymmetrical peaking in the luminance channel with a(defeatable) noise coring function
• Black stretching of non-standard CVBS or luminancesignals
• Integrated chroma band-pass filter with switchablecentre frequency
• Dynamic skin tone control circuit
• Blue stretch circuit which offsets colours near whitetowards blue
• RGB control circuit with “Continuous CathodeCalibration” and white point adjustment
• Possibility to insert a “blue back” option when no videosignal is available
• Horizontal
synchronization
with
two
control
loops
andalignment-free
horizontal
oscillatoroptimised N2 application.Functionally the IC series is split up is 3 categories,
viz:
E.G.Data creazione 01/11/99 17.27
13 / 30
F19MANU.doc
Secam
Decoupling
CVBS OUT
CVBS (int) IN
CVBS / Y IN
(comb filter)
CVBS OUTPUT
CVBS (ext) IN
CHROMA IN
6
TUNER
AGC
54
13
17
11
10
SCL
38
7
SDA
8
TUNER T.O.P
IF
&
TUNER
A G C
gating
calibration
I.F. value
53
PLL
FILTER
49
Sensitivity
MOD
Pos./Neg.
5
A
F
W
VIDEO
AMPLIFIER
AFC
Y DELAY,
C. TRAP,
Y PEAKING
H. SYNC
V . SYNC
SEPARATOR
SEPARATOR
AFA
AFB
55
Deenphasis
V. sync
H. sync
VIDEO
IDENT.
VIDEO
MUTE
PHI 1
AVL
LINE
(45)
Volume
1
INTERCARRIER
IN
BandGap
Decoupling
BRI
MONO AUDIO OUTPUT
AUDIO
LIMITER
1 A 10 MHz
B.P.F.
9
12
8 V Main
Supply
37
8V
Supply
PHI 2
LINE OUT
S.C. GENER.
AUDIO
PLL DEM.
14
56
Ground
Sound
Decoupling
43
Phi 1
filter
42
Phi 2
filter
41
VERTICAL
DRIVE
E-W
GEOMETRY
40
51
52
31
45
Flyback in Line
E-W
Sand
Pulse
DRIVE
Vertical
Castle
Out
Sawtooth
Reference
Out
50
EHT
Overvoltage
Fsc
Y
B-Y
R-Y
Y
B-Y
32
R-Y
23
24
R
25
26
18
RGB CONTROL
AUTO CUT-OFF
& OUTPUT
VERTICAL
SAWTOOTH
GENERATOR
OSCILL.
SWT
AVL
Decoupling
R-Y & B-Y
MATRIX
SAT CONTR.
BLACK STRETCH
SKIN TINT CORR.
RGB SWITCH
CON
AUDIO PRE
AMPLIFIER
& MUTE
SWITCH &
VOLUME
30
27
VERTICAL
DEVIDER
AVL
EXTERNAL
AUDIO
SWITCH
EXTERNAL
AUDIO IN
15
DSA
DETECTOR
DEENPHASIS LINE
Internal
Audio
2
A.F.
SAT
MAT
TDA 8844
BASE BAND
CHROMA
DELAY LINE
GAI
AUTO
SYSTEM
IDENT.
MANAGER
33
29
PAL / NTSC
SECAM
DECODER
CHROMA
CLOCHE &
BANDPASS
36
28
Subcarrier
Chroma
To Sync
I.F IN
Luma
PLL
DEMOD.
& VCO
VIDEO IF
AMPLIFIER
35
BURST PHASE
DETECTOR
& VCXO
IIC
48
34
16
IIC
TRANSRECEIVER
CVBS & Y/C
SWITCH
Loop
filter
Phase
Detector
Xtal
19
20
I
N
P
U
T
G
B
F.B.
Black
O
Currente
U
Input
T
R
P
U
G
T
21
B
47
Vertical
Drive
Output
46
22
V- Guard &
B.C. limiter
TDA8844BLDIA.DRW
E.G.
17 /10 / 99
• Versions intended to be used in economy TV receiverswith all basic functions (envelope:
S-DIP 56 and QFP 64)
• Versions with additional features like E-W geometrycontrol, H-V zoom function and YUV
interface which are intended for TV receivers with 110° picture tubes(envelope: S-DIP 56)
• Versions which have in addition a second RGB inputwith saturation control and a second
CVBS output (envelope: QFP 64)
• Vertical count-down circuit
• Vertical driver optimised for DC-coupled vertical outputstages
GENERAL DESCRIPTION
The various versions of the TDA 884X/5X series areI 2 C-bus controlled single chip TV
processors which are
intended to be applied in PAL, NTSC, PAL/NTSC and multi-standard television receivers.
The N2 version is pin and application compatible with the N1 version, however,a new
feature has been added which makes the N2 more attractive. The IF PLL demodulator has
been replaced byan alignment-free IF PLL demodulator with internal VCO (no tuned circuit
required). The setting of the variousfrequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75
MHz) can be made via the I 2 C-bus.
Because of this difference the N2 version is compatiblewith the N1, however, N1 devices
cannot be used in an optimized N2 application
Functionally the IC series is split up is 3 categories, viz:
• Versions intended to be used in economy TV receivers with all basic functions (envelope:
S-DIP 56 and QFP 64)
• Versions with additional features like E-W geometry control, H-V zoom function and YUV
interface which areintended for TV receivers with 110° picture tubes (envelope: S-DIP 56)
• Versions which have in addition a second RGB input with saturation control and a
second CVBS output (envelope: QFP 64)
FUNCTIONAL DESCRIPTION
Vision IF amplifier
The IF-amplifier contains 3 ac-coupled control stages with a total gain control range which
is higher then 66 dB. The sensitivity of the circuit is comparable with that of modern
E.G.Data creazione 01/11/99 17.27
14 / 30
F19MANU.doc
IF-IC’s.
The video signal is demodulated by means of an alignment-free PLL carrier regenerator
with an internalVCO. This VCO is calibrated by means of a digital control circuit which
uses the X-tal frequency of the colour decoder as a reference. The frequency setting for
the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz) is realised via the I 2 Cbus. To get a good performance for phase modulated carrier signals the control speed of
the PLL can be increased by means of the FFI bit.
The AFC output is generated by the digital control circuit of the IF-PLL demodulator and
can be read via the I 2 C-bus.
For fast search tuning systems the window of the AFC can be increased with a factor 3.
The setting is realised with the AFW bit. The AFC data is valid only when the horizontal
PLL is in lock (SL = 1)
Depending on the type the AGC-detector operates on top-sync level (single standard
versions) or on top sync and top white- level (multi standard versions). The demodulation
polarity is switched via the I 2 C-bus. The AGC detector time-constant capacitor is
connected externally. This mainly because of the flexibility of the application. The timeconstant of the AGC system during positive modulation is rather long to avoid visible
variations of the signal amplitude. To improve the speed of the AGC system a circuit has
been included which detects whether the AGC detector is activated every frame period.
When during 3 field periods no action detected the speed of the system is increased. For
signals without peak white information the system switches automatically to a gated black
level AGC. Because a black level clamp pulse is required for this way of operation the
circuit will only switch to black level AGC in the internal mode.
The circuits contain a video identification circuit which is independent of the
synchronisation circuit. Therefore search tuning is possible when the display section of the
receiver is used as a monitor. However, this ident circuit cannot be made as sensitive as
the slower sync ident circuit (SL) and we recommend to use both ident outputs to obtain a
reliable search system. The ident output is supplied to the tuning system via the I 2 C-bus.
The input of the identification circuit is connected to pin 13 (S-DIP 56 devices), the
“internal” CVBS input (see Fig.6).
This has the advantage that the ident circuit can also be made operative when a
scrambled signal is received (descrambler connected between pin 6 (IF video output) and
pin 13). A second advantage is that the ident circuit can be used when the IF amplifier is
not used (e.g. with built-in satellite tuners).
E.G.Data creazione 01/11/99 17.27
15 / 30
F19MANU.doc
The video ident circuit can also be used to identify the selected CBVS or Y/C signal. The
switching between the 2 modes can be realised with the VIM bit.
Video switches
The circuits have two CVBS inputs (internal and external CVBS) and a Y/C input. When
the Y/C input is not required the Y input can be used as third CVBS input. The switch
configuration is given in Fig.6. The selection of the various sources is made via the I 2 Cbus.
For the TDA 884X devices the video switch configuration is identical to the switch of the
TDA 8374/75 series. So the circuit has one CVBS output (amplitude of 2 VP-P for the
TDA884X series) and the I 2 C-bus control is similar to that of the TDA 8374/75. For the
TDA 885X IC’s the video switch circuit has a second output (amplitude of 1 VP-P ) which
can be set independently of the position of the first output. The input signal for the decoder
is also available on the CVBS1-output.
Therefore this signal can be used to drive the Teletext decoder. If S-VHS is selected for
one of the outputs the luminance and chrominance signals are added so that a CVBS
signal is obtained again.
Sound circuit
The sound bandpass and trap filters have to be connected externally. The filtered
intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL
demodulator. This PLL circuit tunes itself automatically to the incoming carrier signal so
that no adjustment is required.
The volume is controlled via the I 2 C-bus. The deemphasis capacitor has to be connected
externally. The non-controlled audio signal can be obtained from this pin (via a buffer
stage).
The FM demodulator can be muted via the I 2 C-bus. This function can be used to switchoff the sound during a channel change so that high output peaks are prevented.
The TDA 8840/41/42/46 contain an Automatic Volume Levelling (AVL) circuit which
automatically stabilises the audio output signal to a certain level which can be set by the
viewer by means of the volume control. This function prevents big audio output fluctuations
due to variations of the modulation depth of the transmitter. The AVL function can be
activated via the I 2 C-bus.
Synchronisation circuit
E.G.Data creazione 01/11/99 17.27
16 / 30
F19MANU.doc
The sync separator is preceded by a controlled amplifier which adjusts the sync pulse
amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at
50% of the amplitude. The separated sync pulses are fed to the first phase detector and to
the coincidence detector. This coincidence detector is used to detect whether the line
oscillator is synchronised and can also be used for transmitter identification. This circuit
can be made less sensitive by means of the STM bit. This mode can be used during
search tuning to avoid that the tuning system will stop at very weak input signals. The first
PLL has a very high statical steepness so that the phase of the picture is independent of
the line frequency.
The horizontal output signal is generated by means of an oscillator which is running at
twice the line frequency. Its frequency is divided by 2 to lock the first control loop to the
incoming signal. The time-constant of the loop can be forced by the I 2 C-bus (fast or
slow). If required the IC can select the time-constant depending on the noise content of the
incoming video signal.
The free-running frequency of the oscillator is determined by a digital control circuit which
is locked to the reference signal of the colour decoder. When the IC is switched-on the
horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the
horizontal drive signal is switched-on. To obtain a smooth switching-on and switching-off
behaviour of the horizontal output stage the horizontal output frequency is doubled during
switch-on and switch-off (slow start/stop). During that time the duty cycle of the output
pulse has such a value that maximum safety is obtained for the output stage.
To protect the horizontal output transistor the horizontal drive is immediately switched off
when a power-on-reset is detected. The drive signal is switched-on again when the normal
switch-on procedure is followed, i.e. all sub-address bytes must be sent and after
calibration the horizontal drive signal will be released again via the slow start procedure.
When the coincidence detector indicates an out-of-lock situation the calibration procedure
is repeated.
The circuit has a second control loop to generate the drive pulses for the horizontal driver
stage. The horizontal output is gated with the flyback pulse so that the horizontal output
transistor cannot be switched-on during the flyback time.
Via the I 2 C-bus adjustments can be made of the horizontal and vertical geometry. The
vertical sawtooth generator drives the vertical output drive circuit which has a differential
output current. For the E-W drive a single ended current output is available. A special
E.G.Data creazione 01/11/99 17.27
17 / 30
F19MANU.doc
feature is the zoom function for both the horizontal and vertical deflection and the vertical
scroll function which are available in some versions. When the horizontal scan is reduced
to display 4:3 pictures on a 16:9 picture tube an accurate video blanking can be switched
on to obtain well defined edges on the screen.
Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When
an overvoltage condition is detected the horizontal output drive signal will be switched-off
via the slow stop procedure but it is also possible that the drive is not switched-off and that
just a protection indication is given in the I 2 C-bus output byte.
The choice is made via the input bit PRD. The IC’s have a second protection input on the
ϕ2 filter capacitor pin. When this input is activated the drive signal is switched-off
immediately and switched-on again via the slow start procedure. For this reason this
protection input can be used as “flash protection”.
The drive pulses for the vertical sawtooth generator are obtained from a vertical
countdown circuit. This countdown circuit has various windows depending on the incoming
signal (50 Hz or 60 Hz and standard or non standard). The countdown circuit can be
forced in various modes by means of the I 2 C-bus. During the insertion of RGB signals
the maximum vertical frequency is increased to 72 Hz so that the circuit can also
synchronise on signals with a higher vertical frequency like VGA. To obtain short switching
times of the countdown circuit during a channel change the divider can be forced in the
search window by means of the NCIN bit. The vertical deflection can be set in the deinterlace mode via the I 2 C bus. To avoid damage of the picture tube when the vertical
deflection fails the guard output current of the TDA 8350/51 can be supplied to the beam
current limiting input. When a failure is detected the RGB-outputs are blanked and a bit is
set (NDF) in the status byte of the I 2 C-bus. When no vertical deflection output stage is
connected thisguard circuit will also blank the output signals. This can be overruled by
means of the EVG bit.
Chroma and luminance processing
The circuits contain a chroma bandpass and trap circuit. The filters are realised by means
of gyrator circuits and
they are automatically calibrated by comparing the tuning frequency with the X-tal
frequency of the decoder. The luminance delay line and the delay for the peaking circuit
are also realised by means of gyrator circuits. The centre frequency of the chroma
bandpass filter is switchable via the I 2 C-bus so that the performance can be optimised for
E.G.Data creazione 01/11/99 17.27
18 / 30
F19MANU.doc
“front-end” signals and external CVBS signals. During SECAM reception the centre
frequency of the chroma trap is reduced to get a better suppression of the SECAM carrier
frequencies. All IC’s have a black stretcher circuit which corrects the black level for
incoming video signals which have a deviation between the black level and the blanking
level (back porch). The timeconstant for the black stretcher is realised internally.
The resolution of the peaking control DAC has been increased to 6 bits. All IC’s have a
defeatable coringfunction in the peaking circuit. Some of these IC’s have a YUV interface
(see table on page 2) so that picture improvement IC’s like the TDA 9170 (Contrast
improvement), TDA 9177 (Sharpness improvement) and TDA 4556/66 (CTI) can be
applied. When the CTI IC’s are applied it is possible to increase the gain of the luminance
channel by means of the GAI bit in subaddress 03 so that the resulting RGB output signals
are not affected.
Colour decoder
Depending on the IC type the colour decoder can decode PAL, PAL/NTSC or
PAL/NTSC/SECAM signals. The PAL/NTSC decoder contains an alignment-free X-tal
oscillator, a killer circuit and two colour difference demodulators. The 90° phase shift for
the reference signal is made internally.
The IC’s contain an Automatic Colour Limiting (ACL) circuit which is switchable via the I 2
C-bus and which prevents that oversaturation occurs when signals with a high chroma-toburst ratio are received. The ACL circuit is designed such that it only reduces the chroma
signal and not the burst signal. This has the advantage that the colour sensitivity is not
affected by this function. The SECAM decoder contains an auto-calibrating PLL
demodulator which has two references, viz: the 4.4 MHz sub-carrier frequency which is
obtained from the X-tal oscillator which is used to tune the PLL to the desired free-running
frequency and the bandgap reference to obtain the correct absolute value of the output
signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC
is in search or SECAM mode.
The frequency of the active X-tal is fed to the Fsc output (pin 33) and can be used to tune
an external comb filter (e.g. the SAA 4961).
The base-band delay line (TDA 4665 function) is integrated in the PAL/SECAM IC’s and in
the NTSC IC TDA 8846A. In the latter IC it improves the cross colour performance
(chroma comb filter). The demodulated colour difference signals are internally supplied to
the delay line. The colour difference matrix switches automatically between PAL/SECAM
and NTSC, however, it is also possible to fix the matrix in the PAL standard.
E.G.Data creazione 01/11/99 17.27
19 / 30
F19MANU.doc
The “blue stretch” circuit is intended to shift colour near “white” with sufficient contrast
values towards more blue to obtain a brighter impression of the picture.
Which colour standard the IC’s can decode depends on the external X-tals. The X-tal to be
connected to pin 34 must have a frequency of 3.5 MHz (NTSC-M, PAL-M or PAL-N) and
pin 35 can handle X-tals with a frequency of 4.4 and 3.5 MHz. Because the X-tal frequency
is used to tune the line oscillator the value of the X-tal frequency must be given to the IC
via the I 2 C-bus. It is also possible to use the IC in the so called “Tri-norma” mode for
South America. In that case one X-tal must be connected to pin 34 and the other 2 to pin
35. The switching between the 2 latter X-tals must be done externally. This has the
consequence that the search loop of the decoder must be controlled by the µ-computer.
To prevent calibration problems of the horizontal oscillator the external switching between
the 2 X-tals should be carried out when the oscillator is forced to pin 34. For a reliable
calibration of the horizontal oscillator it is very important that the X-tal indication bits (XA
and XB) are not corrupted. For this reason the X-tal bits can be read in the output bytes so
that the software can check the I 2 C-bus transmission.
Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the
colour killer is activated although the colour PLL is still in lock. When this killing action is
not wanted it is possible to overrule the colour killer by forcing the colour decoder to the
required standard and to activate the FCO-bit (Forced Colour On) in the control-5
subaddress.
The IC’s contain a so-called “Dynamic skin tone (flesh) control” feature. This function is
realised in the YUV domain by detecting the colours near to the skin tone. The correction
angle can be controlled via the I 2 C-bus.
RGB output circuit and black-current stabilisation
The colour-difference signals are matrixed with the luminance signal to obtain the RGBsignals. The TDA 884X devices have one (linear) RGB input. This RGB signal can be
controlled on contrast and brightness (like TDA 8374/75). By means of the IE1 bit the
insertion blanking can be switched on or off. Via the IN1 bit it can be read whether the
insertion pin has a high level or not.
The TDA 885X IC’s have an additional RGB input. This RGB signal can be controlled on
contrast, saturation and brightness. The insertion blanking of this input can be switched-off
by means of the IE2 bit. Via the IN2 bit it can be read whether the insertion pin has a high
level or not.
E.G.Data creazione 01/11/99 17.27
20 / 30
F19MANU.doc
The output signal has an amplitude of about 2 volts black-to-white at nominal input signals
and nominal settings of the controls. To increase the flexibility of the IC it is possible to
insert OSD and/or teletext signals directly at the RGB outputs. This insertion mode is
controlled via the insertion input (pin 26 in the S-DIP 56- and pin 38 in the QFP-64
envelope). This blanking action at the RGB outputs has some delay which must be
compensated externally.
To obtain an accurate biasing of the picture tube a “Continuous Cathode Calibration”
circuit has been developed. This function is realised by means of a 2-point black level
stabilisation circuit. By inserting 2 test levels for each gun and comparing the resulting
cathode currents with 2 different reference currents the influence of the picture tube
parameters like the spread in cut-off voltage can be eliminated.
This 2-point stabilisation is based on the principle that the ratio between the cathode
currents is coupled to the ratio between the drive voltages according to:
[ I ki / Ik2 ] = [ Vdr1 / Vdr2 ]
The feedback loop makes the ratio between the cathode currents Ik1 and Ik2 equal to the
ratio between the reference currents (which are internally fixed) by changing the (black)
level and the amplitude of the RGB output signals via 2 converging loops. The system
operates in such a way that the black level of the drive signal is controlled to the cut-off
point of the gun so that a very good grey scale tracking is obtained. The accuracy of the
adjustment of the black level is just dependent on the ratio of internal currents and these
can be made very accurately in integrated circuits. An additional advantage of the 2-point
measurement is that the control system makes the absolute value of Ik1 and Ik2 identical
to the internal reference currents. Because this adjustment is obtained by means of an
adaption of the gain of the RGB control stage this control stabilises the gain of the
complete channel (RGB output stage and cathode characteristic).
As a result variations in the gain figures during life will be compensated by this 2-point
loop.
An important property of the 2-point stabilisation is that the off-set as well as the gain of
the RGB path is adjusted by the feedback loop. Hence the maximum drive voltage for the
cathode is fixed by the relation between the test pulses, the reference current and the
relative gain setting of the 3 channels. This has the consequence that the drive level of the
CRT cannot be adjusted by adapting the gain of the RGB output stage. Because different
picture tubes may require different drive levels the typical “cathode drive level” amplitude
can be adjusted by means of an I 2 C-bus setting. Dependent on the chosen cathode drive
E.G.Data creazione 01/11/99 17.27
21 / 30
F19MANU.doc
level the typical gain of the RGB output stages can be fixed taking into account the drive
capability of the RGB outputs (pins 19 to 21). More details about the design will be given in
the application report.
The measurement of the “high” and the “low” current of the 2- point stabilisation circuit is
carried out in 2 consecutive fields. The leakage current is measured in each field. The
maximum allowable leakage current is 100 µA When the TV receiver is switched-on the
RGB output signals are blanked and the black current loop will try to set the right picture
tube bias levels. Via the AST bit a choice can be made between automatic start-up or a
start-up via the µ-processor. In the automatic mode the RGB drive signals are switched-on
as soon as the black current loop
has been stabilised. In the other mode the BCF bit is set to 0 when the loop is stabilised.
The RGB drive can than be switched-on by setting the AST bit to 0. In the latter mod some
delay can be introduced between the setting of the BCF bit and the switching of the AST
bit so that switch-on effects can be suppressed. It is also possible to start-up the devices
with a fixed internal delay (as with the TDA 837X and the TDA884X/5X N1). This mode is
activated with the BCO bit.
The vertical blanking is adapted to the incoming CVBS signal (50 Hz or 60 Hz). When the
flyback time of the vertical output stage is longer than the 60 Hz blanking time the blanking
can be increased to the same value as that of the 50 Hz blanking. This can be set by
means of the LBM bit.
For an easy (manual) adjustment of the Vg2 control voltage the VSD bit is available. When
this bit is activated the black current loop is switched-off, a fixed black level is inserted at
the RGB outputs and the vertical scan is switched-off so that a horizontal line is displayed
on the screen. This line can be used as indicator for the Vg2 adjustment. Because of the
different requirements for the optimum cut-off voltage of the picture tube the RGB output
level is adjustable when the VSD bit is activated. The control range is 2.5 ± 0.7 V and can
be controlled via the brightness control DAC. It is possible to insert a so called “blue back”
back-ground level when no video is available. This feature can be activated via the BB bit
in the control2 subaddress.
E.G.Data creazione 01/11/99 17.27
22 / 30
F19MANU.doc
FOR VOLTAGE SINTHESIS ONLY
F 19
EF
EF
TR201
TR200
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
IIC
TR202
TO PIN 33
IC100
CVBS
EF
FOR TXT
TR203
TO PIN 24
IC 100
(CVBS FOR TXT)
TO PIN 9
IC 100
AV1
STATUS
SCART 1
EF
VIDEO IN
CINCH
EF
19
8
TR204
15
11
7
16
20
SIF
AUDEXT
NC
NC
PLLIF
IFVIDEO OUT
SCL
SDA
DECOUPLING
TDA884X
I.F.
VIDEO
AGC
AFC
DEM.
IDENT
MSD
PAL
(SECAM)
NTSC
CHR.IN
EX.CVBS/Y IN
VP1
INT CVBS IN
GND
AUDIO OUT
DECOUPLING
C.D. &
RGB
MATRIX
VIDEO
CONTROL
SOUND
PROCES.
(MONO)
EX. CVBS IN
BLKIN
B OUT
G OUT
R OUT
BCL/VG
R IN
SYNC
PROCES.
V. & H.
TIME
BASE
EXT RGB
SWITCH
& RGB
DRIVE
G IN
B IN
RGB INSERT.
Y IN
Y OUT
IIC
TRANSRECEIVER
DECOUPLING
DEENPHASIS
AGC OUT
DECOPLING
I REF
VERT. RAMP
EHT PROTEC.
IF IN 2
IF IN 1
V. DRIVE A
V. DRIVE B
E - W OUT
GND 2
PH. 1 FILTER
PH. 2 FILTER
H. IN, S.C. OUT
HOR. OUT
DECOUPLING
CVBS 1 OUT
VP2
DET FILTER
X TAL 2
X TAL 1
S.C. REF OUT
R - Y IN
B - Y IN
R - Y OUT
B - Y OUT
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TR500
IIC
FROM PIN 6
IC100
AV1 / AV2
SWITCH
1
3.58MHz
TV
CVBS
FROM PIN 7
IC100
AV1 / TV
SWITCH
TO AV2
9
3
2
7
8
SCART 2
1/3 0F IC201
LA7955
CVBS IN
TO PIN 10
IC 100
AV2 STATUS
EF
TR206
8V
RGB AMPLIFIER
MODULE
TR212
CVBS OUT
FROM IC 100
PIN 14, 20, 21
BAND SWITCHING
TR105
FROM
PIN 51
IC 100
4.43MHz
3,57MHz
A10
1
2
3
4
5
5V
5
TR503
VHF H
VHF LTR502
TR208
6
CVBS IN
UHF
10
11
12 V
4
2
3
4
5
6
5V
7
8
9
EF
EF
TR501
1
12 V
TR211
FROM PIN 1
IC 100
∫
UV
6
7
8
9
10
11
12
TR205
CTI
&
4:3
TO
16 : 9
FROM PIN 52
IC 100 4:3 TO 16:9
SWITCH
8
20
19
TO CRT
FROM EHT
8V
VIDEO SIGNAL PATH
F19VIDEP.DRW
E.G.
14 / 11 / 99
F19 RGB AMPLIFIER
IC204 TDA884X
26
23/24/25
RGB
IN
19/20/21
RGB
OUT
12 V
18
FAST
BLK.
IN
RGB IN FROM SCART
3
2
200 V
TO G1 TRC
1
R17,R18,R19
R215
R216
R217
2
R600
5
6/11/14
D800, D801, D802
9/12/15
E.F.
R613
R614
R615
1/3/4
4/5/6
R604
R605
R606
F19 RGBCO.DRW
E.G.
14 / 11 /99
3 X
7/10/13
STV 5112
TO
RGB
KATODE
F 19 FEATURE MODULE
Colour Transient Improvment
&
4 : 3 to 16 : 9 Signal Processing
SAA4981
Monolithic integrated 16 : 9
Compressor
FEATURES
• Fixed horizontal compression by a factor of 4 ¤3 for most video standards
• Three fixed screen positions (left, centre and right)
• 5 MHz bandwidth
• Bypass function
• Inputs for luminance and chrominance of side panels
• Standard video inputs and outputs (Y, (Β-Y) and (Ρ-Y))
• Horizontal and vertical sync signals are not processed
• Pre filters and post filters on chip.
GENERAL DESCRIPTION
The integrated 16 : 9 compressor is an IC which compresses the active part of a video line
by a factor of 4 ¤3 from, for example, 52 ms to 39ms. This is necessary to display 4:3
video software on a 16 : 9 tube in the correctproportion. The capacitively coupled video
inputs are Y, (Β-Y) and (Ρ-Y).
The synchronisation input HREF is a line frequencyreference signal. The bandwidth of the
IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched
Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y,
(Β Y) and (Ρ-Y) and provides the following two possibilities:
1. Bypass function (the input signal is not compressed)
2. Compressed video by a factor of 4 ¤3 with three different fixed screen positions (left,
centre and right). The luminance and chrominance of the side panels are determined by
the external signals YSIDE, BYSIDE and RYSIDE.
The horizontal compression is a time discrete and amplitude continuous signal processing.
This provides pre and post filters which are realized on-chip.
FUNCTIONAL DESCRIPTION
SAA4981 16:9 TO 4:3 PROCESSOR
Pagina 1 di 3
e.g.SAA4981R.doc
19
VEED
8
7
SC LINE MEMORY
CLAMP
SUB
4
MUX
SC LINE
MEMORIES
5 MHz
LOW-PASS FILTER
SC LINE MEMORY
6.7 MHz
LOW-PASS FILTER
18
MUX Y
YOUT
SAA4981
C1
SC LINE MEMORY
22
CLAMP
(B-Y)IN
MUX
SC LINE
MEMORIES
5 MHz
LOW-PASS FILTER
SC LINE MEMORY
6.7 MHz
LOW-PASS FILTER
3
SC LINE MEMORY
21
CLAMP
MUX
SC LINE
MEMORIES
5 MHz
LOW-PASS FILTER
SC LINE MEMORY
6
C2
MUX RY
C1
C2
17
(B-Y)OUT
C3
6.7 MHz
LOW-PASS FILTER
3
HORIZONTAL
SEPARATION
16
(R-Y)OUT
C3
C1
C2
CONTROLLER
3
C3
54 MHz
PLL
TEST
9
10
11
1
2
3
24
5
CTRL3
14
13
MHA277
BYSIDE
RYSIDE
YSIDE
CTRL2
CTRL1
15
CLMBY
Fig.1 Block diagram.
CLMRY
CLAOUT
BGREF
SAA4981
CLMY
Preliminary specification
12
CLAMP REFERENCE
handbook, full pagewidth
HREF
C3
MUX BY
C1
(R-Y)IN
C2
Philips Semiconductors
20
VCCD
Monolithic integrated 16 : 9 compressor
VEEA
BLOCK DIAGRAM
1995 Oct 05
23
YIN
VCCA
Applicable video standards
The integrated 16 : 9 compressor can be used for the following video standards; B, C, D,
G, H, I, K, K1, L, M and N. standards D, I, K, K1 and L will show a reducedvideo bandwidth
above 5 MHz.
Clamping circuit
The clamping circuits clamp the video input signals Y, (Β-Y) and (Ρ-Y) to the DC level of
the clamp reference signal fed from the clamp reference circuit. This is necessary to
ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass
filters and the SC line memories.
Internal pre filters
Before the signals are sampled in the time discrete and amplitude continuous area, lowpass filtering is necessary to avoid any aliasing. Even if the inputs have already been lowpass filtered further filtering is advantageous for the electromagnetic compatibility (EMC).
The same transfer function is used for all three low-pass filters because of the same
bandwidth for the luminance and chrominance signals (up to 5 MHz)
SC line memories
After the low-pass filters the input signals are fed to the SC line memories. The signals are
sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a
clock frequency of 18 MHz in the compression mode. The result of the different clock
frequencies is a horizontal compression by a factor of 4 ¤3 . The clocks and the horizontal
starting pulses for the SC line memories are fed from the controller.
Two line memories are required for each signal path because in the compression mode, in
one video line the signals are sampled to the SC line memories with 13.5 MHz and one
video line later the signals are read with 18 MHz. In the bypass mode, via the SC line
memories, in one video line the signals are sampled with 13.5 MHz and one video line
later the signals are read with 13.5 MHz.
The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a
multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to
the internal post filters.
Output multiplexer MUX Y, MUX (Β-Y) and MUX (Ρ-Y)
SAA4981 16:9 TO 4:3 PROCESSOR
Pagina 2 di 3
e.g.SAA4981R.doc
The output multiplexers are controlled via C1 and C2 fed from the controller. The
multiplexers are used to connect one of the four input signals to the output and, also,
enable fast switching.
The input signals of the multiplexers for one component
• The output signal of the post filter
• The uncompressed signal after the input clamping
• The clamping reference signal
• The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE.
The horizontal separation circuit
The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which
is generated in the positive edge of the burst key of a sandcastle signal.
54 MHz horizontal PLL
The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for
the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHzclock and the
18 MHz clock are line locked.
Clamp reference
Reference voltages are generated In the clamp reference block. These DC signals are
used in the clamping circuits as input signals for the output multiplexers and as reference
voltages for the SC line memories. Four external capacitors at the pins CLMY , CLMBY ,
CLMRY and BGREF respectively are necessary to provide smoothing for the reference
voltages. A black level reference signal is available at CLAOUT.
Controller
The controller generates the clocks and the horizontal start signals for the SC line
memories and, also, the control signals for the output multiplexers. The timing for the start
reading signal for three different screen positions (left, centre and right) and the control
signals for the multiplexers (C1 and C2) is fixed. For the uncompressed signals a bypass
via the SC line memories and a bypass not via the SC line memories is available. When
the signals do not pass the line memories, the frequencyresponse is not affected by the sifunction.
SAA4981 16:9 TO 4:3 PROCESSOR
Pagina 3 di 3
e.g.SAA4981R.doc
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
handbook, full pagewidth
SAA4981
HREF
64 µs
1.5 µs
1.5 µs
(2)
(2)
(1)
sampled video
49 µs (used for compression)
6.3 µs
52 µs
36.75 µs
side
compressed video
side
panel
(centre position)
panel
side
compressed video
panel
(right position)
compressed video
side
(left position)
panel
bypassed video
(bypass via the Line Memories)
(2)
(2)
bypassed video
(1)
(full bypass not through the Line Memories)
MHA278
(1) Nominal timing for a 52 µs active video signal to generate a centred compressed video signal.
(2) Worst case picture position for a 52 µs active video signal to generate no visible blanking between side panels and compressed video.
Fig.3 Horizontal timing.
1995 Oct 05
7
TDA4566
Colour transient improvement circuit
GENERAL DESCRIPTION
The TDA4566 is a monolithic integrated circuit for colour-transient improvement (CTI) and
luminance delay line in gyrator technique in colour television receivers.
Features
• Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient
detecting-, storage- and switching stages resulting in high transients of colour difference
output signals
• A luminance signal path (Y) which substitutes the conventional Y-delay coil with an
integrated Y-delay line
• Switchable delay time from 550 ns to 820 ns in steps of 90 ns and additional fine
adjustment of 37 ns
• Two Y output signals; one of 180 ns less delay
TDA4566 CTI
e.g.TDA4566R.doc
Pagina 1 di 1
Philips Semiconductors
Colour transient improvement circuit
March 1991
3
Preliminary specification
TDA4566
Fig.1 Block diagram.
F19 CTI & 16:9 TO 4 : 3 COMPRESSOR
6
10
12 V
5V
9
IC2 TDA4566
15
13
THESHOLD SWT.
14
IC 1
10
SAA4981
20
8
1
Y
R-Y
17
CLAMP
12
GYRATOR
DELAY CELLS
7 x 90 ns
1
11
INTEGRATOR
& PULSE
FORMER
dV/dt
SWT. &
STORE
8
SWT. &
STORE
7
8
CLAMP
MUX
LPF
Y OUT
MUX
17
R-Y
OUT
4
MUX
16
B-Y
OUT
3
MUX
LPF
LINE MEMORY
Y
R-Y
B-Y
22
21
LINE MEMORY
CLAMP
MUX
LPF
LPF
LINE MEMORY
LINE MEMORY
CLAMP
MUX
LPF
LPF
LINE MEMORY
B-Y
13
2
3
4
5
6
9
18
6
HOR.
SEPAR.
7
JS 7
JS 6
JS 5
H REF
54 MHz
PLL
20
CLAMP
REFERENCE
CONTROLLER
4
12
11 10
9
19
1
2
3
24
14
5
15
5V
TR1
5
R4
16
14
DUAL MONOSTABLE
MULTIVIBRATOR
M.M.
EF
10
M.M.
13
C9
IC 4 HEF 4538
note:
If CTI ( IC 2 TDA4566 IS NOT
PRESENT THAN JS 5, JS 6 & JS7
MUST BE INSERTED
D1
2
15
S.C INPUT
16:9 TO 4:3 SWITCH SIGNAL
T2
C10
8V
11
7
18
LINE MEMORY
t = 180 ns
dV/dt
2
23
8
16
1
3
5
R2
8V
12 V
F19FEAT.DRW
E.G. 12/12/99
12
SCANNING
SECTION
SECTION
TDA8351
DC-coupled vertical deflection
Circuit
FEATURES
Few external components
Highly efficient fully DC-coupled vertical output bridge circuit
Vertical flyback switch
Guard circuit
Protection against:
•
short-circuit of the output pins (7 and 4)
•
short-circuit of the output pins to VP
•
Temperature (thermal) protection
•
High EMC immunity because of common mode inputs
•
A guard signal in zoom mode.
•
GENERAL DESCRIPTION
The TDA8351 is a power circuit for use in 9
and 11
colour deflection systems for
field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection
output circuit, operating as a highly efficient class G system.
FUNCTIONAL DESCRIPTION
The vertical driver circuit is a bridge configuration. The deflection coil is connected
between the output amplifiers, which are driven in phase opposition. An external resistor
(RM ) connected in series with the deflection coil provides internal feedback information.
The differential input circuit is voltage driven. The input circuit has been adapted to enable
it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and
TDA8376 which deliver symmetrical current signals. An external resistor (RCON )
connected between the differential input determines the output current through the
deflection coil.
TDA8351 VERTICAL OUTPUT
Pagina 1 di 2
e.g. TDA8351R
The relationship between the differential input current and the output current is defined by:
Idiff RCON =Icoil RM .
The output current is adjustable from 0.5 A (p-p) to 3 A(p-p) by varying RM . The maximum
input differential voltage is 1.8 V. In the application it is recommended that Vdiff = 1.5 V
(typ). This is recommended because of the spread of input current and the spread in the
value of RCON .
The flyback voltage is determined by an additional supply voltage VFB . The principle of
operating with two supply voltages (class G) makes it possible to fix the supply voltage VP
optimum for the scan voltage and the second supply voltage VFB optimum for the flyback
voltage. Using this method, very high efficiency is achieved.
The supply voltage VFB is almost totally available as flyback voltage across the coil, this
being possible due to the absence of a decoupling capacitor (not necessary, due to the
bridge configuration). The output circuit is fully protected against the following:
thermal protection
•
short-circuit protection of the output pins (pins 4 and 7)
•
short-circuit of the output pins to VP .
A guard circuit VO(guard) is provided. The guard circuit is activated at the following
conditions:
•
during flyback
•
during short-circuit of the coil and during short-circuit of the output pins (pins 4 and 7)
to VP or ground
•
during open loop
•
when the thermal protection is activated. This signal can be used for blanking the
picture tubescreen.
TDA8351 VERTICAL OUTPUT
Pagina 2 di 2
e.g. TDA8351R
Philips Semiconductors
Preliminary specification
DC-coupled vertical deflection circuit
TDA8351
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA8351
DESCRIPTION
SIL9P
VERSION
plastic single-in-line power package; 9 leads
SOT131-2
BLOCK DIAGRAM
VP VO(guard)
handbook, full pagewidth
3
VFB
6
8
VP
CURRENT
SOURCE
VP
TDA8351
7
VO(A)
I drive(pos)
IS
1
IT
9
IT
I drive(neg)
2
V I(fb)
VP
V
IS
4
VO(B)
5
GND
MBC988- 1
Fig.1 Block diagram.
January 1995
VO(A)
3
VO(B)
Philips Semiconductors
Preliminary specification
DC-coupled vertical deflection circuit
TDA8351
PINNING
FUNCTIONAL DESCRIPTION
SYMBOL
PIN
The vertical driver circuit is a bridge configuration. The
deflection coil is connected between the output amplifiers,
which are driven in phase opposition. An external resistor
(RM) connected in series with the deflection coil provides
internal feedback information. The differential input circuit
is voltage driven. The input circuit has been adapted to
enable it to be used with the TDA9150, TDA9151B,
TDA9160A, TDA9162, TDA8366 and TDA8376 which
deliver symmetrical current signals. An external resistor
(RCON) connected between the differential input
determines the output current through the deflection coil.
The relationship between the differential input current and
the output current is defined by: Idiff × RCON = Icoil × RM.
The output current is adjustable from 0.5 A (p-p) to 3 A
(p-p) by varying RM. The maximum input differential
voltage is 1.8 V. In the application it is recommended that
Vdiff = 1.5 V (typ). This is recommended because of the
spread of input current and the spread in the value of
RCON.
DESCRIPTION
Idrive(pos)
1
input power-stage (positive);
includes II(sb) signal bias
Idrive(neg)
2
input power-stage (negative);
includes II(sb) signal bias
VP
3
operating supply voltage
VO(B)
4
output voltage B
GND
5
ground
VFB
6
input flyback supply voltage
VO(A)
7
output voltage A
VO(guard)
8
guard output voltage
VI(fb)
9
input feedback voltage
The flyback voltage is determined by an additional supply
voltage VFB. The principle of operating with two supply
voltages (class G) makes it possible to fix the supply
voltage VP optimum for the scan voltage and the second
supply voltage VFB optimum for the flyback voltage. Using
this method, very high efficiency is achieved.
handbook, 2 columns
I drive(pos)
1
I drive(neg)
2
VP
3
VO(B)
4
GND
5
V FB
6
VO(A)
7
• thermal protection
VO(guard)
8
• short-circuit protection of the output pins (pins 4 and 7)
V I(fb)
9
• short-circuit of the output pins to VP.
The supply voltage VFB is almost totally available as
flyback voltage across the coil, this being possible due to
the absence of a decoupling capacitor (not necessary, due
to the bridge configuration). The output circuit is fully
protected against the following:
TDA8351
A guard circuit VO(guard) is provided. The guard circuit is
activated at the following conditions:
MBC989
• during flyback
• during short-circuit of the coil and during short-circuit of
the output pins (pins 4 and 7) to VP or ground
Metal block connected to substrate pin 5.
• during open loop
Metal on back.
• when the thermal protection is activated.
This signal can be used for blanking the picture tube
screen.
Fig.2 Pin configuration.
January 1995
4
11
HEATER
VOLTAGE
IC 204
TDA8844
47
46
45
1
40
4
200 V
VIDEO
SUPPLAY
LINE
1
9
VG2
D 53
2
2
TDA8351
12
FOCUS
20 mS
IC 5
EHT
146 V
28 V
T3
T2
64 /uS
3
4
EF
5
TR207
TR18
BU508D
3
L22
LINEARITY
50 V
6
TR12
8
L20
C71
9
8
EHT P.
5
SERVICE
FLYBACK
PULSE TO:
PIP
TUNING
OSD SYNC
YOKE
L26
C52
5
16 V C51
BUK474
L25
D25
VERTICAL
YOKE
7
PIN6
TDA8351
D24
B.C.L.
PIN22
TDA8844
PIN 50
TR15
7
10 C154
3
6
PIN 3
TDA8351
R35
F19 VERTICAL & LINE OUTPUT
PLUS E-W CORRECTION
F19 V&HDF.DRW
E.G.
27/12/99
SCART 1
1
CVBS & INTERCARRIER OUT
EF
TR202 TR201
SCART
OUT
6
TR210
EF
6
3
2
TR110
TR525
FROM PIN8
IC 100
SCART/CINCH
SWITCH
55
10
2
EXT. IN
15
2
1
8V
R239
IC 204
12
F575
14
13
TDA844X
SOUND
IF IN
AUDIO
CINCH IN
1
11
R208
IC 400 TDA2613
F576
9
7
6
5
4
3
2
1
IC200 (2/3) HEF 4053
15
R242
FROM PIN 12
IC100
SAA5297A
8
28 V
AUDIO OUT
TR209
TR575
F19 AUDIO MONO SIGNAL PATH
F19AMSPH.DRW
E.G.
29/12799
TDA 9870A & TDA9875A MAIN CHARACTERISTICS
FEATURES
Demodulator and decoder section
•
Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF
sources SIF AGC with 24 dB control range
SIF 8-bit Analog-to-Digital Converter
(ADC)
•
DQPSK demodulation for different standards, simultaneously with 1-channel FM
demodulation
NICAM
decoding
(B/G,
I
and
L
standard)
Two-carrier
multistandard FM demodulation (B/G, D/K and M standard
•
Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite
sound Optional AM demodulation for system L, simultaneously with NICAM
•
Programmable identification (B/G, D/K and M standard) and different identification
times.
•
DSP section
•
Digital crossbar switch for all digital signal sources and destinations
•
Control of volume, balance, contour, bass, treble,
•
pseudo stereo, spatial, bass boost and soft-mute
•
Plop-free volume control
•
Automatic Volume Level (AVL) control
•
Adaptive de-emphasis for satellite
•
Programmable beeper
•
Monitor selection for FM/AM DC values and signals, with peak detection option
I 2 S-bus
interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and
mute.
•
Analog audio section
•
Analog crossbar switch with inputs for mono and stereo
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F19MANU.doc
•
(also applicable as SCART 3 input), SCART 1
•
input/output, SCART 2 input/output and line output
•
User defined full-level/ 3 dB scaling for SCART outputs
•
Output selection of mono, stereo, dual A/B, dual A or Dual B
•
20 kHz bandwidth for SCART-to-SCART copies
•
Standby mode with functionality for SCART copies
•
Dual audio digital-to-analog converter from DSP to analog crossbar switch, bandwidth
15 kHz
Dual audio ADC from analog inputs to DSP
Two dual audio Digital-to-
Analog Converters (DACs) for loudspeaker (Main) and headphone (Auxiliary) outputs;
also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension.
GENERAL DESCRIPTION
The TDA9875A is a single-chip Digital TV Sound Processor (DTVSP) for analog and
digital multi-channel sound systems in TV sets and satellite receivers.
Supported standards
The multistandard/multi-stereo capability of the TDA9875A is mainly of interest in Europe,
but also in Hong Kong/Peoples Republic of China and South East Asia. This includes
B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those
standard combinations otherwise only single standards are transmitted.
M standard is transmitted in Europe by the American Forces Network (AFN) with European
channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. The AM sound of L/L’ standard
is normally demodulated in the 1st sound IF. The resulting AF signal has to be entered into the
mono audio input of the TDA9875A. A second possibility is to use the internal AM demodulator
stage, however this gives limited performance. Korea has a stereo sound system similar to Europe
and is supported by the TDA9875A. Differences include deviation, modulation contents and
identification. It is based on M standard.
FUNCTIONAL DESCRIPTION
Description of the demodulator and decoder section
SIF INPUT
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F19MANU.doc
Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner.
For higher SIF signal levels the SIF input can be attenuated with an internal switchable
10 dB resistor divider. As no specific filters are integrated, both inputs have the same
specification giving flexibility in application. The selected signal is passed through an AGC
circuit and then digitized by an 8-bit ADC operating at 24.576 MHz.
AGC
The gain of the AGC amplifier is controlled from the ADC output by means of a digital
control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC
overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation
the AGC must be switched off. When switched off, the control loop is reset and fixed gain
settings can be chosen from Table 15 (subaddress 0).
MIXER
The digitized input signal is fed to the mixers, which mix one or both input sound carriers
down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access
to the mixer control word registers is via the I 2 C-bus. When receiving NICAM programs,
a feedback signal is added to the control word of the second carrier mixer to establish a
carrier-frequency loop.
FM AND AM DEMODULATION
An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used
for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis
characteristic, an adaptive de-emphasis is available for encoded satellite programs. A
stereo decoder recovers the left and right signal channels from the demodulated sound
carriers. Both the European and Korean stereo systems are supported.
FM IDENTIFICATION
The identification of the FM sound mode is performed by AM synchronous demodulation of
the pilot signal and narrow-band detection of the identification frequencies. The result is
available via the I 2 C-bus interface. A selection can be made via the I 2 C-bus for B/G,
D/K and M standard and for three different modes that represent different trade-offs
between speed and reliability of identification.
NICAM DEMODULATION
The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit/s. The NICAM
demodulator performs DQPSK demodulation and feeds the resulting bitstream and clock
signal onto the NICAM decoder and, for evaluation purposes, to PCLK (pin 1) and NICAM
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F19MANU.doc
(pin 2). A timing loop controls the frequency of the crystal oscillator to lock the sampling
rate to the symbol timing of the NICAM data.
NICAM DECODER
The device performs all decoding functions in accordance with the “EBU NICAM 728
specification”. After locking to the frame alignment word, the data is descrambled by
applying the defined pseudo-random binary sequence; the device will then synchronize to
the periodic frame flag bit C0.
The status of the NICAM decoder can be read out from the NICAM status register by the
user. The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit
indicates that the decoder has locked to the NICAM data and that the data is valid sound
data. The C4 bit indicates that the sound conveyed by the FM mono channel is identical to
the sound conveyed by the NICAM channel. The error byte contains the number of sound
sample errors, resulting from parity checking, that occurred in the past 128 ms period.
NICAM AUTO-MUTE
This function is enabled by setting bit AMUTE LOW subaddress 14 Upper and lower error
limits may be defined by writing appropriate values to two registers in the I 2 C-bus section
(subaddresses 16 and 17; . When the number of errors in a 128 ms period exceeds the
upper error limit the auto-mute function will switch the output sound from NICAM to
whatever sound is on the first sound carrier (FM or AM). When the error count is smaller
than the lower error limit the NICAM sound is restored. The auto-mute function can be
disabled by setting bit AMUTE HIGH. In this condition clicks become audible when the
error count increases; the user will hear a signal of degrading quality.
A decision to enable/disable the auto-muting is taken by the microcontroller based on an
interpretation of the application control bits C1, C2, C3 and C4 and, possibly, any
additional strategy implemented by the set maker in the microcontroller software.
For NICAM L applications, it is recommended to demodulate AM sound in the first sound
IF and connect the audio signal to the mono input of the TDA9875A. By setting the AMSEL
bit subaddress 14. the auto-mute function will switch to the audio ADC instead of switching
to the first sound carrier.
CRYSTAL OSCILLATOR
The digital-controlled crystal oscillator (DCXO) is illustrated in Fig.8 (see Chapter 12). The
circuitry of the DCXO is fully integrated, only the external 24.576 MHz crystal is needed.
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F19MANU.doc
TEST PINS
Both test pins are active HIGH, in normal operation of the device they are wired to VSSD1
Test functions are for manufacturing tests only and are not available to customers. Without
external circuitry these pads are pulled down to LOW level with internal resistors.
POWER FAIL DETECTOR
The power fail detector monitors the internal power supply for the digital part of the device.
If the supply has temporary been lower than the specified lower limit, the power-on reset
bit POR, transmitter register subaddress 0 will be set to HIGH. The CLRPOR bit, slave
register subaddress 1 resets the power-on reset flip-flop to LOW. If this is detected, an
initialization of the TDA9875A has to be carried out to ensure reliable operation.
LEVEL SCALING
All input channels to the digital crossbar switch (except for the loudspeaker feedback path)
are equipped with a level adjust facility to change the signal level in a range of
15 dB. It
is recommended to scale all input channels to be 15 dB below full scale ( 15 dB full scale)
under nominal conditions.
NICAM PATH
The NICAM path has a switchable J17 de-emphasis.
FM (AM) PATH
A high-pass filter suppresses DC offsets from the FM demodulator due to carrier frequency
offsets and supplies the monitor/peak function with DC values and an unfiltered signal, e.g.
for the purpose of carrier detection. The de-emphasis function offers fixed settings for the
supported standards (50 µs, 60 µs 75 µs and J17). An adaptive de-emphasis is available
for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of the A2
stereo, dual and mono signals.
NICAM AUTO-MUTE
If NICAM B/G, I, D/K is received, the auto-mute is enabled and the signal quality becomes
poor, the digital crossbar switch switches automatically to FM and switches the matrix to
channel 1. The automatic switching depends on the NICAM bit error rate.
The auto-mute function can be disabled via the I 2 C-bus. For NICAM L applications, it is
recommended to demodulate AM sound in the first sound IF and connect the audio signal
to the mono input of the TDA9875A. By setting the AMSEL bit subaddress 14 (see Section
10.3.11), the auto-mute function will switch to the audio ADC instead of switching to the
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F19MANU.doc
first sound carrier. The ADC source selector subaddress 23 (see Section 10.3.20) should
be set to mono input, where the AM sound signal should be connected.
LOUDSPEAKER (MAIN) CHANNEL
The matrix provides the following functions; forced mono, stereo, channel swap, channel
1, channel 2 and spatial effects.
There are fixed coefficient sets for spatial settings of 30%, 40% and 52%.
The Automatic Volume Level (AVL) function provides a constant output level of 23 dB full
scale for input levels between 0 and 29 dB full scale. There are some fixed decay time
constants to choose from, i.e. 2, 4 and 8 seconds.
Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter.
There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150,
200 and 300 Hz.
Volume is controlled individually for each channel ranging from +24 to -83 dB with 1 dB
resolution. There is also a mute position. For the purpose of a simple control software in
the microcontroller, the decimal number that is sent as an I 2 C-bus data byte for volume
control is identical to the volume setting in dBs (e.g. the I 2 C-bus data byte +10 sets the
new volume value to +10 dB).
Balance can be realized by independent control of the left and right channel volume
settings.
Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to
the volume setting by means of microcontroller software.
Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable
between +/-12 dB with 1 dB resolution.
For the purpose of a simple control software in the microcontroller, the decimal number
that is sent as an I 2 C-bus data byte for contour, bass or treble is identical to the new
contour, bass or treble setting in dBs (e.g. the I 2 C-bus data byte +8 sets the new value to
+8 dB). Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented
coefficient set serves merely as an example on how to use this filter.
The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The
frequency can be selected via the I 2 C-bus. The beeper output signal is added to
theloudspeaker and headphone channel signals. The beeper volume is adjustable with
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F19MANU.doc
respect to full scale between 0 and
93 dB with 3 dB resolution. The beeper is not
effected by mute.
Soft-mute provides a mute ability in addition to volume control with a well defined time (32
ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine
masking.
HEADPHONE (AUXILIARY) CHANNEL
The matrix provides the following functions; forced mono, stereo, channel swap, channel
and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled
individually for each channel in a range from +24 to
83 dB with 1 dB resolution. There is
also a mute position. For the purpose of a simple control software in the microcontroller,
the decimal number that is sent as an I 2 C-bus data byte for volume control is identical to
the volume setting in dB (e.g. the I 2 C-bus data byte +10 sets the new volume value to
+10 dB). Balance can be realized by independent control of the left and right channel
volume settings.
Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable
between +/- 12 dB with 1 dB resolution.
For the purpose of a simple control software in the microcontroller, the decimal number
that is sent as an I 2 C-bus data byte for bass or treble is identical to the new bass or
treble setting in dB (e.g. the I 2 C-bus data byte +8 sets the new value to +8 dB).
The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The
frequency can be selected via the I 2 C-bus. The beeper output signal is added to the
loudspeaker and headphone channel signals. The beeper volume is adjustable with
respect to full scale between 0 and
93 dB with 3 dB resolution. The beeper is not
effected by mute.
Soft-mute provides a mute ability in addition to volume control with a well defined time (32
ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine
masking.
SCART INPUTS
The SCART specification allows for a signal level of up to 2 V (rms). Because of signal
handling limitations, due to the 5 V supply voltage of the TDA9875A, it is necessary to
have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a +3
dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with maximum 1.4V input),
there are +3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line
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F19MANU.doc
output. The input attenuator is realized by an external series resistor in combination with
the input impedance, both of which form a voltage divider. With this voltage divider the
maximum SCART signal level of 2 V (rms) is scaled down to 1.4 V (rms) at the input pin.
EXTERNAL AND MONO INPUTS
The 3 dB input attenuators are not required for the external and mono inputs, because
those signal levels are under control of the TV designer. The maximum allowed input level
is 1.4 V (rms). By adding external series resistors, the external inputs can be used as an
additional SCART input.
SCART OUTPUTS
The SCART outputs employ amplifiers with two gain settings. The gain can be set to +3
dB or to 0 dB via the I 2 C-bus. The +3 dB position is needed to compensate for the 3 dB
attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be
preferred [under the condition of 1.4 V (rms) maximum input level]. The 0 dB position is
needed, for example, for an external-to-SCART copy with 0 dB gain.
LINE OUTPUT
The line output can provide an unprocessed copy of the audio signal in the loudspeaker
channels. This can be either an external signal that comes from the dual audio ADC, or a
signal from an internal digital audio source that comes from the dual audio DAC. The line
output employs amplifiers with two gain settings. The +3 dB position is needed to
compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for
example, for non-attenuated external or internal digital signals (see Section 6.3.4).
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F19MANU.doc
IIC BUS
TO PIN 9 IC1
TDA9811
STD SWITCH
INTERCARRIER
FROM PIN 20 IC1
TDA9811
EF
6V
TO L/L' FILTER
SWITCH
TR8
L /L' SWITCH
II S
AM AUDIO
FROM PIN 22 IC1 TR6
TDA9811
EF
IIC
INPUT SWITCH
AGC
ADC
IN / OUT
IDENT
I/O
PORT
PEAK
DETEC.
FM DEM
(AM DEM)
QPSK
DEM.
DEMATR
DEEMPH
NICAM
DEC.
LEVEL
ADJ.
VCXO
CLOCK
LEVEL
ADJ.
DAC
CHANNEL
SELECTION
ANALOGUE CROSS BAR SWITCH
TR8
1
PLCK
2 NICAM
3 ADDR1
4
SCL
5
SDA
6
VSSA1
7 VDEC1
8
Iref
9
P1
10
SIF2
11
Vref
12
SIF1
13 ADDR2
14
Vssd1
15
Vdd1
16 CRESET
17
Vssd4
18 XTAL1
19 XTAL0
20
P2
21 SYSLCK
22
SCK
23
WS
24
SDO2
25
SDO1
26
SDI2
27
SDI1
28 TEST1
29 MONOIN
30 TEST2
31 EXT/R
32 EXT/L
DAC
IIS
AUDIO PROCESSING
ENC.
DEC.
L.S.
H.P.
AVL,VOL
CONTOUR
BASS
TREBLE
PSEUDO
BASS CORR
VOL.
BASS
TREB.
DAC
DAC
TEST
VDD2
LOR
LOL
MOL
MOR
Vdda
AUXOL
AUXOR
Vssa3
pcapl
pcapr
vREF3
SCOL2
SCOR2
Vssa4
Vssd2
SCOL1
SCOR2
Vref2
i.c.
i.c.
Vssa2
i.c.
i.c.
Vref(n)
Vref(p)
Vdec2
SCIL2
SCIR2
Vssd3
SCIL1
SCIR1
TDA9875A
TDA9875A PINOUT & PERIPHERALS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
6V
AUDIO LINE OUT
TR9
TO AUDIO
AMPLIFIER
TR10
6V
TR11
TR12
TO HEADPHONES
APLIFIER
IC4
TDA2822M
AUDIO OUT TO SCART
AUDIO FROM SCART
TDA9875A.DRW
E.G. 7/11/99
TDA9811
Multistandard VIF-PLL
with QSS-IF and AM demodulator
FEATURES
•
5 V supply voltage
•
Two switched VIF inputs, gain controlled wide band VIF-amplifier (AC-coupled)
•
True synchronous demodulation with active carrier regeneration
(very linear
demodulation, good intermodulation figures, reduced harmonics, excellent pulse
response)
•
Gated phase detector for L/L accent standard VCO frequency switchable between L
and L accent (alignment external) picture carrier frequency
•
Separate video amplifier for sound trap buffering with high video bandwidth VIF AGC
detector for gain control, operating as peak sync detector for B/G (optional external
AGC) and peak white detector for L; signal controlled reaction time for L
•
Tuner AGC with adjustable takeover point (TOP)
•
AFC detector without extra reference circuit
•
SIF input for single reference QSS mode (PLL controlled); SIF AGC detector for gain
controlled SIF amplifier; single reference QSS mixer able to operate in high
performance single reference QSS mode
•
AM demodulator without extra reference circuit
•
AM mute (especially for NICAM)
•
Stabilizer circuit for ripple rejection and to achieve constant output signals.
GENERAL DESCRIPTION
The TDA9811 is an integrated circuit for multistandard vision IF signal processing and
sound AM demodulation, with single reference QSS-IF in TV and VCR sets.
TDA9811 QSS
Pagina 1 di 4
e.g. TDA9811R
28
3
6
19
TUNER AND VIF-AGC
loop
filter
AFC
7
25
24
23
AFC DETECTOR
VCO TWD
21
video
1 V (p-p)
10
CVBS
2 V (p-p)
5
VIFB
4
2
VIFA
VIDEO
BUFFER
1
4
32
SIF
VIDEO DEMODULATOR
AND AMPLIFIER
FPLL
VIF AMPLIFIER
AND
INPUT SWITCH
SIF
AMPLIFIER
31
22
TDA9811
SINGLE REFERENCE
MIXER AND
AM DEMODULATOR
AF AMPLIFIER
AND SWITCH
13
INTERNAL VOLTAGE
STABILIZER
29
27
12
SIF-AGC
14
26
9
8
20
11
18
16
15
Philips Semiconductors
tuner
AGC
Multistandard VIF-PLL
with QSS-IF and AM demodulator
2 x f PC
TOP
C BL
VIF input switch
30
BLOCK DIAGRAM
dbook, full pagewidth
1995 Oct 03
CAGC
Vi(vid)
AF/AM
n.c.
n.c.
17
1/2 VP
C AGC
5V
standard
switch
L′/L
switch
MHA046
n.c.
mute switch, AM
TDA9811
Fig.1 Block diagram.
n.c.
Preliminary specification
(2nd SIF)
Vo QSS
n.c.
FUNCTIONAL DESCRIPTION
Vision IF amplifier and input switch The vision IF amplifier consists of three AC-coupled
differential amplifier stages. Each differential stage comprises a feedback network
controlled by emitterdegeneration. T
The first differential stage is extended by two pairs of emitter followers to provide two IF
input channels. The VIF input can be selected by pin 30
Tuner and VIF AGC
The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the
tuner AGC to generate the tuner AGC output current (open-collector output).
The tuner AGC takeover point can be adjusted. This allows the tuner and the SWIF filter to
be matched to achieve the optimum IF input level.
The AGC detector charges/discharges the AGC capacitorto the required voltage for setting
of VIF and tuner gain in order to keep the video signal at a constant level.
Therefore for negative video modulation the sync level and for positive video modulation
the peak white level of the video signal is detected. In order to reduce the reaction
time for positive modulation, where a very large time constant is needed, an additional
level detector increases the discharging current of the AGC capacitor (fast mode)
in the event of a decreasing VIF amplitude step. The additional level information is given
by the black-level detector voltage.
Frequency Phase Locked Loop detector (FPLL)
The VIF-amplifier output signal is fed into a frequency detector and into a phase detector
via a limiting amplifier.
During acquisition the frequency detector produces a DC current proportional to the
frequency difference between the input and the VCO signal. After frequency lock-in the
phase detector produces a DC current proportional to the phase difference between the
VCO and the input signal. The DC current of either frequency detector or phase detector is
converted into a DC voltage via the loop filter, which controls the VCO frequency. In the
event of positive modulated signals the phase detector is gated by composite sync in order
to avoid signal distortion for overmodulated VIF signals.
TDA9811 QSS
Pagina 2 di 4
e.g. TDA9811R
VCO, Travelling Wave Divider (TWD) and AFC
The VCO operates with a resonance circuit (with L and C in parallel) at double the PC
frequency. The VCO is controlled by two integrated variable capacitors.
The control voltage required to tune the VCO from its free-running frequency to actually
double the PC frequency is generated by the frequency-phase detector and fed via the
loop filter to the first variable capacitor (FPLL). This control voltage is amplified and
additionally converted into a current which represents the AFC output signal. The VCO
centre frequency can be decreased (required for L accent standard) by activating an
additional internal capacitor. This is achieved by using the L accent switch. In this event
the second variable capacitor can be controlled by a variable resistor at the L accent
switch for setting the VCO centre frequency to the required L accent value. At centre
frequency the AFC output current is equal to zero.
The oscillator signal is divided-by-two with a TWD which generates two differential output
signals with a 90 degree phase difference independent of the frequency.
Video demodulator and amplifier
The video demodulator is realized by a multiplier which is designed for low distortion and
large bandwidth. The vision IF input signal is multiplied with the ‘in phase’ signal of the
travelling wave divider output. In the demodulator stage the video signal polarity can be
switched in accordancewith the TV standard. The demodulator output signal is fed via an
integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The
video amplifier is realized by an operational amplifier with internal feedback and high
bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics
for B/G and L standard. The standard dependent level shift in this stage delivers the same
sync level for positive and negative modulation. The video output signal is 1 V (p-p) for
nominal vision IF modulation.
Video buffer
For an easy adaption of the sound traps an operational amplifier with internal feedback is
used in the event of B/G and L standard. This amplifier is featured with a high bandwidth
and 7 dB gain. The input impedance is adapted output stage delivers a nominal 2 V (p-p)
positive video signal. Noise clipping is provided.
TDA9811 QSS
Pagina 3 di 4
e.g. TDA9811R
SIF amplifier and AGC
The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each
differential stage comprises a controlled feedback network provided by emitter
degeneration. The SIF AGC detector is related to the SIF input signals (average level of
AM or FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the
AM demodulator and single reference QSS mixer. The SIF AGC reaction time is set to
‘slow’ for nominal video conditions. But with a decreasing VIF amplitude step the SIF AGC
is set to ‘fast’ mode controlled by the VIF AGC detector. In FM mode this reaction time is
also set to ‘fast’ controlled by the standard switch.
Single reference QSS mixer The single reference QSS mixer is realized by a multiplier.
The SIF amplifier output signal is fed to the single reference QSS mixer and converted to
intercarrier frequency by the regenerated picture carrier (VCO).
The mixer output signal is fed via a high-pass for attenuation of the video signal
components to the output pin 20. With this system a high performance hi-fi stereo
sound processing can be achieved.
AM demodulator
The AM demodulator is realized by a multiplier. The modulated SIF amplifier output signal
is multiplied in phase with the limited (AM is removed) SIF amplifier output signal. The
demodulator output signal is fed via an integrated low-pass filter for attenuation of the
carrier harmonics to the AF amplifier.
Internal voltage stabilizer and 1 ¤2 VP -reference
The bandgap circuit internally generates a voltage of approximately 1.25 V, independent of
supply voltage and temperature. A voltage regulator circuit, connected to this voltage,
produces a constant voltage of 3.6 V which is used as an internal reference voltage.
For all audio output signals the constant reference voltage cannot be used because large
output signals are required.
TDA9811 QSS
Pagina 4 di 4
e.g. TDA9811R
Philips Semiconductors
Preliminary specification
Multistandard VIF-PLL
with QSS-IF and AM demodulator
TDA9811
PINNING
SYMBOL
PIN
DESCRIPTION
Vi VIF1
1
VIF differential input signal voltage 1
Vi VIF2
2
VIF differential input signal voltage 2
CBL
3
black level detector
Vi VIF3
4
VIF differential input signal voltage 3
Vi VIF1
1
32 V i SIF2
Vi VIF4
5
VIF differential input signal voltage 4
Vi VIF2
2
31 V i SIF1
TADJ
6
tuner AGC takeover adjust (TOP)
C BL
3
30 INSWI
TPLL
7
PLL loop filter
29 VP
8
SIF AGC capacitor
Vi VIF3
4
CSAGC
STD
9
standard switch
Vi VIF4
5
28 C VAGC
Vo CVBS
10
CVBS output signal voltage
TADJ
6
27 GND
TPLL
7
26 Cref
CSAGC
8
andbook, halfpage
LSWI
11
L/L accent switch
Vo AF
12
AM audio voltage frequency output
n.c.
13
not connected
STD
n.c.
14
not connected
Vo CVBS 10
n.c.
15
not connected
n.c.
16
not connected
MUTE
17
AM mute
n.c.
18
not connected
TAGC
19
Vo QSS
Vo(vid)
25 VCO2
TDA9811
24 VCO1
9
23 AFC
LSWI 11
22 Vi(vid)
Vo AF 12
21 Vo(vid)
n.c. 13
20 Vo QSS
tuner AGC output
n.c. 14
19 TAGC
20
single reference QSS output voltage
n.c. 15
18 n.c.
21
composite video output voltage
n.c. 16
17 MUTE
Vi(vid)
22
video buffer input voltage
AFC
23
AFC output
VCO1
24
VCO1 reference circuit for 2fPC
VCO2
25
VCO2 reference circuit for 2fPC
Cref
26
1⁄
GND
27
ground
CVAGC
28
VIF AGC capacitor
VP
29
supply voltage
INSWI
30
VIF input switch
Vi SIF1
31
SIF differential input signal voltage 1
Vi SIF2
32
SIF differential input signal voltage 2
1995 Oct 03
2VP
MHA047
reference capacitor
Fig.2 Pin configuration.
5
TDA9830
TV sound AM-demodulator and
audio source switch
FEATURES
• Adjustment free wideband synchronous AM demodulator
• Audio source-mute switch (low noise)
• Audio level according EN50049
• 5 to 8 V power supply or 12 V alternative
• Low power consumption.
GENERAL DESCRIPTION
The TDA9830, a monolithic integrated circuit, is designed for AM-sound demodulation
used in L- and L’-standard.
The IC provides an audio source selector and also mute switch.
FUNCTIONAL DESCRIPTION
Sound IF input
The sound IF amplifier consists of three AC-coupled differential amplifier stages each with
approximately 20 dB gain. At the output of each stage is a multiplier for gain controlling
(→ current distribution gain control). The overall control range is approximately -6 to +60
dB and the frequency response (-3 dB) of the IF amplifier is approximately 6 to 70 MHz.
The steepness of gain control is approximately 10 mV/dB.
IF AGC
The automatic gain control voltage to maintain the AM demodulator output signal at a
constant level is generated by a mean level detector. This AGC-detector charges and
discharges the capacitor at pin 3 controlled by the output signal of the AM-demodulator
compared to an internal reference voltage. The maximum charge/discharge current is
approximately 5 mA. This value in combination with the value of the AGC capacitor and
the AGC steepness determines the lower cut-off audio frequency and the THD-figure at
low modulation frequency of the whole AM-demodulator. Therefore a large time constant
has to be chosen which leads to slow AGC reaction at IF level change. To speed up the
AGC in case of IF signal jump from low to high level, there is an additional comparator built
in, which can provide additional discharge current from the AGC capacitor up to 5 mA in a
case of overloading the AM demodulator by the internal IF signal.
AM-demodulator
The IF amplifier output signal is fed to a limiting amplifier (two stages) and to a multiplier
circuit. However the limiter output signal (which is not any more AM modulated) is also fed
to the multiplier, which provides AM demodulation (in phase demodulation). After lowpass
filtering (fg ≈ 400 kHz) for carrier rejection and buffering, the demodulator output signal is
present at pin 6. The AM demodulator operates over a wide frequency range, so that in
Philips Semiconductors
3
TV sound AM-demodulator and audio
source switch
June 1994
Product specification
TDA9830
Fig.1 Block diagram.
combination with the frequency response of the IF amplifier applications in a frequency
range from approximately 6 MHz up to 70 MHz are possible.
Audio switch
This circuit is an operational amplifier with three input stages and internal feedback
network determining gain (0 dB) and frequency response (fg ≈ 700 kHz). Two of the input
stages are connected to pin 7 and pin 9, the third input stage to an internal reference
voltage. Controlled by the switching pins 10 and 12, one of the three input stages can be
activated and a choice made between two different AF signals or mute state. The selected
signal is present at pin 8. The decoupling capacitors at the input pins are needed, because
the internally generated bias voltage for the input stages must not be influenced by the
application in order to avoid DC-plop in case of switching.
The AM demodulator output is designed to provide almost the same DC voltage as the
input bias voltage of the audio switch. But there may be spread between both voltages.
Therefore it is possible to connect pin 6 directly to pin 7 (without a decoupling capacitor),
but in this event the DC-plop for switching can increase up to 100 mV.
Reference circuit
This circuit is a band gap stabilizer in combination with a voltage regulation amplifier,
which provides an internal reference voltage of about 3.6 V nearly independent from
supply voltage and temperature. This reference voltage is filtered by the capacitor at pin 4
in order to reduce noise. It is used as a reference to generate all important voltages and
currents of the circuit. For application in 12 V power supply concepts, there is an internal
voltage divider in combination with a Darlington transistor in order to reduce the supply
voltage for all IC function blocks to approximately 6 V.
This is necessary because of use of modern high frequency IC technology, where most of
the used integrated components are only allowed to operate at maximum 9 V supply
voltage.
12
7
6
8
MONO
INPUT
10
9
5
11
EXT. IN
2
1
SCART OUT
4
3
LINE OUT
A3
A1
6V
6V
A2
INTERCARRIER INPUT
SCART SOUND OUT
1
29
31
32
33
34
IIC
35 36 37
38 39
47 48
49 50
51
52
62
63
ANALOGUE CROSS BAR SWITCH
10
12
INPUT
SWITCH
TDA9870A
DAC
FM DEM
(AM DEM)
DEMATR
DEEMPH
LEVEL
ADJ.
IIS
SCL 4
IIC
5
I/O
PORT
IDENT
IIC
PEAK
DETECT.
SDA
3 IIC ADDRES.
6 VSSA1 7
2° IIC ADDRESS
8
17
14
20
9
11
13 15 16
VCXO
CLOCK
18
2
3
VSSA2 43
VSSA3 56
VSSA4 50
4
26V
28
TEST
AVL, VOL
CONTOUR, BASS
TREB, PSEU
BASSCORR
BEEPER
CHANNEL
SELECTION
64
VDDA3 VDDD2
VSSD2 49
AUDIO
PROCESSING
L.S .
DAC
AGC
ADC
59
60
8
DAC
9
61
H.P.
ENC / DEC.
19
22 23 24 25 26 27
21
10
TR10
TR12
57
IIS
7
30
TR9
DAC
VOL, BEEP.
BASS, TREB.
58
TR11
IIS
F19
STEREO A2
MODULE
7
6
HEADPHONES
IC 4 AMPLIFIER
TDA2822M
6V
2
KIA7812
1
2
3
12 V
IC 5
F19STA2 .DRV
E.G
5/11/99
4
1
5
3
6
7
5
12
6
8
11
10
9
2
1
4
3
A1
EXT. IN
IF IN
TR6
6V
A3
6V
12V
A2
SCART SOUND OUT
EF
1
STEREO INTERCARRIER ONLY
29
31
32
TDA9875A
10
12
EF
34
35 36 37
38 39
47 48
QPSK
DEM.
NICAM
DEC.
FM DEM
(AM DEM)
ADC
1
LEVEL
ADJ.
DAC
DEMATR
DEEMPH
LEVEL
ADJ.
I/O
PORT
IDENT
PEAK
DETECT.
SDA
3
6
2° IIC ADDRESS
IIC ADDR.
7
8
59
63
17
14 20
9
11
18
19
21
13 15 16
2
VDDA3 VDDD2
VSSD2 49
VSSA2 43
VSSA3 56
VSSA4 50
3
4
26V
28
TEST
60
22 23 24 25 26 27
10
TR10
8
DAC
9
61
H.P.
ENC / DEC.
7
30
TR12
57
IIS
VCXO
CLOCK
64
AVL, VOL
CONTOUR, BASS
TREB, PSEU
BASSCORR
BEEPER
IIS
DATA
SCL 4
IIC
62
AUDIO
PROCESSING
L.S .
DAC
CHANNEL
SELECTION
2 NICAM
5
51 52
AGC
PLK
IIC
49 50
ANALOGUE CROSS BAR SWITCH
INPUT
SWITCH
TR1
33
IIC
TR9
DAC
VOL, BEEP.
BASS, TREB.
58
TR11
IIS
TR7
6V
TR8
TR5
TR4
1
2
R7
L /L'
4
12 V
5
R5
R6
TR3
F19NICAM.DRV
E.G
5/11/99
D2
FOS 1
2
6V
R6
3
3
6
19
11
25
23
VCO
VIDEO
DEMOD.
FPLL
31
TDA 9811
IC 1
24
SIF
AMPL.
29
5V
FM MIXER
& AM DEM.
27
20
AF AMPL.
& SWT.
1
5
3
6
12 V
AFC
21
IF AMPL.
&
VIDEO
SWITCH
32
TR2
28
TUNER & VIF AGC
1
D1
L1
R20
30 VIF SWT. 9
FOS2
L/L'
STD
8V
EF
7
6
HEADPHONES
AMPLIFIER
IC 4 TDA2822M
2
4
8V
10
22
12
17
MUTE
3
KIA7812 2
1
IC 5
26 V
FROM
PIM 7
A2
F19
NICAM
MODULE
STEREO MODULE CONNECTOR
3
4
7
1
2
8
IC 400 TDA1521A
9
9
8
7
6
5
4
3
2
1
FROM PIN 11
TUNER (I.F.)
1
3
FROM PIN 6 IC 100
AV1 / AV2
SWITCH
2
4
19
20
FROM PIN8
IC 100
SCART/CINCH
SWITCH
TR110
6
16
18
SCART 1
10
2
17
15
1
11
12
13
15
12
14
AUDIO
CINCH IN
13
14
11
8
IC201 (2/3 OF LA7955)
FROM PIN 7 IC 100
TV/AV SWITCH
TO AV2
F19ASSPH.DRW
E.G.
29/12799
SCART 2
6
2
1
3
IC200 (2/3) HEF 4053
F19 AUDIO STEREO SIGNAL PATH
TDA4605
Control IC for Switched-Mode Power Supplies
using MOS-Transistors
Features
•
Fold-back characteristic provides overload protection for external components
•
Burst operation under short-circuit conditions
•
Loop error protection
•
Switch-off if line voltage is too low (undervoltage switch-off)
•
Line voltage compensation of overload point
•
Soft-start for quiet start-up
•
Chip-over temperature protection (thermal shutdown)
•
On-chip parasitic transformer oscillation suppression circuitry
Functional desciption
The IC TDA 4605-1 controls the MOS-power transistor and performs all necessary
regulation and monitoring functions in free running flyback converters. Since good load
regulation over a wide load range is attained, this IC is applicable tor consumer and
industrial power supplies.
The serial circuit of power transistor and primary winding of the flyback transformer is
connected to the input voltage. During the switch - on period of the transistor, energy is
stored in the transformer and during the switch - off period it is fed to the load via the
secondary winding. By varying switch-ontime of the power transistor, the IC controls each
portion of energy transferred to the secondary side such that the output voltage remains
nearly independent ot load variations.
The required control information is taken from the input voltage during the switch-on period
and from a regulation winding during the switch-off period.
In the different load ranges the switched-mode power supply (SMPS) behaves as follow:
TDA4605 SMPS CONTRO I.C.
e.g.tda4605R.doc
Pagina 1 di 6
No load operation:
The power supply unit oscillates at its resonant frequency typ. 100 kHz to 200 kHz.
Depending upon
the transformator windings the output voltage can be slightly above nominal value.
Nominal operation:
The switching frequency declines with increasing load and decreasing AC-voltage. The
duty factor primarly depends on the AC-voltage. The output voltage is load-dependent
only.
Overload point:
Maximal output power is available at this point ot the output characteristic.
Overload:
The energy transferred per operation cycle is limited at the top. Therefore the output
voltage declines by secondary overloading..Semiconductor Group 35
TDA 4605 Pin Definitions and Functions
Pin No. Function
1
Regulating Voltage:
Information input concerning secondary voltage. By
comparing the regulating voltage - obtained from the regulating winding ot the transformer
- with the internal reference voltage, the output impulse width on pin 5is adapted to the
load ot the secondary side (normal, overload, short-circuit, no load).
2
Primary Current Simulation: Information input regarding the primary current.
The primary current rise in the primary winding is simulated at pin 2 as a voltagerise by
means ot external RC-element. When a value is reached that is derivedfrom the regulating
voltage at pin 1, the output impulse at pin 5 is terminated. TheRC-element serves to set
the maximum power at the overload point set.
3
Input for Primary Voltage Monitoring: In the normal operation V 3 is moving
between the thresholds V 3H and V 3L (V 3H > V 3 > V 3L ). V 3 < V 3L : SMPS is
switched OFF (line voltage too low). V 3 > V 3H : Compensation of the overload point
regulation (controlled by pin 2) starts at V 3H : V 3L = 1.7.
TDA4605 SMPS CONTRO I.C.
Pagina 2 di 6
e.g.tda4605R.doc
4
Ground
5
Output: Push-pull-output provides
1 A for rapid charge and discharge of the
gate capacitance ot the power MOS-transistor.
5
Supply Voltage Input: A stable internal reference voltage V REF is derived from
the supply voltage also the switching thresholds V 6A , V 6E , V 6 max and V 6 min for the
supply voltage detector. If V 6 > V 6E then V REF is switched on and swiched off when V
6 < V 6A . In addition the logic is only enable for V 6 min < V 6 < V 6 max .
7
Soft-Start: Input for soft-start. Start-up will begin with short pulses by connecting a
capacitor from pin 7 to ground.
8
Zero Detector: Input tor the oscillation feedback. After starting oscillation, every
zero transit of the feedback voltage (falling edge) triggers an output impulse at
pin 5. The trigger threshold is at + 50 mV typical..Semiconductor Group 36
TDA 4605 Application Circuit
Application circuit shows a flyback converter for video recorders with a power rating of 50
W. The circuit is designed as a wide-range power supply tor AC-line voltages ot 90 to 270
V. The AC-input voltage is rectified by bridge rectifier GR1 and smoothed by C 1 . The
NTC limits the rush in current.In the period before the switch-on threshold is reached the
IC is supplied via resistor R 1 ; during the start-up phase it uses the energy stored in C 2 ,
under steady-state conditions the IC receives its supply voltage from transformer winding n
1 via diode D1. The switching transistor T1 is a BUZ 90.
The parallel-connected capacitor C 3 and the inductance ot primary winding 112 determine
the system resonance frequency. The R 2 - C 4 - D2 circuitry limits overshoot peaks, and
R 3 protects the gate of T1 against static charges.
While T1 conducts, the current rise in the primary winding depends on the winding’s
inductance and the V C1 voltage. A voltage reproduction ot the current rise is tabbed using
the R 4 - C 5 network and forwarded into pin 2 ot the IC. The RC-time constant ot R 4 , R 5
must be dimensioned correctly in order to prevent driving the transformer core into
saturation.
The R 10 /R 11 divider ratio provides the line voltage threshold controlling the
undervoltage control circuit in the IC. The voltage present at pin 3 also determines the
overload. Detection of overload together with the current characteristic at pin 2 controls the
on period ot T1. This keeps the cut-off point stable even with higher AC-line voltages.
TDA4605 SMPS CONTRO I.C.
e.g.tda4605R.doc
Pagina 3 di 6
Pin 3 The down-divide primary voltage applied there stabilizes the overload point. In
addition the logic is disabled in the event of low voltage by comparison with the internal
stable voltage V V in the primary voltage monitor block.
Pin 4 Ground
Pin 5 In the output stage the output signals produced by the logic are shifted to a leved
suitable for MOS-power transistors.
Pin 6 From the supply voltage V 6 are derived a stable internal reference V REF and the
switching threshold V 6A , V 6E , V 6 max and V 6 min for the supply voltage monitor. All
reference values (V R , V 2B , V ST ) are derived from V REF . If V 6 > V VE the V REF is
switched on and switched off when V 6 < V 6A . In addition, the logic is released only for V
6 min < V 6 < V 6 max .
Pin 7 The output of the overload amplifier is connected to pin 7. A load on this output
causes a reductio in maximal impulse duration. This function can be used to implement a
soft start, when pin 7 is connected to ground by a capacitor
Pin 8 The zero detector controlling the logic block recognizes the transformer being
discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for
a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new
pulse (double-pulsing), because an internal circuit inhibits the zero detector for a finite time
t UL after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per sheet 48 is represented on sheet 50
for a line voltage barely above the lower acceptable limit voltage value (without soft-start).
After applying the line voltage at the time t 0 to the tollowing voltages built up:
– V 6 corresponding to the half-wave charge current over R 1
– V 2 to V 2 max (typically 6.6 V)
– V 3 to the value determined by the divider R 10 /R 11 .
The current drawn by the IC in this case is less than 1.6 mA. If V 6 reaches the threshold V
6E (time point t 1 ), the IC switches on the internal reference voltage. The currentdraw
max. rises to 12 mA.
The primary current- voltage reproducer regulates V 2 down to V 2E and the starting
impulse generator generates the starting impulses from time point t 5 to t 6 . The feedback
to pin 8 starts the next impulse and so on. All impulses including the starting impulse are
TDA4605 SMPS CONTRO I.C.
e.g.tda4605R.doc
Pagina 5 di 6
controlled in width by regulating voltage of pin 1. When switching on this corresponds to a
short-circuit event, i.e. V 1 = 0.
Hence the IC starts up with "short-circuit impulses" to assume a width depending on the
regulating voltage feedback (the IC operates in the overload range). The maximum pulse
width is reached at time point t 2 (V 2 = V 2 max ). The IC operates at the overload point.
Thereafter the peak values ot V 2 decrease rapidly, as the IC is operating within the
regulation range. The regulating loop has built up. If voltage V 6 falls below the switch-off
threshold V 6 min before the reversal point is reached, the starting attempt is aborted (pin
5 is switched to low). As the IC remains switched on, V 6 further decreases to V 6 . The IC
switches off; V 6 can rise again (time point 14) and a new start-up attempt begins at time
point t 1 . If the rectified alternating line voltage (primary voltage) collapses during load, V
3 can fall below V 3A , as is happening at time point t 3 (switch-on attempt when voltage is
too low). The primary voltage monitor then clamps V 3 to V 3S until the IC switches off (V
6 < V 6A ). Then a new start-up attempt begins at time point t
Regulation, Overload and No-Load Behaviour
When the IC has started up, it is operating in the regulation range. The potential at pin 1
typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses
(V 5 = H). The peak voltage value at pin 2 increases up to V 2S max . If the secondary
load is further increased, the overload amplifier begins to regulate the pulse width
downward. This point is referred to as the overload point of the power supply. As the IC
supply voltage V 6 is directly proportional to the secondary voltage, it goes down in
accordance with the overload regulation behaviour. If V 6 falls below the value V 6 min ,
the IC goes into burst operation. As the time constant of the half-wave charge-up is
relatively large, the short-circuit power remains small. The overload amplifier cuts back
to the pulse width t pk . This pulse width must remain possible, in order to permit the IC to
start-up without problems from the virtual short circuit, which every switching on with V 1 =
0 represents. If the secondary side is unloaded, the loading impulses (V 5 = H) become
shorter. The frequency increases up to the resonance frequency of the system. If the load
is further reduced, the secondary voltages and V 6 increase. When V 6 = V 6 max , the
logic is blocked. The IC converts to burst operation. This renders the circuit absolutely safe
under no-load conditions.
TDA4605 SMPS CONTRO I.C.
e.g.tda4605R.doc
Pagina 6 di 6
Regulation of the switched-mode power supply is via pin 1. The control voltage of winding
n 1 during the off-period of T1 is rectified by D3, smoothed by C 6 and stepped down at an
adjustable ratio by R 5 , R 6 and R 7 . The R 6 - C 7 network suppresses parasitic
overshoots (transformer oscillation).
The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that
the voltage applied across the control winding, and hence the output voltages, are at the
desired level.
When the transformer has supplied its energy to the load, the control voltage passes
through zero.
The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero
crossings are also produced by transformer oscillation after T1 has turned off if output is
short-circuited. Thereforethe IC ignores zero crossings occurring within a specitied period
of time after T1 turn-off.
The capacitor C 8 connected to pin 7 causes the power supply to be started with shorter
pulses to keep the operating ftrequency outside the audible range during start-up.
On the secondary side, tive output voltages are produced across winding n 3 to n 7
rectified by D4 to D8 and smoothed by C 9 to C 13 . Resistors R 12 , R 14 and R 19 to R
21 are used as bleeder resistors.
Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output
circuits, which are designed to supply only small loads..
TDA 4605 Block Diagram
Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal
reference voltage V R in the regulating and overload amplifier. The output of this stage
is ted to the stop comparator.
Pin 2 A voltage proportional to the drain current ot the switching transistor is generated
there by theexternal RC-combination in conjunction with the primary current transducer.
The output of this transducer is controlled by the logic and referenced to the internal stable
voltage V 2B . If the voltage V 2 exceeds the output voltage of the regulating amplifier, the
logic is reset by the stop comparator and consequently the output ot pin 5 is switched to
low potential. Further inputs tor the logic stage are the output for the start impulse
generator with the stable reference potential V ST and the supply voltage monitor.
TDA4605 SMPS CONTRO I.C.
e.g.tda4605R.doc
Pagina 4 di 6
TDA 4605
Block Diagram
Semiconductor Group
36
F 19
S.M.P.S.
MAINS
INPUT
(CONFIGURATION WITHOUT
ZERO POWER STAND BY MODULE)
NON MAINS ISOLATED SECTOR
line output stage
START-UP
TR 1
STH7N80FI
D13
2
15
TR 4
148 V (110°)
sound
power
TR3
4
R1
SOFTSTART
128 V
D6
3
DRIVE
OUTPUT
PULSE
ZERO CROSSING
DETECTOR
line driver
26 V
10
11
8
5
6
7
1
8
9
3
2
D8
9
stand by
12
1
4
6 / 16
SMPS CONTROL
IC1 TDA 4605
4
12 V
signal
processing
8
2
5
26 V
8,5v
5V
T1
R14
FROM PIN 19 OFF
IC 100
ON
SAA5297A
PRIMARY
VOLTAGE & CURRENT
SENSING
SUPPLY VOLTAGE
ADJUSTMENT
OVER LOAD
PROTECTION
TR6
TR 2
TR5
5V
F19SMPS.DRW
E.G. 7/11/99
line output stage
2
15
TR 4
148 V (110°)
26 V
LOW POWER
STAND-BY
CONFIGURATION
sound
power
TR3
4
128 V
3
line driver
10
26 V
11
12 V
signal
processing
IC10
8
5
1
9
8
TDA8183
2
4
9
5V
stand by
5V
6 / 16
12
F 19
FROM PIN 19
IC 100
SAA5297A
8,5v
OFF
T1
ON
TR 2
MAINS TO MAIN BOARD
T1
1
TR2 BT808
IC2 IL410
9
FROM
MAINS
SWITCH
1
IC 1
L7805CV
7
3
2
5
STAND-BY MODULE
X1
A12
ON-OFF
X2
X3
5 V ST-BY
F19LPSBC.DRW
E.G. 14 /11/99
F19
F19
SERVICE MODE
For the description of the use of the TV make use of the Instruction Manual
Service mode
As already mentioned in the summary the remote control can be used to set all
parameter and to adjust the TV set without to open the back cover.
There are two ways to enter the "SERVICE MODE" that are to use the LOCAL
KEYBOARD or to have a precial prepared REMOTE CONTROL.
FIRST METHOD. (If the special remote control is available use the button following the
indication of the Table 1
Table 1 List of command of the "SERVICE REMOTE CONTROL"
BUTTON
RC5 Sub Decimal Coce
Function
System
0
0
0
Vertical Slope
1
0
1
Vertical Amplitude
2
0
2
Vertical Shift
3
0
3
Vertical S Correctio
4
0
4
Horizontal Shift
5
0
5
HorizontalAmplitude
6
0
6
E-W parabola
7
0
7
E-W Corner
8
0
8
E-W Trapezium
9
0
9
AGC
Pr +
0
32
Up Carousel of all Service Parameter
Pr -
0
33
Down Carousel of all Service Parameter
Vol +
0
16
Adjust Parameter Value (UP)
Vol -
0
17
Adjust Parameter Value (Down)
TV
0
63
Leave SERVICE MODE" without to store
MEM
0
50
Leave SERVICE MODE with store
MENU
0
53
Wred
SERVICE
7
58
SERVICE MODE ENTER
E.G.Data creazione 31/10/99 15.38
3/7
f19intro
Table 2 Parameter and value to be adjusted in "SERVICE MODE"
PARAMETER
VALUE
DESCRIPTION
init ctvfor v0.6
on/ off
Default Initialization
vg2test
on/off
Cut -off adjustment
txtbri
0--63
Adjust TXT brightness
txtcon
0--63
Adjust TXT Contrast
884c04
Bit (FSU)
Increase blue stretch and the dynamic skin
884c03
Bit (FSU)
Adj. acl (automatic colour limiter - and cathode drive level.
88c02
Bit (FSU)
Adj.(black stretch), blue stretch, and the blue back
optionb1
Bit (FSU)
Select TV standard and TXT character set
optionb2
Bit (FSU)
Scart type selections (
optionb3
Bit (FSU) (*) Hotel mode setting
nicamuperror
0--63
Nicam sensitivity (upper limit)
nicamlowerror
0--63
Nicam sensitivity (Lower limit).
nicamcon
Bit (FSU)
Tda9875 CONTROL
pipcontrast
0--15
PIP Contrast control
wblue
0--63
Blue channel gain
wgreen
0--63
“Green channel gain
wred
0--63
“Red channel gain
ydelaypal
0--63
Luma chroma delay
ewtrapeze
0--63
E-W- Trapezium adjustment
ewcorner
0--63
E-W- Corner Adjustment
ewparab
0--63
E-W- Parabola Adjustment
ewwidth
0--63
Horizontal Amplitude
h-shift
0--63
Horizontal shift
s-corr
0--63
Vertical S-Correction
v-shift
0--63
Shift Vertical
v-ampl
0--63
Vertical Amplitude
v-slope
0--63
Slope Vertical
agc
0--63
AGC adjustment
if xx afc 2/3
0--63 (FSU) Factory set up
LEGENDA: (FSU)= FACTORY SET UP
(*) REDUCE OF A QUANITY 4 TO GET HOTEL MODE
WARNING!! Do not change value for those parameter that are highlighted please
E.G.Data creazione 31/10/99 15.38
5/7
f19intro
Note 1
If during the installation of the TV set the AUTOSTORE"
method is used, it is
fundamental, before to start the function, to select the name of the country as the criteria of
listing the broadcasters names is fixed by EBU table that are related to the country itself. It
is possible to find more channels of the same broadcaster on the Arial. In this case the
system will place first the signal having TXT with the strongest signal level than the others
and finally, with the found sequence the weakest one without TXT.
Note 2
To get HOTEL MODE it is necessary to enter "SERVICE MODE" and to change the
parameter "optionb3". Read the original value e subtract 4 (decimal). In HOTEL MODE all
tuning systems are not possible, the volume is pre fixed and the MENU from the LOCAL
KEY BOARD is not accessible.
Note 3
For fast programming (in case of installation of several TV set in Shops or Hotels a
"Black Box" is available on request. The procedure for a quick program is as follows:
1. Install and tune all channel storing it in the program sequence you want
2. Switch off the Set with the remote control and leave it in Stand-by mode
3. Switch on the "Black Box" and connect it to Scart
4. Press the button corresponding to the chassis to be programmed and at the same time
press the button "Read" for a while. (corresponding LED will be on.
5. When the LED "Write" became off (after few seconds) disconnect the "Black Box"
6. Insert the Black Box in the new TV set (in stand by condition)
7. Press F19 and "Write" buttons at same time. Corresponding "Write" LED will light
8. After few seconds when the "Write" LED will switch-off the procedure is finished .
9. Repeat points from 6 to 8 to program others TV set
WARNING!!!!! The above procedure can be applied
only to TV set specially prepared for this functions
E.G.Data creazione 31/10/99 15.38
6/7
f19intro
Table 4 List of languages that can be reproduced as a function of the TXT characters set
setting with the optionb1 (bit number 6)
WEST EUROPE CHARACTER SET
EAST EUROPE CHARACTER SET
LANGUAGES
LANGUAGES
ENGLISH
POLISH
GERMAN
GERMAN
SWEDISH
ESTONIA
ITALIAN
SERB-CROAT
FRENCH
CZECH
SPANISH
RUMEN
TURKISH
Just to give an example how to set the option byte 1, 2, and 3 we can start from
a TV set for BG standard, with hyperband tuner to be sold in a country using West
European character set.
Locking at the table 3 Optionb1 we have the following condition:
BIT
NUMBER
OPTIONB1
0
1
VALUE WEIGHT
0
BG
1
1
L/L'
0
2
I
0
3
DK
0
4
X
0
5
X
0
6
7
E.E.TXT W.E. TXT
CATV
1
1
64
1
128
Adding the value of the
last column we get 193
in decimal form and C!
in hexadecimal.
This means that we
have to choose this
value (C1) for the
optionb1 in service
mode
If we want to change from West Europe character set to East Europe, bit 6
became 0 that is the new value is 129 (128 plus 1)that in hexadecimal format is 41
REMEMBER TO INSERT COUNTRY TABLE
E.G.Data creazione 31/10/99 15.38
7/7
f19intro
THE SECOND METHOD to enter service mode is to use the LOCAL KEY BOARD
as describe here below
1. Starting from TV off press VOLUME + on the LOCAL KEYBOARD and in the
mean time switch on the TV with the mains switch
2. Within three second switch on the TV using the "SWITCH-OFF" button on the
Remote Control
3. A small windows with black background and yellow characters will appear in the
middle of the screen.
PARAMETER VALUE
4. Using the Remote control, program + / - (top bottom) will change the
"PARAMETER" and the VOLUME + / - (left / right) will change the value
5. Each parameter can be stored, leaving the service mode, by using the MEM
(yellow) button on the remote control
6. To leave "SERVICE MODE" without to store the new value use the TV button.
7. It is not necessary to store each value one by one this means that you can
change all value you need and finally leave the SERVICE MODE pressing the
YELLOW button MEM.
In the Table 3 we can find all parameter and related value to be seated. Some
parameter have to adjusted with a simple on-off value, others are just factory option and
more others must be adjusted with value that are expressed in hexadecimal form ranging
from 0 to FF (that is from 0 to 63 in decimal form ).
Table 3 represent the value to be assigned to three parameter to properly set options:
Table 3 Option bye (1, 2 and 3) value and related meaning
BIT
WEIGHT
OPTIONB1
0
1
OPTIONB2
0
OPTIONB3
1
0
1
0
BG
2° SCART
FSU
1
L/L'
MUST BE 1
BACKGROUND
2
I
CINCH
3
DK
SVHS
NTSC M
4
X
RGB
UV1316
5
X
X
V. GUARD
W.E.TXT
X
CATV
X
6
7
E.E.TXT
E.G.Data creazione 31/10/99 15.38
4/7
HOTEL
f19intro
PICTURE IN PICTURE
MODULE
SDA 9288X
PICTURE IN PICTURE
1 General Description
The Picture-in-Picture Processor SDA 9288X A141 generates a picture of reduced size of
a video signal (inset channel) for the purpose of combining it with another video signal
(parent channel). The easy implementation of the IC in an existing system needs only a
few additional external components. There is a great variety of application facilities
professional and consumer products (TV sets, supervising monitors, multi-media, …)
Data Sheet
•
212 luminance and 53 chrominance pixels per inset line for picture size 1/9
•
6-bit amplitude resolution for each incoming signal component
•
Field and frame mode display
•
Horizontal and vertical filtering
•
Special antialias filtering for the luminance signal
16:9 compatibility
•
Operation in 4:3 and 16:9 sets
•
4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively
Analog inputs
•
Y, + (B-Y), + (R-Y) or Y, -(B-Y), -(R-Y)
Analog outputs
•
Y, + (B-Y), + (R-Y) or Y, – (B-Y), – (R-Y) or RGB
•
3 RGB matrices: EBU, NTSC (Japan), NTSC (USA)
Free programmable position of inset picture
•
Steps of 1 pixel and 1 line
•
All PIP and POP positions are possible
2 picture sizes
•
1/9 or 1/16 of normal size
High resolution display
13.5 MHz/27 MHz display clock frequency
Freeze picture
I 2 C Bus control
SDA 9288X P.I.P.
Pagina 1 di 4
e.g. sda9288xR.doc
Threefold PIP/POP facility
•
Three different I 2 C-addresses (pin-programmable)
System Description
AD Conversion, Inset Synchronization
The inset video signal is fed to the SDA 9288X A141 as analog luminance and
chrominance components 1) . The polarity of the chrominance signals is programmable.
After clamping the video components are AD-converted with an amplitude resolution of 6
bit. The conversion is done using a 13.5 MHz clock for the luminance signal and a 3.375
MHz clock for the chrominance signals.
For the adaption to different application the clamp timing for the analog inputs can be
chosen (CLPS; CLPFIX). Setting this bits to ‘1’ can be useful for non-standard input
signals.
For inset synchronization it is possible to feed either a special 3-level signal via pin HVI
(detection of horizontal and vertical pulses) or separate signals via pins SCI for horizontal
and VI for vertical synchronization. SCI is the horizontal synchron signal of the inset
channel. If the burst gate pulse of the sandcastle is used it must be adapted to TTL
compatible levels by a simple external circuit. Centering of the displayed picture area is
possible by a programmable delay for the horizontal synchronization signal (HSIDEL).
The inset horizontal synchronization signals are sampled with 27 MHz. This 27 MHz clock
and the AD converter clocks are derived from the parent horizontal synchronization pulse
or from the quartz frequency converted by a factor of 4/3.
Delay differences between luminance and chrominance signals at the input of the IC
caused by chroma decoding are compensated by a programmable luminance delay line
(YDEL) of about – 290 ns … 740 ns (at decimation input
By analyzing the synchronization pulses the line standard of the inset signal source is
detected and interference noise on the vertical sync signal is removed. For applications
with fixed line standard (only 625 lines or 525 lines) the automatic detection can be
switched off.
The phase of the vertical sync pulse is programmable (VSIDEL; VSPDEL). By this way a
correct detection of the field number is possible, an important condition for frame mode
display.
Input Signal Processing
SDA 9288X P.I.P.
Pagina 2 di 4
e.g. sda9288xR.doc
This stage performs the decimation of the inset signal by horizontal and vertical filtering
and sub-sampling. A special antialias filter improves the frequency response of the
luminance channel. It is optimized for the use of the horizontal decimation factor 3:1.
A window signal, derived from the sync pulses and the detected line standard, defines the
part of the active video area used for decimation. For HSIDEL = ‘0’ the decimation window
is opened about 104 clock periods (13.5 MHz) after the horizontal synchronization pulse.
For the 625 lines standard the 36th video line is the first decimated line, for the 525 lines
standard decimation starts in the 26th video line.
The realized chrominance filtering allows omitting the color decoder delay line for PAL and
SECAM demodulation if the color decoder supplies the same output voltages independent
of the kind of operation. In case of SECAM signals an amplification of the chrominance
signals by a factor of 2 is necessary because just every second line a signal is present.
This chrominance amplification is programmable via pin SYS or I 2 C Bus (AMSEC). The
horizontal and vertical decimation factors are free programmable (DECHOR, DECVER).
Using different decimations horizontal and vertical 16:9 applications become realizable:
DECHOR = ‘1’, DECVER = ‘0’: picture size 1/9 for 4:3 inset signals on 16:9 displays
DECHOR = ‘0’, DECVER = ‘1’: picture size 1/16 for 16:9 inset signals on 4:3 displays
PIP Field Memory
The on-chip memory stores one decimated field of the inset picture. Its capacity is 169 812
bits. The picture size depends on the horizontal and vertical decimation factors.
In field mode display just every second inset field is written into the memory, in frame
mode display the memory is continuously written. Data are written with the lower inset
clock frequency depending on the horizontal decimation factor (4.5 MHz or 3.375 MHz).
Normally the read frequency is 13.5 MHz and 27 MHz for scan conversion systems.
For progressive scan conversion systems and HDTV displays a line doubling mode is
available (LINEDBL). Every line of the inset picture is read twice. Memory writing can be
stopped by program (FREEZE), a freeze picture display results (one field).
Having no scan conversion and the same line numbers in inset and parent channel (625
lines or 525 lines both) frame mode display is possible. The result is a higher vertical and
time resolution because of displaying every incoming field. For this purpose the standards
are internally analysed and activating of frame mode display is blocked automatically when
the described restrictions are not fulfilled.
As in the inset channel a field number detection is carried out for the parent channel.
SDA 9288X P.I.P.
Pagina 3 di 4
e.g. sda9288xR.doc
Depending on the phase between inset and parent signals a correction of the display
raster for the read out data is performed by omitting or inserting lines when the read
address counter outruns the write address counter.
The display position of the inset picture is free programmable (POSHOR, POSVER).
The first possible picture position (without frame) is 54 clock periods (13.5 MHz or 27 MHz)
after the horizontal and 4 lines after the vertical synchronization pulses. Starting at this
position the picture can be moved over the whole display area. Even POP-positions
(Picture Outside Picture) at 16:9 applications are possible.
Horizontal Decimation PIP PIXELS per Line
Having different line standards in inset and parent channels we have a so called mixed
mode display. It causes deformations in the aspect ratio of the inset picture. A special
mixed mode display is available for the picture size 1/9 (MIXDIS):
Synchronization of memory reading with the parent channel is achieved by processing
the parent horizontal and vertical synchronization signals in the same way as described
for the inset channel. The synchronization signals are fed to the IC at pin HP/SCP for
horizontal synchronization and pin VP for vertical synchronization. In the same way as
described for the inset channel the burst gate of the sandcastle signal can be used for
horizontal synchronization. In scan conversion systems also the inputs HPD/SCI and
VPD/VI are available if the input HVI is activated for inset synchronization.
2.4 Output Signal Processing
At the memory output the chrominance components are demultiplexed and linearly
interpolated to the luminance sample rate. Different output formats are available:
luminance signal Y with inverted or non-inverted chrominance signals (B-Y), (R-Y) or RGB.
For the RGB conversion 3 matrices are integrated: Matrix selection is done by pin SYS or I
2 C Bus. The matrices are designed for the following input voltages (100 % white, 75 %
color saturation):
SDA 9288X P.I.P.
Pagina 4 di 4
e.g. sda9288xR.doc
SDA 9288X
1.4
Functional Block Diagram
Figure 2
Semiconductor Group
11
03.96
SDA 9288X
4.2.5
Application Circuit (R, G, B-mode)
Figure 10
Semiconductor Group
42
03.96
TDA8310A
PAL/NTSC colour processor
for PIP applications
FEATURES
• Video switch with 2 CVBS inputs. One input can beswitched between CVBS and Y/C and the circuit can
automatically detect whether the incoming signal is CVBS or Y/C
• Integrated chrominance trap and bandpass filters (automatically calibrated)
• Integrated luminance delay line
• Automatic PAL/NTSC decoder which can decode all standards available in the world
• Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications
• Horizontal PLL with an alignment-free horizontal oscillator
• Vertical count-down circuit
• RGB/YUV and fast blanking switch with 3-state output and active clamping
• Low dissipation (560 mW)
• Small amount of peripheral components compared with competition Ics
GENERAL DESCRIPTION
The TDA8310A is an alignment-free PAL/NTSC colour processor for Picture-in-Picture (PIP) applications.
The main difference between the TDA8310 and the TDA8310A is that the vision IF amplifier has been omitted
in the TDA8310A. Therefore, the circuit contains an input signal selector, a PAL/NTSC colour decoder, horizontal
and vertical synchronization and an RGB/YUV switch.
The input signal selector has 2 CVBS inputs. One of the inputs can be switched between CVBS and Y/C and the
circuit can automatically detect whether the incoming signal is CVBS or Y/C. The output signals for the PIP
processor are:
•
Luminance signal
•
Colour difference signals (U and V)
•
Horizontal and vertical synchronization pulses.
•
The RGB/YUV switch can select between two RGB or YUV sources, e.g. between the PIP processor and the
SCART input signal.
•
The supply voltage for the IC is 8 V. It is available in a 52-pin SDIP package.
FUNCTIONAL DESCRIPTION
CVBS switch
The circuit contains a 2 input CVBS switch and one of the inputs can be switched between CVBS and Y/C.
The circuit contains an identification circuit which can automatically switch between the CVBS and Y/C signals.
It is also possible to force the switch to CVBS or Y/C.
TDA8310A CHROMA DECODER FOR PIP
Pagina 1 di 2
e.g. TDA8310A.doc
Synchronization circuit
The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed
level. The sync pulses are fed to the slicing stage (separator) which operates at 50% of the amplitude.
The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence
detector is used to detect whether the line oscillator is synchronized and for transmitter identification. The first
PLL has a very high static steepness this ensures that the phase of the picture is independent of the line
frequency.
The line oscillator operates at twice the line frequency. The oscillator network is internal. Because of the spread of
internal components an automatic adjustment circuit has been added to the IC.
The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in
a free-running frequency which deviates less than 2% from the typical value.
The horizontal output pulse is derived from the horizontal oscillator via a pulse shaper. The pulse width of the
output pulse is 5.4 ms, the front edge of this pulse coincides with the front edge of the sync pulse at the input.
The vertical output pulse is generated by a count-down circuit. The pulse width is approximately 380 ms. Both the
horizontal and vertical output pulses will always be available at the outputs even when no input signal is
available. In addition to the horizontal and vertical sync pulse outputs
the IC has a sandcastle pulse output which contains burst key and blanking pulses.
Integrated video filters
The circuit contains a chrominance bandpass and trap circuit. The filters are realised by gyrator circuits that are
automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. When a Y/C
signal is supplied to the input the chrominance trap is automatically switched off by the Y/C detection circuit
however, it is also possible to force the filters in the CVBS or Y/C position.
The luminance delay line is also realised by gyrator circuits.
Colour decoder
The colour decoder contains an alignment-free crystal oscillator, a colour killer circuit and colour difference
demodulators. The 90° phase shift for the reference signal is achieved internally.
The colour decoder is very flexible. Together with the SECAM decoder (TDA8395) an automatic multistandard
decoder can be designed but it is also possible to use it for one standard when only one crystal is connected to the
IC.
The decoder can be forced to one of the standards via the ‘forced mode’ pins. The crystal pins which are not used
must be connected to the positive supply line via a 8.2 κΩ resistor. It is also possible to connect the non-used pins
with one resistor to the positive supply line. In this event the resistor must have a value of 8.2 κΩ divided by the
number of pins.
The chrominance output signal of the video switch is externally available and must be used as an input signal
for the SECAM decoder.
RGB/YUV switch
The RGB/YUV switch is for switching between two RGB or YUV video sources. The outputs of the switch can be
set to high-impedance state so that other switches can be used in parallel.
The switch is controlled via pins 13 and 52.
TDA8310A CHROMA DECODER FOR PIP
Pagina 2 di 2
e.g. TDA8310A.doc
COINCIDENCE/
NOISE
DETECTOR
DECBG
DECDIG
37
35
21
VP2
19
HOUT VOUT
30
41
39
36
40
10
VCO
+
CONTROL
PHASE
DETECTOR
SAND
PULSE
SHAPER
R1
SANDCASTLE
GENERATOR
11
12
G1
B1
13
i.c.
n.c.
BLANK1
22, 29
VERTICAL
SYNC
SEPARATOR
SYNC
SEPARATOR
33, 34
14
HORIZONTAL/
VERTICAL
DIVIDER
CLAMP
8
RGB/YUV
SWITCH
7
6
DECFT
5
TDA8310A
15
1
4
2
3
CHROMINANCE
BANDPASS
CHROMINANCE
TRAP
52
FILTER
TUNING
4
32
REF
28
AUTOMATIC
Y/C
DETECTOR
31
20
17
CVBSEXT
GND2
PAL/NTSC
DECODER
INPUT
SELECTOR
CVBSINT
9
16
CHROMAI
SYSTSW
47
48
LUMINANCE
DELAY LINE
27
46
45
44
43
42
PLL
XTAL4
XTAL3
XTAL2
XTAL1
SECAM
R/W
CHROMAO
26
24
50
23
LOGIC2
LOGIC1
B Y
51
18
38
GND1
GND3
49
R
G
B
BLANK
R2
G2
B2
BLANK2
IDENT
HUE
Y
MGD128
R Y
Product specification
TDA8310A
Fig.1 Block diagram.
25
COLOUR2
COLOUR1
handbook, full pagewidth
CVBSSW
Philips Semiconductors
VP1
PH1LF
PAL/NTSC colour processor
for PIP applications
BLOCK DIAGRAM
1996 Jan 25
INTB
Philips Semiconductors
Product specification
PAL/NTSC colour processor
for PIP applications
TDA8310A
PINNING
SYMBOL
PIN
SYMBOL
DESCRIPTION
PIN
DESCRIPTION
R2
1
RED input 2 (PIP)
HUE
28
HUE control input
G2
2
GREEN input 2 (PIP)
i.c.
29
internally connected (test purposes)
B2
3
BLUE input 2 (PIP)
INTB
30
internal bias
IDENT
4
colour standard identification output
GND2
31
ground 2 (0 V)
BLANK
5
blanking output
CVBSSW
32
B
6
BLUE output
CVBS positive/negative modulation
control switch input
G
7
GREEN output
n.c.
33
not connected
R
8
RED output
n.c.
34
not connected
35
bandgap decoupling
SYSTSW
9
CVBS/system switch
DECBG
R1
10
RED input 1
VOUT
36
vertical sync output pulse
G1
11
GREEN input 1
PH1LF
37
phase 1 loop filter
B1
12
BLUE input 1
GND3
38
ground 3 (0 V)
39
horizontal sync output pulse
BLANK1
13
blanking input 1
HOUT
CLAMP
14
clamping pulse input
SAND
40
sandcastle pulse output
DECFT
15
decoupling filter tuning
VP2
41
supply voltage 2 (+8 V)
42
4.4336 MHz crystal
CHROMAI
16
chrominance input
XTAL1
CVBSEXT
17
external CVBS/Y input
XTAL2
43
3.5820 MHz crystal for PAL-N
GND1
18
ground 1 (0 V)
XTAL3
44
3.5756 MHz crystal for PAL-M
45
3.5795 MHz crystal for NTSC
46
PLL colour filter
VP1
19
supply voltage 1 (+8 V)
XTAL4
CVBSINT
20
internal CVBS input
PLL
DECDIG
21
decoupling digital supply rail
CHROMAO
47
chrominance output for TDA8395
48
SECAM reference output
i.c.
22
internally connected (test purposes)
SECAM
LOGIC2
23
crystal logic 2 input/output
Y
49
Y output
LOGIC1
24
crystal logic 1 input/output
B−Y
50
B−Y output
51
R−Y output
52
blanking/insertion input 2 (PIP)
COLOUR2
25
colour system logic 2 input/output
R−Y
COLOUR1
26
colour system logic 1 input/output
BLANK2
R/W
27
read/write selection input
1996 Jan 25
5
TDA8395
SECAM DECODER
FEATURES
• Fully integrated filters
• Alignment free
• For use with baseband delay
GENERAL DESCRIPTION
The TDA8395 is a self-calibrating, fully integrated SECAM decoder. The IC should
preferably be used in conjunction with the PAL/NTSC decoder TDA8362 or TDA8366 and
with the switched capacitor baseband delay circuit TDA4660. The IC incorporates HF and
LF filters, a demodulator and an identification circuit (luminance is not processed in this
IC). The IC needs no adjustments and very few external components are required. A
highly stable reference frequency is required for calibration and a two-level sandcastle
pulse for blanking and burst gating.
FUNCTIONAL DESCRIPTION
The TDA8395 is a self-calibrating SECAM decoder designed for use with a baseband
delay circuit.
During frame retrace a 4.433619 MHz reference frequencyis used to calibrate the filters
and the demodulator. Thereference frequency should be very stable during this period.
The Cloche filter is a gyrator-capacitor type filter theresonance frequency of which is
controlled during the calibration period and offset during scan; this ensures thecorrect
frequency during calibration.
The demodulator is a Phase-Locked Loop (PLL) type demodulator which uses the
frequency reference and the bandgap reference to force the PLL to the required
demodulation characteristic.
The low frequency de-emphasis is matched to the PLL and is controlled by the tuning
voltage of the PLL.
Secam secoder TDA8395
Pagina 1 di 2
e.g. TDA8395R
Philips Semiconductors
Preliminary specification
SECAM decoder
TDA8395
Fig.1 Block diagram.
PINNING
SYMBOL
Fig.2 Pin configuration
October 1991
3
PIN
DESCRIPTION
fref/ IDENT
1
reference frequency
input/identification input
TEST
2
test output
VP
3
positive supply voltage
n.c.
4
not connected
n.c.
5
not connected
GND
6
ground
CLOCHEref
7
Cloche reference filter
PLLref
8
PLL reference
−(R−Y)
9
−(R−Y) output
−(B−Y)
10
−(B−Y) output
n.c.
11
not connected
n.c.
12
not connected
n.c.
13
not connected
n.c.
14
not connected
SAND
15
sandcastle pulse input
CVBS
16
video (chrominance) input
A digital identification circuit scans the incoming signal for SECAM (only line-identification
is implemented). The identification circuit needs to communicate with theTDA8362 to
guarantee that the output signal from the decoder is only available when no PAL signal
has been identified. If a SECAM signal is decoded a request for colour-on is transmitted to
pin 1 (current is sunk). If the signal request is granted (i.e. pin 1 is HIGH therefore no
PAL) the colour difference outputs (-(Β-Y) and -(Ρ-Y)) from the TDA8362 are high
impedance and the output signals from the TDA8395 are switched ON. If no SECAM
signal is decoded during a two-frame period the demodulator will be initialized before
another attempt is made also during a two-frame period. The CD outputs will be blanked or
high-impedance depending on the logic level at pin 1.
A two-level sandcastle pulse generates the required blanking periods and, also, clocks the
digital identification pulse on the falling edge of the burst gate pulse. To enable The
calibration period to be defined the vertical retrace is discriminated from the horizontal
retrace, this is achieved by measuring the width of the blanking period.
Secam secoder TDA8395
Pagina 2 di 2
e.g. TDA8395R
TEA6415C
BUS-CONTROLLED VIDEO MATRIX SWITCH
DESCRIPTION
•
20MHz BANDWIDTH
•
CASCADABLE WITH ANOTHER TEA6415C (INTERNAL ADDRESS CAN BE
CHANGED BY PIN 7VOLTAGE)
•
INPUTS (CVBS, RGB, MAC, CHROMA, ...)
•
POSSIBILITY OF MAC OR CHROMA SIGNAL
•
FOR EACH INPUT BY SWITCHING-OFF THE
•
CLAMP WITH AN EXTERNAL RESISTOR BRIDGE
•
BUS CONTROLLED
•
6.5dB GAIN BETWEEN ANY INPUT AND OUT-PUT
•
-55dB CROSSTALK AT 5MHz
•
FULLY ESD PROTECTED
GENERALDESCRIPTION
The mainfunctionof the IC is to switch 8 video input sources on 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the
lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB
signals).
Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal
the align-ment is switched off by forcing, with an external resistor bridge, 5 VDC on the
input. Each input can be used as a normal input or as a MAC or Chroma input (with
external resistor bridge). All the switch-ing possibilities are changed through the BUS.
Driving 75Ω load needs an external transistor. It is possible to have the same input
connected to several outputs.
The starting configuration upon power on (power supply : 0 to 10V) is undetermined. In
this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1
word of 16 bits is necessary to determine one configura-tion
TEA6415C video matrix switch
Pagina 1 di 1
e.g. TEA6415C.doc
TDA4665
Baseband delay line
FEATURES
• Two comb filters, using the switched-capacitor technique, for one line delay time (64 ms)
• Adjustment-free application
• No crosstalk between SECAM colour carriers (diaphoty)
• Handles negative or positive colour-difference input signals
• Clamping of AC-coupled input signals (±(Ρ-Y) and ±(Β-Y))
• VCO without external components
• 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle
pulse (64 ms line)
• Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal
• Addition of delayed and non-delayed output signals
• Output buffer amplifiers
• Comb filtering functions for NTSC colour-difference signals to suppress cross-colour
GENERAL DESCRIPTION
The TDA4665 is an integrated baseband delay line circuit with one line delay. It is suitable
for decoders with colour-difference signal outputs ±(Ρ-Y) and ±(Β-Y).
TDA4665 Crhroma Delay line
Pagina 1 di 3
e.g.TDA4665.doc
SIGNAL
CLAMPING
SAMPLEAND-HOLD
LINE
MEMORY
colour-difference
input signals
pre-amplifiers
14
±(B−Y)
3
VP1
sandcastle
pulse input
11
LP
9
5
addition output
stages buffers
SIGNAL
CLAMPING
LINE
MEMORY
SAMPLEAND-HOLD
12
SANDCASTLE
DETECTOR
FREQUENCY
PHASE
DETECTOR
3 MHz shifting clock
DIVIDER
BY 192
6 MHz
CCO
LP
10
GND1
TDA4665
digital supply
DIVIDER
BY 2
VP2
±(B−Y)
n.c.
n.c.
n.c.
n.c.
i.c.
4, 8
GND2
MED848
Product specification
TDA4665
Fig.1 Block diagram.
2
6
13
15
7
3
1
±(R−Y)
colour-difference
output signals
LP
analog supply
Philips Semiconductors
16
±(R−Y)
Baseband delay line
BLOCK DIAGRAM
1996 Dec 17
handbook, full pagewidth
SAA55xx
Standard TV microcontrollers with On-Screen Display (OSD)
1 FEATURES
• Single-chip microcontroller with integrated On-Screen Display (OSD)
• Versions available with integrated data capture
• One Time Programmable (OTP) memory for both program Read Only Memory (ROM)
and character sets
• Single power supply: 3.0 to 3.6 V
• 5 V tolerant digital inputs and I/O
• 29 I/O lines via individual addressable controls
• Programmable I/O for push-pull, open-drain and quasi-bidirectional
• Two port lines with 8 mA sink (at <0.4 V) capability, for direct drive of Light Emitting
Diode (LED)
• Single crystal oscillator for microcontroller, OSD and data capture
• Power reduction modes: Idle and Power-down
• Byte level I 2 C-bus with dual port I/O
• Pin compatibility throughout family
• Operating temperature: -20 to +70 °C.
2 GENERAL DESCRIPTION
The SAA55xx standard family of microcontrollers are a derivative of the Philips industrystandard 80C51 microcontroller, and are intended for use as the central control
mechanism in a television receiver. They provide control functions for the television
system, OSD, and some versions include an integrated data capture and display function.
The data capture hardware has the capability of decoding and displaying both 525 and
625-line World System Teletext (WST), Video Programming System (VPS) and
Wide Screen Signalling (WSS) information. The same display hardware is used both for
Teletext and OSD, which means that the display features available give greater
flexibility to differentiate the TV set.
The SAA55xx standard family offers a range of functionality from non-text, 16-kbyte
program ROM and 256-byte Random Access Memory (RAM), to a 10-page text version,
64-kbyte program ROM and 1.2-kbyte RAM.
SDA
Main outR
60
8
IREF
AUX outR
57
9
Port 1
VSSA3
56
10
SIF2
PCAPL 55
VDDD1
R5
390
C6
470N
C7
1µ
16V
C8
10
QZ1
24,576MHZ
C9
10
+6V
C10
470N
8
12
11
10
9
A1-F
A1-L
A1-K
A1-J
A1-I
A1-E
6
A1-H
5
A1-G
C5
1000µ
10V
Sc2 outR
52
50
VSSD2
49
RESET CAP
17
VSSD4
Sc1 outL
48
18
XTAL IN
Sc1 outR
47
19
XTAL OUT
20
PORT2
I.C. 45
21
SYSCLK
I.C. 44
22
SCK
23
WS
24
SDO2
25
SDO1
VREF(N)
40
26
SOI2
VREF(P)
39
VSSA2
C22
2µ2
16V
C20
10N
R22
1K
R24
1K2
TR4
BC848
C23
2µ2
16V
TEST1
Sc2 InL
37
29
MONO IN
Sc2 InR
36
30
TEST2
31
Ex InR
Sc1 InL
34
32
Ex InL
Sc1 InR
33
R28
1K
C27
2µ2
16V
C26
470µ
35V
C28
2µ2
16V
R30
1K
C30
2N2
5
6
7
1
IC2
KIA7812
3
35
R36
C33
47µ
16V
+26V
C41
1000µ
16V
C37
2µ2
16V
C36
2µ2
16V
R38
4,7
C45
2µ2
16V
R39
4,7
C34
330N
C43
100N
15K
R37
15K
1
2
C42
1000µ
16V
C40
1000µ
16V
270
C32
470N
R32
10K
8
IC3 TDA2822M
4
3
2
R35
R31
10K
C39
100µ
16V
R34
1K8
C38
100µ
16V
R33
1K8
VDEC2 38
SDI1
R27
47K
C29
2N2
43
28
C25
2µ2
16V
C31
47µ
16V
46
27
R25
10K
R29
1K
C46
2µ2
16V
R40
2K2
C44
100N
C35
330N
R41
2K2
+26V
2
1
4
SC1/
SC2
CINCH
BB
R21
47K
R26
47K
I.C. 41
TDA 9870A
1K2
TR3
BC848
R19
10K
C21
47µ
16V
I.C. 42
VSSD3
R23
R20
47K
51
16
IC1
C19
10N
53
VSSA4
VREF2
+6V
C24
2µ2
16V
3
10
4
7
3
6
OUT
SC
5
8
CUFFIA
AP
9
1
2
A2-A
VSSD1
15
R15
1K
A2-B
14
L1
100µH
R14
1K
A2-I
R4
4,7
7
VREF3
Sc2 outL
R13
47K
A2-H
I2C addr 2
R12
47K
A2-E
SIF1
13
R9
10K
A2-F
12
R8
10K
C18
470µ
10V
PCAPR 54
100
+6V
+6V
A2-C
VREF1
12
A2-G
11
C4
100µH
C17
2µ2
16V
A2-J
C3
100N
58
C15
2µ2
16V
A2-D
C2
100N
AUX outL
R7
A1-C
10K
VDEC1
A1-D
R3
VSSA1
7
A1-A
C1
470N
1K2
L3
VDDA3 59
6
1K2
R18
TR2
BC848
Approvato:
5
100
R16
470
R17
TR1
BC848
R11
47K
R10
47K
Di Maio
61
C16
2µ2
16V
Disegnato:
Main outL
531.01S
531.00S
SCL
C14
2µ2
16V
C13
2µ2
16V
Sost.schema:
4
+6V
Cod. Schema:
62
+26V
3
06/07/1999
Line outL
2
Scala:
I2C addr1
1
Data:
3
C12
2µ2
16V
+6V
820
Stabilimento di Sessa Aurunca (CE)
63
R6
Stereo-Nicam i.c. per Telaio F19
Line outR
L2
100µH
Descr.
NICAM data
C11
470N
Industrie Formenti Italia s.p.a.
2
VDDD264
A3-C
PCLK
A1-B
R1
100
R2
1
A3-A
A3-B
S
1.531.01S
S10.135
Vi
LSW
11
R3
22K
C2
100N
L1
77,8
MHZ
24
25
C3
2µ2
16V
+8V
L7
18
100µH
+12V D1
LL103
BA682
R5
BA782
2K7
BA783
C40
1000µ
10V
+12V
+12V
R6
4K7
R7
4K7
1
FOS1
K9453
2
3
D2
LL103
BA682
BA782
BA783
5
Tpll
Vp
30
INSW
TR3
BC848
32
SIF2
VIF1
1
FOS2
K3953M
2
TR5
BF 959
L2
1µH
R35
47K
C10
100N
+6V
3
R34
390
C31
470N
C32
1µ
16V
+12V
1
3
2
+8V
C69
470µ
16V
C5
1000µ
10V
C12
1000µ
16V
C11
100N
C17
470N
R13
150
C14
1N
56
10
SIF2
PCAPL 55
11
VREF1
PCAPR54
12
SIF1
VREF3
13
I2C addr 2
QZ1
24,576MHZ
14
VSSD1
15
VDDD1
6
8
11
10
9
12
A1-I
5
A1-L
7
Sc2 outL
Sc2 outR
52
R40
47K
50
VSSD2
49
RESET CAP
VSSD4
Sc1 outL
48
18
XTAL IN
Sc1 outR
47
19
XTAL OUT
20
PORT2
21
SYSCLK
22
SCK
23
WS
24
SDO2
25
SDO1
VREF(N)
40
26
SOI2
VREF(P)
39
VREF2
46
I.C.
45
C43
10N
C44
10N
R54
R45
47K
R61
10K
1K2
R46
47K
R47
1K
R55
C45
47µ
16V
1K2
R48
47K
C42
2µ2
16V
R62
10K
C56
2µ2
16V
TR12
BC848
R49
47K
R50
1K
C47
47µ
16V
C64
2N2
SDI1
28
TEST1
Sc2 InL
37
29
MONO IN
Sc2 InR
36
30
TEST2
31
Ex InR
Sc1 InL
34
Ex InL
Sc1 InR
33
C46
470µ
35V
C59
2µ2
16V
C65
2N2
5
IC4
6
7
TDA2822M
8
4
3
1
2
VDEC238
35
R59
2
1
+26V
C68
1000µ
16V
C50
47µ
16V
C54
2µ2
16V
C55
2µ2
16V
R70
4,7
C60
2µ2
16V
R69
4,7
C52
330N
C33
100N
15K
R60
15K
R66
10K
C62
1000µ
16V
C63
1000µ
16V
270
C51
470N
R65
10K
IC5
KIA7812
3
R58
R64
1K
C66
100µ
16V
R67
1K8
C67
100µ
16V
R68
1K8
43
27
C58
2µ2
16V
R63
1K
I.C. 41
TDA 9875
R43
1K
TR11
BC848
C41
2µ2
16V
I.C. 42
VSSD3
R42
1K
+6V
I.C. 44
VSSA2
R41
47K
2
R72
2K2
C35
100N
C53
330N
C61
2µ2
16V
R73
2K2
+26V
1
4
3
10
4
7
3
6
OUT
SC
5
8
CUFFIA
AP
9
1
2
Sost.schema:
Approvato:
511.05S
511.04S
Cod. Schema:
A3-B
A3-C
R56
10K
C57
2µ2
16V
SC1/
SC2
CINCH
BB
R57
10K
C15
470µ
10V
51
VSSA4
17
IC3
+6V
53
16
32
A1-J
R18
1K
A1-K
R16
120
57
VSSA3
12
4
A1-F
R15
120
AUX outR
Port 1
5
A1-H
C13
1N
L5
100µH
IC2
L78M08CS
A1-E
R14
47
R27
47K
47K
A1-G
1K
R33
4,7
C34
10
R12
TR4
BF 959
IREF
9
+6V 100
C36
10
1
8
C30
C26
1µ
16V
3
2
R25
12K
C25
100N
AUX outL
R9
R10
22
R17
3K9
C22 C24
100N 100N
4
C29
100N
R28
47K
5
VIF2
+12V
R11
100
R24
IC1
TDA 9811
4
47K
C9
100N
Cbl
R23
47K
TR8
BC848
100
C21
100N
C28
100N
R79
10K
C23
100N
6
SIF1
1N
R8
VIF4
47K
C19
100N
C20
2µ2
16V
7
10K
R26
10K
1K
9
31
C8
TR2
BC848
TAdj
VIF3
29
22K
R31
2K7
C7
1N
R4
CsAgc8
CvAgc
28
C6
10N
VCO2
GND
27
R74
STD
Cref
26
C4
2µ2
16V
VCO1
TR7
BC848
VDEC1
100µH
A2-F
C1
1µ
16V
R20
22K
C27
470N
R32
R22
C18
100N
R21
CVBS10
AFC
23
22K
C73
10n
58
C48
2µ2
16V
Di Maio
22
R19
1K
VSSA1
7
C39
2µ2
16V
Disegnato:
12
VDDA359
6
R44
05/07/2000
VoAf
R71
1K
1K2
L4
A2-C
R2
Vo
60
A2-G
R36
270
21
Main outR
Data:
13
SDA
Scala:
NC
5
100
1K2
R53
TR10
BC848
Stabilimento di Sessa Aurunca (CE)
VoQss
61
Stereo-Nicam per Telaio F19
20
270
Main outL
TR9
BC848
R39
47K
R38
47K
Descr.
14
SCL
C49
2µ2
16V
Industrie Formenti Italia s.p.a.
NC
4
C38
2µ2
16V
C71
2µ2
16V
R51
470
R52
A2-A
TAGC
100
R30
+26V
+6V
A2-B
19
TR6
BC848
62
3
A2-I
15
Line outL
2
A2-H
NC
I2C addr1
1
A2-J
R76
1K5
R1
220
NC
3
C70
2µ2
16V
A2-D
F1
TPS
6,5
18
R29
63
+6V
820
A1-C
R75
TR1
BC848
16
Line outR
R37
A1-D
L8
6.8µH
NC
NICAM data
L3
100µH
A1-A
R77
1K2
MUTE
2
C37
470N
A1-B
C72
220µ
16V
17
PCLK
A2-E
+12V
R78
100
VDDD264
1
A3-A
S
1.511.05S
1.511.05S
TOP SILK
C5
C48
J5
C49
C55
C71
R29
C39
L3
R44
C54
C45
C42
C41
R60
C38
C70
R37
J4
R59
C47
R30
C53
C52
C56
C57
J6
A3
C51
C15
L4
R33
C50
IC2
J10
C40
C3
C69
C46
J9
R74
L7
IC3
L5
C66
L1
C4
C12
C1
F1
FOS1
QZ1
C67
C17
L8
C68
IC4
C58
C32
J8
L2
TR4
FOS2
IC1
C63
1
A1
C60
J7
TR5
J2
C59
R28
C26
C20
12
R20
C72
IC5
C62
1
A2
J3
C61
10
S50.115.1
.CELE.TOB
1
2
3
4
5
6
7
8
9
10
12
11
SOLO PER SINTESI DI TENSIONE
SOLO PER SINTESI DI FREQUENZA
SOLO PER MONO
SOLO PER MONO BG
H
Status
PIP
R167
+5V
15K
5
BLUE
JS100
R158
1K
R189
330
CORB
29
RED
34
TR101
BC848
R187
270
R508
1K2
R165
15K
J35
R173
1K
C111
100n
R119
820
CVBS1
R114
+5V
C109
100n
D102
1N4148
H 2Vpp
J148
R145
24K
I ref
15K
X5
15K
15K
+5V
H.Sync
36
FRAME
27
D108
1N4148
R107
H 5,6Vpp
V.Sync
37
X out
42
QZ100
12MHZ
+3V3
R105
C103
18
1
X in
41
D105
ZPD
2V4
R176
C101
470n
10K
R178
R191
4K7
D106
1N4148
10K
X gnd
J120
J121
J123
J127VDDP
C102
18
RESET
D
R106
+3V3
OSCILLATOR
80C51
MICROCONTROLLER
VDDC
39
DATA
C104
100µ
10V
1
50
MSDA
R100
49
MSCL
R101
52
SW 16/9
TR8
BC
547B
R40
560
+3V3
TR7
BC
547B
C
D5
ZPD
2V7
+5VSTBY
VSSA
22
SCL1
46
48
A13-A
A13-B
A13-C
A13-D
A13-J
A13-F
A13-H
A13-E
TUN
5
AGC
2
C501
330n
9
R502
33K
C500
100n
+5V
1
8
TR502
BC858
C502
330N
+5V
J5
12K
D104
C231
47µ
16V
R506
10K
C505
100n
X7
+5V
C551
470µ
10V
C550
100n
JS502
R511
4K7
7
R501
12K
C504
100n
IF2
+5V
6
1N4148
IR
J149
470
L201
BV53
-106
2
3
A14-A
A14-B
5
2
F203
K3953
JS501
R510
390
C6
C7
2n2
150µ
400V 400V
680
R261
18K
C232
1µ
16V
B
X2
FUS1
T2AH
250V
L2
47MH
C9
680N
400V
DEGAUSS
L1
47MH
1 2
H 500Vpp
3
C2
4n7
500V
L3
D1
1N4007
BV53-117
2*47MH
D3
R3
4K7
C3
4n7
500V
D2
1N4007
R1
R4
47
10n
250V
PTC1
L4
7
8
4
3
2
1
IC1 TDA 4605
L5
C32
100
R12
820
LIVE AREA
COMPONENTI SOTTO RETE
R10 C11
4K7 4n7
R11
220
ADJ.
54
IF AGC
53
VIDEO
AMPLIFIER
TOP
7
SDA
8
2
3
+8V5
+12V
I2C BUS
TRANSCEIVER
TR105
BC 548B
PIP
+12V
12
A7
R181
10K
11
TR109
BC 548B
10
9
A5
8
7
6
5
C223 C222
100n 100µ
10V
TR208
BC 548B
R238
R226
470K
3
2
1
3
2
15
4
JS1
+148V
JS6
+128V
C220
100n
QZ202
3,58205
TR206
BFS 19
QZ201
4,43
C24
100n
C21
330
500V
C19
100n
250V
C219 18
1N4148
9
1
C22
C23
6
2
3
R19
4K7
C25
2200µ
35V
4
R20
4K7
TDA 8138
5
6
7
8
9
C30
1000µ
25V
1 2 3
C16
1µ
63V
J92
J94
R23
10K
J48
J74
3 2
JS10
C29
1000µ
16V
R26
4K7
R27
1K
TR2
BC 548B
R29
4K7
R28
J103
Non inserire con modulo zero power
Solo con modulo zero power
X3
220
TR5
BC 548B
J12
J55
J96
J105
J106
SVHS-C
23
Rin
24
Gin
25
Bin
26
FBlank
46
50
Sand.
G
R51
J134
33K
3
X4
+5VSTBY
5
6
TR6
BC 638
J112
J128
7
+5V
3K3
16V
R66
10K
IC5
TDA 8351
R22 47K
47K
C82
100µ
25V
BL.Curr.
19
Blue
R215
20
Green
100
R216
21
Red
43
R SC in
L SC in
+12V
GND
L.SC OUT
R.SC OUT
1
2
2
C276
100
D200
ZPD
3
3
8V2
4
4
5
5
6
6
100
R217
12 11 4 3 5
C55 C52
220n 470µ
50V
R53
270
R58
22
V 45Vpp
4K7
+28V STBY
R75
56
C78
150n
100V
R76 R77 R94
820 820 820
220
H 8Vpp
A3
R266
220
1
1,5
RED 6
VERT.
YOKE
C80
10µ
100V
C269
1n
2
3
4
5
6
3
6
VIDEO IN
20
4
5
9
13
14
17
C270 C271
1n
1n
15
11
D
7
BLNK
16
R37
47K
BA 157
R34
12K
C81
680n
D28
R38
BA 157
47K
R91
R90
150K
150K
D23
R80
C68
10n
V 12Vpp
R67
R70
82K
0,1
J57
TR12
BUK474
200A
C72
1µ
350V
200V
6V3
R87
C61
100n
250V
L20
D24
BY228
1,5KV
C73
1µ
250V
D26
BA 157
C70
C71
2n2
1µ
1,6KV 100V
2
A3
R85 10
5W
L26
1,2mH
D25
BA 157
3
L25
610µH
J56
J130
* *
1
2
3
3
2
1
J67
C75
* MOUNTED L25
OR L26
9
10
12
11
14
13
15
1K
27
680
3
D607
ZPD
9V1
H 100Vpp
68K
R605
1K
R606
1K
D602
1N4148
D600
1N4148
C615
100
A601-A
D611
BAV103
R612
C613
1K
220
R611
C612
1K
220
R610
C611
1K
220
D604
1N4148
D603
1N4148
R618
R617
3
R616
2
R620 120K
R619
100
11
B
6
G
8
R
0
10
R621
C607
2µ2
250V
R624
C605
100n
250V
1M
C609
10µ
100V
R625
18K
1
2
5
7
3
C608
100n
250V
D608
1N4004
X12
C610
2n2
1KV
EAT
R627
470K
A600-C
X10
G2
1
8
2
B
1
R626
1K8
BF 422
C606
2µ2
250V
9
110
10M
TR600
FOC
3
R86
0,1
A
5
T3
D52
BA
157
R55
0,1
R35
12K
Industrie Formenti Italia s.p.a.
Stabilimento di Sessa Aurunca (CE)
H 150Vpp
Descr.
75
D51
Data:
R41
75
BA 157
Scala:
8
1
1K8
1K8
1K8
D606
1N4148
R623
560
100
C614
2n2
1KV
D605
1N4148
D610
BAV103
D609
BAV103
R622
560
R628
D601
1N4148
R629
82
C601 C600
100n 47µ
16V
C77
150n
C
2
H 100Vpp
68K
R42
7
1
H 100Vpp
6
C76
680n
250V
H 60Vpp
8
R89
0,1
5n6
400V
1
TS
STV 5112
7
68K
R604
1K
EAT
1
7
6
82
R600
9
R64
0,1
5
R615
R603
10
J26
4
22
A601-C
FOC
100µH
3
3
1
2
2
0,39
L23
R84
39
+148V/128V
110MH 3
C69
22n
400V
C74
J68 10µ
250V
L24
BV53
-120
H 1200Vpp
A4
SC1
R250
75
R614
12
3
D27
BA 157
1
A601-D
R247
100
R613
G2
C79
100n
400V
A3
4
A601-B
L22
BV52-105
BV52-109
R83
15K
R82
15K
J1
J59
J70
J104
47
H 12Vpp
TR15
BC 639
C67
2µ2
100V
R61
D22
R78
10K
BA 157 10K
R81
1K2
TR16
BU 508D
3
+12V 1
47n
0,1
4
CUT
OFF 2
JS12
R59
39K
GND
R246
100
A11
TELAIO BASE F19
12/09/2000
Cod. Schema:
Disegnato:
1
R249
100
1
2
LEFT IN
BLUE IN
R602 680
C604
BLUE
R36
47K
5
A601-E
J73
V 1Vpp
4
R253 560
LEFT OUT
GREEN IN
R601 680
C603
GREEN 5
BA 157
C266
2µ2
100V
D21
5,6 µH
BV53-130
2
R69
82K
A3
J7
19
RIGHT IN
RED IN
6
A601-F
H 70Vpp
D202
C224
100n
L21
BA 157
J69
10µ
16V
RIGHT OUT
R284 220
IC600
H 2Vpp
H 2Vpp
C226
1µ
16V
4
C66
4n7
H 40Vpp
3
C58
22n
R92
22K
R79
3
J85 R60
V 11Vpp
R57
4,7
T2
C65
470µ
35V
TR207
BC 338-40
C260
C268
1n
1
C602
H 2Vpp
J46
Digi DEC
IC204
TDA 8844
R93
7 6 9 10 1
A9
C50
J83
2 8
PIP
R220
15K
Phi-1
C227
4n7
39
+12V
J66
R251 560
R245
100
1
R243
2nd LOOP
+
HOR. OUT
D50
1N4148
R254 560
10µ
16V
TO RGB
J50
C253
1000µ
16V
R281 10K
C234
2n2
42
D53
1N4148
R252 560
10µ
16V
C297
D201
Beam Current
EWGEOMETRY
D204
1N4148
R73
47K
R68
390
C57
220n
+8V5
R56
1,8
C56
10n
9
R21
C51
2200µ
25V
V 5Vpp
C54
22n
C59
100µ
25V
8
X14X6
+8V
R71
2K2
4
C27
1000µ
10V
+8V
1N4148
TR11
BC858
R50
1
2
J131
J132
C62
6n8
10µ
16V
C258
FB
10K
J147
D20
J71
+12V
C294
R283 220
H 27Vpp
68n
J39
8
VIDEO OUT
R282 220
H 120Vpp
C53
AV
R230 47
J60
H 8Vpp
+8V
18
H 2,5Vpp
B
R88
J82
21
E
C238
1000µ
16V
TR204
BC848
J34
R
22n
CH1
VIDEO IN
R268
75
J110
2n2
22n
C211 22n
18
22
CONTR.BRIG.
27K
R65
1K
C216
47n
J18
R43
41
J28
8
R213
150
C208
47n
H/V
DIVIDER
VERT. SYNC
SEPARATOR
45
6 7
J10
R210
1K
100
40
H. out
INTER.
+6V
C210
CH2
AUDIO
LEFT IN
C293
1n
3
J109
R232
1K
R214
75
4K7
R221
100
Phi-2
C212
RIGHT IN
IC200-C
100n
C209
VCO +
CONTROL
VERTICAL
GEOMETRY
68
+8V
1
JS11
C31
1000µ
10V
SYNC SEP.
+
1st LOOP
47
EHT
C225
2n2
10
J32
5
J41
R231
75
1K
TR202
BC848
J61
C239
10µ
16V
12
13
IC200-A
9
F
CH3
AUDIO
C263
1n
IC200-D
C244
100n
11
C241
1000µ
10V
X8
A12
330
500V
D12
BYW95A
WHITE P.
51
VdriveB
R275
33K
AvlCap
EW-drive
R280
10K
VdriveA
C204
C240
10µ
16V
J27
J23
14
16
+12V
TR203
BC 548B
R228
J42
IC202
L78M08CS
TR3
BC848
C28
1000µ
16V
C26
100n
+8V
J79
+
OUTPUT
HUE
J37
100K
CVBS input
52
V Iref
R54
+27,8V
J88
R24
2K2
330
500V
C60
+28V STBY
TR4
TIP 115
R25
2K2
R15 4M7
C17
2n2
400V
R276
+8V
C228
1n
RGB CONTROL
SECAM
DECODER
34
Vsawtooth
R270
39K 2%
17
2
1
IC200-B
+12V
C201
18
C300
82
C298
10µ
16V
+12V
BLACKCURRENT
STABILISER
PAL/NTSC
QZ200
3,57954
MHZ
V 3Vpp
CVBS1 out
C299
10µ
16V
4
+8V
R206
1K
R205
330
SC2
R229
1K
BC858
C213
H 1Vpp
1K
F201
4,5-6,5
TR201
1
J78
FILTER
TUNING
REF
35
XTAL 3,57
J51
C217 TR205
22n
BFS 19
+148V/128V
C20
100µ
250V
D11
BYV95C
R14
2K2
18
C252
100n
0,1
R18
0,1
16
JS200
47K
J93
IC10
R17
16
C205
36
33
SecPllDec
XTAL 4,43
-3,58
38
L205
6,8µH
CHROMA TRAP
+
BANDPASS
37
Chroma Ref
C235
10µ
16V
RIGHT OUT
560
BAT 81
BASE BAND REF
DELAY LINE
Colour PLL
R207
100K
J36
J65
C218
22n
BLACK STRETCH
RGB MATRIX
RGB1 INPUT
SW
29
VCC
C215
220n
J84
C18
330
500V
LUMA DELAY
PEAKING
CORING
A10
47K
ONLY FOR
AUTOMATIC
TESTING
D9
BYV95C
D10
BYV95C
10
C15
4n7
1
C221 3N3
+8V
0,1
8
28
30
R263
47K
+8V
R227
F200
5,5
TR200
BC848
1000µ
10V
CVBS int
+8V
+8V
J43
13
C277 R269
100n 47K
L206
3,3µH
R201
1K
R259
2K7
11 SVHS-Y
CD MATRIX
SAT CONTROL
BLUE STRETCH
SKIN TINT CORR
32
Y out
R-Y out
C243 C262
470 470
15K
R16
3
2
R225
470K
V 1,8Vpp
12
R13
3K9
4
R211
0
CVBS
SWITCH
VIDEO
IDENT
R264
47K
100K
R209 390
R212
75
C206
2µ2
16V
VIDEO out
C207
100n
CVBS -Y/C
SWITCH
CTI - 16:9
47K
5
4
31
R-Y in
R236
470K
J54
R175
+5VSTBY
IDENT
J64
4,7
R237
27
B-Y out
JS3
+12V
R219
+8V
Y in
B-Y in
C236
100
C254
10µ
16V
G
3
4
R255
+12V
11
R240
R208
330
680
TR210
BC848
Bandgap
C203
100N
6
H 1,4Vpp
JS2
J77
4
5
6
R152
R6
47
R7
H 1Vpp
9
J40
LEFT OUT
560
C250
1000µ
16V
15
TR209
BC 548B
R242
19
IC200
HEF4053
+12V
R528
100
+8V
560
R241
10K
R256
R279
330
C273
1n
10
J17
TR525
BC848
R239
F576
C576
VIDEO
MUTE
R262
47K
J15
R265
47K
68
R578
390
CONTROL DAC
1x8 BITs
14x6 BITs
1x4 BITs
SAT
H 1Vpp
JS203
J49
VIDEO OUT
J6
+12V
J13
R525
47
R527
1K
H 2,5Vpp
44
SCL
+12V
C265
100µ
16V
C237
100
R233
47
C272
1n
6
10
12
2 A15-B
TR212
BC848
JS8
S.DEC
GND
10
R235 C251
1K5 100N
R526
330
C233
10µ
16V
F575
1 A15-A
C255
10µ
16V
C278
100N
20
5
9
13
17
18
14
R248
100
15
JS9
R530
4K7
R303
47K
+12V
R278
12K
11
2
C257
10µ
16V
C274 C275
1n
1n
R277
47K
14
R531
4K7
C292
10µ
16V
De Emph.
1 SIF
POL
JS4
+5V
1
J119
11
4,7
14
LIMITER
AGC FOR
IF + TUNER
C230
2µ2
16V
J141
J98
D8
R32
100K
390K
R9
560K
PLL FM
DEMOD.
16V
6
VIDEO IN
J8
16
17
J9
120
C264
3n3
56
VIDEO
MUTE
R260
330
J97
R180
100K
10K
6
55
SOUND MUTE
SOUND
PRE AMP
+MUTE
VIDEO IF
AMPLIFIER
+ PLL DEMOD.
C248
10µ
9
R285
TR216
BC 548B
J19
5
20
19
18
J4
R301
18K
C577
1µ
EXT.S.in
7
J2
R304
47K
BC 548B
8
12
13
JS202
+12V
IC201
LA7955
4
2
LEFT IN
R271
150
C280
100n
1
3
C256
10µ
16V
R286
120
JS201
0,5Vpp
C246
10µ
16V
C245
10µ
16V
JS526
AFC
Tuner AGC
C242
100n
J3
J20
R148
C14
470
2000V
R5
1N4148
C10
220n
5
R8
C1
D7
BYV95C
TR1
STH7N90FI
D6
C8
47µ
D13
25V BA157
C5
4n7
500V
1
A
R33
4,7
150K
D4
2
A2
H 10Vpp
1N4007 1N4007
C4
4n7
500V
X1
C12
33n
630V
R2
68K
A6
TR217
BC 548B
+12VTR215 J21
2
JS7
R274
12K
J24
R307
1K
SW.
R272
560
C279
100n
8
RIGHT IN
R257 560
150
C247
R287
10µ
100
16V
JS525
C291
10µ
16V
VOL.
48
IF
TR220
BC848
T1
1
TASTO1
C288
330n
R308
4K7
SWITCH
+
VOLUME
10µ
16V
TR211
BC848
R258 560
J25
R244
8
R302
15
C249
R273
47K
R314
560
47K
J44
J144
MOUNTED
JS1 OR JS6
R30 R31
330K 330K
7
49
IF
4
3
R224
C229
1n
3
2
2
JS500
+8V
R147
R182
12K
4
6
3
IC101
ST24C04CB
1
5
AV
10µ
16V
2
R288
150
C286 C287
4µ7
4µ7
J16
+5VSTBY
1
4
4
5
GND
R156
10K
R127 5K6
6
3
16V
1
+12V
+12V
5
390
1
1µH
+12V
47K
7
2
AFC
C214
100n
IF1
10 11
11
J75
R305
1K
PLL IF
5
J22
2
3
1,5Vpp
S.T.
H 1,4Vpp
+5VSTBY
8
1
1
9
R306
1K5
R577
4K7
J99
R155
100K
J137
10
12 Supply
IRR100
R151
D109
1N4148
11
J45
AUDIO out
12
10µ
16V
C261
J146
C296
100n
R203 100
+5VSTBY
TIMER/
Ctrs
~
R313
100K
4
IC203
L7806CV
J62
TR219
BC848
8K2
R575
4K7
R202 100
J14
Vcc
GND
4K7
12
IC102 TDA 9830
16V
C267 D203
10µ
ZTK
100V 33B
KEY1-E
P+
J135
13
5
4K7
R552
100
14
J72
R309
R551
100
15
R295 C284
120 1n
IF1
R223
2K7
AM/FM IN
IF1
SCL
SW TV/AV
SDA
+12V
GND
EX.L. OUT
GND
IF2
J76
R126 5K6
SDA1
230V
A1
4
C503
100n
TR503
BC858
C100
68n
IC100
SAA5553M3
R292
120
C290
330n
16
TR218
BC848
47K
R311
+5V +5V
4
3
R310
3
+8V5
J89
C289
100n
2
BA 682
R312
2K7
6
J30
J38
+12V
F204
L9454M
C295
100n
R289
1K
RIGHT
100
LED1
13
C107
100µ
10V
+33V AGC
2K2
15K
+5V
COL.AUT.
28
A400-C
KEY1-D
P-
100
J117J136
INTO
PORT 1
DRAM
3K TO 28K
VPE
SDA
VHIGH VLOW
3
R154
15K
R104
VSSC
SCL
KEY1-C
ANA+
SW AM/FM
47
31
C150
100n
+5VSTBY
UHF
TR501
BC858
KEY1-B
SEL
100
R153
51 SW.XTAL
R39
1K
A400-D
C407
1n
R267
+5V
47K
SRAM
256 Bytes
VDDA
R504
KEY1-A
ANA-
R164
C105
100n
C106
100µ
10V
C406
1n
R512
4K7
+5V
45
R113
+5V
+5VSTBY
ROM
16K TO 128K
1
+3V3
4
3
+5V
R171 R170
5K6 5K6
+5VSTBY
ADDRESS
C285
R294
47
1K
43
38
L400
47MH
35V
BA 682
D206
1n
TR214
BF 959
150
1
R115
I2C
44
VSSP
J100 C402
2200µ
R503
4K7
2K2
19 ON/OFF
40
D107
1N4148
TR108
BC 548B
2K2
8
9
10
100
J133
V 5Vpp
R505
J107
6
7
100
R116
16 KEY0 J124
R296
1K
R293
R200
J108
3
4
5
R117
1K
C281
1n
H1
PLL
1
2
R118
17 KEY1 J125
DISPLAY
TIMING
TR213
BF 959
R300
2K7
8
J33
+12V
R299
2K7
D205
L480
47µH
C413
22n
ADD
PORT 0
100
R144
22K
R290
2K7
+12V
R298
4K7
100 L207
1µH
J47
J86
22K
J140
JS451
R297
J95
R123 R121 R122
18 KEY2 J126
JS490
+12V
R291
47
C283 C282
100µ 100n
16V
8
7
2
3
4
5
J139
R491 82
+12V
LEFT
TR575
BC848
25
S.FILTER
A400-B
J29
J53
J138 1
L481
47µH
R490 82
TR107
BC848
R160
100K
J111
VHF-H
ACQUISITION
TIMING
26
JS13
R576
4K7
R513
DATA
SLICER
24
C405
1n
A400-A
10K
R159
21 VHF-L
23
CVBS0
C110
100n
J63
E
TELETEXT
ACQUISITION
H 2,5Vpp
J122
1
2
R425
82
C404
1n
9
J31
L401
47MH
R424
82
R161
14 UHF
20
C484
2µ2
100V
7
C575
220µ
25V
+5V
PAGE
RAM
R192
680
1
C451
2200µ
35V
R402
8,2
C450
22n
TEXT
INTERFACE
35
BLNK
0
10
1
+12V
+5V
15 SW TV/AV
R163
2
+27,8V
47K
1N4148
3
R507
220K
R188
330
D103
4
TR500
BC 550C
R509
5K6
R162
1K
2
C495
1n
R450
8,2
C482 C481 C483
2200µ 2200µ 68n
35V
35V
X13
C506
100
D
I
S
P
L
A
Y
3
J102
C400
100n
+5V
+5V
Voltage
1 Tuning
4
JS450
J90
R131
15K
R172
2K7
33
10
J91
+27,8V
J87
15K
0
5
IC400
TDA1521A
TDA2613
+5V
+5V
GREEN
R186
270
J52
15K
R128
DSC
R157
1K
R190
330
+5V
R174
0
Status
Formato
32
2
TR102
BC848
+5V
JS104
JS102
0
R150
270
6
J101
J114
4 CTI
11
15K
TR103
BC848
7
C401
220µ
25V
J142
Status
Status
Cuffia
8
C454
1n
PORT 2
JS105
R146
+5V
F
30
9
C496
2µ2
100V
R166
15K
SWITCH
L/L"
6
+12V
R169
100K
+5V
3
5
J145
PORT 3
12
3° SYS
8
TR110
BC848
R168
47K
R184
100K
9
47K
R177
15K
R179
7
C259
+12V +12V
A600-B
R185
10K
+5V
A8
A600-A
+5V
J118
TR111
BC 548B
R139
15K
8 SWITCH
CINCH/SC
J116
+
ADC
100n
STEREO NICAM
+
R143
10K
R133R132
12K 12K
A13-I
10
A13-G
+5V
+5V
-
Status
AV2
+12VC113
R183
10K
R140 5K6
EX.R. OUT
SWITCH
6 SC1/SC2
21
PWM
D101
1N4148
G
R141 5K6
7 SC1 to SC2
R. AP OUT
COPY
9
R103
10K
C112
100n
+12V
-
R142
15K
J113
+5V
R137
15K
R138
15K
+26V
Status
AV1
L. AP OUT
D100
1N4148
15K
H
J115
+5V
R102
SOLO PER MONO BG/L L"
SOLO PER STEREO
SOLO PER DOPPIA SCART
SOLO CON SINGOLA SCART
9
10
11
Sost.schema:
DI MAIO
Approvato:
12
497.07B
497.06B
P-
TR600
R122
R622
R619
C607
D606
C601
D607
R629
C600
C614 R628
R600
A601
D605
C608
R617
D608
R623
R624
R625
C27
C29
D12
R19
R20
C23
ANA+
A600
P+
R121
IC5
C55
R621
C30
L2
C59
J67
C80
L25
D52
R91
150Vpp
ANAKEY1
40Vpp
12Vpp
TR12
3
X1
1Vpp
R17
C22
4
C67
C71
45Vpp
D24
R90
C69
C1
T2AH
X2
C32
D8
C16
R12
PTC1
FUS1
R55
3
GND
T1
R32
R13
A6
R18
GND
R14
R15
SC2
C82
J70 GND
J92
C54
C78
SEL
X12
D600
R615
C57
D28
C81
R70
R92
1
60Vpp
C255
1
GND
R89
D20
J57
C51
11Vpp
J56
1Vpp
D21
J46
J35
C77
C74
C261
C609
X5
C28
+12V
TR2
TR4
1,8Vpp
C50
R144
GND
C238
J41
J39
2,5Vpp
J34
C52
J32
A4
C259
A15
C610
R606
IC600
R601
R616
R614
X8
GND
GND
+12V
GND
J81
R145
J59
TR203
J22
C258
C254
C298
J25
GND
C235
J144 GND
C249
C260
R620
D604
C603 R613
D602
R602
D601
R618
C602
C606
D603
C605
R605
R26
JS11
X3
DIS1
R603
C604
+5V
STBY
D200
J28
J27
J23
CRT
C216
C299
F200
497.06B
CH1
GIALLO
VIDEO
IN
X6
+5V
J118
J110
J104
J93
+8V5
J105
J94
J120
1Vpp
C248
C257
R626
CH2
BIANCO
LEFT
IN
2,5Vpp
J122
GND
R159
J116
R142
R102
J115
J113
J109
J103
J95
J88
D201
2,5Vpp
J73
J69
J85
J84
J83
J82
J79
J106 +12V
J74
J51
RGB
C253
2,5Vpp
C250
C294
R627
CH3
ROSSO
RIGHT
IN
J119
JP3
C266
C246
TR209
F575
F576
C206
C208
C213
A9
GND
+12V
C247
C297
G2
LED1
H1
X14
+5V
+5V
TR111
DSC
R309
C267
C575
IC204
J18
C577
GND
J12
R230
SC1
X10
R104
R151
GND J133
+5V STBY
J134
J148
5,6Vpp
R190
D103
R188
R189
C31
TR5
J127
R114
X13
TR500
J112
C502
+12V
+8V5
R604
K4
A400
IRR100
K3
L401
J132
D102
TR6
5Vpp
R147
R153
J96
+5V
J76
J90
TR105
TR109
J77
IC202
JP5
C226
IC200
J6
J4
J2
C6
C406
L
J131
+5V
C104
GND
X4
+5V STBY
TR7
J128
D5
TR8
R167
R106
GND
R181
+12V
C241
TR208
QZ200
QZ201
QZ202
C222
3Vpp
C233
R527
GND
C252
F203
J72
C230
J37
TR213
C283
GND
J31
C265
J24
J19
L201
0,5Vpp
J10
GND
K1
L400
C404
C407
C405
R
C402
C451
R113
D108
D107
D106
QZ100
J117
C101
NVM
R100
R101
J30
GND
J86
J107
J108
J98
J97
J89
J91 GND
J145
R156
C481
R266
J87
R152
J64
JS13
JP4
C482
C496
C484
R105
TR108
J121
C107
D105
A5
C401
J62
J53
J66
L207
J45
TR207
8Vpp
C291
GND
+12V
TR215
C231
C232
AGC
J3
D2
L481
C501
IC10
C9
L1
L3
C4
A2
C15
R1
L5
D6
L22
C2
C8
C7
C5
TASTO1
C66
C72
J143
DEGAUSS
C11
C10
2
1
C25
C21
T2
TR15
C68
C70
R75
3
C58
T3
A3
1200Vpp
L23
A1
F19
R30
R31
TR1
C24
10Vpp
27Vpp
120Vpp
500Vpp
R84
C75
C79
C76
C65
C12
497.07B
230Vac
R87
C17
R79
D23
D7
D4
D27
C19
C20
LIVE AREA
R2
R85
GND
+8V5
J54
J52
+12V
J21
JS502
TR216
J16
J14
JP2
R504
R513
R505
+5V
R501
TR217
F204
R311
C287
+5V
J55
C286
J5
C551
R80
L4
R88
IC1
D13
R4
R33
R3
C18
D9
R77
R81
R7
D1
JS1
R9
R10
R16
R8
JS6
K5
C73
J26
R5
D3
R94
R76
R82
R11
D10
+128V
D26
R6
D22
+148V
R83
L24
12Vpp
L21
00 01 02 03 04 05
GFMAMGLASOND
J130
D11
R53
D25
GND
C61
C14
TR16
K2
L26
C3
R86
J71
D51
R64
R57
R56
D109
TUNER
L20
C56
JS10
R21
GND
J68
C239
J9
JS12
SDA
SCL
R123
R24
R25
R58
A12
C240
J47
R50
J8
J7
J49
C293
A7
A11
J60
C263
D101
D203
R243
JS450
R491
R268
+12V
L205
R240
J48
C256
J42
J50
F201
GND
J78
JS7
J40
R233
R201
J17
L206
GND
J36
LA7955
IC201
GND
J1
J43
J63
R200
C245
D100
D202
R244
D50
J75
J65
JP1
R276
J141
A10
D53
J147
J61
HEF4053
R118
R117
R116
J126
J125
J124
MICROCONTROLLER
GND
J44
J139
C106
IC100
A14
R219
L480
R224
J140
D204
R71
+5V STBY
J135
J149
IC101
J138
GND
J20
D104
JS451
JS490
SCL
SDA
TR214
R490
R425
GND
J137
J136
IC102
GND
R424
A13
GND
J38
A8
J101
J102
J100
C292
IC400
GND IC203
J146
B70.794