Download STD 7000 7605 Programmable TTL 1/0 Card USER'S MANUAL

STD 7000
7605
Programmable
TTL 1/0 Card
USER'S MANUAL
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7605
Programmable TTL I/O Card
USER'S MANUAL
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7605 TTL PROGRAMMABLE TTL I/O CARD
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TABLE OF CONTENTS
SECTION 1
Product Overview
- Block Diagram
SECTION 2
Functional Description
- General Purpose Interface
SECTION 3
Mapping
SECTION 4
Address Decoder Operation
- Changing the 7605'5 Port Address
SECTION 5
7605 Card Environmental Specifications
SECTION 6
Electrical Specifications
SECTION 7
Mechanical
SECTION 8
7605 Operating Subroutine Modules
SECTION 9
Maintenance
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0 1,
PRODUCT DATA SHEET -. 7605 PROGRAMMABLE TTL f /0 CARD
A.
PRODUCT OVERV lEW
The 7605 suppl ies four 8-bit I/O ports th.at can be programmed as input,
output, or output w·i th readback (tota 1 of 32 p rog rammabl e 1010 1 i nes) .
Port access is via
two 40-pin latched connectors with. ~025 inch
square post headers. The output lines are TTL compatible open-collector
drivers w'ith lK pullups·. These lines are ti"ed to i"nput ports! After
power-on reset, all ports are in input mode~ To use ~n output port, the
user simply wri·tes to the port 1 ines desired. The 7605 decodes 8 address
lines with provision for expansion~ An on~card jumper sY'5'tem allows the
user to map the four cons'ecut lye port addresses· occup ted by th.e 7605
anywhere in the 256 port address ~ield,
B.
PRODUCT FEATURES
...
...
...
...
...
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C.
32 I/O Lines, Each Programmable as Input, Output, or Output with Readback
User-selectable Port Address (256 port Field)
Socketed ICs
Single +5V Operation
Uses Two Latching 40-pin Headers
Input Port Loadi"ng 14 LSTTL Loads
Output can Drive 50 LSTTL Loads
BLOCK DIAGRAM
DATA eus
00.07
10EI~'
CAIIO
SELiCT
OICOOEIt
10AO'
AOOfIIISS
INPUT
~T
ALEer
OECOOEIt
A,2 .... ,
"0'
OUT"'T
~T
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SELI:T
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ot.OOtItlSS
All· ...,
SYS"ESE T'
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PIlI TTL I 0 C"'''O
'INOtC"'T,S ACTIYI LOW LOGIC
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FIGURE 1
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2.
FUNCTIONAL DESCRtPTION
The 7605 provides 32 alternating bidirectional data and ground lines, These
signal lines can be up to 10 feet (3.05H) long with proper electrical considerations. Each bidirectional line characteristic (whether input or output)
is determined by the circuit shown in the Bidi'rectiona1 1'/0 Circuit diagram .
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The output circuit capability is supplied through
an open-collector inverting driver, and a pu1lup resistor. There are no
programming constraints in the output mode; active high data is written to
the output port c~using the user interface pin to operate tn the active low
state.
Input circuit capability is provided through an inverting i'nput port buffer,
The Schmitt-trigger characteristic of the input port buffer removes noise~
induced voltage spikes from the input signal. There is one programming constraint in the input mode: active-high data cannot be written to the output
port bit that is to be used on an input port bit. This constraint is required
to disable the open-collector output drive for that bit. NOTE: On system
power-up the SYSRESET* signal clears the output port and places the output
drivers in the disabled state. Thus programming overhead is not requlred to
select the input mode of operation.
GENERAL PURPOSE INTERFACE
The 7605 is useful as
twisted pair discrete
of the I/O connectors
in electrically noisy
a genera] purpose TTL interface card. Tf=ftat cable or
wire cable assemblies are used, the ground-signal-ground
minimizes crosstalk between inter-system signal lines
environments.
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The bidirectional signal lines at the card edge connector are active-low on
both input and output. The signals are terminated with a lK pul1up resistor.
TOSTD-......-'""DATA BUS
BUFFER
+5V
7406
')
Q I - - - -....
.. 14 LSTTL
OUTPUT STROBE
RESEr _ _ _ _ _....
FROM
PORT·SELECT
DECODERS
FROM OTHER CLRCUTS
Typical Bldlrectlon.II/O Circuit
FIGURE
2
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4C)
3.
CARD ADDRESS MAPPING
The 7605 is selected by a decoded combination of address lines A2-A7. The
user chooses the card address combination by connecting one jumper wire from
SX and SY to pad matrices adjacent to U2 and U3 (see the 7605 Assembly diagram),
The 7605 is shipped mapped at hex port address 00. To map the 7605 anywhere
in the hexadecimal address range of 00 to FF, change the decoder outputs
connected to SX and SY.
4.
ADDRESS DECODER OPERATION
Refer to the schematic, Document #105778.
The 7605 uses four cascaded 74LS42 decoders (U2, U3~ U5 and u6) to decode
add ress 1 i nes AO-A7. These decoders are enab 1ed on 1y when tORQ* and '-OEXP''(
are active. The WR* signal is used to gate the select strobes from u6 that
control the output ports. The RD* signal is used to gate the select st~05es
from U5 that control the input ports.
CHANGING THE 7605's PORT ADDRESS
Refer to the Assembly diagram, Document #105779
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Locate decoders U2 and U3 (74LS42) adjacent to the STD BUS edge connector,
Each decoder device has a dual row of pads which form decoder output select
matrices. Make one (and only one) connection to each of the matrices adjacent
to U2 and U3.
The decoder jumper pads numbered as shown in Figure 3 are adjacent to the
decoder chips on the 7605. Also shown are the jumpers Cat XO and YO} which
produce hexadecimal port addresses 00,01,02 and 03, the selections made
when the card is shipped.
Sy
,I
0
sx
,I
0
U2
0
,
0
0
0
to
0
0
0
0
0
0
4
~
"
0
0
0
0
0
0
0
0
0
5
b
.,.
0
0
S
0
.,
0
U3
0
0
,
0
0
1.
3
4f
0
u4
FIGURE 3 - DECODER JUMPER PAD NUMBERING
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The I/O address mapping and jumper selection table for four addresses per
card shows where to place jumper straps to obtain any four sequential port
addresses in the hexadecimal range OO-FF. Using the lower of the 2~digit
hexadecimal addresses desired, find the most significant hexadecimal address
digit along the vertical axis, and the least significant hex digit on the
horizontal axi~. For example, port addresses 50,51,52 and 53 are obtained
by connecting jumpers at X2 and Y4.
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The only restriction ihat applies in address selection for the 7605 is that the
lower of the four port addresses (00 as shipped) must occur only at every
fourth possible addr~ss; for example, the sequence 01, 02, 03 and 04 is not
allowed by the decoder.
The pad matrices adjacent to U2 and U3
are on 0.10 inch (0. 25cm) centers,
The jumpei wires may be conveniently replaced by wi rewrap post if frequent
address selection changes are anticipated.
MOST
SIGNIFICANT
HEX ADDRESS
LEAST SIGNIFICANT HEX ADDRESS
01
1 1 2 \3
4
I I I
5
6
7
aJ9JAIs
JUMPER
SELECTION
X&Y
cl J 1F
D
E
0
xo
YO
XO
Y1
XO
Y2
XO
Y3
1
XO
Y4
XO
YS
XO
Y6
XO
Y7
Y3
2
X1
YO
X1
Y1
X1
Y2
X1
3
X1
Y4
X1
YS
X1
Y6
X1
Y7
4
X2
YO
)(2
Y1
X2
Y2
X2
Y3
5
X2
Y4
X2
YS
X2
Y6
X2
Y7
6
X3
YO
X3
Y1
X3
Y2
X3
Y3
7
X3
Y4
X3
YS
X3
Y6
X3
Y7
a
X4
YO
X4
Y1
X4
Y2
X4
Y3
9
X4
Y4
X4
YS
X4
Y6
X4
Y7
A
XS
YO
XS
Y1
XS
Y2
XS
Y3
S
XS
Y4
XS
YS
XS
Y6
X5
Y7
C
X6
YO
X6
Y1
X6
Y2
X6
Y3
D
X6
Y4
X6
YS
X6
Y6
X6
Y7
E
X7
YO
X7
Y1
X7
Y2
X7
Y3
F
X7
Y4
X7
YS
X7
Y6
X7
Y7
"-
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X
AND
Y
l/
1/0 Address Mapping And Jumper Selection Table For 4 Addresses Per Card
FIGURE 4
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---------------------------
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5.
7605 CARD ENVIRONMENTAL SPECIFICATIONS
RECOMMENDED OPERATING L1:11 TS
PARAMETER
HIN
Free Ai r Temperature
I
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Humidity
CD
CD
0
S
ABSOLUTE NON-OPERATING LlnlTS
TV?
MAX
til
25
55
95
Non-condensing
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UNITS
-40
75
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0
95
%RH
~
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6. ELECTRICAL SPECIFICATIONS
7605 GENERAL PURPOSE TTL I/O CARD ELECtRICAL TEST SPECIFICATION
RECOMMENDED OPERATING LIMITS
MNEM.
PARAMETER
ABSOLUTE NON-OPERATING LIMITS
MIN.
TYP.
MAX.
MIN.
MAX.
UNIT
Vee
Supply voltage
4.75
5.00
5.25
0.0
7.00
Volt
TA
Free air temp.
a
25
55
-40
75
C
•
USER WORST CASE ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST LIMITS
MIN
PARAMETER
£
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OL LOW LEVEL INTERFACE VOLTAGE
IOL LOW LEVEL INTERFACE CURRENT
VOH HIGH LEVEL INTERFACE VOLTAGE
10H HIGH LEVEL INTERFACE CURRENT
-.-
MAX
IUNIT
I
.70
i
j
30
I
15. 50
1 TYP
I
I
4.50
mA
I
f
&
I!
V
-3.5 I
I
V
mA
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STD BUS ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST LIMITS
PARAMETER
MIN
TVP
STO BUS INPUT LOAD
See Fi gu re
,
STD BUS OUTPUT DRIVE
See Fi gure
r.
605
ICC SUPPLY CURRENT
.&
MAX
I UNITS
840
I
I
rnA
At 2 volt
~ At 30rnA current level
~ At 0.70 Volt level.
AC ELECTRICAL CHARACTERISTICS
Must meet all requirements for TTL I/O cards timing as specified in the Series 7000
General Test Specification.
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~
7.
MECHANICAL
The 7605 is shtpped fully populated. Power dissipation can be reduced by
removing unused input or output ports by removing the ICs:
INPUT/OUTPUT PORT SELECTION
PORT NO.
FOR ONLY AN INPUT
FOR ONLY AN OUTPUT
PORT REMOVE ICs
PORT REMOVE tC
PORT 0
U7, U15, U19
u8
PORT 1
U9, U16, U20
U10
PORT 2
U11, U17, U21
U21
PORT 3
ul3, Ul8, U22
ul4
Leav i ng the input buffers in p1ace a 11 ows~ the processor to read back the
output port data to check for noise a1terati"on or to use the output port as
a data regis.ter.
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...~
;
~
CIt
CIt
C
J2 .----...-.../'\.
1 2
00
00
00
00
')0
00
,
:,~g 0
00
gg V1
gg ...
or:
00
0
00 ~
00
00
00 N
J
gg
40
7605 Allembly
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FIGURE 5
Refer to the Component Placement diagram for component pl~cement information~
The 7505 meets all STO BUS general mechanical specificationS', The 7605
requires one card S'lot in a standard STD BUS card rack. The I/Q connectors
use low-profile, masS' termination 0.25 inch square post latching connectors.
Recommended flat cable card edge connectors include 3~M part number 3417-6040-1
or equivalent.
STD/760S EDGE CONNECTOR PIN LIST
7605 USER INTERFACE CONNECTOR PIN LIST
CONNECTOR J1
PIN NUMBER
PIN NUMBER
+SV
PIN NUMBER
OUTPUT (LSTTL DRIVE)
CONNECTOR J2
SIGNAL
INPUT (LSTTL LOADS)
SIGNAL
J1-2
J2-2
PIN NUMBER
OUTPUT (LSTTL DRIVE)
-Ide
INPUT (LSTTL LOADS) '.
MNEMONIC
+SV
+5 VOLTS
GROUND
MNEMONIC
vCC
GNO
2
4
J1-4
J2-4
+SV
J1-6
J1-8
J2-6
J2-8
06
P2-S*
P2-4*
J1-10
J1-12
J2-10
J2-12
PO-7'
PO-S'
Po-so
PO-4*
04
P2-3'
J1-14
J2-14
PO-3*
16
P2-2*
J2-16
PO-2*
A13
20
P2-1'
J1-16
J1-18
A15
A14
J2-18
A12
P2-o*
J1-20
J2-20
PO-1*
Po-O'
All
22
24
""SV
+SV
J1-22
J2-22
+SV
Al0
26
J1-24
J2-24
+SV
A9
28
9
11
13
15
17
19
21
23
25
27
A8
30
29
6
07
,
55
S5
8
10
1
1
55
55
12
14
1
05
18
VCC
3
+SV
-5V
.. 5 VOLTS
GNO GROUNO
-5V
1
P2-7*
P2-6*
5
7
55
~I\
55
55
1
1
03
02
1
01
1
00
1
A7
1
A6
1
AS
1
1
A4
A3
2
2
A2
2
P3-7*
J1-26
J2-26
P1-7*
RO"
32
31
1
P3-6*
J1-28
J2-28
P1-6*
MEMRO"
34
33
P3-S*
J2-30
,J2-32
P1-S*
P1-4*
MEMEX*
36
P3-4*
J1-30
J1-32
MCSYNC*
P3-3*
J1-34
J2-34
P1-3*
STATUS 0"
38
40
35
37
1
1
BUSRO"
42
39
41
P3-2*
J1-36
P1-2'
INTRa"
44
43
P3-1*
J1-38
J2-36
J2-38
P1-1*
NMIRO"
46
45
P3-0"
J1-40
J2-40
P1-0'
PBRESET*
48
47
CNTRl"
50
49
52
51
54
56
53
55
"low level Active
All odd numbered pins go to ground
Interface Connector Pin List
4[)
1
PCI
AUX GNO
IN
AUX -v
"low level Active
A1
AO
WR"
lORa"
IOEXP"
REFRESH"
STATUS 1"
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BUSAK*
INTAK"
WAITRO*
1
OUT
SYSRESET*
CLOCK"
PCO
AUX GNO
AUX +V
,'t* Des i gnates LSTTL Loads
Edge Connector Pin List
FIGURE 6
NOTE; Vcc is provided on the user interface pins Jl and J2. These should
be used only after the system designer has thoroughly studied the system
implication. Care must be taken to avoid ground loops.
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B.
760S OPERATING SUBROUTINE MODULES
This section provides flow diagrams and subroutines to operate your 7605
card. These may be used intact, or used as models to construct subroutines
for a specific application.
The subroutines are written in BOBO-family assembly code and will execute
on BoBO, BoBS, and zBo processors. The memory addresses selected are
compatible with Pro~Logls 7B01 (BOBSA) and 7B03 (ZBO) processor cards.
The 760S port addresses used are the address jumper selections made when
the 760S is shipped.
To use these subroutines in systems other than those described above, the
memory and/or I/O port addresses may require change for compatibility,
The flow diagrams presented can be easily translated into the ass'emb1y code
used by any microprocessor since they show' the steps req.uired to achieve
760s operation without reference to a particular microprocessor~
The following subroutines are written to act only on a s.ingle bit on the
output or input ports. For routines which act on all 8 bits of a port at
the same time, see the 7604 User's Manual.
c
NAME AND DESCRIPTION
REGISTERS
CHANGED
FLOW
DIAGRAM
PROGRAM
PAGE
PAGE
START
ADDRESS
(Initialize 760S)
This subroutine sets all outputs
to a predefined state. It also
i nit i ali zes all viariables used
by the other subroutines.
A
H
L
1300
i
I
I
(Set bit)
This routine accepts a hex value
in the accumulator which corresponds to the I/O module to be
turned on. If the I/O module
number is out of range, the carry
flag will be set.
A
B
C
H
L
PAGE
PAGE
1394
I
I
(C 1ear bit)
This routine accepts a hex value
in the accumulator which corresponds to the I/O module to be
turned off. If the I/O module
number is out of range, the carry
flag will be set.
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I
A
B
C
H
L
PAGE
PAGE
l3AO
cont i nued
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NAME AND DESCRlPTtON
REGtSTERS
CHANGED
START
ADDRESS
FLOW
DIAGRAM
PROGRAM
PAGE
PAGE
13BO
PAGE
P,L\GE
1342
(Test bit)
This routi'ne accepts a hex value
in the accumulator which corresponds to the I/O module to be
tested. If the I/O module number is out of range, the carry
flag will be set. The s:ubroutrne
returns with P=O if there was no
change and P=l if the addressed
module did change since the last
test. The Z flag =0 if the bit
is set and Z=l if the input port
is clear.
A
B
H
L
C
F
(Complement a bit)
This routine accepts a hex value
in the accumulator whi'ch corresponds to the I/O module to be
complemented. If the I/O module
is out of range the carry flag
wi 11 be set.
A
B
H
L
o
C
J
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INITIALIZE 7605
INITIALIZE
OUTPUT
PORTS
tNITIALIZE
VARlABLES
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f,
J
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X4
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SET A BtT
TEST fNPUT
BIT
COMPLEMENT ItA" BIT
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CLEAR A BIT
TEST INPUT
BrT
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COMPLEMENT "A" BfT
WHICH PORT
AND BIT
MASK OFF BIT
ON PORT 00
MASK OFF BIT
ON PORT 0]
MASK OFF BIT
ON PORT 02
MASK OFF BIT
ON PORT 03
SET ERROR
COMPARE MEMORY
AND INPUT PORT
UPDATE
MEMORY
SET FLAG
()
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WHICH PORT
AND BIT
COMPLEMENT
OUTPUT 00
COMPLEMENT
OUTPUT 01
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COMPLEMENT
OUTPUT 02
SET ERROR
COMPLEMENT
OUTPUT 03
UPDATE
MEMORY
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