Download Cypress CY7C150 User's Manual

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Maximum Access Time (ns)
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12
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25
SENSE AMPS
ROW DECODER
50
Military
Maximum Operating Current (mA)
Commercial
90
Military
Cypress Semiconductor Corporation
Document #: 38-05024 Rev. **
•
3901 North First Street
•
12
15
25
35
90
90
90
90
100
100
100
100
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
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THÉVENIN EQUIVALENT
OUTPUT
Document #: 38-05024 Rev. **
125Ω
1.9V
Page 2 of 11
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W 15 .100 25 M.T 35 ns
WW tAA .100Y. Address
.TtoW
M
.100
MHold
O
W
O
WW 200Y.CO 2 .TW
W
C
t
Output
from
Address
2
2
2
ns
.
W
C
W
Y
W
W
0
W
T
.
1
0
WWOHA .100Y.Change
T
M
.
.
1
M
.
O
W
O
W
.C
OM
W
W
.CLOW
W12W .100Y
W Valid WW .100Y.8C M.TW
YCS
to.T
Data
10
15 OM.T 20
ns
0
WtW
ACS
0
1
W
M
.
O
W
O to Low Z[6]
W 0 00Y.C 0 .TW ns
W
C
.
W
C
W
.
Y
W
W
t
CS
LOW
0
0
0
W
W
.T
00
WLZCS .100Y
W.1 Y.COM W
M.T [6,7]
W.1 6Y.COM 8 W
O
W
W
W
C
tHZCS
CS
HIGH
to
High
Z
11
20
25
ns
.
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
C
Oto Data Valid
tDOE WW OE LOW
6
8
10 WW
15 Y.
20TWns
.
W
WW .100Y.C M.TW
100
0Y.C M.T[6]
W
M
.
0
O
1
W
.
O
tLZOE
OE LOW toOLow Z
0W
0
0
0
0
ns
C
.
W
W
C
W
.TW
W
00Y
Y.Cto High.ZT[6,7]
WW .6100Y.
TW
.
1
0
WW OE
M
.
0
M
tHZOE
HIGH
8
9
20
25
ns
O
WW 00Y.C
W.1 [8] Y.COM W
W
WW 00Y.CO .TW
W
T
W
.
W
1
W CYCLE.100
M
.
WRITE
.T
1
M
.
O
W
M
O
O
W
WW 0012Y.C
0Y.C M.ns
WW .1035
TW
W
Y.C
W
T15W
tWC WW Write Cycle
Time
10
25
.
0
T
.
1
0
M
.
O
1
W
M
.
O
W
C
.
O
W
.C
.C End .TW
tSCS
to Write
6WW
11
15WW
ns
.TW
00Y
.TW
120
080Y
WWCS LOW
M
.
1
00Y
M
.
O
1
W
M
.
O
W
W Set-Up toOWrite End
tAW
Address
8
20 WW
30 0Y.C
ns .TW
.C 13.TW
WW .10
10
00Y
WW .100Y.C M.TW
M
.
1
M
O
W
O 2
W2
tHA
Address
fromO
Write End
2
5
WW 5.100Y.C nsM.TW
WW Hold
W
Y.C
WW .100Y.C M.TW
0
W
T
.
0
Ons
1
W5
tSA
Address
to Write
2
2
2
5
MStart
.Set-Up
WW 00Y.CO .TW
WW .100Y.C M.TW
WW 00Y.CO .TW
W
W
tPWE
WE Pulse .Width
6
8 .1
11M
15
20
ns
WW 00Y.CO .TW
W 1 Y.COM W
.CO .TW
WW
Y
W
W
0
W
tSD
Data
Set-Up
to
Write
End
6
8
11
15
20
ns M
1
0
W
.1
W.
M.T
.100
OM
W
CO
.
O
W
W
C
.
Y
W
C
W5
W from 0Write
tHD
Data
00 ns M.TW
Y. End .TW 2
W 2 .100Y 2 M.TW 5
1
0
WHold
.
O
W
W
W.1 Z[6]Y.COM W0
W
.0CO .TW0
Yns.C
W
tLZWE
WE HIGH
0
0W
0
Y
W
0
0
W
1
0
0
WWto Low
T
M.T
.
.
1
0 [6,7]
M
.
O
1
W
M
.
O
W
C
.
O
tHZWE
WE LOW to W
High Z
6
8
12
20
WW 25 .100nsY
.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
M
O
W
RESET CYCLE
O
W
O
W
W
WW .100Y.C M.TW
0Y.C M.T
WW .1030
WWTime .100Y.C M.T20W
tRRC
Reset Cycle
24
50
70
O
WW ns00Y.CO .T
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W to Beginning
tSAR
Address Valid
0
0
0
0
M
.1ns
.0T
00 of
W.1 Y.COM W
WW 00Y.CO .T
W.1 Y.COM W
Reset
W
W
W
W
.T
00
W
.1
OM
100
Wns
M0.T
W.01 Y.COM
C
tSWER
Write Enable HIGHW
to.Beginning
0
0
0
.
O
W
Y
W
C
W
.
0
W
W
0
W
of Reset
WW .100Y
M.T
.100
W.1 Y.COM
M.T
O
W
O
W
W
C
.
W
Y 0 .TW 0
W ns .100
tSCSR
Chip Select LOW
to Beginning
0
Yof.C 0 .TW 0
W
WW
M
.100
M
.100
O
W
Reset
O
WW
W
C
.
W
C
W
.
Y
W
W
W
0
Y
W
T
.
0
0
W
.T
0
tPRS
Reset Pulse Width
15 .1
20 M
30
ns
W.1 Y.C10OM W 12
WW 00Y.CO .TW
W
W
W End of.100 0 M.T 0
tHCSR
Chip Select Hold After
0
0
0
ns
1
OM
W.
O
W
C
.
W
Reset
C
.
Y
W
W
Y
W
W
.100 30
100 8 OM.T 12
W
tHWER
Write Enable Hold After End
of.
15
40
ns
W
W
C
W
WW .100Y.
.TW
Reset
M
O
W
Y.C
tHAR
Address Hold After EndW
ofW
Reset 010
12W
15
30
40
ns
0
1
M.T
.
O
W
[6]
C
.
tLZRS
Reset HIGH to Output inW
Low
0 Y
0
0
0
0
ns
WZ
.100 6
W
tHZRS
Reset LOW to Output in
8
12
20
25
ns
WW
High Z[6,7]
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
7. tHZCS, tHZOE, tHZR, and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write.
Document #: 38-05024 Rev. **
Page 3 of 11
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
M
.1
M.T
.100
W.1 Y.COM W
WW 00Y.CO .TW
W
W
WW 00Y.CO .TW
W
.T
00
W.1 Y.COM W
M
.1
W.1 Y.COM W
O
W
W
W
C
.
W
.T
W
00
W
WW .100Y
M.T
.100
W.1 Y.COM W
M.T
O
W
CY7C150
O
W
W
C
.
W
.T
WW .100Y
.TW
100
WW .100Y.C M.TW
M
.
M
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
W
WW 00Y.CO .TW
.CO Waveforms
WW .100Y.C M.TW
W
Y
W
0
WW .1Switching
T
.
0
M
.1
OM
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
0
W
.T [9,10]
.1
W.1 Y.COM W
MNo.1
.10Read Cycle
OM
W
O
W
W
C
.
W
C
W
Y
W
.T
W
W
WW .100Y.
.100
M.T tRC
.100
OM
W
M.T
O
W
C
.
O
W
W
C
W
Y
W
WW .100Y.
.TW
0Y.C M.TW
WW .10ADDRESS
M.T
.100
M
O
W
O
W
C
.
O
W
WW .100Y
.TW
0Y.C M.TW
WW .10tAA
WW .100Y.C M.TW
M
O
W
O
O
W
WW 00Y.C
WW .100Y.C M.TW
WtOHA
.TW
WW .100Y.C M.TW
1
M
.
O
O PREVIOUS DATA VALID
WWDATA0VALID
WDATA OUT
W
Y.C
WW 00Y.CO .TW
C
.
0
W
W
W
Y
W
W
M.T
.1
.T
1
00
M
.
O
1
W
M
.
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
C150-5
O
W
O
W
C
.
O
W
W
C
W
.
Y
W
C
W
.
0
Y
W
T
W
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WW .100Y
M.
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.TW
100
M
.
O
W
M
O
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O
WW .100Y.
WW 00Y.C[9,11]
.TW
WW .100Y.C M.TW
W
M
.TW
O
1
W
M
.
Read Cycle
No.
2
W
O
W
.CO .TW
WW .100Y.C M.TW
WW t.RC
00Y
WW .100Y.C M.TW
1
M
CE
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
.T
00
W.1 Y.COM W
W.1 Y.COM W
W
W.1 Y.COM W
W
W
W
t
ACS
W
W
M.T
.100
00
M.T
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O
W
M.T
O
W
OE W.1
C
.
O
WW .100Y
.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
M
O
W
O
W
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O
W
W
W
.TW
WtDOE
00Y
WW .100Y.C M.TW
tHZCS
1
WW .100Y.C M.tT
M
.
O
W
HIGH.C
O LZOE
W
WW 00Y.CO .TW
.CIMPEDANCE
0Y
WW IMPEDANCE
WW 00HIGH
W
0
Y
W
1
W
T
M.T
.
.
1
M
.
DATA OUT
DATA
VALID
O
1
W
M
.
O
W
C
O
W
WW .100Y.
.TW
WW .100Y.C M.TW
WW .100Y.CtLZCS M.TW
M
O
W
O
W
O
W
W
Y.C
WW .100C150-6
WW .100Y.C M.TW
WW .100Y.C M.TW
M.T
O
W
O
W
C
W
.CO
WW .100Y.
.TW
WW .100Y.C M.TW
WW
M
00Y [8] M.TW
O
1
Write CycleNo.1
(WE Controlled)
W
.
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
W
O
WW 00Y.CO .TW
W
.CO .TW
tWC W
C
.
Y
W
W
W
0
Y
W
0
W
M
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.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
ADDRESS
W
W
W
.T
00
W
W.1 Y.COM
M.T t
.100
W.1 Y.COM W
O
W
W
W
C
SCS
.
W
.T
W
00
W
WW .100Y
M.T
.100
W.1 Y.COM
M.T
O
W
O
W
W
C
.
CE
W
W
WW .100Y
WW .100Y.C M.TW
M.T
.100
M.T
O
W
O
W
C
.
O
W
W
tAW
Y
W
.C
Y.C tHA .TW
W
W
WW tSA
M
.100
.TW
tPWE
100
00Y
M
.
1
W
M
.
O
W
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O
W
W
C
.
Y
W
C
W
.
0
Y
W
W
W
0
0
Y
W
.T
0
W
WE
.T
00
W.1
W.1 Y.COM W
W
W.1 Y.COM W
W
W
W
tW
SD
W
.100 tHD OM.T
M.T
.100
W
O
W
.C
W
C
W
DATAW
DATA IN
IN VALID
00Y
WW .100Y.
.TW
1
M.T
.
M
O
W
O
W
C
W
Y.
WW .100Y.C M.TW tHZWE W
100tLZWE
.
W
HIGH IMPEDANCE
.CO .TW
WW
DATA I/O
WW
DATA
UNDEFINED
W
00Y
1
M
.
O
W
WW .100Y.C M.TW
C150-7
O
W
C
.
W
Y
W
00
W.1
Notes:
W
W
9. WE is HIGH for read cycle.
10. Device is continuously selected, CS and OE = VIL.
11. Address prior to or coincident with CS transition LOW.
Document #: 38-05024 Rev. **
Page 4 of 11
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
M
.1
M.T
.100
W.1 Y.COM W
WW 00Y.CO .TW
W
W
WW 00Y.CO .TW
W
.T
00
W.1 Y.COM W
M
.1
W.1 Y.COM W
O
W
W
W
C
.
W
.T
W
00
W
WW .100Y
M.T
.100
W.1 Y.COM W
M.T
O
W
CY7C150
O
W
W
C
.
W
.T
WW .100Y
.TW
100
WW .100Y.C M.TW
M
.
M
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
0Y.C M.Waveforms
WW .10Switching
TW
O
W
(continued)
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
[8,12]
.
W
W
W
Y
W
Write
Cycle
No.
2
(CS
Controlled)
0
W
.1
W.1 Y.COM W
M.T
.10
OM tWC
W
O
W
W
C
.
W
C
W
Y
W
.T
W
W
WW .100Y.
.100
M.T
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OM
W
M.T
O
W
C
.
O
W
W
C
ADDRESS
W
Y
W
WW .100Y.
.TW
WW .100Y.C M.TW
M.T
.100
M
O
W
O
W
C
.
O
W
W
Y
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100
WW .100Y.C M.TW
M
.
O
W
O
W
O
W CE
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW tHA00Y.CO .TW
W
WW tAW00Y.CO .TW
C
.
W
W
W
Y
W
W
M
.1
.T
00
W.1 Y.COM tPWE
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
W
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W
WE
W.1 Y.COM W
M.T
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O
W
W
W
C
.
W
W
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WW .100Y
M.T
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100
M
.
O
W
M
O
W
C
O
W
Y.
HD
WtW
.TW
WW .100Y.C M.tTSDW
100
WW .100Y.C M.TW
M
.
O
W
O IN VALID
W
O
W
DATA
IN
WW .100Y.C M.TW
WW .100Y.C DATA
.TW
WW .100Y.C M.TW
M
O
WW 00Y.CO .TW
W
CO
WW 00Yt.HZWE
C
W
.
W
W
W
Y
W
T
.
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M
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00
W.1 Y.COM WHIGH IMPEDANCE
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
DATA
I/O
W
DATA UNDEFINED
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W
.100
W.1 Y.COM W
M.T
.100
OM
W
O
W
W
C
.
W
C
W
Y
W
W
00
W
C150-8.T
WW .100Y.
M.T
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M.T
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W
O
W
W
C
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W
WW .100Y
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WW .100Y.C M.TW
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O
W
O
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C
.
O
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W
WW 00Y.C
[13]
WW .100Y.C M.TW
M.T
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O
1
W
M
.
O
W
C
O
W
WW .100Y.
.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
M
O
W
t
O
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O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
ADDRESS
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TtW
O
W
O
SAR
tHAR
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
WE
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WW 00Y.CO .TW
W
CO
WW 00Y.tHWER
C
W
.
W
W
W
Y
W
T
.
W
M
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00
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W.1 Y.COM W
W
W
W
W
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00
W
W.1 Y.COM
M.T
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W.1 Y.COM W
O
W
W
W
C
.
W
tHCSR
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W
00
W
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WW .100Y
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M.T
O
W
O
W
W
C
.
W
W
WW .100Y
WW .100Y.C M.TWtPRS
M.T
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M.T
O
W
O
W
C
.
O
W
W
Y
W
WW .100Y.C M.TW
WW .100Y.C M.TW
M
.100
W
O
W
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O
W
W
C
.
Y
W
C
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W
.
0
Y
W
W
W
0
0
Y
W
.T
0
W
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00
W.1
W.1 Y.COM W
OM
W
W.1 tHZRS
tLZRS
W
C
.
W
W
W
Y
W
.T
W
.100
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OM
W
O
W
C
.
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W
C
W
Y
W HIGH W
WW .100Y.
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O
W
O
W
C
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WW .10OUTPUT
WW .100Y.C M.TW
C150-9
W
O
W
WW
WW .100Y.C M.TW
O
W
Notes:
WW .100Y.C state.M.TW
12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance
O
13. Reset cycle is defined by the overlap of RS andW
CSW
for the minimum.C
Y reset pulse width.
0
W
0
W.1
WW
Document #: 38-05024 Rev. **
Page 5 of 11
Document #: 38-05024 Rev. **
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
NORMALIZED ICC
SB
NORMALIZED I,CC
I
NORMALIZED t AA
DELTA tAA (ns)
NORMALIZED I PO
NORMALIZED t AA
NORMALIZED I,CC
I
SB
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
M
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M.T
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W.1 Y.COM W
WW 00Y.CO .TW
W
W
WW 00Y.CO .TW
W
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00
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M
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© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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