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Download Dataram 4GB DDR3-1333
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DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM Identification DTM64329D 512Mx64 4GB 2Rx8 PC3-10600U-9-11-B1 Performance range Clock / Module Speed / CL-tRCD -tRP 667 MHz / PC3-10600 / 9-9-9 533 MHz / PC3-8500 / 8-8-8 533 MHz / PC3-8500 / 7-7-7 400 MHz / PC3-6400 / 6-6-6 Description Features DTM64329D is an Unbuffered 512Mx64 memory module, which conforms to JEDEC's DDR3, PC3-10600 standard. The assembly is Dual-Rank. Each Rank consists of eight 256Mx8 DDR3 Hynix SDRAMs. One 2K-bit EEPROM is used for Serial Presence Detect. Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I/O signals. 240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm high Operating Voltage: 1.5 V ±0.075 V I/O Type: SSTL_15 Data Transfer Rate: 10.6 Gigabytes/sec Data Bursts: 8 and burst chop 4 mode ZQ Calibration for Output Driver and On-Die Termination (ODT) Programmable ODT / Dynamic ODT during Writes Programmable CAS Latency: 6, 7, 8, and 9 Differential Data Strobe signals SDRAM Addressing (Row/Col/Bank): 15/10/3 Fully RoHS Compliant Pin Configuration Front Side Pin Description Back Side Name Function 211 VSS CB[7:0] Data Check Bits 182 VDD 212 DM5 DQ[63:0] Data Bits 183 VDD 184 CK0 185 /CK0 186 VDD 213 214 215 216 DQS[8:0], /DQS[8:0] DM[8:0] CK[1:0], /CK[1:0] CKE[1:0] Differential Data Strobes Data Mask Differential Clock Inputs Clock Enables 217 VSS 218 DQ52 219 DQ53 /CAS /RAS /S[3:0] Column Address Strobe Row Address Strobe Chip Selects 220 VSS 221 DM6 222 NC /WE A[15:0] BA[2:0] Write Enable Address Inputs Bank Addresses 61 A2 91 DQ41 121 VSS 2 VSS 62 VDD 92 VSS DQ0 33 /DQS3 DQ1 34 DQS3 VSS 35 VSS /DQS0 36 DQ26 63 CK1 64 /CK1 65 VDD 66 VDD 93 94 95 96 7 DQS0 37 DQ27 8 VSS 38 VSS 9 DQ2 39 CB0, NC* 67 VREFCA 68 NC 69 VDD 97 DQ43 127 VSS 157 VSS 187 NC 98 VSS 128 DQ6 158 CB4, NC* 188 A0 99 DQ48 129 DQ7 159 CB5, NC* 189 VDD 10 DQ3 11 VSS 12 DQ8 40 CB1, NC* 41 VSS 42 /DQS8** 70 A10/AP 71 BA0 72 VDD 100 DQ49 130 VSS 160 VSS 190 BA1 101 VSS 131 DQ12 161 DM8, NC* 191 VDD 102 /DQS6 132 DQ13 162 NC 192 /RAS 13 DQ9 43 DQS8** 3 4 5 6 32 VSS 151 VSS 181 A1 1 VREFDQ 31 DQ25 122 DQ4 152 DM3 /DQS5 123 DQ5 DQS5 124 VSS VSS 125 DM0 DQ42 126 NC 153 NC 154 VSS 155 DQ30 156 DQ31 73 /WE 103 DQS6 133 VSS 14 VSS 44 VSS 15 /DQS1 45 CB2, NC* 16 DQS1 46 CB3, NC 17 VSS 47 VSS 74 /CAS 75 VDD 76 /S1 77 ODT1 104 VSS 105 DQ50 106 DQ51 107 VSS 163 VSS 18 DQ10 48 VTT 19 DQ11 49 VTT 20 VSS 50 CKE0 78 VDD 79 /S2, NC* 80 VSS 108 DQ56 138 DQ15 168 /RESET 109 DQ57 139 VSS 169 CKE1 110 VSS 140 DQ20 170 VDD 193 /S0 NC VSS DQ46 DQ47 223 VSS ODT[1:0] On Die Termination Inputs 224 225 226 227 DQ54 DQ55 VSS DQ60 SA[2:0] SCL SDA /RESET SPD Address SPD Clock Input SPD Data Input/Output Reset for register and DRAMs 198 /S3, NC* 199 VSS 200 DQ36 228 DQ61 229 VSS 230 DM7 A12/BC A10/AP VSS Combination input: Addr12/Burst Chop Combination input: Addr10/Auto-precharge Ground 134 DM1 164 CB6, NC* 194 VDD 135 NC 165 CB7, NC* 195 ODT0 136 VSS 166 VSS 196 A13 137 DQ14 167 NC(TEST) 197 VDD 21 DQ16 51 VDD 81 DQ32 111 /DQS7 141 DQ21 171 A15 * 201 DQ37 231 NC VDD Power 22 DQ17 52 BA2 23 VSS 53 NC 24 /DQS2 54 VDD 25 DQS2 55 A11 82 DQ33 83 VSS 84 /DQS4 85 DQS4 112 DQS7 113 VSS 114 DQ58 115 DQ59 202 VSS 203 DM4 204 NC 205 VSS 232 233 234 235 VDDSPD VREFDQ VREFCA VTT SPD EEPROM Power Reference Voltage for DQ’s Reference Voltage for CA Termination Voltage 26 VSS 56 A7 142 VSS 143 DM2 144 NC 145 VSS 172 A14 173 VDD 174 A12/BC 175 A9 VSS DQ62 DQ63 VSS 86 VSS 116 VSS 146 DQ22 176 VDD 206 DQ38 236 VDDSPD NC 27 DQ18 57 VDD 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 29 VSS 59 A4 30 DQ24 60 VDD 88 DQ35 89 VSS 90 DQ40 118 SCL 119 SA2 120 VTT 148 VSS 178 A6 149 DQ28 179 VDD 150 DQ29 180 A3 208 VSS 209 DQ44 210 DQ45 238 SDA 239 VSS 240 VTT No Connection * = Not used Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 Page 1 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM Front view 133.35 [5.250] 9.50 [0.374] 30.00 [1.181] 17.30 [0.681] 5.00 [0.197] 5.175 [0.204] 47.00 [1.850] 71.00 [2.795] 2.50 [0.098] 123.00 [4.843] Back view Side view 4.00 Max [0.157 Max 4.00 Min [0.157] Min 1.27 ±.10 [0.0500 ±0.0040] Notes Tolerances on all dimensions except where otherwise indicated are ±.13 (.005). All dimensions are expressed: millimeters [inches] Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 Page 2 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM /S1 /S0 DMR0 DQSR0 /DQSR0 DMR4 DQSR4 /DQSR4 /DQS DQR[7:0] DQS CS I/O[7:0] CK /CS DM /DQS DQS CS I/O[7:0] CK CKE ODT /CS DM CKE ODT DMR1 DQSR1 /DQSR1 DQS CS I/O[7:0] CK /CS DM CKE ODT /DQS DQS CS I/O[7:0] CK /CS DM CKE ODT /DQS DQS CS I/O[7:0] CK /CS DM CKE ODT DQR[47:40] CKE ODT DQS CS I/O[7:0] CK /CS DM CKE ODT /DQS DQS CS I/O[7:0] CK /CS DM CKE ODT DMR6 DQSR6 /DQSR6 /DQS DQS CS I/O[7:0] CK /CS DM /DQS DQS CS I/O[7:0] CK CKE ODT /CS DM /DQS DQR[55:48] CKE ODT DMR3 DQSR3 /DQSR3 DQS CS I/O[7:0] CK /CS DM CKE ODT /DQS DQS CS I/O[7:0] CK /CS DM CKE ODT DMR7 DQSR7 /DQSR7 /DQS DQR[31:24] /DQS /CS DM DMR2 DQSR2 /DQSR2 DQR[23:16] DQS CS I/O[7:0] CK DMR5 DQSR5 /DQSR5 /DQS DQR[15:8] /DQS DQR[39:32] DQS CS I/O[7:0] CK /CS DM CKE ODT /DQS DQS CS I/O[7:0] CK /CS DM /DQS DQR[63:56] CKE ODT DQS CS I/O[7:0] CK /CS DM CKE ODT /DQS DQS CS I/O[7:0] CK /CS DM CKE ODT CK0, /CK0 CK1, /CK1 CKE0 CKE1 ODT0 ODT1 All 15 OHMS 2.2 pF DQR[63:0] DQ[63:0] DQS[7:0] DQRS[7:0] /DQS[7:0] /DQRS[7:0] CK[1:0] /CK[1:0] DMR[7:0] DM[7:0] VDD All 36 OHMS 100 nf GLOBAL SDRAM CONNECTS /CK0 CK0 All 39 OHMS BA[2:0] 100 nf /CK1 A[15:0] /RAS /CAS /WE CK1 VTT All 39 OHMS CKE[1:0] ODT[1:0] /S[1:0] VTT VDDSPD VDD VREF_DQ VSS VREF_CA VTT DECOUPLING Serial PD All SDRAMs All SDRAMs All SDRAMs All SDRAMs All SDRAMs All 240 OHMS ZQ SCL VSS Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 SERIAL PD SDA SA0 SA1 SA2 Page 3 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM Absolute Maximum Ratings (Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.) PARAMETER Symbol Minimum Maximum Unit Temperature, non-Operating TSTORAGE -55 100 C TA 0 70 C TCASE 0 95 C VDD -0.4 1.975 V VIN,VOUT -0.4 1.975 V Ambient Temperature, Operating DRAM Case Temperature, Operating Voltage on VDD relative to VSS Voltage on Any Pin relative to VSS Notes: DRAM Operating Case Temperature above 85C requires 2X refresh. Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Power Supply Voltage Symbol VDD Minimum 1.425 Typical 1.5 Maximum 1.575 Unit V Note I/O Reference Voltage VREFDQ 0.49 VDD 0.50 VDD 0.51 VDD V 1 I/O Reference Voltage VREFCA 0.49 VDD 0.50 VDD 0.51 VDD V 1 Notes: The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may not exceed ±1% of its DC value. For Reference VDD/2 ± 15 mV. DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(DC) Minimum VREF + 0.1 Maximum VDD Unit V Logical Low (Logic 0) VIL(DC) VSS VREF - 0.1 V AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(AC) Minimum VREF + 0.175 Maximum - Unit V Logical Low (Logic 0) VIL(AC) - VREF - 0.175 V Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 Page 4 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Differential Input Logic High Symbol VIH.DIFF Minimum +0.200 Maximum DC:VDD AC:VDD+0.4 Unit V VIL.DIFF DC:VSS AC:VSS-0.4 -0.200 V VIX - 0.150 + 0.150 V Differential Input Logic Low Differential Input Cross Point Voltage relative to VDD/2 Capacitance (TA = 25 C, f = 100 MHz) PARAMETER Pin Symbol Minimum Maximum Unit CCK 8.6 13.4 pF BA[2:0], A[14:0], /RAS, /CAS, /WE CI 12 20.8 pF /S[1:0], CKE[1:0], ODT[1:0] CI 6 10.4 pF CDIO 3 5 pF Input Capacitance, Clock Input Capacitance, Address Input Capacitance Control CK[1:0], /CK[1:0] Input/Output Capacitance DQ[63:0], DQS[7:0], /DQS[7:0], DM[7:0] DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Input Leakage Current Symbol Minimum Maximum Unit Note IIL -16 +32 μA 1,2 IOL -10 +10 μA 2,3 (Any input 0 V < VIN < VDD) Output Leakage Current (0V < VOUT < VDDQ) Notes: 1) All other pins not under test = 0 V 2) Values are shown per pin 3) DQ, DQS, DQS and ODT are disabled Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 Page 5 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Symbol Test Condition Operating One Operating current : One bank ACTIVATE-to-PRECHARGE Bank ActiveIDD0* Precharge Current Operating One Operating current : One bank ACTIVATE-to-READ-toBank Active-ReadPRECHARGE IDD1* Precharge Current Precharge PowerPrecharge power down current: Slow exit IDD2P** Down Current Precharge PowerPrecharge power down current: Fast exit IDD2P** Down Current Precharge Quiet Precharge quiet standby current IDD2Q** Standby Current Precharge Standby Precharge standby current IDD2N** Current Active Power-Down Active power-down current IDD3P** Current Active Standby Active standby current IDD3N** Current Operating Burst Burst write operating current IDD4W* Write Current Operating Burst Burst read operating current IDD4R* Read Current Burst Refresh Refresh current IDD5** Current Self Refresh Self-refresh temperature current: MAX TC = 85°C IDD6** Current Operating Bank All bank interleaved read current Interleave Read IDD7** Current * One module rank in this operation, the other in IDD2P: Slow exit. ** All module ranks in this operation. Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 Max Value Unit 320 mA 360 mA 160 mA 208 mA 240 mA 240 mA 192 mA 288 mA 640 mA 600 mA 1440 mA 160 mA 1920 mA Page 6 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data tAA 13.125 20 ns CAS-to-CAS Command Delay tCCD 4 - tCK tCH(avg) 0.47 0.53 tCK tCK 1.5 3.3 ns tCL(avg) 0.47 0.53 tCK tDH 65 - ps Clock High Level Width Clock Cycle Time Clock Low Level Width Data Input Hold Time after DQS Strobe tDIPW 400 - ps DQS Output Access Time from Clock tDQSCK -255 +255 ps Write DQS High Level Width tDQSH 0.45 0.55 tCK(avg) Write DQS Low Level Width tDQSL 0.45 0.55 tCK(avg) DQS-Out Edge to Data-Out Edge Skew tDQSQ - 125 ps Data Input Setup Time Before DQS Strobe tDS 30 - ps DQS Falling Edge from Clock, Hold Time tDSH 0.2 - tCK(avg) DQS Falling Edge to Clock, Setup Time tDSS 0.2 - tCK(avg) Clock Half Period tHP minimum of tCH or tCL - ns Address and Command Hold Time after Clock tIH 140 - ps DQ Input Pulse Width tIS 190 - ps Load Mode Command Cycle Time tMRD 4 - tCK DQ-to-DQS Hold tQH 0.38 - tCK(avg) Active-to-Precharge Time tRAS 36 9*tREFI ns Active-to-Active / Auto Refresh Time tRC 49.125 - ns RAS-to-CAS Delay tRCD 13.125 - ns Average Periodic Refresh Interval tREFI - 7.8 μs Auto Refresh Row Cycle Time tRFC 160 - ns Row Precharge Time tRP 13.125 - ns Read DQS Preamble Time tRPRE 0.9 Note-1 tCK(avg) Read DQS Postamble Time tRPST 0.3 Note-2 tCK(avg) Row Active to Row Active Delay tRRD Max(4nCK, 6ns) - ns Internal Read to Precharge Command Delay tRTP Max(4nCK, 7.5ns) - ns Write DQS Preamble Setup Time tWPRE 0.9 - tCK(avg) Write DQS Postamble Time Address and Command Setup Time before Clock tWPST 0.4 - tCK(avg) Write Recovery Time tWR 15 - ns Internal Write to Read Command Delay Notes: 1. The maximum preamble is bound by tLZDQS(min) 2. The maximum postamble is bound by tHZDQS(max) tWTR Max(4nCK, 7.5ns) - ns Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 Page 7 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte# Function. Value Hex Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage. Bit 3 ~ Bit 0. SPD Bytes Used Bit 6 ~ Bit 4. SPD Bytes Total Bit 7. CRC Coverage - 0 1 SPD Revision. 2 Key Byte / DRAM Device Type. 176 256 Bytes 0-116 Rev. 1.1 0x92 0x11 DDR3 SDRAM 0x0B Key Byte / Module Type. 3 Bit 3 ~ Bit 0. Module Type Bit 7 ~ Bit 4. Reserved - UDIMM 0 0x02 4 Bit 3 ~ Bit 0. Total SDRAM capacity, in megabits Bit 6 ~ Bit 4. Bank Address Bits Bit 7. Reserved SDRAM Addressing. 2GB 8 banks 0 0x03 5 Bit 2 ~ Bit 0. Column Address Bits Bit 5 ~ Bit 3. Row Address Bits Bit 7, 6. Reserved 10 15 0 UNUSED 0x19 SDRAM Density and Banks. 6 Reserved. 0x00 Module Organization. 7 Bit 2 ~ Bit 0. SDRAM Device Width Bit 5 ~ Bit 3. Number of Ranks Bit 7, 6. Reserved Module Memory Bus Width. 8-Bits 2-Rank 0 0x09 8 Bit 2 ~ Bit 0. Primary bus width, in bits Bit 4, Bit 3. Bus width extension, in bits Bit 7 ~ Bit 5. Reserved Fine Timebase (FTB) Dividend / Divisor. 64-Bits 0-Bits 0 0x03 9 Bit 3 ~ Bit 0. Fine Timebase (FTB) Divisor Bit 7 ~ Bit 4. Fine Timebase (FTB) Dividend Medium Timebase (MTB) Dividend. 0x52 0x0C 0x00 12 SDRAM Minimum Cycle Time (tCKmin). 2 5 1 (MTB = 0.125ns) 8 (MTB = 0.125ns) 1.5ns 13 Reserved. UNUSED 10 11 Medium Timebase (MTB) Divisor. 0x01 0x08 CAS Latencies Supported, Least Significant Byte. 14 Bit 0. CL = 4 Bit 1. CL = 5 Bit 2. CL = 6 Bit 3. CL = 7 Bit 4. CL = 8 Bit 5. CL = 9 Bit 6. CL = 10 Bit 7. CL = 11 - Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 X X X X 0x3C Page 8 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM CAS Latencies Supported, Most Significant Byte. Bit 0. CL = 12 Bit 1. CL = 13 Bit 2. CL =14 Bit 3. CL = 15 Bit 4. CL = 16 Bit 5. CL = 17 Bit 6. CL = 18 Bit 7. Reserved. 15 16 Minimum CAS Latency Time (tAAmin). 17 Minimum Write Recovery Time (tWRmin). 18 Minimum RAS# to CAS# Delay Time (tRCDmin). 19 Minimum Row Active to Row Active Delay Time (tRRDmin). 20 Minimum Row Precharge Delay Time (tRPmin). 0x00 13.125ns 0x69 15.0ns 0x78 13.125ns 0x69 6.0ns 0x30 13.125ns 0x69 1 1 36.0ns 0x11 Upper Nibbles for tRAS and tRC. 21 22 23 24 25 26 27 28 29 Bit 3 ~ Bit 0. tRAS Most Significant Nibble Bit 7 ~ Bit 4. tRC Most Significant Nibble Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte. Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte. Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte. Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte. Minimum Internal Write to Read Command Delay Time (tWTRmin). Minimum Internal Read to Precharge Command Delay Time (tRTPmin). Upper Nibble for tFAW. Bit 3 ~ Bit 0. tFAW Most Significant Nibble Bit 7 ~ Bit 4. Reserved Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte. SDRAM Optional Features. 49.125ns 160.0ns 160.0ns 7.5ns 7.5ns 0 0 30.0ns Bit 0. RZQ / 6 Bit 1. RZQ / 7 Bit 6 ~ Bit 2. Reserved Bit 7. DLL-Off Mode Support X X Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh (ASR) On-die Thermal Sensor (ODTS) Readout Reserved Reserved Reserved Reserved - X 30 0x20 0x89 0x00 0x05 0x3C 0x3C 0x00 0xF0 0x83 SDRAM Drivers Supported. 31 Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 X 0x05 Page 9 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM 32-59 Reserved UNUSED 0x00 Module Nominal Height. 60 Bit 4 ~ Bit 0. Module Nominal Height max, in mm Bit 7 ~ Bit5. Reserved Module Maximum Thickness. 29<h<=30 0 0x0F 61 Bit 3 ~ Bit 0. Front, in mm (baseline thickness = 1 mm) Bit 7 ~ Bit 4. Back, in mm (baseline thickness = 1 mm) Reference Raw Card Used. 1<th<=2 1<th<=2 0x11 62 Bit 4 ~ Bit 0. Reference Raw Card Bit 6, Bit 5. Reference Raw Card Revision Bit 7. Reserved Address Mapping from Edge Connector to DRAM. R/C B Rev.1 0 0x31 Mirrored 0 UNUSED 0x01 63 Bit 0. Rank 1 Mapping (Registered DIMM - Reserved) Bit 7 ~ Bit 1. Reserved 64-112 Module-Specific Section Module-Specific Section. 113 114-116 Module-Specific Section Module Manufacturer ID Code, Least Significant Byte 117 Module Manufacturer ID Code, Most Significant Byte 118 Module Manufacturing Location 119 120,121 Module Manufacturing Date 122-125 Module Serial Number Cyclical Redundancy Code (CRC). 126 Cyclical Redundancy Code (CRC). 127 128-131 Module Part Number Module Part Number 132 Module Part Number 133 Module Part Number 134 Module Part Number 135 Module Part Number 136 Module Part Number 137 Module Part Number 138 Module Part Number 139 Module Part Number 140 Module Part Number 141 Module Part Number 142 Module Part Number 143 Module Part Number 144 Module Part Number 145 146,147 Module Revision Code DRAM Manufacturer ID Code, Least Significant Byte 148 DRAM Manufacturer ID Code, Most Significant Byte 149 150-175 Manufacturer’s Specific Data 176-255 Open for customer use UNUSED UNUSED UNUSED CRC CRC D A T A R A M 6 4 3 2 9 UNUSED UNUSED UNUSED UNUSED 0x00 0x00 0x00 0x01 0x91 0x00 0x20 0x20 0xA8 0xC6 0x20 0x44 0x41 0x54 0x41 0x52 0x41 0x4D 0x20 0x36 0x34 0x33 0x32 0x39 0x20 0x20 0x00 0x00 0x00 0xFF Bytes: 122-125 change per DIMM. Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 Page 10 DTM64329D 4GB - 240-Pin 2Rx8 Unbuffered Non-ECC DDR3 DIMM DATARAM CORPORATION, USA Corporate Headquarters, P.O. Box 7528, Princeton, NJ 08543-7528; Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com All rights reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Dataram assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Dataram. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Dataram. Document 06203, Revision A, 2-Apr-13, Dataram Corporation © 2013 Page 11
