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Download Atmel AT91SAM9X35 User guide
Transcript
SAM9G15-EK
SAM9G25-EK
SAM9G35-EK
SAM9X25-EK
SAM9X35-EK
...................................................................................................................
User Guide
11115A–ATARM–27-Jul-11
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11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Section 1
Introduction .................................................................................................................1-1
1.1
Scope ................................................................................................................................. 1-1
1.2
Applicable Documents ....................................................................................................... 1-2
Section 2
Kit Contents ................................................................................................................2-1
2.1
Deliverables ....................................................................................................................... 2-1
2.2
Evaluation Board Specifications......................................................................................... 2-2
2.3
Electrostatic Warning ......................................................................................................... 2-3
Section 3
Power Up ....................................................................................................................3-1
3.1
Power Up the Board........................................................................................................... 3-1
3.2
DevStart ............................................................................................................................. 3-1
3.3
Recovery Procedure .......................................................................................................... 3-2
3.4
Sample Code and Technical Support ................................................................................ 3-2
Section 4
Evaluation Kit Hardware .............................................................................................4-1
4.1
Introduction ........................................................................................................................ 4-1
4.2
Computer Module (CM)...................................................................................................... 4-3
4.3
4.4
4.2.1
CM Board Overview............................................................................................. 4-3
4.2.2
Equipment List ..................................................................................................... 4-3
4.2.3
Function Blocks ................................................................................................... 4-5
4.2.4
Configuration ..................................................................................................... 4-14
4.2.5
Connectors ........................................................................................................ 4-15
4.2.6
Schematics ........................................................................................................ 4-16
EK Board Description....................................................................................................... 4-21
4.3.1
EK Board Overview ........................................................................................... 4-21
4.3.2
Equipment List ................................................................................................... 4-22
4.3.3
Function Blocks ................................................................................................. 4-23
4.3.4
Configuration ..................................................................................................... 4-39
4.3.5
Connectors ........................................................................................................ 4-45
4.3.6
Schematics ........................................................................................................ 4-63
Optional Display Module (DM) Board Hardware .............................................................. 4-78
4.4.1
DM Board Overview........................................................................................... 4-78
4.4.2
Equipment List ................................................................................................... 4-78
4.4.3
Function Blocks ................................................................................................. 4-78
Evaluation Kit (EK) User Guide
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11115A–ATARM–27-Jul-11
4.4.4
Schematics ........................................................................................................ 4-82
Section 5
Revision History..........................................................................................................5-1
5.1
Revision History ................................................................................................................. 5-1
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11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Section 1
Introduction
1.1
Scope
This User Guide introduces the Evaluation Kit and describes the development and debugging capabilities running on an AT91SAM9 ARM®-based Embedded MPUs as listed below:
SAM9G15
SAM9G25
SAM9X25
SAM9G35
SAM9X35
The User Guide pertains to the following Evaluation Kit references:
SAM9G15-EK
SAM9G25-EK
SAM9X25-EK
SAM9G35-EK
SAM9X35-EK
This User Guide gives design details on the Evaluation Kit and is made up of 5 sections:
Section 1 includes a photo of the board, device and kit references and applicable documents.
Section 2 describes the kit contents, its main features.
Section 3 provides instructions to power up the Evaluation Kit and describes how to use it.
Section 4 describes the CPU Module (CM), the Main Board (MB) and optional Display Module (DM).
Evaluation Kit (EK) User Guide
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11115A–ATARM–27-Jul-11
Introduction
Figure 1-1.
1.2
Board Photo (Display module is optional)
Applicable Documents
Table 1-1. Applicable Documents
Reference
Title
Comment
Atmel lit° 11052
Atmel lit° 11032
Atmel lit° 11054
Atmel lit° 11053
Atmel lit° 11055
SAM9G15 datasheet
SAM9G25 datasheet
SAM9X25 datasheet
SAM9G35 datasheet
SAM9X35 datasheet
These documents provide technical support for each one of the
Atmel ARM-based Embedded MPU products supported by these
Evaluation Kits.
The datasheets can be found on www.atmel.com in the
SAM9G/SAM9X product families by means of the link below:
http://www.atmel.com/products/at91/default.asp?category_id=163&family_id=605&source=global_nav
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Evaluation Kit (EK) User Guide
Section 2
Kit Contents
2.1
Deliverables
The Evaluation Kits include:
Board
– One EK board
– One of the five available CPU modules (CM)
SAM9G15-CM
SAM9G35-CM
SAM9X35-CM
SAM9G25-CM
SAM9X25-CM
– One optional DM board featured in SAM9G15, SAM9G35, SAM9X35 kits only.
Power supply
– Universal input AC/DC power supply with US, Europe and UK plug adapters
– One 3V Lithium Battery type CR1225
Cables
– One serial RS232 cable
– One micro A/B-type USB cable
– One RJ45 crossed cable
A Welcome Letter
Evaluation Kit (EK) User Guide
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11115A–ATARM–27-Jul-11
Kit Contents
Figure 2-1.
Unpacked Evaluation Kit
Unpack and inspect the kit carefully. Contact your local Atmel distributor, should there be issues concerning the contents of the kit.
2.2
Evaluation Board Specifications
Table 2-1. Evaluation Kit Specifications
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11115A–ATARM–27-Jul-11
Characteristics
Specifications
Clock speed
400 MHz PCK, 133 MHz MCK
Ports
Ethernet, USB, RS232, DBGU, JTAG, CAN, Audio, SD Card
Board supply voltage
5 VDC from connector
Temperature
- operating
- storage
-10° to +50° C
-40° to +85° C
Relative humidity
0 to 90% (non condensing)
Dimensions
EK (Evaluation Kit)
CM (Computer Module)
DM (Display Module)
165 mm x 135 mm
67.6 mm x 35 mm
135 mm x 80 mm
RoHS status
Compliant
Evaluation Kit (EK) User Guide
Kit Contents
2.3
Electrostatic Warning
The Evaluation Kit is shipped in a protective anti-static package. The board system must not be subjected to high electrostatic potentials. A grounding strap or similar ESD protective device should be worn
when handling the board in hostile ESD environments (offices with synthetic carpet, for example). Avoid
touching the component pins or any other metallic element on the board.
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Section 3
Power Up
3.1
Power Up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the
screen and enjoy the demo.
3.2
DevStart
The on-board NAND Flash contains an installation guide named: “SAM9x5-EK DevStart”.
It is stored in the “SAM9x5-EK DevStart” folder on the USB Flash disk available when the Evaluation Kit
is connected to a host computer.
Click the file “welcome.html” in this folder to launch the SAM9x5-EK DevStart.
DevStart guides the user through the installation processes of IAR™ EWARM, Keil™ MDK and GNU
toolkits. Then, it gives step-by-step instructions on how to rebuild a single example project and how to
program it into the Evaluation Kit. Optionally, if the user has a SAM-ICE™ interface, instructions are also
given about how to debug the code.
It is strongly recommended that users backup the “SAM9x5-EK DevStart” folder on their computer before launching it.
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Power Up
3.3
Recovery Procedure
The DevStart ends by giving step-by-step instructions on how to recover the Evaluation Kit to the state
as it was when shipped by Atmel.
Follow the instructions if contents of the NAND Flash or the SPI DataFlash® have been deleted, in order
to recover from this situation.
3.4
Sample Code and Technical Support
After boot up, designers can run sample code or their own application, on the development kit. Users
can download sample code and get technical support from the Atmel web site:
http://www.atmel.com/products/at91/default.asp?category_id=163&family_id=605&source=global_nav
Figure 3-1.
Atmel Web Site
Note: Different interfaces on the EK boards share the same connections to the CPU module. Therefore the actual
usage depends on the CPU module featured in the evaluation kit.
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Evaluation Kit (EK) User Guide
Section 4
Evaluation Kit Hardware
4.1
Introduction
The Evaluation Kit is a fully-featured evaluation platform for the Atmel MPU. The Evaluation Kit enables
users to extensively evaluate, prototype and create application-specific designs.
The Evaluation Kit is a new platform architecture based on a Main Board (MB), a CPU Module (CM)
equipped with one of the five processors and an optional Display Module (DM).
The Evaluation Kit consists of three boards:
1. The CPU Module (CM) board, is a single-board computer that integrates all the core components
and is mounted onto an application-specific carrier board (EK board). The CPU Module has specified pinouts based on the SODIMM200 connector. It provides the functional requirements for an
embedded application. These functions include, but are not limited to, graphics, audio, mass storage,
network and multiple serial and USB ports. A single SODIMM200 connector provides an interface for
the carrier board to carry all the I/O signals to and from the CPU Module.
2. The Evaluation Kit board (EK Main Board) provides all the interface connectors required to attach
the system to the application specific peripherals. This versatility allows the designer to create a
densely packed solution, which results in a more reliable product while simplifying system
integration.
3. The optional Display Module (DM) board integrates LCD, TouchScreen and Qtouch® technology.
Table 4-1, on the page that follows, lists the features provided on the Evaluation Kit:
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Evaluation Kit Hardware
Table 4-1. Evaluation Kit Features
Supported modules
Expansion Slot
SAM9 products
SO-DIMM200
SAM9
G15
Processor options
MII/RMII Ethernet 10/100 w/PHY and three
Led status
ETH0
RMII Ethernet 10/100 w/PHY and three Led
status
ETH1
RS232 four wires/RS485
Shared interface
COM0
RS232 four wires
COM3
RS232 two wires
DBGU
SAM9
G25
SAM9
G35
SAM9
X25
SAM9
X35
X
X
X
X
LAN
USART/UART
CAN
X
X
X
X
X
X
X
X
X
X
X
X
X
CAN0
X
X
CAN1
X
X
CAN interface Shared interface
2 * USB 2.0 Host
X
X
X
X
X
1 * USB 2.0 Host/Device
X
X
X
X
X
Software Modem Device
X
X
X
X
X
USB
SMD
µSD Card Slot Onboard
HSMCI
0
X
X
X
X
X
MMC/MMC+/SD/SDIO/CE-ATA
HSMCI
1
X
X
X
X
X
Memory Card Support
ISI
X
LCD + Touch Screen
24-bit Output Mode
®
X
X
X
ZigBee
X
X
X
X
X
SPI
X
X
X
X
X
TWI
X
X
X
X
X
X
X
X
X
X
DEBUG
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JTAG Test Access Port
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.2
Computer Module (CM)
4.2.1
CM Board Overview
The CM board is the CPU module at the heart of the system. It connects to the EK board through a SODIMM200 interface. It carries the processor and external memories. The CM board serves as a minimal
CPU sub-system. All five processors:SAM9G15, SAM9G25, SAM9X25,SAM9G35 and SAM9X35 share
the same CM circuitry with minor configuration settings.
Note:
There are three CM boards from three different manufacturers. The five processors are
implemented as shown in Table 4-2 below:
Table 4-2. CM Board Implementation
Manufacturer &
Module kind
SAM9G15-CM
mfg 1
x
SAM9G25-CM
SAM9G35-CM
x
SAM9X35-CM
x
x
x
x
x
mfg 2
mfg 3
SAM9X25-CM
x
x
The three CM boards share the same circuitry design but with different designator information and PCB layouts. The
circuitry reference in this guide, for common design parts, refers to schematics from SAM9G25-CM (mfg 3). All the
other schematics are provided in Section 4.2.6 ”Schematics”.
Figure 4-1.
4.2.2
Board Architecture
Equipment List
The CM board is built around the integration of an ARM926-based microcontroller (BGA217 package)
with external memory and optional Ethernet PHYsical Layer Transceiver.
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Evaluation Kit Hardware
4.2.2.1
Devices
Following is the list of the CM board components:
One SAM9 Embedded MPU from the list below
–
–
–
–
–
4.2.2.2
12 MHz crystal
32.768 KHz crystal
1 Gbit DDR2 memory
2 Gits NAND Flash memory with Chip Selection control switch
32 Mbits SPI Serial DataFlash with Chip Selection control switch
512 Kbits EEPROM
1 Kbyte 1-Wire EEPROM
On-board power regulation
Two user LEDs
Optional PHY
Interface Connection
4.2.2.3
SAM9G15
SAM9G25
SAM9G35
SAM9X25
SAM9X35
SODIMM200 card edge interface
Configuration Items
Dual ON/OFF switch for NAND Flash and SPI DataFlash Chip Select connection
Figure 4-2.
CM Board Layout Commented
NAND Flash
DDR2 SDRAM
Sodimm200 card edge
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SAM9 chip
PHY
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.2.3
Function Blocks
4.2.3.1
Processor
The CM Board is equipped with an Atmel ARM-based embedded MPU, as listed below, in a 217-ball
BGA package. The five devices share an identical footprint. All five share the same CM Board PCB with
minor configuration differences.
The five devices are:
SAM9G15
SAM9G25
SAM9G35
SAM9X25
SAM9X35
As different interfaces can be defined using the same pins, it depends on the actual configuration of the
CPU as to which functions are in fact available to the EK board.
Refer to Section 4.2.4.1 ”Chip Identification” for details. The processor runs at a nominal frequency of
400 MHz for the core and 133 MHz for the system bus.
The peripheral configuration possibilities and implementation requirements of the CM are dependent on
the module's chipset. Two configuration resistors are implemented on board in order to select the mode
of configuration.
4.2.3.2
Clock Circuitry
The CM includes 3 clock sources:
Two are alternatives for the processor main clock
One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip
Table 4-3. Main Components Associated with the Clock Systems
Quantity
4.2.3.3
Description
Component assignment
1
Crystal for Internal Clock, 12 MHz
Y1
1
Crystal for RTC Clock, 32.768 kHz
Y2
1
Oscillator for Ethernet Clock RMII, 50 MHz
Y3
Reset Circuitry
The reset sources for the CM board are:
Power on reset
Push button reset (Push button is equipped on EK board)
JTAG reset from an in-circuit emulator (JTAG interface is equipped on EK board)
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Evaluation Kit Hardware
4.2.3.4
Power Supplies
The CM Board is driven by +3V3 input power rail from the EK board through the SODIMM200 connector.
The CM Board embeds all the necessary power rails required for the micro processor.
When additional voltages are required, for example VDDCORE, they are generated on board from the
3.3V supply. The detailed power supply requirements for any given module are specified within the corresponding product documentation. The following table summarizes the power specifications.
Table 4-4. Power Rails Associated with the Systems
Nominal
Name
Powers
3.3v
VDDNF
the NAND Flash I/O and control, D16-D32 and
multiplexed SMC lines
From SODIMM200 connector
3.3v
VDDIOP0
Partial Peripheral I/O lines
From SODIMM200 connector
3.3v
VDDIOP1
Partial Peripheral I/O lines
From SODIMM200 connector
3.0v
VDDBU
the Slow Clock oscillator, the internal 32 kHz
RC, the internal 12 MHz RC and a part of the
System Controller
From SODIMM200 connector
3.3v
VDDUTMII
the USB device and host UTMI+ interface
From SODIMM200 connector
3.3v
VDDOSC
the Main Oscillator cells
From SODIMM200 connector
3.3v
VDDANA
the Analog to Digital Converter
From SODIMM200 connector
1.8v
VDDIOM
the External Memory Interface I/O lines
on-board
1.0v
VDDUTMIC
DC Supply UDPHS and UHPHS UTMI+ Core
on-board
3.3v
VDDPLLUTMI
DC Supply UDPHS and UHPHS UTMI+
Interface
From SODIMM200 connector
1.0v
VDDPLLA
the PLLA cell
on-board
1.0v
VDDCORE
the core, including the processor, the
embedded memories and the peripherals
on-board
3.0V or 3.3V
configurable
ADVREF
ADC Reference voltage
From SODIMM200 connector
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11115A–ATARM–27-Jul-11
Component
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
Figure 4-3.
CM Power Supply
+3V3
4
MN3
AS1301EHT-adj
IN
L2
3
LX
VDDCORE
2.2uH 3D16
EN
C11
22pF
5
FB
2
PWR_EN1
GND
C10
4.7uF
MN1
AS1301EHT-adj
IN
C1
4.7uF
1
C3
4.7uF
C8
100nF
EN
L1
3
LX
VDDIOM
2.2uH 3D16
C9
22pF
5
FB
2
PWR_EN
C12
10uF
C7
100nF
R4
59K 1%
GND
4
R2
39.2K 1%
C6
100nF
R1
118K 1%
C13
100nF
C2
10uF
C14
100nF
C15
100nF
R3
59K 1%
1
B2
2
VDDNF
C4
100nF
120 OHM@100MHZ
C5
100nF
L5
10uH/150mA
VDDUTMII
C38
100nF
R22
1R
C39
4.7uF
C40
100nF
L6
10uH/150mA
VDDOSC
C41
100nF
C42
100nF
R25
1R
C43
4.7uF
IN
OUT
EN
NR
L4
10uH/150mA
+1V
5
VDDPLLA
C16
1uF
4
C32
100nF
R17
C33
100nF
1R
C18
10nF
2
C17 PWR_EN3
1uF
MN4
TPS71710DCK
GND
1
C34
4.7uF
ADVREF
ADVREF
VDDUTMIC
C35
100nF
C30
100nF
VDDBU
VDDBU
C36
1uF
C37
100nF
VDDIOP0
VDDANA
L3
VDDIOP0
VDDANA
R10
10uH/150mA
C20
100nF
C21
100nF
C27
100nF
VDDIOP1
C25
100nF
C26
100nF
1R
VDDIOP1
C23
100nF
Evaluation Kit (EK) User Guide
C28
4.7uF
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11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.2.3.5
Memory
The Device serial processor features a DDR/SDR memory interface and an External Bus Interface (EBI)
to enable interfacing to a wide range of external memories and to almost any kind of parallel peripheral.
The External Bus Interface (EBI) is connected to two kinds of memory devices:
One 1 Gbyte DDR2 SDRAM
One 2 Gbytes (or 4 Gbytes depending on supplier) NAND Flash
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11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Evaluation Kit (EK) User Guide
PD0/NANDOE
PD1/NANDWE
PD2/A21/NANDALE
PD3/A22/NANDCLE
PD4/NCS3
PD5/NWAIT
PD6/D16
PD7/D17
PD8/D18
PD9/D19
PD10/D20
PD11/D21
PD12/D22
PD13/D23
PD14/D24
PD15/D25/A20
PD16/D26/A23
PD17/D27/A24
PD18/D28/A25
PD19/D29/NCS2
PD20/D30/NCS4
PD21/D31/NCS5
MN2E
SAM9x5_LBGA217 - PIOD
NRD
NWR0/NWRE
NWR1/NBS1
NWR3/NBS3/DQM3
NCS0
NCS1/SDCS
SDWE
SDCKE
SDA10
SDCK
#SDCK
RAS
CAS
DQM0
DQM1
DQS0
DQS1
EBI_SDWE
EBI_SDCKE
EBI_SDA10
EBI_SDCK
EBI_NSDCK
A12
B12
C8
D11
C11
P13
R14
R13
P15
P12
P14
N14
R15
M14
N16
N17
N15
K15
M15
L14
M16
L16
L15
K17
J17
K16
J16
D9
C9
C7
A8
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
(NANDOE)
(NANDWE)
(NANDALE)
(NANDCLE)
(NANDCS)
NCS0
EBI_NCS1_SDCS
EBI_RAS
EBI_CAS
B11
C10
B9
B8
EBI_DQM0
EBI_DQM1
EBI_DQS0
EBI_DQS1
EBI_A13
EBI_A14
EBI_A15
EBI_A16
EBI_A17
EBI_A18
EBI_A2
EBI_A3
EBI_A4
EBI_A5
EBI_A6
EBI_A7
EBI_A8
EBI_A9
EBI_A10
EBI_A11
EBI_D0
EBI_D1
EBI_D2
EBI_D3
EBI_D4
EBI_D5
EBI_D6
EBI_D7
EBI_D8
EBI_D9
EBI_D10
EBI_D11
EBI_D12
EBI_D13
EBI_D14
EBI_D15
A10
B10
A11
A9
J15
H16
H15
H17
G17
G16
F17
E17
F16
G15
G14
F15
D17
C17
E16
D16
C16
B17
E15
E14
D14
D15
A16
B16
A17
B15
C14
B14
A15
C15
D12
C13
A14
B13
A13
C12
EBI_NCS1_SDCS R38
PD0
PD1
PD2
PD3
PD4
PD6
(NANDOE)
(NANDWE)
(NANDALE)
(NANDCLE)
(NANDCS)
(NANDR/B)
1
0R
0R
0R
0R
0R
0R
8
7
6
5
8
7
6
5
PD3 R40
PD2 R43
PD0 R44
PD1 R41
C64
104
C62
104
NAND_FSH_D0
NAND_FSH_D1
NAND_FSH_D2
NAND_FSH_D3
NAND_FSH_D4
NAND_FSH_D5
NAND_FSH_D6
NAND_FSH_D7
VDDNF
VDDNF
R39
1.5K 1%
R34
1.5K 1%
DDR2_NCS1
B3
F3
DDR2_DQM1
DDR2_DQM0
R49
DNP
470K
0R
470K
470K
0R
0R
0R
0R
WP
RB
CLE
ALE
RE
WE
CE
F7
E8
DDR2_DQS0
EBI_A15
B7
A8
DDR2_DQS1
7
1
2
3
4
5
6
10
11
14
15
20
23
24
35
21
22
38
19
MT29F2G08AAD
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
DNU1
DNU2
DNU3
WP
R/B
CLE
ALE
RE
WE
CE
MN11
RFU1
RFU2
RFU3
RFU4
RFU5
UDM
LDM
LDQS
LDQS
UDQS
UDQS
WE
CAS
RAS
CS
CK
CK
CKE
ODT
VSS
VSS
VSS_N.C
VSS_N.C
VCC
VCC
VCC_N.C
VCC_N.C
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8_N.C
I/O9_N.C
I/O10_N.C
I/O11_N.C
I/O12_N.C
I/O13_N.C
I/O14_N.C
I/O15_N.C
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VSS
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
VDD
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M16HR DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
A12
DQ12
DQ13
BA0
DQ14
BA1
DQ15
BA2
MN5
16
17
8
18
9
A2
E2
R3
R7
R8
K3
L7
K7
L8
J8
K8
K2
DDR2_SDWE
NANDOE
NANDWE
NANDALE
NANDCLE
NANDCS
NANDR_B
R46
PD5 R42
R47
R48
DDR2_NCS1
DDR2_SDWE
DDR2_SDCKE
DDR2_CAS
DDR2_RAS
DDR2_SDCK
DDR2_NSDCK
DDR2_SDCK
DDR2_NSDCK
DDR2_SDCKE
DDR2_RAS
DDR2_CAS
L2
L3
L1
EBI_A16
EBI_A17
EBI_A18
K9
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
EBI_A2
EBI_A3
EBI_A4
EBI_A5
EBI_A6
EBI_A7
EBI_A8
EBI_A9
EBI_A10
EBI_A11
EBI_SDA10
EBI_A13
EBI_A14
DDR2_DQM0
DDR2_DQM1
DDR2_DQS0
DDR2_DQS1
DDR2_D0
DDR2_D1
DDR2_D2
DDR2_D3
DDR2_D4
DDR2_D5
DDR2_D6
DDR2_D7
DDR2_D8
DDR2_D9
DDR2_D10
DDR2_D11
DDR2_D12
DDR2_D13
DDR2_D14
DDR2_D15
SW1A
SWITCH-2-1.27mm
1
4
C63
4.7uF
R33
1R
RR17A
RR17B
RR17C
RR17D
RR16A
RR16B
RR16C
RR16D
PD4
R50
R51
R52
R53
R54
R55
1
2
3
4
1
2
3
4
10uH
150mA
27R
27R
7
8
6
5
8
6
7
5
5
7
8
7
6
5
8
6
ON
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD[5..21] {3,5}
C61
4.7uF
L7
27R
R36
R37
EBI_SDCK
EBI_NSDCK
VDDIOM
27R
27R
R32
R35
EBI_SDWE
EBI_SDCKE
27R
27R
R30
R31
27R
27R
27R
27R
EBI_RAS
EBI_CAS
RR1B
RR1A
RR2C
RR1D
RR2A
RR1C
RR2B
RR2D
RR3D
RR4B
RR4A
RR3B
RR3C
RR4D
RR3A
RR4C
R26
R27
R28
R29
2
1
3
4
1
3
2
4
4
2
1
2
3
4
1
3
EBI_DQM0
EBI_DQM1
EBI_DQS0
EBI_DQS1
EBI_D0
EBI_D1
EBI_D2
EBI_D3
EBI_D4
EBI_D5
EBI_D6
EBI_D7
EBI_D8
EBI_D9
EBI_D10
EBI_D11
EBI_D12
EBI_D13
EBI_D14
EBI_D15
13
36
25
48
12
37
34
39
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
A3
E3
J3
N1
P9
J2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
A1
E1
J9
M9
R1
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
100nF
100nF
100nF
100nF
100nF
C60
100nF
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C49 100nF
C44
C45
C46
C47
C48
C65
100nF
VDDNF
C66
100nF
NAND FLASH
NAND_FSH_D0
NAND_FSH_D1
NAND_FSH_D2
NAND_FSH_D3
NAND_FSH_D4
NAND_FSH_D5
NAND_FSH_D6
NAND_FSH_D7
DDR2 SDRAM
DDR_VREF
VDDIOM
DDR2_D0
DDR2_D1
DDR2_D2
DDR2_D3
DDR2_D4
DDR2_D5
DDR2_D6
DDR2_D7
DDR2_D8
DDR2_D9
DDR2_D10
DDR2_D11
DDR2_D12
DDR2_D13
DDR2_D14
DDR2_D15
Figure 4-4.
A0/NBS0
A1/NBS2/DQM2/NWR2
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16/BA0
A17/BA1
A18/BA2
A19
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MN2F
SAM9x5_LBGA217 - EBI
Evaluation Kit Hardware
CM Board External Memory
11115A–ATARM–27-Jul-11
4-9
Evaluation Kit Hardware
4.2.3.6
Serial Peripheral Interface (SPI) Controller
The serial processor provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is
used to interface with the on-board serial DataFlash®.
Figure 4-5.
SPI
VDDIOP0
R56
470K
SW1B
SWITCH-2-1.27mm
3
(SPI0_MOSI) R57
(SPI0_MIS0) R58
(SPI0_SPCK) R59
5
2
6
0R
0R
0R
1
(SPI0_NPCS0)
ON
2
2
PA14
PA12
PA11
PA13
MN7
AT25DF321
SI
SO
SCK
VCC
WP
HOLD
CS
GND
4.2.3.7
8
3
7
VDDIOP0
C69
100nF
4
Two Wire Interface (TWI)
The serial processor has a full speed (400 kHz) master/slave TWI Serial Controller. The controller is
mostly compatible with industry standard I2C and SMBus Interfaces. This port is used to interface with
the on-board Serial EEPROM, ISI, QTouch device and audio codec interface.
Figure 4-6.
TWI
VDDIOP0
VDDIOP0
R61
4.7K
PA31
PA30
R62
4.7K
(TWCKO)
(TWDO)
VDDIOP0
C70
100nF
4.2.3.8
VDDIOP0
R63
10K
MN8
AT24C512BN-SH25-B
6
1
A0 2
5 SCL
SDA
A1 3
A3
8
VCC
4
GND
R64
DNP
7
WP
1-Wire EEPROM
The Evaluation Kit uses a 1-Wire device as “firmware label” to store the information such as chip type,
manufacturer’s name, production date etc.
Figure 4-7.
1-Wire Device
VDDANA
R65
1.5K
0R
2
IO
NC1
NC2
NC3
NC4
GND
R66
3
4
5
6
1
PB18
MN9
DS2431P+
4-10
11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.2.3.9
Optional PHY
Some of the device modules provide a location for a 10/100 Ethernet MAC/PHY interface.
For more information about the Ethernet controller device, refer to the Davicom DM9161 controller manufacturer's datasheet.
Evaluation Kit (EK) User Guide
4-11
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
PB[0..18]
DNP to remain
single PHY
connection on
EK board
1
2
Y3
OE
R70
10K
50MHz
VSS
VDD
OUT
4
3
C71
100nF
VDDANA
R74
22R
42
7
6
5
26
27
28
29
22R
E0_TXCK
2 RR13B
3 RR13C
4 RR13D
6
5
R73
PB4
E0_TX1
E0_TX0
E0_TXEN
3 RR14C
4 RR14D
34
37
17
18
19
20
21
22
PB10
PB9
PB7
E0_RX1
E0_RX0
7
TP27
SMD
PB1
PB0
2 RR15B
R94
10K
R95
DNP
23
30
41
100nF
100nF
VDDANA
39
24
25
32
36
35
16
38
R86
1.5K
E0_RXDV
VDDANA
C79
100nF
40
10
15
33
44
C80
0R
C81
R99
REF_CLK/XT2
MN10
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
RXD3/PHY AD3
RXD2/PHY AD2
RXD1/PHY AD1
RXD0/PHY AD0
RX_CLK/10BTSER
RX_DV/TESTMODE
TX_ER/TXD4
RX_ER/RXD4/RPTR
XT1
TX+
TX-
RX+
RX-
AVDDR
AVDDR
AVDDT
AGND
AGND
AGND
BGRESG
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
DM9161AEP
COL/RMII
CRS/PHY AD4
MDC
MDIO
MDINTR
DISMDIX
DVDD
DVDD
DVDD
DGND
DGND
DGND
PWRDWN
RESET
R100
0R
43
7
8
3
AVDDT
R71
49.9R 1%
100nF
49.9R 1%
R83
TP28
SMD
100nF
4
B1
C73
BLM21BD222TN1
C74
+ C76
10uF
C72
100nF
R72
49.9R 1%
R84
49.9R 1%
C78
100nF
GND_ETH
1
10KX4
RR9
GND_ETH
2
+ C75
10uF
R98
10K
VDDANA
100nF
0R
AVDDT
C77
R97
6.8K
R96
9
5
6
46
47
45
48
31
11
12
13
14
8
7
6
5
1
2
3
4
PB3
RR8
10KX4
DNP
4.7K
10K
6
8
7
8
VDDANA
NRST
R91
R92
R93
3 RR15C
1 RR14A
2 RR14B
1 RR15A
8
7
6
5
E0_RXER
E0_MDC
E0_MDIO
E0_INTR
1
2
3
4
PB2
PB6
PB5
PB8
8
7
6
5
RR7
10KX4
1
2
3
4
GND_ETH
ETH0_TX+
ETH0_TX-
ETH0_RX+
ETH0_RX-
LED0
LED1
LED2
Evaluation Kit (EK) User Guide
4-12
VDDANA
+ C82
10uF
GND_ETH
11115A–ATARM–27-Jul-11
Ethernet
Figure 4-8.
Evaluation Kit Hardware
4.2.3.10 SODIMM200 Interface
The CM board uses SODIMM200 card edge connector to interface with the EK board.
Figure 4-9.
SODIMM200 Interface on CM Board
+3V3
C83
10uF
HHSDPC
HHSDMC
HHSDMB
HHSDPB
DIBP
DIBN
HHSDMA
HHSDPA
VDDNF
NANDOE
NANDALE
NANDCS
NANDR_B
PD8
PD10
PD12
PD14
PD16
PD18
PD20
VDDIOP0
PA0
PA2
PA4
PA11
PA13
PA8
PA22
PA31
PA16
PA18
PA20
PA5
PA10
PA25
PA27
PA29
VDDIOP1
PC0
PC2
PC4
PC7
PC9
PC11
PC12
PC14
PC17
PC19
PC21
PC22
PC24
PC26
PC29
PC31
PB0
PB2
PB4
PB6
PB8
PB9
PB11
PB13
PB15
PB17
PB18
ETH0_TX+
ETH0_TXETH0_RX+
ETH0_RX-
VDDANA
VDDBU
C84
1uF
+3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
J1
VCC_3V3
VCC_3V3
GND
USBC_DP
USBC_DM
GND
USBB_DM
USBB_DP
GND
DIBP
DIBN
GND
USBA_DM
USBA_DP
GND
RFU1
RFU3
RFU5
RFU7
RFU9
VCC_3V3
VCC_3V3
VBAT
JTAGSEL
WKUP
SHDN
BMS
nRST
nTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
RFU2
RFU4
RFU6
RFU8
RFU10
GND
GND
RFU11
RFU12
RFU13
RFU14
RFU15
RFU16
RFU17
RFU18
GND
GND
RFU19
RFU20
RFU21
RFU22
RFU23
RFU24
RFU25
RFU26
VDDNF
VDDNF
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
NC
GND
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
VDDIOP0
VDDIOP0
PA0
PA1
PA2
PA3
PA4
GND
PA11
PA12
PA13
PA14
GND
PA7
PA8
PA21
PA22
PA23
PA31
PA30
GND
PA15
PA16
PA17
PA18
PA19
PA20
GND
PA5
PA6
PA10
PA9
GND
PA24
PA25
PA26
PA27
PA28
PA29
GND
VDDIOP1
VDDIOP1
PC0
PC1
PC2
PC3
PC4
PC5
GND
PC6
PC7
PC8
PC9
PC10
PC11
GND
PC12
PC13
PC14
PC15
GND
PC16
PC17
PC18
PC19
PC20
PC21
GND
PC22
PC23
PC24
PC25
PC26
PC27
GND
PC28
PC29
PC30
PC31
SELCONFIG0
VDDANA
VDDANA
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
GNDANA
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
GNDANA
PB18
ADVREF
GND
LED0
ETH0_TX+
LED1
ETH0_TXLED2
ETH0_RX+
AVDDT
ETH0_RXGND_ETH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
JTAGSEL
WKUP
SHDN
BMS
NRST
NTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
VDDNF
C85
4.7uF
PD5
PD7
PD9
NANDWE
NANDCLE
PD11
PD13
PD15
PD17
PD19
PD21
VDDIOP0
PA1
PA3
C86
4.7uF
PA12
PA14
PA7
PA21
PA23
PA30
PA15
PA17
PA19
PA6
PA9
PA24
PA26
PA28
VDDIOP1
PC1
PC3
PC5
PC6
PC8
PC10
C87
4.7uF
PC13
PC15
PC16
PC18
PC20
+3V3
PC23
PC25
PC27
PC28
PC30
VDDANA
R101
DNP
PB1
PB3
PB5
PB7
ADVREF
PB10
PB12
PB14
PB16
R102
0R
C88
1uF
R101 only if G15, G35, X35
LED0
LED1
LED2
R102 only if G25, X25
AVDDT
PIO 200-pin SODIMM
GND_ETH
Evaluation Kit (EK) User Guide
4-13
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.2.4
Configuration
4.2.4.1
Chip Identification
The CM board may be equipped with any of the five processors, all sharing an identical BGA217 footprint. There are two resistors on the CM board for the purpose of identifying which of the five is the one
actually mounted.
The tables below show in detail how the CM board, relative to different processors, determines the dedicated “SELCONFIG” logic.
Table 4-5. Resistor Identification
Resistor
SAM9G15
SAM9G25
SAM9G35
SAM9X25
SAM9X35
R49
Populated
Not Populated
R50
Not Populated
Populated
R87
Populated
Populated
R88
Not Populated
Not Populated
R101
Populated
Not Populated
Populated
Not Populated
Populated
R102
Not Populated
Populated
Not Populated
Populated
Not Populated
Table 4-6. Module Configuration Identification
CM
Setting
EK
Setting
DM
Setting
4-14
11115A–ATARM–27-Jul-11
SAM9G15
module
SAM9G35
module
SAM9X35
module
SAM9G25
module
SAM9X25
module
R101
Populated
Populated
Populated
Not Populated
Not Populated
R102
Not Populated
Not Populated
Not Populated
Populated
Populated
SELCONFIG
(SODIMM200
pin 166)
High
High
High
Low
Low
USART3
Not Selected
Not Selected
Not Selected
Selected
Selected
ETH1
Not Selected
Not Selected
Not Selected
Not Selected
Selected
LCD
Selected
Selected
Selected
Not Selected
Not Selected
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.2.4.2
Boot Configuration
In order to use SAM-BA boot, the NAND Flash and SPI DataFlash must be deselected. SW1 is dedicated to this purpose.
Table 4-7. Boot Configuration
4.2.5
Designation
Default Setting
Feature
SW1 (1, 4)
ON
Set to OFF disables the NAND flash
SW1 (2, 3)
ON
Set to OFF disables the SPI DataFlash
Connectors
Figure 4-10. CM Board Dimensions
Evaluation Kit (EK) User Guide
4-15
11115A–ATARM–27-Jul-11
A
B
C
DIBN
DIBP
{5}
HHSDMC
HHSDPC
{5}
{5}
{5}
HHSDMB
HHSDPB
{5}
{5}
BMS
HHSDMA
HHSDPA
{5}
{5}
{5}
PWR_EN
{5}
5
R7
R8
R23
R24
R19
R20
VDDIOP0
R11
C1
4.7uF
1
4
27R
27R
39R
39R
R16
6.8K
100K
39R
39R
PWR_EN
EN
IN
2
GND
U17
P9
B7
U15
U14
T15
T14
FB
LX
P11
R11
M17
L17
P17
R17
P16
R16
C31
10pF
MN1
AS1301EHT-adj
2.2uH
3D16
C9
22pF
DIBP
DIBN
HFSDMC
HFSDPC
HHSDMB
HHSDPB
HFSDMB
HFSDPB
VBG
BMS
TST
HHSDMA
HHSDPA
HFSDMA
HFSDPA
TP20
SMD
TP17
SMD
4
R3
59K 1%
R1
118K 1%
TP14
SMD
MN2G
SAM9x5_LBGA217 - INTERFACE
5
3
L1
C2
10uF
VDDIOM
VDDANA
+1V
+3V3
SHDN
WKUP
NRST
NTRST
TDI
TMS
TCK
RTCK
TDO
JTAGSEL
XOUT32
XIN32
XOUT
XIN
D8
A7
P10
T11
T9
U11
U10
R10
T10
D7
A5
A6
U12
T12
R6
DNP
+3V3
TP2
SMD
TP21
SMD
TP18
SMD
TP15
SMD
R18
Y2
+3V3
C10
4.7uF
C19
20pF
C24
SHDN
WKUP
R21
100K
VDDBU
VDDNF
VDDIOP1
FB
LX
3
1
2.2uH
PWR_EN 3
5
3
{5}
{5}
{4,5}
R14
100K
3
TP22
SMD
TP19
SMD
TP16
SMD
R15
100K
VDDIOP0
C17
1uF
+3V3
SHDN
WKUP
NRST
R13
100K
VDDIOP0
100K VDDIOP0
NRST
NTRST
TDI
TMS
TCK
RTCK
TDO
R12
DNP
C29
20pF
20pF
32.768 kHz
VDDBU
20pF
EN
IN
Y1
12MHz
1
4
MN3
AS1301EHT-adj
C22
1
4
D
+3V3
2
3
4
1
2
GND
4-16
2
11115A–ATARM–27-Jul-11
EN
IN
NR
OUT
MN4
TPS71710DCK
3D16
L2
GND
{5}
{5}
{5}
{5}
{5}
{5}
+1V
C41
100nF
+3V3
C38
100nF
+3V3
NTRST
TDI
TMS
TCK
RTCK
TDO
+1V
1
C16
1uF
+3V3
C12
10uF
B2
2
TP1
SMD
VDDNF
C3
4.7uF
C28
4.7uF
C43
4.7uF
L6
10uH/150mA
C39
4.7uF
1R
R25
1R
R22
C34
4.7uF
L4
10uH/150mA
10uH/150mA
L3
C20
100nF
VDDIOP0
120 OHM@100MHZ
L5
10uH/150mA
C32
100nF
C27
100nF
VDDANA
{5}
C18
10nF
R4
59K 1%
R2
39.2K 1%
JTAGSEL
4
5
C11
22pF
VDDCORE
1R
2
TP7
SMD
R17
1R
R10
C21
100nF
C13
100nF
VDDIOM
C6
100nF
2
C30
100nF
C36
1uF
VDDBU
+1V
C25
100nF
C4
100nF
C14
100nF
C7
100nF
C42
100nF
C40
100nF
C37
100nF
TP11
SMD
C35
100nF
ADVREF
C33
100nF
C26
100nF
C23
100nF
VDDIOP1
C5
100nF
C15
100nF
C8
100nF
T13
U16
B5
A4
R12
T17
C6
H4
P7
J14
K14
D10
D13
F14
H14
K8
K9
- POWER
Title:
U13
B6
T16
D6
M4
P6
H9
H10
J9
J10
H8
J8
K10
MBC-SAM9X5
1
Date: Thursday, November 04, 2010
Document Number:
AT91SAM9G45-I&POWER
GNDOSC
GNDBU
GNDUTMI
GNDANA
GNDIOP
GNDIOP
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDCORE
GNDCORE
GNDCORE
Draw By: Zhu Xueliang
Size:
A3
VDDOSC
VDDUTMII
VDDBU
ADVREF
VDDPLLA
VDDUTMIC
VDDANA
VDDIOP1
VDDIOP0
VDDNF
VDDNF
VDDIOM
VDDIOM
VDDIOM
VDDCORE
VDDCORE
VDDCORE
MN2A
SAM9X5_LBGA217
1
SHDN
WKUP
NRST
TDO
Sheet: 1 of 5
Rev:
A
TP13
SMD
TP12
SMD
TP10
SMD
TP9
SMD
TP8
SMD
TP6
SMD
RTCK
TP5
SMD
TCK
TP4
SMD
TP3
SMD
TMS
TDI
NTRST
A
B
C
D
4.2.6
2
5
Evaluation Kit Hardware
Schematics
Figure 4-11. CM Board Schematics – 1of 5
Evaluation Kit (EK) User Guide
Evaluation Kit (EK) User Guide
A
B
C
D
EBI_SDWE
EBI_SDCKE
EBI_SDA10
EBI_SDCK
EBI_NSDCK
A12
B12
C8
D11
C11
P13
R14
R13
P15
P12
P14
N14
R15
M14
N16
N17
N15
K15
M15
L14
M16
L16
L15
K17
J17
K16
J16
D9
C9
C7
A8
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
(NANDOE)
(NANDWE)
(NANDALE)
(NANDCLE)
(NANDCS)
NCS0
EBI_NCS1_SDCS
EBI_RAS
EBI_CAS
B11
C10
B9
B8
EBI_DQM0
EBI_DQM1
EBI_DQS0
EBI_DQS1
EBI_A13
EBI_A14
EBI_A15
EBI_A16
EBI_A17
EBI_A18
EBI_A2
EBI_A3
EBI_A4
EBI_A5
EBI_A6
EBI_A7
EBI_A8
EBI_A9
EBI_A10
EBI_A11
EBI_D0
EBI_D1
EBI_D2
EBI_D3
EBI_D4
EBI_D5
EBI_D6
EBI_D7
EBI_D8
EBI_D9
EBI_D10
EBI_D11
EBI_D12
EBI_D13
EBI_D14
EBI_D15
A10
B10
A11
A9
J15
H16
H15
H17
G17
G16
F17
E17
F16
G15
G14
F15
D17
C17
E16
D16
C16
B17
E15
E14
D14
D15
A16
B16
A17
B15
C14
B14
A15
C15
D12
C13
A14
B13
A13
C12
NCS0
PD[5..21]
4
PD0
PD1
PD2
PD3
PD4
PD6
R38
(NANDOE)
(NANDWE)
(NANDALE)
(NANDCLE)
(NANDCS)
(NANDR/B)
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
{3,5}
TP24
SMD
EBI_NCS1_SDCS
R36
R37
R32
R35
EBI_SDWE
EBI_SDCKE
EBI_SDCK
EBI_NSDCK
R30
R31
R26
R27
R28
R29
2
1
3
4
1
3
2
4
4
2
1
2
3
4
1
3
EBI_RAS
EBI_CAS
EBI_DQM0
EBI_DQM1
EBI_DQS0
EBI_DQS1
EBI_D0
EBI_D1
EBI_D2
EBI_D3
EBI_D4
EBI_D5
EBI_D6
EBI_D7
EBI_D8
EBI_D9
EBI_D10
EBI_D11
EBI_D12
EBI_D13
EBI_D14
EBI_D15
4
27R
27R
27R
27R
27R
27R
27R
27R
27R
27R
27R
RR17A
RR17B
RR17C
RR17D
RR16A
RR16B
RR16C
RR16D
R50
R51
R52
R53
R54
R55
1
2
3
4
1
2
3
4
RR1B
RR1A
RR2C
RR1D
RR2A
RR1C
RR2B
RR2D
RR3D
RR4B
RR4A
RR3B
RR3C
RR4D
RR3A
RR4C
7
8
6
5
8
6
7
5
5
7
8
7
6
5
8
6
0R
0R
0R
0R
0R
0R
8
7
6
5
8
7
6
5
1
NAND_FSH_D0
NAND_FSH_D1
NAND_FSH_D2
NAND_FSH_D3
NAND_FSH_D4
NAND_FSH_D5
NAND_FSH_D6
NAND_FSH_D7
PD4
DDR2_NCS1
DDR2_SDCK
DDR2_NSDCK
DDR2_SDWE
DDR2_SDCKE
DDR2_RAS
DDR2_CAS
DDR2_DQM0
DDR2_DQM1
DDR2_DQS0
DDR2_DQS1
DDR2_D0
DDR2_D1
DDR2_D2
DDR2_D3
DDR2_D4
DDR2_D5
DDR2_D6
DDR2_D7
DDR2_D8
DDR2_D9
DDR2_D10
DDR2_D11
DDR2_D12
DDR2_D13
DDR2_D14
DDR2_D15
SW1A
SWITCH-2-1.27mm
4
3
3
NANDOE
NANDWE
NANDALE
NANDCLE
NANDCS
NANDR_B
ON
5
PD0/NANDOE
PD1/NANDWE
PD2/A21/NANDALE
PD3/A22/NANDCLE
PD4/NCS3
PD5/NWAIT
PD6/D16
PD7/D17
PD8/D18
PD9/D19
PD10/D20
PD11/D21
PD12/D22
PD13/D23
PD14/D24
PD15/D25/A20
PD16/D26/A23
PD17/D27/A24
PD18/D28/A25
PD19/D29/NCS2
PD20/D30/NCS4
PD21/D31/NCS5
MN2E
SAM9x5_LBGA217 - PIOD
NRD
NWR0/NWRE
NWR1/NBS1
NWR3/NBS3/DQM3
NCS0
NCS1/SDCS
SDWE
SDCKE
SDA10
SDCK
#SDCK
RAS
CAS
DQM0
DQM1
DQS0
DQS1
A0/NBS0
A1/NBS2/DQM2/NWR2
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16/BA0
A17/BA1
A18/BA2
A19
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MN2F
SAM9x5_LBGA217 - EBI
5
{5}
{5}
{5}
{5}
{5}
{5}
VDDNF
VDDNF
R46
PD5 R42
R47
R48
PD3 R40
PD2 R43
PD0 R44
PD1 R41
L2
L3
L1
EBI_A16
EBI_A17
EBI_A18
A2
E2
R3
R7
R8
EBI_A15
R49
DNP
470K
0R
470K
470K
WP
RB
1
2
3
4
5
6
10
11
14
15
20
23
24
35
21
22
38
19
7
16
17
8
18
9
B3
F3
DDR2_DQM1
DDR2_DQM0
CLE
ALE
RE
WE
CE
F7
E8
DDR2_DQS0
0R
0R
0R
0R
K3
L7
K7
DDR2_CAS
DDR2_RAS
B7
A8
L8
DDR2_NCS1
DDR2_DQS1
J8
K8
DDR2_SDCK
DDR2_NSDCK
DDR2_SDWE
K2
DDR2_SDCKE
K9
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
EBI_A2
EBI_A3
EBI_A4
EBI_A5
EBI_A6
EBI_A7
EBI_A8
EBI_A9
EBI_A10
EBI_A11
EBI_SDA10
EBI_A13
EBI_A14
MT29F2G08AAD
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
DNU1
DNU2
DNU3
WP
R/B
CLE
ALE
RE
WE
CE
MN11
RFU1
RFU2
RFU3
RFU4
RFU5
UDM
LDM
LDQS
LDQS
UDQS
UDQS
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
BA2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VSS
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
2
2
VSS
VSS
VSS_N.C
VSS_N.C
VCC
VCC
VCC_N.C
VCC_N.C
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8_N.C
I/O9_N.C
I/O10_N.C
I/O11_N.C
I/O12_N.C
I/O13_N.C
I/O14_N.C
I/O15_N.C
A0
DDR2 SDRAM
A1
A2 MT47H64M16HR
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
MN5
13
36
25
48
12
37
34
39
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
A3
E3
J3
N1
P9
J2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
A1
E1
J9
M9
R1
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
C65
100nF
VDDNF
100nF
100nF
100nF
100nF
100nF
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C63
4.7uF
R33
1R
L7
10uH
150mA
C64
104
C62
104
MBC-SAM9X5
R39
1.5K 1%
DDR_VREF
R34
1.5K 1%
1
Date: Thursday, November 04, 2010
Document Number:
AT91SAM9G45-II&DDR2&NAND FLASH
Title:
NAND FLASH
C61
4.7uF
VDDIOM
DDR2 SDRAM
Draw By: Zhu Xueliang
Size:
A3
C66
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C49 100nF
C44
C45
C46
C47
C48
C60
100nF
NAND_FSH_D0
NAND_FSH_D1
NAND_FSH_D2
NAND_FSH_D3
NAND_FSH_D4
NAND_FSH_D5
NAND_FSH_D6
NAND_FSH_D7
DDR_VREF
VDDIOM
DDR2_D0
DDR2_D1
DDR2_D2
DDR2_D3
DDR2_D4
DDR2_D5
DDR2_D6
DDR2_D7
DDR2_D8
DDR2_D9
DDR2_D10
DDR2_D11
DDR2_D12
DDR2_D13
DDR2_D14
DDR2_D15
1
Sheet: 2 of 5
Rev:
A
TP23
SMD
A
B
C
D
Evaluation Kit Hardware
Figure 4-12. CM Board Schematics – 2 of 5
1
11115A–ATARM–27-Jul-11
4-17
11115A–ATARM–27-Jul-11
4-18
A
B
C
D
EBI_SDWE
EBI_SDCKE
EBI_SDA10
EBI_SDCK
EBI_NSDCK
A12
B12
C8
D11
C11
P13
R14
R13
P15
P12
P14
N14
R15
M14
N16
N17
N15
K15
M15
L14
M16
L16
L15
K17
J17
K16
J16
D9
C9
C7
A8
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
(NANDOE)
(NANDWE)
(NANDALE)
(NANDCLE)
(NANDCS)
NCS0
EBI_NCS1_SDCS
EBI_RAS
EBI_CAS
B11
C10
B9
B8
EBI_DQM0
EBI_DQM1
EBI_DQS0
EBI_DQS1
EBI_A13
EBI_A14
EBI_A15
EBI_A16
EBI_A17
EBI_A18
EBI_A2
EBI_A3
EBI_A4
EBI_A5
EBI_A6
EBI_A7
EBI_A8
EBI_A9
EBI_A10
EBI_A11
EBI_D0
EBI_D1
EBI_D2
EBI_D3
EBI_D4
EBI_D5
EBI_D6
EBI_D7
EBI_D8
EBI_D9
EBI_D10
EBI_D11
EBI_D12
EBI_D13
EBI_D14
EBI_D15
A10
B10
A11
A9
J15
H16
H15
H17
G17
G16
F17
E17
F16
G15
G14
F15
D17
C17
E16
D16
C16
B17
E15
E14
D14
D15
A16
B16
A17
B15
C14
B14
A15
C15
D12
C13
A14
B13
A13
C12
NCS0
PD[5..21]
4
PD0
PD1
PD2
PD3
PD4
PD6
R38
(NANDOE)
(NANDWE)
(NANDALE)
(NANDCLE)
(NANDCS)
(NANDR/B)
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
{3,5}
TP24
SMD
EBI_NCS1_SDCS
R36
R37
R32
R35
EBI_SDWE
EBI_SDCKE
EBI_SDCK
EBI_NSDCK
R30
R31
R26
R27
R28
R29
2
1
3
4
1
3
2
4
4
2
1
2
3
4
1
3
EBI_RAS
EBI_CAS
EBI_DQM0
EBI_DQM1
EBI_DQS0
EBI_DQS1
EBI_D0
EBI_D1
EBI_D2
EBI_D3
EBI_D4
EBI_D5
EBI_D6
EBI_D7
EBI_D8
EBI_D9
EBI_D10
EBI_D11
EBI_D12
EBI_D13
EBI_D14
EBI_D15
4
27R
27R
27R
27R
27R
27R
27R
27R
27R
27R
27R
RR17A
RR17B
RR17C
RR17D
RR16A
RR16B
RR16C
RR16D
R50
R51
R52
R53
R54
R55
1
2
3
4
1
2
3
4
RR1B
RR1A
RR2C
RR1D
RR2A
RR1C
RR2B
RR2D
RR3D
RR4B
RR4A
RR3B
RR3C
RR4D
RR3A
RR4C
7
8
6
5
8
6
7
5
5
7
8
7
6
5
8
6
0R
0R
0R
0R
0R
0R
8
7
6
5
8
7
6
5
1
NAND_FSH_D0
NAND_FSH_D1
NAND_FSH_D2
NAND_FSH_D3
NAND_FSH_D4
NAND_FSH_D5
NAND_FSH_D6
NAND_FSH_D7
PD4
DDR2_NCS1
DDR2_SDCK
DDR2_NSDCK
DDR2_SDWE
DDR2_SDCKE
DDR2_RAS
DDR2_CAS
DDR2_DQM0
DDR2_DQM1
DDR2_DQS0
DDR2_DQS1
DDR2_D0
DDR2_D1
DDR2_D2
DDR2_D3
DDR2_D4
DDR2_D5
DDR2_D6
DDR2_D7
DDR2_D8
DDR2_D9
DDR2_D10
DDR2_D11
DDR2_D12
DDR2_D13
DDR2_D14
DDR2_D15
SW1A
SWITCH-2-1.27mm
4
3
3
NANDOE
NANDWE
NANDALE
NANDCLE
NANDCS
NANDR_B
ON
5
PD0/NANDOE
PD1/NANDWE
PD2/A21/NANDALE
PD3/A22/NANDCLE
PD4/NCS3
PD5/NWAIT
PD6/D16
PD7/D17
PD8/D18
PD9/D19
PD10/D20
PD11/D21
PD12/D22
PD13/D23
PD14/D24
PD15/D25/A20
PD16/D26/A23
PD17/D27/A24
PD18/D28/A25
PD19/D29/NCS2
PD20/D30/NCS4
PD21/D31/NCS5
MN2E
SAM9x5_LBGA217 - PIOD
NRD
NWR0/NWRE
NWR1/NBS1
NWR3/NBS3/DQM3
NCS0
NCS1/SDCS
SDWE
SDCKE
SDA10
SDCK
#SDCK
RAS
CAS
DQM0
DQM1
DQS0
DQS1
A0/NBS0
A1/NBS2/DQM2/NWR2
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16/BA0
A17/BA1
A18/BA2
A19
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MN2F
SAM9x5_LBGA217 - EBI
5
{5}
{5}
{5}
{5}
{5}
{5}
VDDNF
VDDNF
R46
PD5 R42
R47
R48
PD3 R40
PD2 R43
PD0 R44
PD1 R41
L2
L3
L1
EBI_A16
EBI_A17
EBI_A18
A2
E2
R3
R7
R8
EBI_A15
R49
DNP
470K
0R
470K
470K
WP
RB
1
2
3
4
5
6
10
11
14
15
20
23
24
35
21
22
38
19
7
16
17
8
18
9
B3
F3
DDR2_DQM1
DDR2_DQM0
CLE
ALE
RE
WE
CE
F7
E8
DDR2_DQS0
0R
0R
0R
0R
K3
L7
K7
DDR2_CAS
DDR2_RAS
B7
A8
L8
DDR2_NCS1
DDR2_DQS1
J8
K8
DDR2_SDCK
DDR2_NSDCK
DDR2_SDWE
K2
DDR2_SDCKE
K9
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
EBI_A2
EBI_A3
EBI_A4
EBI_A5
EBI_A6
EBI_A7
EBI_A8
EBI_A9
EBI_A10
EBI_A11
EBI_SDA10
EBI_A13
EBI_A14
MT29F2G08AAD
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
DNU1
DNU2
DNU3
WP
R/B
CLE
ALE
RE
WE
CE
MN11
RFU1
RFU2
RFU3
RFU4
RFU5
UDM
LDM
LDQS
LDQS
UDQS
UDQS
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
BA2
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VSS
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
2
2
VSS
VSS
VSS_N.C
VSS_N.C
VCC
VCC
VCC_N.C
VCC_N.C
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8_N.C
I/O9_N.C
I/O10_N.C
I/O11_N.C
I/O12_N.C
I/O13_N.C
I/O14_N.C
I/O15_N.C
A0
DDR2 SDRAM
A1
A2 MT47H64M16HR
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
MN5
13
36
25
48
12
37
34
39
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
A3
E3
J3
N1
P9
J2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
A1
E1
J9
M9
R1
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
C65
100nF
VDDNF
100nF
100nF
100nF
100nF
100nF
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C63
4.7uF
R33
1R
L7
10uH
150mA
C64
104
C62
104
MBC-SAM9X5
R39
1.5K 1%
DDR_VREF
R34
1.5K 1%
1
Date: Thursday, November 04, 2010
Document Number:
AT91SAM9G45-II&DDR2&NAND FLASH
Title:
NAND FLASH
C61
4.7uF
VDDIOM
DDR2 SDRAM
Draw By: Zhu Xueliang
Size:
A3
C66
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C49 100nF
C44
C45
C46
C47
C48
C60
100nF
NAND_FSH_D0
NAND_FSH_D1
NAND_FSH_D2
NAND_FSH_D3
NAND_FSH_D4
NAND_FSH_D5
NAND_FSH_D6
NAND_FSH_D7
DDR_VREF
VDDIOM
DDR2_D0
DDR2_D1
DDR2_D2
DDR2_D3
DDR2_D4
DDR2_D5
DDR2_D6
DDR2_D7
DDR2_D8
DDR2_D9
DDR2_D10
DDR2_D11
DDR2_D12
DDR2_D13
DDR2_D14
DDR2_D15
1
Sheet: 2 of 5
Rev:
A
TP23
SMD
A
B
C
D
Evaluation Kit Hardware
Figure 4-13. CM Board Schematics – 3 of 5
1
Evaluation Kit (EK) User Guide
A
B
7
6
8
7
8
2 RR15B
3 RR15C
1 RR14A
2 RR14B
1 RR15A
E0_RXDV
E0_RXER
E0_MDC
E0_MDIO
E0_INTR
PB3
PB2
PB6
PB5
PB8
5
{1,5}
6
5
7
6
5
3 RR14C
4 RR14D
2 RR13B
3 RR13C
4 RR13D
22R
E0_RX1
E0_RX0
E0_TX1
E0_TX0
E0_TXEN
PB10
PB9
PB7
R73
PB1
PB0
E0_TXCK
PB4
Install as need to
alter PHYaddress,
must override internal
pullup on SAM9x5
PB[0..18]
NRST
VDDANA
RR7
10KX4
4
8
7
6
5
1
2
3
4
RR8
10KX4
2
1
VSS
50MHz
OE
Y3
OUT
VDD
VDDANA
3
4
DNP
4.7K
10K
R91
R92
R93
C
{3,5}
8
7
6
5
1
2
3
4
R70
10K
10K
R94
D
DNP
R95
4
R86
TP27
SMD
R74
R99
0R
100nF
100nF
C81
100nF
VDDANA
C80
1.5K
22R
C79
C71
100nF
VDDANA
RESET
PWRDWN
DGND
DGND
DGND
DVDD
DVDD
DVDD
DISMDIX
MDC
MDIO
MDINTR
R100
0R
3
ETHERNET
+ C82
10uF
BGRESG
AGND
AGND
AGND
AVDDT
AVDDR
AVDDR
RX-
RX+
TX-
TX+
XT1
GND_ETH
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
DM9161AEP
COL/RMII
CRS/PHYAD4
TX_ER/TXD4
RX_ER/RXD4/RPTR
RX_CLK/10BTSER
RX_DV/TESTMODE
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
REF_CLK/XT2
MN10
VDDANA
40
10
15
33
44
23
30
41
39
24
25
32
36
35
16
38
34
37
26
27
28
29
17
18
19
20
21
22
42
3
C74
45
48
31
11
12
13
14
47
5
6
46
R97
6.8K
R96
AVDDT
C77
2
9
C73
1
4
3
8
7
43
0R
100nF
100nF
100nF
+ C75
10uF
10K
R98
2
10KX4
2
+ C76
10uF
AVDDT
GND_ETH
RR9
VDDANA
BLM21BD222TN1
B1
8
7
6
5
Evaluation Kit (EK) User Guide
1
2
3
4
5
R71
R83
49.9R 1%
TP28
SMD
49.9R 1%
Draw By: Zhu Xueliang
Size:
A3
GND_ETH
{5}
{5}
ETH0_RX+
ETH0_RX-
Title:
MBC-SAM9X5
{5}
{5}
{5}
{5}
ETH0_TX-
LED0
LED1
LED2
{5}
ETH0_TX+
1
Date: Thursday, November 04, 2010
Document Number:
ETHERNET
49.9R 1%
R84
49.9R 1%
R72
100nF
C78
100nF
GND_ETH
C72
1
Rev:
A
Sheet: 4 of 5
A
B
C
D
Evaluation Kit Hardware
Figure 4-14. CM Board Schematics – 4 of 5
11115A–ATARM–27-Jul-11
4-19
11115A–ATARM–27-Jul-11
4-20
A
B
C
D
PB[0..18]
PC[0..31]
{3}
PA[0..31]
{3,4}
{3}
5
5
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
VDDIOP1
VDDIOP0
{4}
{4}
{4}
{4}
{2}
{2}
{2}
{2}
{1}
{1}
ETH0_TX+
ETH0_TXETH0_RX+
ETH0_RX-
4
NANDOE
NANDALE
NANDCS
NANDR_B
HHSDMA
HHSDPA
DIBP
DIBN
HHSDMB
HHSDPB
{1}
{1}
{1}
{1}
HHSDPC
HHSDMC
{1}
{1}
4
PB0
PB2
PB4
PB6
PB8
PB9
PB11
PB13
PB15
PB17
PB18
PC29
PC31
PC17
PC19
PC21
PC22
PC24
PC26
PC7
PC9
PC11
PC12
PC14
PC0
PC2
PC4
PA25
PA27
PA29
PA16
PA18
PA20
PA5
PA10
PA8
PA22
PA31
PA0
PA2
PA4
PA11
PA13
PD10
PD12
PD14
PD16
PD18
PD20
PD8
VDDANA
VDDNF
C83
10uF
+3V3
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VCC_3V3
VCC_3V3
VBAT
JTAGSEL
WKUP
SHDN
BMS
nRST
nTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
RFU2
RFU4
RFU6
RFU8
RFU10
PIO 200-pin SODIMM
3
GND
GND
RFU11
RFU12
RFU13
RFU14
RFU15
RFU16
RFU17
RFU18
GND
GND
RFU19
RFU20
RFU21
RFU22
RFU23
RFU24
RFU25
RFU26
VDDNF
VDDNF
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
NC
GND
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
VDDIOP0
VDDIOP0
PA0
PA1
PA2
PA3
PA4
GND
PA11
PA12
PA13
PA14
GND
PA7
PA8
PA21
PA22
PA23
PA31
PA30
GND
PA15
PA16
PA17
PA18
PA19
PA20
GND
PA5
PA6
PA10
PA9
GND
PA24
PA25
PA26
PA27
PA28
PA29
GND
VDDIOP1
VDDIOP1
PC0
PC1
PC2
PC3
PC4
PC5
GND
PC6
PC7
PC8
PC9
PC10
PC11
GND
PC12
PC13
PC14
PC15
GND
PC16
PC17
PC18
PC19
PC20
PC21
GND
PC22
PC23
PC24
PC25
PC26
PC27
GND
PC28
PC29
PC30
PC31
SELCONFIG0
VDDANA
VDDANA
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
GNDANA
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
GNDANA
PB18
ADVREF
GND
LED0
ETH0_TX+
LED1
ETH0_TXLED2
ETH0_RX+
AVDDT
ETH0_RXGND_ETH
VCC_3V3
VCC_3V3
GND
USBC_DP
USBC_DM
GND
USBB_DM
USBB_DP
GND
DIBP
DIBN
GND
USBA_DM
USBA_DP
GND
RFU1
RFU3
RFU5
RFU7
RFU9
J1
3
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
+3V3
GND_ETH
VDDANA
VDDNF
VDDBU
C85
4.7uF
AVDDT
PB10
PB12
PB14
PB16
PB1
PB3
PB5
PB7
PC23
PC25
PC27
PC28
PC30
PC13
PC15
PC16
PC18
PC20
PC1
PC3
PC5
PC6
PC8
PC10
PA6
PA9
PA24
PA26
PA28
PA12
PA14
PA7
PA21
PA23
PA30
PA15
PA17
PA19
PA1
PA3
PD11
PD13
PD15
PD17
PD19
PD21
PD5
PD7
PD9
C84
1uF
LED0
LED1
LED2
{2}
{2}
{1}
{1}
{1}
{1}
{1,4}
{1}
{1}
{1}
{1}
{1}
{1}
{1}
{4}
{4}
{4}
C88
1uF
ADVREF
C87
4.7uF
VDDIOP1
C86
4.7uF
VDDIOP0
NANDWE
NANDCLE
JTAGSEL
WKUP
SHDN
BMS
NRST
NTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
2
2
R102
0R
R101
DNP
+3V3
Title:
MBC-SAM9X5
PD[5..21]
1
Date: Thursday, November 04, 2010
Document Number:
AT91SAM9G45-II
Draw By: Zhu Xueliang
Size:
A3
PD5
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
1
{2,3}
Rev:
A
Sheet: 5 of 5
A
B
C
D
Evaluation Kit Hardware
Figure 4-15. CM Board Schematics – 5 of 5
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3
EK Board Description
4.3.1
EK Board Overview
The EK board serves as the main board that carries the CPU module. It features all necessary peripherals and interfaces for processor evaluation.
Figure 4-16. Commented EK Board Layout
Evaluation Kit (EK) User Guide
4-21
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.2
Equipment List
Based on the processor installed on the CM board, the EK board is equipped with the following interfaces or peripherals:
4.3.2.1
Devices
List of the EK board peripherals:
4.3.2.2
4.3.2.3
Two EMAC PHY
One Audio codec
Two high speed MCI Card interfaces
Two CAN transceivers
Three RS232 ports with level translator features: DBGU, USART0 and USART3
One Smart DAA port
Two USB host ports
One USB host/device port
On-board power regulation
LCD/ISI extension interface
ZigBee® interface
One-wire device
Board Interface Connection
Main power supply (J4)
One SODIMM200 socket (CON1)
USB A Host/Device, support USB host/device using a type micro AB connector (J20)
USB B Host, support USB host using a type A connector (J19, upper)
USB C Host, support USB host using a type A connector (J19, lower)
DBGU (RX and TX only) connected to a 9-way male RS232 connector (J11)
USART1 (RX, TX, RTS, CTS) connected to a 9-way male RS232 connector (J8)
USART3 (RX, TX, RTS, CTS) connected to a 9-way male RS232 connector (J12)
JTAG, 20 pin IDC connector (J9)
MicroSD connector (J6)
SD/MMC connector (J7)
Headphone (J15), line-in (J13)
Image sensor connector (J21)
DM board connection for QTouch and TFT LCD display with Touch Screen and backlight (J21, J22)
DAA connecter RJ11 6P4C type (J16)
CAN bus connectors RJ12 6P6C type (CON2, CON3)
ZigBee connector (J10)
Three IO expansion ports (J1, J2, J3)
Test points, various test points are located throughout the board
Push Button Switches
Reset, board reset (BP1)
Wake up, push button to bring the processor out of low power mode (BP2)
4-22
11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.3
Function Blocks
4.3.3.1
Processor
The Evaluation Kit board may be used with any of the Core Modules:
SAM9G15
SAM9G25
SAM9G35
SAM9X25
SAM9X35
Evaluation Kit (EK) User Guide
4-23
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
Figure 4-17. SODIMM Interface on EK Board
3V3
USBC_DP
USBC_DM
USBB_DM
USBB_DP
DIBP
DIBN
USBA_DM
USBA_DP
3V3
CON1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VCC1
VCC3
GND1
USBC_DP
USBC_DM
GND3
USBB_DM
USBB_DP
GND4
DIBP
DIBN
GND5
USBA_DM
USBA_DP
GND6
RFU1
RFU3
RFU5
RFU7
RFU9
VCC2
VCC4
VBAT
JTAGSEL
WKUP
SHDN
BMS
nRST
nTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
RFU2
RFU4
RFU6
RFU8
RFU10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VDDIOP0
R83
4.7k
VBAT
JP9 f or BMS Conf ig:
When Open,BMS=1: Boot on embedded ROM
When Close,BMS=0: Boot on External memory
JP9
WAKE UP
SHDN
BMS
1
NRST
NTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
2
SIP2
JTAG
KEY
VDDNF
PD0
PD2
PD4
PD6
PD8
PD10
PD12
PD14
PD16
PD18
PD20
PA0
PA2
PA4
PA11
PA13
(MCI1_CD)
ZB_RSTN
EN5V_HDA#
EN5V_HDC#
VDDIOP0
(MCI1_DA1)
(MCI1_DA3)
(MCI1_DA0)
(MCI1_CK)
PA8
PA22
PA31
PA16
PA18
PA20
PA5
PA10
PA25
PA27
PA29
PD10
PD12
PD14
PD16
PD18
PD20
TXD0
RTS0
SPI1_NPCS1 PA0
ZB_IRQ1
TWCK0
SPI1_MOSI
PA8
PA22
PA31
PA16
PA18
PA20
PA5
PA10
(MCI0_CDA)
(MCI0_DA1)
(MCI0_DA3)
CANTX1
CANTX0
PA2
PA4
PA11
PA13
DTXD
PA25
PA27
PA29
TF
RD
RF
VDDIOP1
PC0
PC2
PC4
ISI_D0
ISI_D2
ISI_D4
LCDDAT0
LCDDAT2
LCDDAT4
PC0
PC2
PC4
PC7
PC9
PC11
PC12
PC14
ISI_D7
ISI_D9
ISI_D11
ISI_PCK
ISI_HSYNC
LCDDAT7
LCDDAT9
LCDDAT11
LCDDAT12
LCDDAT14
PC7
PC9
PC11
PC12
PC14
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT22
LCDDISP
LCDPWM
PC17
PC19
PC21
PC22
PC24
PC26
LCDDEN
PC29
PC31
PC17
PC19
PC21
PC22
PC24
PC26
PC29
PC31
VDDANA
PB0
PB2
PB4
PB6
PB8
PB9
PB11
PB13
PB15
PB17
PB18
E1_TX1
E1_RX1
E1_INTR
TXD3
RTS3
E1_TXCK
E1_MDIO
E0_RX0
E0_RXER
E0_TXCK
E0_MDC
E0_INTR
E0_TX0
AD0_XP
AD2_YP
AD4_LR
ONE_WIRE
ETH0_TX+
ETH0_TXETH0_RX+
ETH0_RX-
OVCUR_USB
PB0
PB2
PB4
PB6
PB8
PB9
PB11
PB13
PB15
PB17
PB18
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
42
GND7
GND8 44
RFU11
RFU12 46
RFU13
RFU14 48
RFU15
RFU16 50
RFU17
RFU18 52
GND9
GND10 54
RFU19
RFU20 56
RFU21
RFU22 58
RFU23
RFU24 60
RFU25
RFU26 62
VDDNF1
VDDNF2 64
PD0/NANDOE
PD1/NANDWE 66
PD2/A21/NANDALE
PD3/A22/NANDCLE 68
PD4/NCS3
PD5/NWAIT 70
PD6/D16
PD7/D17 72
PD8/D18
PD9/D19 74
NC
GND11 76
PD10/D20
PD11/D21 78
PD12/D22
PD13/D23 80
PD14/D24
PD15/D25/A20 82
PD16/D26/A23
PD17/D27/A24 84
PD18/D28/A25
PD19/D29/NCS2 86
PD20/D30/NCS4
PD21/D31/NCS5 88
VDDIOP0_0
VDDIOP0_1 90
PA0/TXD0/SPI1_NPCS1
PA1/RXD0 92
PA2/RTS0/MCI1_DA1/E0_ETX0
PA3/CTS0/MCI1_DA2/E0_ETX1 94
PA4/SCK0/MCI1_DA3/E0_ETXER
GND12 96
PA11/SPI0_MISO/MCI1_DA0
PA12/SPI0_MOSI/MCI1_CDA 98
PA13/SPI0_SPCK/MCI1_CK
PA14/SPI0_NPCS0 100
GND13
PA7/TXD2 102
PA8/TIOA0/SPI1_MISO
PA21/RXD2/SPI1_NPCS0 104
PA22/TIOA1/SPI1_MOSI
PA23/TIOA2/SPI1_SPCK 106
PA31/TWCK0/SPI1_NPCS2/E0_ETXEN PA30/TWD0/SPI1_NPCS3/E0_EMDC 108
GND14
PA15/MCI0_DA0 110
PA16/MCI0_CDA
PA17/MCI0_CK 112
PA18/MCI0_DA1
PA19/MCI0_DA2 114
PA20/MCI0_DA3
GND16 116
PA5/TXD1/CANTX1
PA6/RXD1/CANRX1 118
PA10/DTXD/CANTX0
PA9/DRXD/CANRX0 120
GND15
PA24/TCLK0/TK 122
PA25/TCLK1/TF
PA26/TCLK2/TD 124
PA27/TIOB0/RD
PA28/TIOB1/RK 126
PA29/TIOB2/RF
GND17 128
VDDIOP1_0
VDDIOP1_1 130
PC0/LCDDAT0/ISI_D0/TWD1
PC1/LCDDAT1/ISI_D1/TWCK1 132
PC2/LCDDAT2/ISI_D2/TIOA3
PC3/LCDDAT3/ISI_D3/TIOB3 134
PC4/LCDDAT4/ISI_D4/TCLK3
PC5/LCDDAT5/ISI_D5/TIOA4 136
GND18
PC6/LCDDAT6/ISI_D6/TIOB4 138
PC7/LCDDAT7/ISI_D7/TCLK4
PC8/LCDDAT8/ISI_D8/UTXD0 140
PC9/LCDDAT9/ISI_D9/URXD0
PC10/LCDDAT10/ISI_D10/PWM0 142
PC11/LCDDAT11/ISI_D11/PWM1
GND19 144
PC12/LCDDAT12/ISI_PCK/TIOA5
PC13/LCDDAT13/ISI_VSYNC/TIOB5 146
PC14/LCDDAT14/ISI_HSYNC/TCLK5
PC15/LCDDAT15/ISI_MCK 148
GND20
PC16/LCDDAT16/E1_RXER/UTXD1 150
PC17/LCDDAT17/URXD1
PC18/LCDDAT18/E1_TX0/PWM0 152
PC19/LCDDAT19/E1_TX1/PWM1
PC20/LCDDAT20/E1_RX0/PWM2 154
PC21/LCDDAT21/E1_RX1/PWM3
GND21 156
PC22/LCDDAT22/TXD3
PC23/LCDDAT23/RXD3 158
PC24/LCDDISP/RTS3
PC25/CTS3 160
PC26/LCDPWM/SCK3
PC27/LCDVSYNC/E1_TXEN/RST1 162
GND22
PC28/LCDHSYNC/E1_CRSDV/CTS1 164
PC29/LCDDEN/E1_TXCK/SCK1
PC30/LCDPCK/E1_MDC 166
PC31/FIQ/E1_MDIO/PCK1
SELCONFIG 168
VDDANA_0
VDDANA_1 170
PB0/E0_RX0/RTS2
PB1/E0_RX1/CTS2 172
PB2/E0_RXER/SCK2
PB3/E0_RXDV/SPI0_NPCS3 174
PB4/E0_TXCK/TWD2
PB5/E0_MDIO/TWCK2 176
PB6/E0_MDC/AD7
PB7/E0_TXEN/AD8 178
PB8/E0_TXER/AD9
GNDANA1 180
PB9/E0_TX0/PCK1/AD10
PB10/E0_TX1/PCK0/AD11 182
PB11/E0_TX2/PWM0/AD0
PB12/E0_TX3/PWM1/AD1 184
PB13/E0_RX2/PWM2/AD2
PB14/E0_RX3/PWM3/AD3 186
PB15/E0_RXCK/AD4
PB16/E0_CRS/AD5 188
PB17/E0_COL/AD6
GNDANA2 190
PB18/IRQ/ADTRG
ADVREF 192
GND23
LED0 194
ETH0_TX+
LED1 196
ETH0_TXLED2 198
ETH0_RX+
AVDDT 200
ETH0_RXGND_ETH
VDDNF
PD1
PD3
PD5
PD7
PD9
PD11
PD13
PD15
PD17
PD19
PD21
PA1
PA3
PA12
PA14
PA7
PA21
PA23
PA30
PA15
PA17
PA19
PD5
PD9
ZB_SLPTR
PD11
PD13
PD15
PD17
PD19
PD21
(MCI1_DA2)
PA1
PA3
(MCI0_CD)
EN5V_HDB#
VDDIOP0
RXD0
CTS0
(MCI1_CDA)
ZB_IRQ0
SPI1_MISO
SPI1_SPCK
TWD0
PA6
PA9
PA24
PA26
PA28
DRXD
(MCI0_DA0)
(MCI0_CK)
(MCI0_DA2)
CANRX1
CANRX0
TK
TD
RK
PA12
PA14
PA7
PA21
PA23
PA30
PA15
PA17
PA19
PA6
PA9
PA24
PA26
PA28
VDDIOP1
PC1
PC3
PC5
PC6
PC8
PC10
LCDDAT1
LCDDAT3
LCDDAT5
LCDDAT6
LCDDAT8
LCDDAT10
PC13
PC15
PC16
PC18
PC20
LCDDAT13 ISI_VSYNC
LCDDAT15 ISI_MCK
E1_RXER
LCDDAT16
E1_TX0
LCDDAT18
E1_RX0
LCDDAT20
PC13
PC15
PC16
PC18
PC20
PC23
PC25
PC27
PC28
PC30
LCDDAT23 RXD3
CTS3
LCDVSYNC
LCDHSYNC
LCDPCK
PC23
PC25
PC27
PC28
PC30
SELCONFIG
VDDANA
PB1
PB3
PB5
PB7
ISI_D1
ISI_D3
ISI_D5
ISI_D6
ISI_D8
ISI_D10
PB1
PB3
PB5
PB7
PC1
PC3
PC5
PC6
PC8
PC10
E1_TXEN
E1_CRSDV
E1_MDC
E0_RX1
E0_RXDV
E0_MDIO
E0_TXEN
PB10 PCK0
PB12
PB14
PB16 VBUS_SENSE
E0_TX1
AD1_XM
AD3_YM
PB10
PB12
PB14
PB16
ADVREF
ETH0_LED0
ETH0_LED1
ETH0_LED2
ETH0_AVDDT
ETH0_GND
1612618-4
4-24
11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.3.2
Power Supplies
The EK Board features one adjustable LDO. It accepts DC 5V power input and outputs a regulated
+3.3V to most other circuits on the board through four 3.3V rails.
VDDPIO0
VDDPIO1
VDDANA
VDDISI
This LDO is enabled through a dual FET scheme. The processor can assert SHDN (which is a VDDBUpowered I/O) to shut down the LDO to enter the so-called backup mode. The regulator on CM board is
also shut down by the action of the SHDN signal.
If the 3V battery is mounted on J5, both CM and EK boards can be woken up by action on the BP2 button, which drives the WKUP signal (also a VDDBU-powered I/O).
JP4
1
C4
100n
3
3V3
D1
J5
BAT54CLT1G
C8
1u
R5
15k
47k
R2
GND
ADJ
VOUT
NC
8
7
6
5
10n
C9
10u
1
C5
SIP2
2
VBAT
VDDIOP1
L17
220ohm at 100MHz
1
2
VDDIOP0
L16
220ohm at 100MHz
1
2
D2
Red
L1
220ohm at 100MHz
1
2
R3
470R
2
3V3
1
VOUT =
0.8V x (Rtop + Rbottom)/Rbottom
2
VDDANA
L2
220ohm at 100MHz
1
2
VDDISI
Figure 4-18. EK Board Power Management
C7
1u
PGOOD
EN
VIN
VDD
C6
10u
SHDN
SIP2
FORCE
POWER
ON
JP5
100n
C57
1
15p
1 C10
5
Q1
6
Si1563EDH
2
PWR_EN#
R4
100k
C120
1u
2
R7
10k
3
5V
4
R8
10k
POWER_EN
5V
PWR_EN
R25
10k
1
Q6
IRLML2402 3
2
3V3
C22
1u
Place C22 near MN3.pin2
R1
100k
1
2
3
4
MN3
RT9018A
EP
3V3
9
Evaluation Kit (EK) User Guide
4-25
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
There is another 3.3V rail, VDDNF, supplied from the CM board. VDDNF is set to 3.3V in the current CM
design. The processors also support a 1.8V NAND Flash device, in which case VDDNF is set to 1.8V. In
order to avoid potential voltage conflict on user-defined applications, a level shifter is inserted between
the PIO lines on VDDNF rail and the 3.3V application.
Figure 4-19. Level Shifter For VDDNF Rail
VDDNF
3V3
MN18
1
2
3
4
5
6
7
8
9
10
11
12
C118 100n
PD17
PD16
PD20
PD19
PD18
VCCA VCCB1
DIR VCCB2
A1
OE
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
GND1
B8
GND2 GND3
24
23
22
21
20
19
18
17
16
15
14
13
C119 100n
EN5V_HDC#
EN5V_HDB#
EN5V_HDA#
ZB_SLPTR
ZB_RSTN
SN74AVC8T245PWR
4.3.3.3
JTAG/ICE
Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a standard USB-to-JTAG in-circuit emulator such as SAM-ICE™.
Figure 4-20. JTAG Interface
VDDIOP0
VDDIOP0
2
4
6
8
10
12
14
16
18
20
4-26
R47
R48
R49
100k
100k
100k
100k
DNP
DNP
DNP DNP
VDDIOP0
J9
BR20-H
11115A–ATARM–27-Jul-11
R46
1
3
5
7
9
11
13
15
17
19
R54
DNP
R50
0R
R51
0R
0R
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
R58
0R
DNP
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.3.4
DBGU
The UART is connected to the DB-9 male socket through an RS-232 Transceiver (TXD and RXD only).
A jumper, JP11, is used to select DBGU or CAN0 between IO (PA9, PA10) sharing scheme. Close JP11
to select DBGU.
Figure 4-21. DBGU Com Port
VDDIOP0
VDDIOP0
2
MN8
17
C1+
C30
100n
R60
100k
100k
4
5 C1C2+
C36
100n
PA10
7
0R
13
R71
0R
10
C38
100n
100n
15
T1
8
T2
J11
1
6
2
7
3
8
4
9
5
14
R1
R73
100k
9
R2
1 EN
2
VDDIOP0
SEL_CAN
R67
V-
C33
10
DRXD
3
V+
C2-
11
PA9
GND
6
12
DTXD
C31
100n
16
18
SD
ADM3222ARW
R72
11
R59
VCC
0R
PWR_EN
EARTH_RS232
1
JP11
SIP2
Evaluation Kit (EK) User Guide
4-27
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.3.5
USART
The USART0 and USART3 are used as serial communication ports. Both USARTs are buffered with an
RS-232 Transceiver (TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male
socket. The software must assign the appropriate PIO pins to enable the USART function.
The USART3 is only supported by SAM9G25 and SAM9X25 processors. The RS-232 Transceiver for
USART3 is enabled by the signal SELCONFIG comprised of a pull down resistor on CM board. Ref to
Section 4.4.1 ”DM Board Overview” for details.
Figure 4-22. USART Com Port
VDDIOP0
R22
R23
R24
C14
4.7u
100n
3
23
C15
100n
1
C18
100n
21
19
47k
PA2
PA0
RTS0
TXD0
R27
R28
0R
0R
PA3
PA1
CTS0
RXD0
R30
R31
0R
0R
47k
5
47k
7
8
9
VCC
C1+
GND
C1-
V+
C2+
V-
C2-
SD
C3+
EN
C3-
T1IN
T2IN
T3IN
10
11
12
T1OUT
T2OUT
T3OUT
R1OUT
R2OUT
R3OUT
R1IN
R2IN
R3IN
6
C16
100n
C17
100n
C19
100n
20
2
4
24
22
18
17
16
15
14
13
RTSC0
TXDC0
R29
0R
CTSC0
RXDC0
VDDIOP1
VDDIOP1
R61
R62
R63
R64
MN9
C28
C29
4.7u
100n
3
23
C35
100n
1
C37
100n
21
19
47k
SELCONFIG
PC24
PC22
RTS3
TXD3
R65
R66
0R
0R
PC25
PC23
CTS3
RXD3
R69
R70
0R
0R
47k
47k
47k
5
7
8
9
10
11
12
VCC
C1+
GND
C1-
V+
C2+
V-
C2-
SD
C3+
EN
C3-
T1IN
T2IN
T3IN
R1OUT
R2OUT
R3OUT
T1OUT
T2OUT
T3OUT
R1IN
R2IN
R3IN
ADM3312EARU
6
C32
100n
C34
100n
C39
100n
20
2
4
24
22
18
17
16
15
14
13
J12
1
6
2
7
3
8
4
9
5
RTSC3
TXDC3
R68
11
(only for SAM9G25/SAM9X25)
10
USART3
4-28
L5
220ohm at 100MHz
1
2
EARTH_RS232
ADM3312EARU
11115A–ATARM–27-Jul-11
J8
1
6
2
7
3
8
4
9
5
11
VDDIOP0
MN4
C13
10
USART0
0R
CTSC3
RXDC3
EARTH_RS232
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.3.6
USB Ports
The Evaluation Kit features three USB communication ports:
Port A
Host High Speed (EHCI) and Full Speed (OHCI) multiplexed with USB
Device High speed Micro AB connector, J20
Port B
Host High Speed (EHCI) and Full Speed (OHCI) standard type A
connector, J19 upper port
Port C
Host Full speed OHCI only standard type A connector, J19 lower port
All three USB Host ports are equipped with 500 mA high-side power switch for self-powered and buspowered applications. The USB device port features VBUS insert detection function through the resistor
ladder R138 and R139.
Refer to the embedded MPU product datasheet for detailed programming information. For datasheet reference numbers and titles, see Section 1.2 ”Applicable Documents”.
Figure 4-23. USB Port (A)
3V3
USB A HOST/DEVICE INTERFACE
R137
47k
L14
1
5V_INTER
2
8
5V
C107
100n
7
+ C106 220ohm at 100MHz
C108
33u
100n
L15
1
C109
100n
6
2
5
MN15
OUTA
ENA
IN
FLGA
GNG
FLGB
OUTB
ENB
1
ACTIVE LOW
LCD_DETECT#
2
3
PB17
OVCUR_USB
4
EN5V_HDA#
AIC1526-0GS
+ C110 220ohm at 100MHz
33u
3V3
R138
C111
15p
SHD
7
J20
VBUS
DM
DP
ID
GND
(VBUS_SENSE)
PB16
R139
47k
R140
47k
1
2
3
4
5
USBA_DM
USBA_DP
(IDUSBA)
6
EARTH_USB
82k
G3515-09010101-00
EARTH_USB
Figure 4-24. USB Port (B & C)
USB HOST B&C INTERFACE
USBB_DP
USBB_DM
L12
1
2
8
5V
C102
100n
C101
100n
+ C103
33u
L13
1
C105
100n
J19
7
220ohm at 100MHz
+ C104
33u
2
220ohm at 100MHz
6
5
MN14
OUTA
ENA
IN
FLGA
GNG
FLGB
OUTB
ENB
1
EN5V_HDB#
2
3
4
OVCUR_USB
PB17
EN5V_HDC#
AIC1526-0GS
Dual USB A
A1
A2
A3
A4
B
1 2
L21
220ohm at 100MHz
1
2
EARTH_USB
Evaluation Kit (EK) User Guide
B1
B2
B3
B4
A
USBC_DM
USBC_DP
3 4
EARTH_USB
4-29
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.3.7
Ethernet 10/100 (EMAC) Port
Except for SAM9G15, the processor has two 10/100 Mbps Ethernet Mac Controllers.
EMAC
SAM9G15
SAM9G35
SAM9X35
SAM9G25
SAM9X25
–
RMII
RMII
MII
MII + RMII
The EK board is equipped with two Davicom DM9161AEP PHYs for each Ethernet port. Both PHY
Transceivers are configured as RMII mode. Both PHY transceivers have an RJ45 port with embedded
transformer and three-status LEDs.
By default, the ETH0 interface is implemented on the EK board. Additionally, for monitoring and control
purposes, an LED functionality is carried on the RJ45 connectors to indicate activity, link, and speed status information for the respective ports.
4-30
11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
PB6
PB5
PB8
PB1
PB0
PB3
PB2
PB10
PB9
PB7
1
2
3
4
R219
R220
R221
E0_MDC
E0_MDIO
E0_INTR
22R
RR17
1
2
3
4
8
7
6
5
22R
NRST
22R
22R
22R
8
7
6
5
22R
RR18
R218
E0_RX1
E0_RX0
E0_RXDV
E0_RXER
E0_TX1
E0_TX0
E0_TXEN
E0_TXCK
RR8
10k
RR7
10k
JP12
VDDANA
RR6
10k
VDDANA
0R
R105
3
4
8
7
6
5
1
2
3
4
PB4
OUT
VDD
VSS
50MHz
OE
Y1
8
7
6
5
1
2
3
4
2
1
8
7
6
5
1
2
3
4
2
100n
R117
EARTH_ETH0
C87
10u
10V
RESET
0R
PWRDWN
DGND
DGND
DGND
DVDD
DVDD
DVDD
DISMDIX
MDC
MDIO
MDINTR
BGRESG
AGND
AGND
AGND
AVDDT
AVDDR
AVDDR
RX-
RX+
TX-
TX+
XT1
ETH0_GND
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
DM9161AEP
COL/RMII
CRS/PHY AD4
TX_ER/TXD4
RX_ER/RXD4/RPTR
RX_CLK/10BTSER
RX_DV/TESTMODE
RXD3/PHY AD3
RXD2/PHY AD2
RXD1/PHY AD1
RXD0/PHY AD0
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
REF_CLK/XT2
MN12
C79
2
100n
100n
FULL DUPLEX
R114
6.8k
R113 0R
ETH0_GND
45
48
31
11
12
13
14
47
5
6
46
E0_AVDDT
9
C82 100n
C77
1
4
3
8
7
43
R171
R172
R173
RR9
10k
0R
0R
0R
2 D7
ETH0_GND
VDDANA
2
C81
10u
10V
2200R
L10
R177
ETH0_GND
C80
10u
10V
1
E0_AVDDT
(Not available for SAM9G15)
ETH0
R119
40
10
15
33
44
23
30
41
VDDANA
0R
100n
100n
C86
39
24
25
32
36
35
16
38
34
37
VDDANA
C85
1.5k
C84
R112
R108
26
27
28
29
17
18
19
20
21
0R DNP 22
42
0R
R106
C75
100n
VDDANA
L19
220ohm at 100MHz
1
2
1
VDDANA
0R DNP
0R DNP
0R DNP
R168
470R
C83
100n
R111
49.9R
R109
49.9R
ETH0_LED2
ETH0_LED1
ETH0_LED0
EARTH_ETH0
0R
R182
C78
100n
0R
0R
R179
R181
0R
R178
Optional PHY
Embedded on CM board
R174
R175
R176
Red
1
R110
49.9R
0R
R107
49.9R
C76
100n
11
10
5
J17
1nF
Right LED
Left LED
8 RD-
6 CT
7 RD+
2 TD-
3 CT
1 TD+
4
0R
0R
0R
0R
0R
DNP
DNP
DNP
DNP
DNP
ETH0_AVDDT
ETH0_TX+
ETH0_TXETH0_RX+
ETH0_RX-
Optional PHY
Embedded on CM board
75 75
R116
R115
75
75
3
6
RX+
RX-
470R
470R
8
7
5
4
2
TX-
EARTH_ETH0
J0026D21B
TX+
1
VDDANA
RJ45 ETHERNET CONNECTOR
R180
R183
R184
R185
R186
Place close to J17
15
10k
8
7
6
5
1
2
3
4
16
9
Evaluation Kit (EK) User Guide
12
R104
Evaluation Kit Hardware
Figure 4-25. ETH0 Port
11115A–ATARM–27-Jul-11
4-31
Evaluation Kit Hardware
Ethernet 1 is only available for SAM9X25. The PHY on Ethernet 1 is enabled by the SELCONFIG signal
from a pull-down resistor on the CM board. Refer to Section 4.4.1 ”DM Board Overview” for detail.
Some pins (PC16, PC20, PC21, PC28, PC26 and PC29) are configured as Ethernet 1 input from PHY
for SAM9X25, whereas they are configured as LCD data pins on other processors. An IO buffer MN17 is
inserted in series with these signals to prevent the LCD from being disturbed by unknown status of the
PHY device.
4-32
11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
PC30
PC31
PC26
PC21
PC20
PC28
PC16
1
2
3
4
1
2
3
4
SELCONFIG
PC29
PC19
PC18
PC27
E1_TXCK
E1_INTR
E1_RXER
1
2
3
4
5
6
7
8
9
10
0R
74AC244SC
GND
OE1
I0
O4
I1
O5
I2
O6
I3
O7
MN17
C100
10u
10V
R136
VDDIOP1
E1_CRSDV
E1_RX0
L20
220ohm at 100MHz
1
2
8
7
6
5
8
7
6
5
E1_RX1
EARTH_ETH1
22R
RR12
22R
RR10
SELCONFIG
8
7
6
5
E1_INTR
SELCONFIG
E1_TXCK
E1_MDC
E1_MDIO
E1_INTR
20
19
18
17
16
15
14
13
12
11
VDDIOP1
GND_ETH1
VCC
OE2
O0
I4
O1
I5
O2
I6
O3
I7
E1_TXCK
E1_TX1
E1_TX0
E1_TXEN
C114 100n
VDDIOP1
E1_RXER
RR13
10k
NRST
SELCONFIG
RR14
10k
RR15
10k
0R
JP13
VDDIOP1
R133
0R
47k
R134
100n
100n
C98
C99
100n
C97
1.5k
40
10
15
33
44
23
30
41
VDDIOP1
39
24
25
32
36
35
16
38
34
37
26
27
28
29
R125
42
OUT
VDD
17
18
19
20
21
0R DNP 22
VSS
50MHz
OE
Y2
0R
2
1
R122
VDDIOP1 R128
E1_CRSDV
E1_RX1
E1_RX0
R121
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
1
2
3
4
22R
RR11
8
7
6
5
1
2
3
4
2
1
C88
100n
RESET
PWRDWN
DGND
DGND
DGND
DVDD
DVDD
DVDD
DISMDIX
MDC
MDIO
MDINTR
BGRESG
AGND
AGND
AGND
AVDDT
AVDDR
AVDDR
RX-
RX+
TX-
TX+
XT1
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
DM9161AEP
COL/RMII
CRS/PHY AD4
TX_ER/TXD4
RX_ER/RXD4/RPTR
RX_CLK/10BTSER
RX_DV/TESTMODE
RXD3/PHY AD3
RXD2/PHY AD2
RXD1/PHY AD1
RXD0/PHY AD0
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
REF_CLK/XT2
MN13
3
4
VDDIOP1
C92
2
100n
100n
45
48
31
11
12
13
14
47
5
6
46
R130
6.8k
R129 0R
E1_AVDDT
9
C95 100n
C90
1
4
3
8
7
43
2200R
L11
C93
10u
10V
1
2
R124
49.9R
C89
100n
1 Red
EARTH_ETH1
2 D8
FULL DUPLEX
RR16
10k
VDDIOP1GND_ETH1
C96
100n
C91
100n
75 75
470R
VDDIOP1
Right LED
Left LED
R169
11
10
5
4
8 RD-
6 CT
7 RD+
2 TD-
3 CT
1nF
J18
J0026D21B
R132
R131
75
75
2
3
6
TX-
RX+
RX-
470R
470R
8
7
5
4
1
TX+
EARTH_ETH1
VDDIOP1
RJ45 ETHERNET CONNECTOR
1 TD+
GND_ETH1
GND_ETH1
R127
49.9R
E1_AVDDT
R123
49.9R
E1_AVDDT
R126
49.9R
C94
10u
10V
ETH1
(Only availabel for SAM9X25)
15
10k
8
7
6
5
1
2
3
4
16
9
Evaluation Kit (EK) User Guide
12
R120
Evaluation Kit Hardware
Figure 4-26. ETH1 Port
11115A–ATARM–27-Jul-11
4-33
11115A–ATARM–27-Jul-11
4-34
2
1
C61
470p
1
AUDIO_GND
3
2
R162
R91
47k
C60
C59
0R
DNP
470p
C44
C121
22p
220uF/10V
220uF/10V
AUDIO_GND
AUDIO_GND
470p
C41
AUDIO_GND
R90
47k
L7
220ohm at 100MHz
1
2
AUDIO_GND
5.6K
R81
AUDIO_GND
5.6K
R80
R78
5.6K
L6
220ohm at 100MHz
1
2
C62
470p
AUDIO_GND
C43
470p
L4
220ohm at 100MHz
1
2
22R DNP
L3
R74
220ohm at 100MHz
5.6K
1
2
PCK0
+
4
STEREO_3.5mm
J15
5
HEADPHONE
C42
4
3 470p
STEREO_3.5mm
J13
AUDIO_GND
5
LINE_IN
PB10
R164
2
LHPOUT
9
OSC
AUDIO_GND
15
AGND
RHPOUT
MICBIAS
MICIN
10
17
100n 18
C55
RLINEIN
19
1u
C52
LLINEIN
20
ROUT
13
XTO
26
LOUT
XTI/MCLK
25
12
CLKOUT
2
MN10
Y3
12.288MHz
C122
22p
1u
3
C49
1
11
HPGND
28
DGND
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
VMID
HPVDD
AVDD
DCVDD
DBVDD
MODE
CSB
SDIN
SCLK
C56
R88
R89
R86
R87
C54
VCC_DAC
VDDIOP0
TWI_addr
TWD0
TWCK0
R75
10k
0R
0R
0R
33R
C115
10u
VDDIOP0
R77
4.7k
100n
10u
10u
100n
10u
PA28
PA24
PA26
PA25
PA27
PA29
AUDIO_GND
AUDIO_GND
R79
4.7k
VDDIOP0
C116
100n
R165
0R
AUDIO_GND
C117
100n
VCC_DAC
L18
220ohm at 100MHz
1
2
RK
TK
TD
TF
RD
RF
100n
10u
100n
100n
C53
10u
C51
C50
C47
C48
C46
C45
C40
R76
10k
CSB = 1:
addr=0011011
IIS of Audio Interface
in Slave Mode
3
4
5
6
7
16
8
14
27
1
21
22
23
24
WM8731SEDS
MODE = 0: 2-wire
MPU mode for 9x5
TWI interface
PA30
PA31
4.3.3.8
4
R164 near SODIMM
R162 near CODEC
Evaluation Kit Hardware
Audio
The Evaluation Kit includes a WM8731 CODEC for digital sound input and output. This interface
includes audio jacks for line audio input (J13) and headphone line output (J15).
The SAM9 processor is configured in IIS slave mode to interface with the WM8731 Codec. The IIS master mode is also possible for evaluation by populating R162/R164 and removing the crystal Y3.
Figure 4-27. Audio Interface
+
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.3.9
1-Wire EEPROM
The EK board also features a 1-Wire device acting as a “firmware label” to store information like chip
type, manufacturer’s name, production date etc.
Figure 4-28. 1-Wire on EK
VDDANA
R144
1.5k
R145
ONE_WIRE
PB18
2
0R
MN16
I/O
1
GND
NC1
NC2
NC3
NC4
3
4
5
6
DS2431P
4.3.3.10 CAN Bus
Two boards, the SAM9X35-EK and SAM9X25-EK, feature two Controller Area Network (CAN) ports with
transceiver.
CAN0 uses the same IOs (PA9, PA10) as the DBGU. A jumper, JP11, is used to select either of the
interfaces.
Open JP11 to select the CAN function.
Close JP11 to select the DBGU function.
A 3-state output buffer, MN19 is inserted in series with the output channels of the CAN transceiver,
which share IOs with the DBGU. This is necessary because the CAN transceiver does not feature
3-state outputs.
Figure 4-29. CAN on EK
JP7
(only for SAM9X35/SAM9X25)
PA10
CANTX0
1
PA9
R21
10k
8
R20
0R
1
5
SEL_CAN
2
CANRX0
3
MN19
OE VCC
A
Y
5
VDDIOP0
1
MN5
4
RS
D
CANH
CANL
EN
VCC
R
GND
120R
SIP2
7
6
3V3
5V
VDDIOP0
3
2
SN65HVD234DR
4
R19
2
CON2
1
2
3
4
5
6
CAN0
MJM0606GE06-H
C20
100n
C21
10u
GND
SN74LVC1G126DBV
JP8
1
MN6
PA5
CANTX1
VDDIOP0
PA6
CANRX1
R32
10k
8
R33
0R
1
R35
5
10k
R37
0R
4
RS
D
CANH
CANL
EN
VCC
R
GND
2
7
6
VDDIOP0
3
2
SN65HVD234DR
3V3
5V
CON3
1
2
3
4
5
6
CAN1
MJM0606GE06-H
C23
100n
Evaluation Kit (EK) User Guide
R34
120R
SIP2
C24
10u
4-35
11115A–ATARM–27-Jul-11
DIBP
DIBN
0R
R167
150pF
C71
0R
R166
0R can be replaced by
bead to improve EMI
150pF
C72
4
1
LAN0066-50
3
TX1
2
C70
47pF
DAA_GND
C73
100n
DVDD
DAA_GND
C66
100n
DAA_GND
C65
100n
DVDD
DIBP
DIBN
AVDD
PWR
TEST
DAA_GND
C74
100n
1
14
16
2
15
13
7
8
9
10
6
11
5
R93
0805
6.81M
R99
1
DAA_GND
R102
110R
MMBAT42
Q3
100R
1
DAA_GND
6.81M
DAA_GND 100V
C68 47n
100n
237K
R94
C67
CX20548-11Z
GPIO
TXF
TXO
EIF
EIO
RXI
EIC
TAC
RAC
4
0805
D3
MMBD3004S-7-F
2
R100
3.01R
1%
1
MMBAT42 DAA_GND
Q2
C69
10n
D5 MMBD3004S-7-F
1
2
1
3
2
R92
3
2
3
3
12
VC
3
EP
17
3
2
2
R103
9R1
1%
1206
Q4
MMBAT42
1
3
R101
3.01R
1%
1
2
L9
220ohm at 100MHz
1
L8
220ohm at 100MHz
1
2
1
4-36
2
11115A–ATARM–27-Jul-11
2
MN11
MMBAT42
Q5
470p
C64
470p
C63
R96
280R
1%
1206
R95
280R
1%
1206
TB3100M-13-F
D4
R97
280R
1%
1206
RJ11
R98
280R
1%
1206
MJM0606GE06-H
J16
1
2
3
4
5
6
Evaluation Kit Hardware
4.3.3.11 Telephone Interface
The Evaluation Kit features a smart DAA (Data Access Arrangement) chip to drive an analog telephone
line on RJ11 6P4C port (J16).
Figure 4-30. Telephone Interface
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.3.12 SD/MMC Interface
The Evaluation Kit has two high-speed MultiMedia Card Interfaces (MCI). The first interface is used as a
4-bit interface (MCI0), connected to a MicroSD card slot. The second interface is used as a 4-bit interface (MCI1), connected to an SD/MMC card slot.
The memory card is not included in the Evaluation Kit.
Please note that the power is connected to VCC, which is 3.3 volts.
Figure 4-31. SD/MMC Interface
VDDNF
VDDIOP0
R10 R11 R12 R13
R9
10k
R14
10k
68k 68k 68k 68k
PA17
PA16
PA20
PA19
RR1
1
2
3
4
(MCI0_DA1)
(MCI0_DA0)
(MCI0_CK)
1
2
3
4
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
RR2
8
7
6
5
C11
100n
27R
VDDIOP0
JP6
1
R15 R16 R17 R18
2
PA13
PA12
PA4
PA3
RR3
10k
(MCI1_WP)
(MCI1_CD)
(MCI1_CK)
RR4 27R
1
8
2
7
3
6
4
5
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
1
2
3
4
(MCI1_DA1)
(MCI1_DA0)
8 RR5
7 27R
6
5
8
7
6
5
4
3
2
1
9
3V3
C12
100n
Evaluation Kit (EK) User Guide
PJS008-2110-0
9
1
2
3
4
68k 68k 68k 68k
PA2
PA11
11
12
13
14
VDDNF
SIP2
PD14
Micro SD
J6
10
8 SW2
7
6
5
4
3
2
1
27R
8
7
6
5
SW1
PA18
PA15
(MCI0_CD)
8
7
6
5
PD15
J7
DAT1
DAT0
VSS
CLK
VDD
VSS
CMD
DAT3
DAT2
CD
WP
GND
GND
SH
SH
10
11
12
13
14
15
7SDCN-B0-0101-F
4-37
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.3.13 ZigBee
The EK board has a 10-pin male connector for the Atmel RZ600 ZigBee module.
DNP 0 Ohm resistors have been implemented in series with the PIO lines that are used elsewhere in the
design. Thereby, enable their individual disconnections, should a conflict occur in user application.
Figure 4-32. ZigBee Interface
DNP
DNP
DNP
DNP
PD16
ZB_IRQ1
SPI1_NPCS1
SPI1_MISO
ZB_RSTN
PA13
PA0
PA21
R52
R56
R55
R82
0R
0R
0R
0R
1
3
5
7
9
J10
DNP
DNP
2
4
6
8
10
R53
R57
0R
0R
HD2X05
C25
15p
ZB_IRQ0
PD17
SPI1_MOSI
SPI1_SPCK
2
1
JP10
C27 DNPDNP
2.2u
C26
2.2n
PA7
ZB_SLPTR
PA22
PA23
3V3
4.3.3.14 LED Indicators
The EK board has three LED indicators for purposes shown below:
Table 4-8. LED Indicators
Reference
Color
Function
D2
Red
3v3 Power indicator
D7
Red
ETH0 Full Duplex
D8
Red
ETH1 Full Duplex
Refer to Section 4.3.3.2 ”Power Supplies” and Section 4.3.3.7 ”Ethernet 10/100 (EMAC) Port” for
details.
4.3.3.15 Expansion Ports
Most GPIOs are routed to expansion ports J1, J2, J3.
All I/Os of the MPU Image Sensor Interface (ISI) are routed to connectors J21.
The LCD and touch screen interfaces are routed to connectors J21, J22.
Figure 4-33. I/O Expansion
3V3
5V
3V3
JP1
3V3
4-38
11115A–ATARM–27-Jul-11
3V3
5V
JP3
3
1
3
1
3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J1
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J2
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J3
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
3V3
3V3
2
2
1
2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
5V
JP2
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
3V3
3V3
PB16
PB17
PB18
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
3V3
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
Figure 4-34. LCD and ISI Expansion
3V3_LCD
3V3
R5
R6
0R DNP
0R DNP
CHANGE#
ZB_IRQ0
TWCK0
LCDDAT1
LCDDAT3
LCDDAT5
LCDDAT7
LCDDAT9
LCDDAT11
J2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
TWD0
LCDDAT15
LCDDAT13
LCDDAT14
LCDDAT12
LCDDAT0
LCDDAT2
LCDDAT4
LCDDAT6
LCDDAT8
LCDDAT10
TSM-115-01-L-DV-A
5V_INTER
LCDDAT16
LCDDAT18
LCDDAT20
LCDDAT22
LCDDISP
LCDVSY NC
LCDDEN
AD0_XP
AD2_Y P
AD4_LR
SELCONFIG R22
0R
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT23
LCDPWM
LCDHSY NC
LCDPCK
AD1_XM
AD3_Y M
R19
0R
LCD_DETECT R23
ONE_WIRE
0R
TSM-120-01-L-DV-A
4.3.4
Configuration
This section describes the PIO usage, the jumpers, the test points and the solder drops of the EK board.
4.3.4.1
JTAG/ICE Configuration
Table 4-9. JTAG/ICE
4.3.4.2
Designation
Default Setting
Feature
R50
Not Populated
R51
Populated
Enables the ICE RTCK return. R94 must
be opened
R54
Populated
Enables the ICE NRST input
R58
Not Populated
Disables the ICE NTRST input
Disables TCK <-> RTCK local loop
Boot Mode Select Configuration
Table 4-10. BMS
Designation
Default Setting
JP9
Open
Evaluation Kit (EK) User Guide
Feature
Default to boot on embedded ROM
Close to boot on external memory
4-39
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.4.3
Force Power ON Configuration
Table 4-11. Force Power ON
4.3.4.4
Designation
Default Setting
JP5
Close
Feature
Keep on-board regulator always on
Open to feature SHDN function
White Protection Configuration on MCI1
Table 4-12. Write Protection on MCI1
4.3.4.5
Designation
Default Setting
JP6
Close
Feature
MCI1 write protect selected
Open to disable protection
Selection between DBGU and CAN
Table 4-13. Select DBGU or CAN
4.3.4.6
Designation
Default Setting
JP11
Close
Feature
Default to select DBGU
Open to select CAN0
Codec IIS Configuration
Table 4-14. Codec IIS
4.3.4.7
Designation
Default Setting
R162, R164
Not Populated
C121, C122, Y3
Populated
Feature
IIS master mode, clock the codec by PCK0
IIS slaver mode, clock the codec by
external crystal
ETH0 Configuration
Table 4-15. ETH0
4-40
11115A–ATARM–27-Jul-11
Designation
Default Setting
R180, R183, R184,
R185, R185, R186,
R174, R175, R176
Not Populated
R177, R178, R179,
R181, R182, R218,
R171, R172, R173
Populated
Feature
Populated to select the PHY channel on
CM. Channel on EK must be cut if select
the PHY on CM.
Selection of PHY channel on EK
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.4.8
PIO Usage
Table 4-16. PIO A Pin Assignment and Signal Description
Signal
Alternate
Periph A
Periph B
Periph C
PA0
TXD0
SPI1_NPCS1
TXD0/ ZigBee
USART0 shared with ZigBee
PA1
RXD0
SPI0_NPCS2
RXD0
USART0
PA2
RTS0
MCI1_DA1
E0_ETX0
RTS0/ MCI1
USART0 shared with MCI1
PA3
CTS0
MCI1_DA2
E0_ETX1
CTS0/ MCI1
USART0 shared with MCI1
PA4
SCK0
MCI1_DA3
E0_ETXER
MCI1
PA5
TXD1
CANTX1
CAN1
PA6
RXD1
CANRX1
CAN1
PA7
TXD2
SPI0_NPCS1
ZB_IRQ0
PA8
RXD2
SPI1_NPCS0
DataFlash
PA9
CANRX0
DBGU+CAN0
DBGU shared with CAN0
PA10
CANTX0
DBGU+CAN0
DBGU shared with CAN0
PA11
SPI0_MISO
MCI1_DA0
MCI1
PA12
SPI0_MOSI
MCI1_CDA
MCI1
PA13
SPI0_SPCK
MCI1_CK
MCI1
PA14
SPI0_NPCS0
MCI0
PA15
MCI0_DA0
MCI0
PA16
MCI0_CDA
MCI0
PA17
MCI0_CK
MCI0
PA18
MCI0_DA1
MCI0
PA19
MCI0_DA2
MCI0
PA20
MCI0_DA3
DataFlash
PA21
TIOA0
SPI1_MISO
ZigBee
DataFlash
PA22
TIOA1
SPI1_MOSI
ZigBee
DataFlash
PA23
TIOA2
SPI1_SPCK
ZigBee
SSC
PA24
TCLK0
TK
SSC
PA25
TCLK1
TF
SSC
PA26
TCLK2
TD
SSC
PA27
TIOB0
RD
SSC
PA28
TIOB1
RK
SSC
PA29
TIOB2
RF
SSC
PA30
TWD0
SPI1_NPCS3
E0_EMDC
TWD0
PA31
TWCK0
SPI1_NPCS2
E0_ETXEN
TWCK0
Evaluation Kit (EK) User Guide
ZB_IRQ1
4-41
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
Table 4-17. PIO B Pin Assignment and Signal Description
Signal
Alternate
Periph A
Periph B
Periph C
Module CM
PB0
E0_RX0
RTS2
ETH0
PB1
E0_RX1
CTS2
ETH0
PB2
E0_RXER
SCK2
ETH0
PB3
E0_RXDV
SPI0_NPCS3
ETH0
PB4
E0_TXCK
TWD2
ETH0
PB5
E0_MDIO
TWCK2
ETH0
EK
PB6
AD7
E0_MDC
ETH0
PB7
AD8
E0_TXEN
ETH0
PB8
AD9
E0_TXER
ETH0_INTR
PB9
AD10
E0_TX0
PCK1
ETH0
PB10
AD11
E0_TX1
PCK0
ETH0
PB11
AD0xp
E0_TX2
PWM0
TSC
PB12
AD1xm
E0_TX3
PWM1
TSC
PB13
AD2yp
E0_RX2
PWM2
TSC
PB14
AD3ym
E0_RX3
PWM3
TSC
PB15
AD4lr
E0_RXCK
TSC
PB16
AD5
E0_CRS
VBUS_SENSE (USB)
PB17
AD6
E0_COL
OVCUR_USB (Open drain)
PB18
4-42
11115A–ATARM–27-Jul-11
IRQ
ADTRG
USER_LED1#
ONE_WIRE
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
Table 4-18. PIO C Pin Assignment and Signal Description
Signal
Alternate
Periph A
Periph B
Periph C
EK f (LCD)
EK f (ISI+IO)
PC0
LCDDAT0
ISI_D0
TWD1
LCDDAT0
ISI_D0
PC1
LCDDAT1
ISI_D1
TWCK1
LCDDAT1
ISI_D1
PC2
LCDDAT2
ISI_D2
TIOA3
LCDDAT2
ISI_D2
PC3
LCDDAT3
ISI_D3
TIOB3
LCDDAT3
ISI_D3
PC4
LCDDAT4
ISI_D4
TCLK3
LCDDAT4
ISI_D4
PC5
LCDDAT5
ISI_D5
TIOA4
LCDDAT5
ISI_D5
PC6
LCDDAT6
ISI_D6
TIOB4
LCDDAT6
ISI_D6
PC7
LCDDAT7
ISI_D7
TCLK4
LCDDAT7
ISI_D7
PC8
LCDDAT8
ISI_D8
UTXD0
LCDDAT8
ISI_D8
PC9
LCDDAT9
ISI_D9
URXD0
LCDDAT9
ISI_D9
PC10
LCDDAT10
ISI_D10
PWM0
LCDDAT10
ISI_D10
PC11
LCDDAT11
ISI_D11
PWM1
LCDDAT11
ISI_D11
PC12
LCDDAT12
ISI_PCK
TIOA5
LCDDAT12
ISI_PCK
PC13
LCDDAT13
ISI_VSYNC
TIOB5
LCDDAT13
ISI_VSYNC
PC14
LCDDAT14
ISI_HSYNC
TCLK5
LCDDAT14
ISI_HSYNC
PC15
LCDDAT15
ISI_MCK
PCK0
LCDDAT15
ISI_MCK/PCK0
PC16
LCDDAT16
E1_RXER
UTXD1
LCDDAT16
E1_RXER
PC17
LCDDAT17
URXD1
LCDDAT17
PC18
LCDDAT18
E1_TX0
PWM0
LCDDAT18
E1_TX0
PC19
LCDDAT19
E1_TX1
PWM1
LCDDAT19
E1_TX1
PC20
LCDDAT20
E1_RX0
PWM2
LCDDAT20
E1_RX0
PC21
LCDDAT21
E1_RX1
PWM3
LCDDAT21
E1_RX1
PC22
LCDDAT22
TXD3
LCDDAT22
TXD3
PC23
LCDDAT23
RXD3
LCDDAT23
RXD3
PC24
LCDDISP
RTS3
LCDDISP
RTS3
PC25
SSC
CTS3
CTS3
PC26
LCDPWM
SCK3
PC27
LCDVSYNC
E1_TXEN
RTS1
LCDVSYNC
E1_TXEN
PC28
LCDHSYNC
E1_CRSDV
CTS1
LCDHSYNC
E1_CRSDV
PC29
LCDDEN
E1_TXCK
SCK1
LCDDEN
E1_TXCK
PC30
LCDPCK
E1_MDC
LCDPCK
E1_MDC
PC31
FIQ
E1_MDIO
Evaluation Kit (EK) User Guide
Eth1_Intr1
PCK1
LCDPWM
E1_MDIO
4-43
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
Table 4-19. PIO D Pin Assignment and Signal Description
Signal
Alternate
Periph A
Periph B
Periph C
Module CM
EK
PD0
NANDOE
Nand Flash
PD1
NANDWE
Nand Flash
PD2
A21/NANDALE
Nand Flash
PD3
A22/NANDCLE
Nand Flash
PD4
NCS3
CS NAND Flash
PD5
NWAIT
NAND_RD/BY
PD6
D16
Nand Flash
PD7
D17
Nand Flash
PD8
D18
Nand Flash
PD9
D19
Nand Flash
PD10
D20
Nand Flash
MCI0_CD (switch)
PD11
D21
Nand Flash
MCI1_CD (switch)
PD12
D22
Nand Flash
ZB_RSTN
PD13
D23
Nand Flash
ZB_SLPTR
PD14
D24
PD15
D25
A20
EN5V_HDB#
PD16
D26
A23
EN5V_HDC#
PD17
D27
A24
PD18
D28
A25
PD19
D29
NCS2
PD20
D30
NCS4
PD21
D31
NCS5
4-44
11115A–ATARM–27-Jul-11
EN5V_HDA#
POWR_LED
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.5
Connectors
4.3.5.1
Power Supply
Figure 4-35. Power Supply Connector J4
Table 4-20. Power Supply Connector J2 Signal Description
4.3.5.2
Pin
Mnemonic
Signal description
1
Center
+5V
2
GND
3
Floating
SODIMM Card Edge Socket
The Evaluation Kit uses a SODIMM200 standard connector for CM board interfacing.
Please note that this is not an industry standard pin-out and that it is unlikely to be compatible with offthe-shelf SODIMM cards.
Figure 4-36. SODIMM200 Socket CON1
Table 4-21. SODIMM200 CON1 Signal Descriptions
Function
Type
x5 pad name
Front Side
SODIMM 200
x5 pad name
A
B
Type
Function
Back Side
VCC 3V3
POWER OUTPUT
1
2
POWER OUTPUT
VCC 3V3
VCC 3V3
POWER OUTPUT
3
4
POWER OUTPUT
VCC 3V3
5
6
POWER OUTPUT
GND
VBAT
USBC_DP
I/O
USB Data Positive
7
8
SYSC
JTAGSEL
USBC_DM
I/O
USB Data Negative
9
10
SYSC
WKUP
11
12
SYSC
SHDN
GND
Evaluation Kit (EK) User Guide
4-45
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
Table 4-21. SODIMM200 CON1 Signal Descriptions (Continued)
Function
Type
x5 pad name
USBB_DM
I/O
USB Data Negative
13
USBB_DP
I/O
USB Data Positive
GND
SODIMM 200
x5 pad name
Type
Function
14
SYSC
BMS
15
16
SYSC
nRST
17
18
SYSC
nTRST
DIBP
I/O
19
20
RSTJTAG
TDI
DIBN
I/O
21
22
RSTJTAG
TCK
23
24
RSTJTAG
TMS
GND
USBA_DM
I/O
USB Data Negative
25
26
RSTJTAG
TDO
USBA_DP
I/O
USB Data Positive
27
28
RSTJTAG
RTCK
29
30
GND
PWR_EN
RFU
RFU
31
32
RFU
RFU
RFU
RFU
33
34
RFU
RFU
RFU
RFU
35
36
RFU
RFU
RFU
RFU
37
38
RFU
RFU
RFU
RFU
39
40
RFU
RFU
KEY
GND
41
42
GND
RFU
RFU
43
44
RFU
RFU
RFU
RFU
45
46
RFU
RFU
RFU
RFU
47
48
RFU
RFU
RFU
RFU
49
50
RFU
RFU
51
52
GND
GND
RFU
RFU
53
54
RFU
RFU
RFU
RFU
55
56
RFU
RFU
RFU
RFU
57
58
RFU
RFU
RFU
RFU
59
60
RFU
RFU
61
62
VDDNF
POWER DOMAIN FROM CM
POWER DOMAIN FROM CM
VDDNF
PD0
GPIO D
NANDOE
63
64
NANDWE
GPIO D
PD1
PD2
GPIO D
A21/NANDALE
65
66
A22/NANDCLE
GPIO D
PD3
PD4
GPIO D
NCS3
67
68
NWAIT
GPIO D
PD5
PD6
GPIO D
D16
69
70
D17
GPIO D
PD7
PD8
GPIO D
D18
71
72
D19
GPIO D
PD9
73
74
GND
GND
PD10
GPIO D
D20
75
76
D21
GPIO D
PD11
PD12
GPIO D
D22
77
78
D23
GPIO D
PD13
PD14
GPIO D
D24
79
80
D25/A20
GPIO D
PD15
PD16
GPIO D
D26/A23
81
82
D27/A24
GPIO D
PD17
PD18
GPIO D
D28/A25
83
84
D29/NCS2
GPIO D
PD19
4-46
11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
Table 4-21. SODIMM200 CON1 Signal Descriptions (Continued)
Function
Type
x5 pad name
USBB_DM
I/O
USB Data Negative
13
USBB_DP
I/O
USB Data Positive
GND
SODIMM 200
x5 pad name
Type
Function
14
SYSC
BMS
15
16
SYSC
nRST
17
18
SYSC
nTRST
DIBP
I/O
19
20
RSTJTAG
TDI
DIBN
I/O
21
22
RSTJTAG
TCK
23
24
RSTJTAG
TMS
GND
USBA_DM
I/O
USB Data Negative
25
26
RSTJTAG
TDO
USBA_DP
I/O
USB Data Positive
27
28
RSTJTAG
RTCK
29
30
GND
PWR_EN
RFU
RFU
31
32
RFU
RFU
RFU
RFU
33
34
RFU
RFU
RFU
RFU
35
36
RFU
RFU
RFU
RFU
37
38
RFU
RFU
RFU
RFU
39
40
RFU
RFU
KEY
GND
41
42
GND
RFU
RFU
43
44
RFU
RFU
RFU
RFU
45
46
RFU
RFU
RFU
RFU
47
48
RFU
RFU
RFU
RFU
49
50
RFU
RFU
51
52
GND
GND
RFU
RFU
53
54
RFU
RFU
RFU
RFU
55
56
RFU
RFU
RFU
RFU
57
58
RFU
RFU
RFU
RFU
59
60
RFU
RFU
61
62
VDDNF
POWER DOMAIN FROM CM
POWER DOMAIN FROM CM
VDDNF
PD0
GPIO D
NANDOE
63
64
NANDWE
GPIO D
PD1
PD2
GPIO D
A21/NANDALE
65
66
A22/NANDCLE
GPIO D
PD3
PD4
GPIO D
NCS3
67
68
NWAIT
GPIO D
PD5
PD6
GPIO D
D16
69
70
D17
GPIO D
PD7
PD8
GPIO D
D18
71
72
D19
GPIO D
PD9
73
74
GND
GND
PD10
GPIO D
D20
75
76
D21
GPIO D
PD11
PD12
GPIO D
D22
77
78
D23
GPIO D
PD13
PD14
GPIO D
D24
79
80
D25/A20
GPIO D
PD15
PD16
GPIO D
D26/A23
81
82
D27/A24
GPIO D
PD17
PD18
GPIO D
D28/A25
83
84
D29/NCS2
GPIO D
PD19
Evaluation Kit (EK) User Guide
4-47
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
Table 4-21. SODIMM200 CON1 Signal Descriptions (Continued)
Function
Type
x5 pad name
USBB_DM
I/O
USB Data Negative
13
USBB_DP
I/O
USB Data Positive
GND
SODIMM 200
x5 pad name
Type
Function
14
SYSC
BMS
15
16
SYSC
nRST
17
18
SYSC
nTRST
DIBP
I/O
19
20
RSTJTAG
TDI
DIBN
I/O
21
22
RSTJTAG
TCK
23
24
RSTJTAG
TMS
GND
USBA_DM
I/O
USB Data Negative
25
26
RSTJTAG
TDO
USBA_DP
I/O
USB Data Positive
27
28
RSTJTAG
RTCK
29
30
GND
PWR_EN
RFU
RFU
31
32
RFU
RFU
RFU
RFU
33
34
RFU
RFU
RFU
RFU
35
36
RFU
RFU
RFU
RFU
37
38
RFU
RFU
RFU
RFU
39
40
RFU
RFU
KEY
GND
41
42
GND
RFU
RFU
43
44
RFU
RFU
RFU
RFU
45
46
RFU
RFU
RFU
RFU
47
48
RFU
RFU
RFU
RFU
49
50
RFU
RFU
51
52
GND
GND
RFU
RFU
53
54
RFU
RFU
RFU
RFU
55
56
RFU
RFU
RFU
RFU
57
58
RFU
RFU
RFU
RFU
59
60
RFU
RFU
61
62
VDDNF
POWER DOMAIN FROM CM
POWER DOMAIN FROM CM
VDDNF
PD0
GPIO D
NANDOE
63
64
NANDWE
GPIO D
PD1
PD2
GPIO D
A21/NANDALE
65
66
A22/NANDCLE
GPIO D
PD3
PD4
GPIO D
NCS3
67
68
NWAIT
GPIO D
PD5
PD6
GPIO D
D16
69
70
D17
GPIO D
PD7
PD8
GPIO D
D18
71
72
D19
GPIO D
PD9
73
74
GND
GND
PD10
GPIO D
D20
75
76
D21
GPIO D
PD11
PD12
GPIO D
D22
77
78
D23
GPIO D
PD13
PD14
GPIO D
D24
79
80
D25/A20
GPIO D
PD15
PD16
GPIO D
D26/A23
81
82
D27/A24
GPIO D
PD17
PD18
GPIO D
D28/A25
83
84
D29/NCS2
GPIO D
PD19
4-48
11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
Table 4-21. SODIMM200 CON1 Signal Descriptions (Continued)
Function
Type
x5 pad name
PD20
GPIO D
D30/NCS4
VDDIOP0
POWER OUTPUT
SODIMM 200
85
86
87
88
x5 pad name
Type
Function
D31/NCS5
GPIO D
PD21
POWER OUTPUT
VDDIOP0
PA0
GPIO A
TXD0/SPI1-NPCS1
89
90
RXD0/SPI0-NPCS2
GPIO A
PA1
PA2
GPIO A
MCI1_DA1/E0_ETX0
91
92
CTS0/ MCI1_DA2/
E0_ETX1
GPIO A
PA3
PA4
GPIO A
SCK0/MCI1_DA3/
E0_ETXER
93
94
PA11
GPIO A
SPI0_MISO/
MCI1_DA0
95
96
SPI0_MOSI/
MCI1_CDA
GPIO A
PA12
PA13
GPIO A
SPI0_SPCK/
MCI1_CK
97
98
SPI0_NPCS0
GPIO A
PA14
99
100
TXD2/
SPI0_NPCS1
GPIO A
PA7
GND
GND
PA8
GPIO A
RXD2/SPI1_NPCS0
101
102
TIOA0 /SPI1_MISO
GPIO A
PA21
PA22
GPIO A
TIOA1/SPI1_MOS1
103
104
TIOA2/
SPI1_SPCK
GPIO A
PA23
PA31
GPIO A
TWCK0/SPI1_NPCS2/
E0_ETXEN
105
106
TWD0/
SPI1_NPCS3/
E0_EMDC
GPIO A
PA30
107
108
MCI0_DA0
GPIO A
PA15
GND
PA16
GPIO A
MCI0_CDA
109
110
MCI0_CK
GPIO A
PA17
PA18
GPIO A
MCI0_DA1
111
112
MCI0_DA2
GPIO A
PA19
PA20
GPIO A
MCI0_DA3
113
114
PA5
GPIO A
TXD1/CANTX1
115
116
RXD1/CANRX1
GPIO A
PA6
PA10
GPIO A
DTXD/CANTX0
117
118
DRXD/CANRX0
GPIO A
PA9
119
120
TCLK0/TK
GPIO A
PA24
GND
GND
PA25
GPIO A
TCLK1/TF
121
122
TCLK2/TD
GPIO A
PA26
PA27
GPIO A
TIOB0/RD
123
124
TIOB1/RK
GPIO A
PA28
PA29
GPIO A
TIOB2/RF
125
126
127
128
VDDIOP1
POWER OUTPUT
GND
POWER OUTPUT
VDDIOP1
PC0
GPIO C
LCDDAT0/ISI_D0
129
130
LCDDAT1
GPIO C
PC1
PC2
GPIO C
LCDDAT2/ISI_D2
131
132
LCDDAT3
GPIO C
PC3
PC4
GPIO C
LCDDAT4
133
134
LCDDAT5
GPIO C
PC5
135
136
LCDDAT6
GPIO C
PC6
GND
PC7
GPIO C
LCDDAT7
137
138
LCDDAT8
GPIO C
PC8
PC9
GPIO C
LCDDAT9
139
140
LCDDAT10
GPIO C
PC10
PC11
GPIO C
LCDDAT11
141
142
PC12
GPIO C
LCDDAT12
143
144
LCDDAT13
GPIO C
PC13
PC14
GPIO C
LCDDAT14
145
146
LCDDAT15
GPIO C
PC15
147
148
LCDDAT16
GPIO C
PC16
GND
Evaluation Kit (EK) User Guide
GND
4-49
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
Table 4-21. SODIMM200 CON1 Signal Descriptions (Continued)
Function
Type
x5 pad name
x5 pad name
Type
Function
PC17
GPIO C
LCDDAT17
149
150
LCDDAT18
GPIO C
PC18
PC19
GPIO C
LCDDAT19
151
152
LCDDAT20
GPIO C
PC20
PC21
GPIO C
LCDDAT21
153
154
PC22
GPIO C
LCDDAT22
155
156
PC24
GPIO C
LCDDISP
157
158
PC26
GPIO C
LCDPWM
159
160
161
GND
SODIMM 200
GPIO C
PC23
GPIO C
PC25
LCDVSYNC
GPIO C
PC27
162
LCDHSYNC
GPIO C
PC28
E1_MDC
GPIO C
PC30
PC29
GPIO C
LCDDEN
163
164
PC31
GPIO C
E1_MDIO
165
166
167
168
VDDANA
POWER OUTPUT
GND
LCDDAT23
SELCONFIG
POWER OUTPUT
VDDANA
PB0
GPIO B
E0_RX0
169
170
E0_RX1
GPIO B
PB1
PB2
GPIO B
E0_RXER
171
172
E0_RXDV
GPIO B
PB3
PB4
GPIO B
E0_TXCK
173
174
E0_MDIO
GPIO B
PB5
PB6
GPIO B
E0_MDC
175
176
E0_TXEN
GPIO B
PB7
PB8
GPIO B
E0_TXER
177
178
GNDANA
PB9
GPIO B
E0_TX0
179
180
E0_TX1
GPIO B
PB10
PB11
GPIO B
E0_TX2
181
182
E0_TX3
GPIO B
PB12
PB13
GPIO B
E0_RX2
183
184
E0_RX3
GPIO B
PB14
PB15
GPIO B
E0_RXCK
185
186
E0_CRS
GPIO B
PB16
PB17
GPIO B
E0_COL
187
188
GNDANA
PB18
GPIO B
IRQ
189
190
191
192
ETH
LED0
GND
POWER OUTPUT
POWR_REF
ETH0_TX+
ETH
193
194
ETH
LED1
ETH0_TX-
ETH
195
196
ETH
LED2
ETH0_RX+
ETH
197
198
ETH
AVDDT
ETH0_RX-
ETH
199
200
4.3.5.3
GND_ETH
JTAG/ICE Connector
Figure 4-37. JTAG J9
4-50
11115A–ATARM–27-Jul-11
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
Table 4-22. JTAG/ICE Connector J13 Signal Descriptions
Pin
Mnemonic
Description
1
VTref. 3.3V power
This is the target reference voltage. It is used to check if the target has power,
to create the logic-level reference for the input comparators, and to control the
output logic levels to the target. It is normally fed from VDD on the target board
and must not have a series resistor.
2
Vsupply. 3.3V power
This pin is not connected in SAM-ICE. It is reserved for compatibility with other
equipment. Connect to VDD or leave open in target system.
3
nTRST TARGET RESET - Active-low output
signal that resets the target
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
4
GND
Common ground
5
TDI TEST DATA INPUT - Serial data output
line, sampled on the rising edge of the TCK
signal.
JTAG data input of target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TDI on target CPU.
6
GND
Common ground
7
TMS TEST MODE SELECT
JTAG mode set input of target CPU. This pin should be pulled up on the target.
Typically connected to TMS on target CPU. Output signal that sequences the
target's JTAG state machine, sampled on the rising edge of the TCK signal.
8
GND
Common ground
9
TCK TEST CLOCK - Output timing signal,
for synchronizing test logic and control
register access.
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TCK on target CPU.
10
GND
Common ground
11
RTCK - Input Return test clock signal from
the target.
Some targets must synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, a returned and retimed TCK can be used to
dynamically control the TCK rate. SAM-ICE supports adaptive clocking which
waits for TCK changes to be echoed correctly before making further changes.
Connect to RTCK if available, otherwise to GND.
12
GND
Common ground
13
TDO JTAG TEST DATA OUTPUT - Serial
data input from the target.
JTAG data output from target CPU. Typically connected to TDO on target CPU.
14
GND
Common ground
15
nSRST RESET
Active-low reset signal. Target CPU reset signal.
16
GND
Common ground
17
RFU
This pin is not connected in SAM-ICE.
18
GND
Common ground
19
RFU
This pin is not connected in SAM-ICE.
20
GND
Common ground
Evaluation Kit (EK) User Guide
4-51
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.5.4
USB Type A Dual Port
Figure 4-38. USB Type A Dual Port J19
Table 4-23. USB Type A Dual Port J19 Signal Descriptions
Pin
Mnemonic
Description
A1
Vbus – USB_A
5V power
A2
DM – USB_A
Data minus
A3
DP – USB_A
Data plus
A4
GND
Common ground
B1
Vbus – USB_A
5V power
B2
DM – USB_A
Data minus
B3
DP – USB_A
Data plus
B4
GND
Common ground
Mechanical pins
4-52
11115A–ATARM–27-Jul-11
Shield
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.5.5
USB Micro AB
Figure 4-39. USB USB Host/Device Micro AB Connector J20
Table 4-24. USB USB Host/Device Micro AB Connector J20 Signal Descriptions
4.3.5.6
Pin
Mnemonic
Description
1
Vbus
5v power
2
DM
Data minus
3
DP
Data plus
4
ID
On the Go Identification
5
GND
Common ground
DBGU
Figure 4-40. DBGU Connector J11
Table 4-25. DBGU Connector J11 Signal Descriptions
Pin
Mnemonic
1, 4, 6, 9
Description
NO CONNECTION
2
RXD (RECEIVED DATA)
RS232 serial data output signal
3
TXD (TRANSMITTED Data)
RS232 serial data input signal
5
GND
Common ground
7
RTS (REQUEST TO SEND)
NO USED
8
CTS (CLEAR TO SEND)
NO USED
Mechanical pins
Evaluation Kit (EK) User Guide
Shield
4-53
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.5.7
RS232 Connector with RTS/CTS Handshake Support
Figure 4-41. USART Connector J12, J13
Table 4-26. USART Connector J12 Signal Descriptions
Pin
Mnemonic
Description
1, 4, 6, 9
NO CONNECTION
2
RXD (RECEIVED DATA)
PA1
RS232 serial data output signal
3
TXD (TRANSMITTED Data)
PA0
RS232 serial data input signal
5
GND
7
RTS (REQUEST TO SEND)
PA2
Active-positive RS232 input signal
8
CTS (CLEAR TO SEND)
PA3
Active-positive RS232 output signal
Common ground
Mechanical pins
Shield
Table 4-27. USART Connector J13 Signal Descriptions
Pin
Mnemonic
Description
1, 4, 6, 9
NO CONNECTION
2
RXD (RECEIVED DATA)
PC23
RS232 serial data output signal
3
TXD (TRANSMITTED Data)
PC22
RS232 serial data input signal
5
GND
7
RTS (REQUEST TO SEND)
PC24
Active-positive RS232 input signal
8
CTS (CLEAR TO SEND)
PC25
Active-positive RS232 output signal
Mechanical pins
4-54
11115A–ATARM–27-Jul-11
Common ground
Shield
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.5.8
DAA RJ11 Socket (6P4C)
Figure 4-42. DAA RJ11 Socket J16
Table 4-28. DAA RJ11 Socket J16 Signal Descriptions
Pin
Mnemonic
1, 2, 5, 6
4.3.5.9
Description
NO CONNECTION
3
RAC
RING side of ordinary telephone line
4
TAC
TIP side of ordinary telephone line
CAN RJ12 Socket (6P6C)
Figure 4-43. CAN RJ12 Socket CON2, CON3
Table 4-29. DAA RJ11 Socket J16 Signal Descriptions
Pin
Mnemonic
Description
1
3V3
POWER PIN
2
5V
POWER PIN
4
CANL
CAN bus differential pair
5
CANH
CAN bus differential pair
4, 6
GND
Common ground
Evaluation Kit (EK) User Guide
4-55
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.5.10 MicroSD MCI0
Figure 4-44. MicroSD Socket J6
Table 4-30. MicroSD Socket J6 Signal Descriptions
Pin
Mnemonic
Description
1
DAT2
Data Bit 2
2
CD/DAT3
Card Detect/Data Bit 3
3
CMD
Command Line
4
VCC
Supply Voltage 3.3V
5
CLK
Command Line
6
VSS
Common ground
7
DAT0
Data Bit 0
8
DAT1
Data Bit 1
9
SW1
No use, grounded
10
CARD DETECT
CARD DETECT
4.3.5.11 SD/MMC MCI1
Figure 4-45. SD/MMC Socket J7
Table 4-31. SD Socket J7 Signal Descriptions
Signal
Pin
Mnemonic
PIO
SD Card
MMC Card
1-Bit Mode
4-Bit Mode
1
MCI1_DA2
PA3
Not Used
Read Wait (RW)
Data Line DAT2 or Read Wait (RW)
2
MCI1_DA3
PA4
Reserved
Not Used
Data Line DAT3
3
MCI1_CDA
PA12
4
VDDIOP0
4-56
11115A–ATARM–27-Jul-11
Command/Response
Supply Voltage (3.3-volts) VDDIOP0
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
Table 4-31. SD Socket J7 Signal Descriptions (Continued)
Signal
Pin
Mnemonic
PIO
SD Card
MMC Card
1-Bit Mode
PA13
4-Bit Mode
5
MCI1_CK
Clock
6
GND
7
MCI1_DA0
PA11
8
MC1_DA1
PA2
9
GND
10
MCI1_CD
11
WP
Write Protect Detect, connects to jumper JP6
12
GND
Ground
13
GND
Ground
14
GND
Ground
15
GND
Ground
Ground
Data Line DAT0
Not Used
Interrupt (IRQ)
Data Line DAT1 or Interrupt (IRQ)
Ground
PD14
Card Detect, configured as GPIO, Power domain VDDNF
4.3.5.12 Ethernet RJ45 Socket J17, J18
Figure 4-46. Ethernet RJ45 Socket J17, J18
Table 4-32. DAA RJ11 Socket J16 Signal Descriptions
Pin
Mnemonic
Description
1
TX+
DIFFERENTIAL OUTPUT PLUS
2
TX-
DIFFERENTIAL OUTPUT MINUS
3
RX+
DIFFERENTIAL INPUT PLUS
4
Reserved
5
Reserved
6
RX-
7
Reserved
8
Reserved
Evaluation Kit (EK) User Guide
DIFFERENTIAL INPUT MINUS
4-57
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.5.13 ZigBee Socket J10
Figure 4-47. ZigBee Socket J10
Table 4-33. ZigBee Socket J10 Signal Descriptions
Signal
Name
Function
Reset
Port
/RST
Pin
1
Pin
Port
Signal
Name
2
Function
Misc.
Interrupt
Request
IRQ
3
4
SLP_TR
SLP_TR
SPI chip select
/SEL
5
6
MOSI
SPI MOSI
SPI MISO
MISO
7
8
SCLK
SPI CLK
Power Supply
GND
9
10
VCC
VCC
GND
VCC
Option on misc. port set by
OR or solder shunts
EEprom for MAC
address, cap array
settings and serial
number
TST: test mode
activation
CLKM: RF chip clock
output
Voltage range: 1.8v to 5.5v,
regulated to 3.3v
4.3.5.14 LCD/ISI Socket J21
Figure 4-48. LCD/ISI Socket J21
Table 4-34. LCD/ISI Socket J21 Signal Descriptions
4-58
11115A–ATARM–27-Jul-11
LCD
ISI
Pin Num
Pin Num
ISI
LCD
3V3
3V3
1
2
GND
GND
VDDISI
VDDISI
3
4
GND
GND
ZB_IRQ0
ZB_IRQ0
5
6
ZB_IRQ1
TWCK0
TWCK0
7
8
TWD0
GND
GND
9
10
ISI_MCK
LCDDAT15
GND
GND
11
12
ISI_VSYNC
LCDDAT13
GND
GND
13
14
ISI_HSYNC
LCDDAT14
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
Table 4-34. LCD/ISI Socket J21 Signal Descriptions (Continued)
LCD
ISI
Pin Num
Pin Num
ISI
LCD
GND
GND
15
16
ISI_PCK
LCDDAT12
GND
GND
17
18
ISI_D0
LCDDAT0
LCDDAT1
ISI_D1
19
20
ISI_D2
LCDDAT2
LCDDAT3
ISI_D3
21
22
ISI_D4
LCDDAT4
LCDDAT5
ISI_D5
23
24
ISI_D6
LCDDAT6
LCDDAT7
ISI_D7
25
26
ISI_D8
LCDDAT8
LCDDAT9
ISI_D9
27
28
ISI_D10
LCDDAT10
LCDDAT11
ISI_D11
29
30
GND
GND
4.3.5.15 LCD/TSC Socket J22
Figure 4-49. LCD/TSC Socket J22
Table 4-35. LCD/TSC Socket J22 Signal Descriptions
LCD
Pin Num
Pin Num
LCD
5V
5V_INTER
1
2
GND
GND
5V
5V_INTER
3
4
GND
GND
LCDDAT16
5
6
LCDDAT17
LCDDAT18
7
8
LCDDAT19
LCDDAT20
9
10
LCDDAT21
LCDDAT22
11
12
LCDDAT23
13
14
LCDDISP
15
16
LCDPWM
LCDCSYNC
17
18
LCDHSYNC
LCDDEN
19
20
LCDPCK
GND
GND
GND
GND
GND
GND
21
22
GND
GND
AD0_XP
TSC
23
24
TSC
AD1_XM
AD2_YP
TSC
25
26
TSC
AD3_YM
AD4_LR
TSC
27
28
GND
GND
29
30
SPI1_MISO
31
32
SPI1_MOSI
SPI1_SPCK
33
34
SPI1_NPCS1
35
36
37
38
39
40
EN_PWRLCD
SELCONFIG
PD16
GND
Evaluation Kit (EK) User Guide
GND
ONE_WIRE
GND
LCD_DETECT
GND
LCD_DETECT#
PD17
GND
GND
4-59
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.5.16 IO Expansion Port J1
Figure 4-50. IO Expansion Socket J1
Table 4-36. Expansion Socket J1 Signal Descriptions
PIO
4-60
11115A–ATARM–27-Jul-11
Power
Pin Num
Pin Num
Power
PIO
3V3, or 5V
1
2
3V3, or 5V
GND
3
4
GND
PA0
5
6
PA16
PA1
7
8
PA17
PA2
9
10
PA18
PA3
11
12
PA19
PA4
13
14
PA20
PA5
15
16
PA21
PA6
17
18
PA22
PA7
19
20
PA23
PA8
21
22
PA24
PA9
23
24
PA25
PA10
25
26
PA26
PA11
27
28
PA27
PA12
29
30
PA28
PA13
31
32
PA29
PA14
33
34
PA30
PA15
35
36
PA31
GND
37
38
GND
3V3
39
40
3V3
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.3.5.17 IO Expansion Port J2
Figure 4-51. IO Expansion Socket J2
Table 4-37. Expansion Socket J1 Signal Descriptions
PIO
Power
Pin Num
Pin Num
Power
3V3, or 5V
1
2
3V3, or 5V
GND
3
4
GND
PC0
5
6
PC16
PC1
7
8
PC17
PC2
9
10
PC18
PC3
11
12
PC19
PC4
13
14
PC20
PC5
15
16
PC21
PC6
17
18
PC22
PC7
19
20
PC23
PC8
21
22
PC24
PC9
23
24
PC25
PC10
25
26
PC26
PC11
27
28
PC27
PC12
29
30
PC28
PC13
31
32
PC29
PC14
33
34
PC30
PC15
35
36
PC31
GND
37
38
GND
3V3
39
40
3V3
Evaluation Kit (EK) User Guide
PIO
4-61
11115A–ATARM–27-Jul-11
Evaluation Kit Hardware
4.3.5.18 IO Expansion Port J3
Figure 4-52. IO Expansion Socket J3
Table 4-38. Expansion Socket J1 Signal Descriptions
PIO
4-62
11115A–ATARM–27-Jul-11
Power
Pin Num
Pin Num
Power
PIO
3V3, or 5V
1
2
3V3, or 5V
GND
3
4
GND
PB0
5
6
PB16
PB1
7
8
PB17
PB2
9
10
PB18
PB3
11
12
-
PB4
13
14
-
PB5
15
16
-
PB6
17
18
-
PB7
19
20
-
PB8
21
22
PD14
PB9
23
24
PD15
PB10
25
26
PD16
PB11
27
28
PD17
PB12
29
30
PD18
PB13
31
32
PD19
PB14
33
34
PD20
PB15
35
36
PD21
GND
37
38
GND
3V3
39
40
3V3
Evaluation Kit (EK) User Guide
5
PIO C
PIO B&D
PIO
CONNECTOR
PIO
CONNECTOR
Sheet 3
PIO A
PIO A,...D
SmartDAA
PIO
CONNECTOR
A
B
C
C
O
N
N
E
C
T
O
R
S
O
D
I
M
M
ICE
USB A,B,C
ANALOG Reference 3V
VBAT
3V3 INPUT
4
Sheet 10
RJ 45
10/100 FAST
ETH0
Sheet 14
ISI
HE 14
POWER SUPPLY
4
LCD
INTERFACE
HE 14
5V
Sheet 4
Sheet 11
RJ 45
USER
INTERFACE
ANALOG
3V
Sheet 13
Sheet 13
10/100 FAST
EHT1
Battery
Sheet 4
3
AUDIO
ONE WIRE
EEPROM
Sheet 8
IN
USBB
HOST & DEVICE HOST
USBA
OUT
Sheet 12
3
USBC
HOST
HE10
PIO A,...D
Sheet 6
ICE
INTERFACE
2
RJ11
Sheet 5
CARD
READER
CARD
READER
Sheet 6
ZIGBEE
INTERFACE
CAN1
CAN0
Sheet 7
COM3
COM1
DBGU
SmartDAA
Sheet 9
2
RS232
RJ11
HE10
Evaluation Kit (EK) User Guide
MMC SD
SDIO
B
A
SCALE
REV
1/1
MODIF.
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
X.X
X.X
B
REV.
VER.
1
1
14
SHEET
DATE
XX-XXX-XX
XX-XXX-XX
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
BLOCK Diagram
AT91SAM9x5-EK
1
A
B
C
D
4.3.6
MMC SD
SDIO
D
5
Evaluation Kit Hardware
Schematics
Figure 4-53. EK Board Schematics
11115A–ATARM–27-Jul-11
4-63
11115A–ATARM–27-Jul-11
4-64
A
B
C
D
2010.07
2010.10
A
B
SECOND RELEASED
ORIGINAL RELEASED
NOTE
3.3V or 5V selection for J2
1-2
1-2
OPEN
CLOSE
CLOSE
JP9
JP4
JP5
JP13
JP14
11
13
CLOSE
1-2
CLOSE
POWER SUPPLY
HSMCI
Zigbee,Can Interface,JTAG
USART0,USART3,Debug port
AUDIO
SmartDAA
ETH0
ETH1
USB Interface
Miscellaneous
4
5
6
7
8
9
10
11
12
13
PA18
PA19
PA20
MCI1_DA1
MCI1_DA2
MCI1_DA3
RTS0
CTS0
PA2
PA3
PA31
5
PA30
MCI0_DA0
PA15
PA29
PA28
PA27
PA14
ZB_IRQ1 MCI1_CK
MCI1_CDA
PA12
PA13
MCI1_DA0
CANTX0 DTXD
PA10
PA11
PA25
PA26
PA24
PA23
CANRX0 DRXD
ZB_IRQ0
PA7
PA22
PA9
CANRX1
PA6
PA8
CANTX1
PA5
PA21
PA17
PA4
SPI1_NPCS1 PA16
RXD0
PA1
USAGE
TXD0
PA0
PIOA
PIO MUXING
PIOA
SODIMM
LCD&ISI
Describe
3
14
Block Diagram
2
DESCRIPTION
1
PAGE
TWCK0
TWD0
RF
RK
RD
TD
TF
TK
MCI0_DA3
MCI0_DA2
MCI0_DA1
MCI0_CK
MCI0_CDA
SPI1_SPCK
SPI1_MOSI
SPI1_MISO
4
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PIOB
ADVREF input selection
MDIX ON/OFF(ETH1)
MDIX ON/OFF(ETH0)
DEBUG and CAN0 selection
USAGE
TABLE OF CONTENTS
JP12
10
CAN1 diff termination select
CLOSE
CAN0 diff termination select
CLOSE
Zigbee Power on/off select
CLOSE
OPEN
JP8
JP7
JP10
MCI1 write protect select
CLOSE
Force power on function
Backup supply on/off
JP6
JP11
TP3
TP4
TP5
TP6
TP7
4
4
4
4
4
REFERENCE
TP1, TP2
4
PAGE
TEST POINT
LCDDAT2
LCDDAT3
PC3
PC10
PC11
PC12
PC13
PC14
PC15
PCK0
AD0_XP
AD1_XM
AD2_YP
AD3_YM
AD4_LR
E0_TX1
3
PC9
PC8
PC7
PC6
PC5
PC4
PC2
ONE_WIRE
PB18
ISI_D9
ISI_D8
ISI_D7
ISI_D6
ISI_D5
ISI_D4
ISI_D3
ISI_D2
ISI_D1
ISI_D0
R164,R162
R187
PC28
PC27
PC26
LCDDAT15 ISI_MCK
PC31
LCDDAT14 ISI_HSYNC PC30
PD15
E1_MDIO
2
PD14
E1_MDC
LCDPCK
PD13
PD11
E1_TXCK
PD9
CTS3
LCDDEN
PD8
RTS3
PD10
PD7
RXD3
E1_CRSDV PD12
PD6
TXD3
LCDHSYNC
LCDDISP
PC24
PD5
E1_RX1
E1_TXEN
LCDDAT23
PC23
PD4
LCDVSYNC
LCDDAT22
PC22
PD3
E1_INTR
LCDDAT21
PC21
PD2
E1_RX0
MCI0_CD
MCI1_CD
EN5V_HDC#
EN5V_HDB#
EN5V_HDA#
SCALE
REV
1/1
MODIF.
1
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
X.X
X.X
B
REV.
VER.
1
2
14
SHEET
DATE
XX-XXX-XX
XX-XXX-XX
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
DESCRIBE
B
A
USAGE
ZB_SLPTR
ZB_RSTN
AT91SAM9x5-EK
PD21
PD20
PD19
PD18
PD17
E1_TX1
PD16
PIOD
PD1
USAGE
PD0
PIOD
E1_TX0
E1_RXER
Optional clock input to WM8371(MN10)
Optional for Qtouch2
LCDPWM
LCDDAT20
PC25
LCDDAT19
LCDDAT18
PC20
LCDDAT13 ISI_VSYNC PC29
LCDDAT12 ISI_PCK
LCDDAT11 ISI_D11
USAGE
LCDDAT17
LCDDAT16
PC19
PC18
PC17
PC16
PIOC
Optional ETH0 extended
Optional clock input to TX_CLK(ETH1)
R174,R175,R176,R180,R183,R184,R185,R186
R125
Optional clock input to TX_CLK(ETH0)
R108
Optional TCK and RTCK
Disconnect NTRST signal
R58
Optional Zigbee
Optional Pull UP at EK BOARD
R50
FUNCTION
R46, R47,R48,R49
REFERENCE
R52, R53,R55,R56,R57,R82,JP10
LCDDAT10 ISI_D10
LCDDAT9
LCDDAT8
LCDDAT7
LCDDAT6
LCDDAT5
LCDDAT4
LCDDAT1
LCDDAT0
PC1
USAGE
8
3
11
10
6
PAGE
OVCUR_USB
PC0
USART3
SAM9G15 SAM9G35 SAM9X35 SAM9G25 SAM9X25
DEFAULT NO POPULATE PARTS
QTouch
TSC
LCD
RS232
ISI
CAN1
CAN0
Shared DBGU
RMII
USART0
RS232
Audio
ETH1
Conexant
VBUS_SENSE
PIOC
SubD9
Shared USART0
HSMCI1
ZigBee
DDR2 / Flash
DBGU
RMII
EBI
HSMCI0
Jtag
USB
ETH0
SAM9x5 Config
(2) "DNP" means the component is not populated
by default
(1) Resistance Unit: "K" is "Kohm", "R" is "Ohm
PB17
USAGE
2
SCHEMATICS CONVENTIONS
PB16
PIOB
VDDNF
VDDIOP1
VDDIOP0
3V3
5V
GND
FUNCTION
3
E0_TX0
E0_INTR
E0_TXEN
E0_MDC
E0_MDIO
E0_TXCK
E0_RXDV
E0_RXER
E0_RX1
E0_RX0
USAGE
Default boot on embedded ROM,Close boot on external memory
3.3V or 5V selection for J3
3.3V or 5V selection for J1
1-2
JP2
FUNCTION
JP3
DEFAULT
4
JP1
REFERENCE
7
6
5
4
3
PAGE
JUMPER and SOLDERDROP
DATA
REV
REVISION HISTORY
5
A
B
C
D
Evaluation Kit Hardware
Evaluation Kit (EK) User Guide
A
B
C
D
PA25
PA27
PA29
PC0
PC2
PC4
PC7
PC9
PC11
PC12
PC14
PC17
PC19
PC21
PC22
PC24
PC26
PC29
PC31
VDDANA
PB0
PB2
PB4
PB6
PB8
PB9
PB11
PB13
PB15
PB17
PB18
{8}
{8}
{8}
{14}
{14}
{14}
{14}
{14}
{14}
{14}
{14}
{14}
{11,14}
{11,14}
{7,14}
{7,14}
{11,14}
{11,14}
{11}
{10}
{10}
{10}
{10}
{10}
{10}
{14}
{14}
{14}
{12}
{13,14}
PA16
PA18
PA20
PA5
PA10
{5}
{5}
{5}
{6}
{6,7}
{6,7,14}
{5,7}
{5}
{5}
{5,6,14}
PA8
PA22
PA31
PA0
PA2
PA4
PA11
PA13
{5}
{12,14}
{12}
{12}
{6,14}
{8,14}
PD10
PD12
PD14
PD16
PD18
PD20
5
{12}
{12}
{10}
{10}
{10}
{10}
ONE_WIRE
E0_RX0
E0_RXER
E0_TXCK
E0_MDC
E0_INTR
E0_TX0
E1_TXCK
E1_MDIO
E1_INTR
E1_TX1
E1_RX1
TF
RD
RF
CANTX1
CANTX0
(MCI0_CDA)
(MCI0_DA1)
(MCI0_DA3)
(MCI1_DA1)
(MCI1_DA3)
(MCI1_DA0)
(MCI1_CK)
USBA_DM
USBA_DP
DIBP
DIBN
USBB_DM
USBB_DP
{12}
{12}
{9}
{9}
USBC_DP
USBC_DM
{12}
{12}
ETH0_TX+
ETH0_TXETH0_RX+
ETH0_RX-
AD0_XP
AD2_YP
AD4_LR
OVCUR_USB
PB0
PB2
PB4
PB6
PB8
PB9
PB11
PB13
PB15
PB17
PB18
PC29
PC31
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT22
LCDDISP
LCDPWM
LCDDEN
PC17
PC19
PC21
PC22
PC24
PC26
LCDDAT7
LCDDAT9
LCDDAT11
LCDDAT12
LCDDAT14
ISI_D7
ISI_D9
ISI_D11
ISI_PCK
ISI_HSYNC
TXD3
RTS3
PC7
PC9
PC11
PC12
PC14
PC0
PC2
PC4
PA25
PA27
PA29
PA16
PA18
PA20
PA5
PA10
PA8
PA22
PA31
PA0
PA2
PA4
PA11
PA13
LCDDAT0
LCDDAT2
LCDDAT4
VDDIOP1
SPI1_MOSI
ZB_IRQ1
SPI1_NPCS1
PD10
PD12
PD14
PD16
PD18
PD20
PD0
PD2
PD4
PD6
PD8
ISI_D0
ISI_D2
ISI_D4
DTXD
TWCK0
TXD0
RTS0
VDDIOP0
ZB_RSTN
EN5V_HDA#
EN5V_HDC#
(MCI1_CD)
VDDNF
3V3
4
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
4
KEY
VCC2
VCC4
VBAT
JTAGSEL
WKUP
SHDN
BMS
nRST
nTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
RFU2
RFU4
RFU6
RFU8
RFU10
3
GND7
GND8
RFU11
RFU12
RFU13
RFU14
RFU15
RFU16
RFU17
RFU18
GND9
GND10
RFU19
RFU20
RFU21
RFU22
RFU23
RFU24
RFU25
RFU26
VDDNF1
VDDNF2
PD0/NANDOE
PD1/NANDWE
PD2/A21/NANDALE
PD3/A22/NANDCLE
PD4/NCS3
PD5/NWAIT
PD6/D16
PD7/D17
PD8/D18
PD9/D19
NC
GND11
PD10/D20
PD11/D21
PD12/D22
PD13/D23
PD14/D24
PD15/D25/A20
PD16/D26/A23
PD17/D27/A24
PD18/D28/A25
PD19/D29/NCS2
PD20/D30/NCS4
PD21/D31/NCS5
VDDIOP0_0
VDDIOP0_1
PA0/TXD0/SPI1_NPCS1
PA1/RXD0
PA2/RTS0/MCI1_DA1/E0_ETX0
PA3/CTS0/MCI1_DA2/E0_ETX1
PA4/SCK0/MCI1_DA3/E0_ETXER
GND12
PA11/SPI0_MISO/MCI1_DA0
PA12/SPI0_MOSI/MCI1_CDA
PA13/SPI0_SPCK/MCI1_CK
PA14/SPI0_NPCS0
GND13
PA7/TXD2
PA8/TIOA0/SPI1_MISO
PA21/RXD2/SPI1_NPCS0
PA22/TIOA1/SPI1_MOSI
PA23/TIOA2/SPI1_SPCK
PA31/TWCK0/SPI1_NPCS2/E0_ETXEN PA30/TWD0/SPI1_NPCS3/E0_EMDC
GND14
PA15/MCI0_DA0
PA16/MCI0_CDA
PA17/MCI0_CK
PA18/MCI0_DA1
PA19/MCI0_DA2
PA20/MCI0_DA3
GND16
PA5/TXD1/CANTX1
PA6/RXD1/CANRX1
PA10/DTXD/CANTX0
PA9/DRXD/CANRX0
GND15
PA24/TCLK0/TK
PA25/TCLK1/TF
PA26/TCLK2/TD
PA27/TIOB0/RD
PA28/TIOB1/RK
PA29/TIOB2/RF
GND17
VDDIOP1_0
VDDIOP1_1
PC0/LCDDAT0/ISI_D0/TWD1
PC1/LCDDAT1/ISI_D1/TWCK1
PC2/LCDDAT2/ISI_D2/TIOA3
PC3/LCDDAT3/ISI_D3/TIOB3
PC4/LCDDAT4/ISI_D4/TCLK3
PC5/LCDDAT5/ISI_D5/TIOA4
GND18
PC6/LCDDAT6/ISI_D6/TIOB4
PC7/LCDDAT7/ISI_D7/TCLK4
PC8/LCDDAT8/ISI_D8/UTXD0
PC9/LCDDAT9/ISI_D9/URXD0
PC10/LCDDAT10/ISI_D10/PWM0
PC11/LCDDAT11/ISI_D11/PWM1
GND19
PC12/LCDDAT12/ISI_PCK/TIOA5
PC13/LCDDAT13/ISI_VSYNC/TIOB5
PC14/LCDDAT14/ISI_HSYNC/TCLK5
PC15/LCDDAT15/ISI_MCK
GND20
PC16/LCDDAT16/E1_RXER/UTXD1
PC17/LCDDAT17/URXD1
PC18/LCDDAT18/E1_TX0/PWM0
PC19/LCDDAT19/E1_TX1/PWM1
PC20/LCDDAT20/E1_RX0/PWM2
PC21/LCDDAT21/E1_RX1/PWM3
GND21
PC22/LCDDAT22/TXD3
PC23/LCDDAT23/RXD3
PC24/LCDDISP/RTS3
PC25/CTS3
PC26/LCDPWM/SCK3
PC27/LCDVSYNC/E1_TXEN/RST1
GND22
PC28/LCDHSYNC/E1_CRSDV/CTS1
PC29/LCDDEN/E1_TXCK/SCK1
PC30/LCDPCK/E1_MDC
PC31/FIQ/E1_MDIO/PCK1
SELCONFIG
VDDANA_0
VDDANA_1
PB0/E0_RX0/RTS2
PB1/E0_RX1/CTS2
PB2/E0_RXER/SCK2
PB3/E0_RXDV/SPI0_NPCS3
PB4/E0_TXCK/TWD2
PB5/E0_MDIO/TWCK2
PB6/E0_MDC/AD7
PB7/E0_TXEN/AD8
PB8/E0_TXER/AD9
GNDANA1
PB9/E0_TX0/PCK1/AD10
PB10/E0_TX1/PCK0/AD11
PB11/E0_TX2/PWM0/AD0
PB12/E0_TX3/PWM1/AD1
PB13/E0_RX2/PWM2/AD2
PB14/E0_RX3/PWM3/AD3
PB15/E0_RXCK/AD4
PB16/E0_CRS/AD5
PB17/E0_COL/AD6
GNDANA2
PB18/IRQ/ADTRG
ADVREF
GND23
LED0
ETH0_TX+
LED1
ETH0_TXLED2
ETH0_RX+
AVDDT
ETH0_RXGND_ETH
1612618-4
VCC1
VCC3
GND1
USBC_DP
USBC_DM
GND3
USBB_DM
USBB_DP
GND4
DIBP
DIBN
GND5
USBA_DM
USBA_DP
GND6
RFU1
RFU3
RFU5
RFU7
RFU9
CON1
3
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DRXD
LCDDAT13
LCDDAT15
LCDDAT16
LCDDAT18
LCDDAT20
LCDDAT23
PC13
PC15
PC16
PC18
PC20
PC23
PC25
PC27
PC28
PC30
2
ETH0_LED0 {10}
ETH0_LED1 {10}
ETH0_LED2 {10}
ETH0_AVDDT {10}
ETH0_GND {10}
E0_TX1
PB10 PCK0
PB12
PB14
PB16 VBUS_SENSE
E1_TXEN
E1_CRSDV
E1_MDC
E1_RXER
E1_TX0
E1_RX0
E0_RX1
E0_RXDV
E0_MDIO
E0_TXEN
AD1_XM
AD3_YM
RXD3
CTS3
ISI_VSYNC
ISI_MCK
ISI_D1
ISI_D3
ISI_D5
ISI_D6
ISI_D8
ISI_D10
PB1
PB3
PB5
PB7
LCDVSYNC
LCDHSYNC
LCDPCK
LCDDAT1
LCDDAT3
LCDDAT5
LCDDAT6
LCDDAT8
LCDDAT10
TK
TD
RK
CANRX1
CANRX0
(MCI0_DA0)
(MCI0_CK)
(MCI0_DA2)
(MCI1_CDA)
(MCI1_DA2)
1
SIP2
JP9
JTAG
ZB_SLPTR
{6,10,11,13}
{6}
{6}
{6}
{6}
{6}
{6}
{4,7}
SPI1_MISO
TWD0
VDDIOP1
SPI1_SPCK
ZB_IRQ0
RXD0
CTS0
NRST
NTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
PC13
PC15
PC16
PC18
PC20
PC1
PC3
PC5
PC6
PC8
PC10
PA6
PA9
PA24
PA26
PA28
PA12
PA14
PA7
PA21
PA23
PA30
PA15
PA17
PA19
PA1
PA3
PD11
PD13
PD15
PD17
PD19
PD21
PD9
PD5
{14}
{14}
{11,14}
{11,14}
{11,14}
{14}
{14}
{14}
{14}
{14}
{14}
{6}
{6,7}
{8}
{8}
{8}
{6,14}
{6,14}
{6,14}
{8,14}
{5}
{5}
{5}
{5}
{7}
{5,7}
{5}
{12,14}
{12}
3V3
3V3
{13}
{8,10}
{14}
{14}
{12}
JP1
1
3
JP2
JP3
1/1
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PB16
PB17
PB18
5V
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
5V
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
5V
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
J3
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3
J2
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3
J1
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
MODIF.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3V3
SCALE
REV
B
A
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3V3
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SODIMM
AT91SAM9x5-EK
ADVREF
PB10
PB12
PB14
PB16
PC23
{7,14}
PC25
{7}
PC27
{11,14}
PC28
{11,14}
PC30
{11,14}
SELCONFIG {7,11,14}
VDDANA
PB1
{10}
PB3
{10}
PB5
{10}
3V3
PB7
{10}
2
JP9 for BMS Config:
When Open,BMS=1: Boot on embedded ROM
When Close,BMS=0: Boot on External memory
VDDIOP0
R83
{4,13}
4.7k
WAKE UP {13}
SHDN
{4}
VBAT
VDDIOP0
EN5V_HDB#
(MCI0_CD)
VDDNF
PC1
PC3
PC5
PC6
PC8
PC10
PA6
PA9
PA24
PA26
PA28
PA12
PA14
PA7
PA21
PA23
PA30
PA15
PA17
PA19
PA1
PA3
PD11
PD13
PD15
PD17
PD19
PD21
PD1
PD3
PD5
PD7
PD9
BMS
3V3
2
2
2
Evaluation Kit (EK) User Guide
2
5
X.X
X.X
SHEET
3
14
B
DATE
XX-XXX-XX
XX-XXX-XX
REV.
VER.
3V3
3V3
3V3
A
B
C
D
Evaluation Kit Hardware
11115A–ATARM–27-Jul-11
4-65
A
B
C
{3}
100n
C57
SHDN
SIP2
FORCE
POWER
ON
JP5
5
2
R7
10k
3
4
5V
{3,7}
Z6
Bumpon
Z8
Bumpon
5V
C3
100n
R8
10k
Z7
Bumpon
Z9
Bumpon
C6
10u
Z17
4
Bumpon
CB
PSG CG1
CG2
CG3
B
PGOOD
EN
VIN
VDD
MN3
RT9018A
C7
1u
1
2
3
4
R1
100k
3V3
3
1
MN2
BNX002-01
C22
1u
Place C22 near MN3.pin2
POWER_EN
2
ADHESIVE FEET
15p
1 C10
5
PWR_EN
R4
100k
C120
1u
Q1
6
Si1563EDH
PWR_EN#
2
R25
10k
3V3
Q6
IRLML2402 3
1
1
3
2
DC POWER JACK
5V/2A Input
J4
MN1
ZEN056V230A16LS
3
5V_INPUT 1
4
EP
9
D
1
2
GND
ADJ
VOUT
NC
4
5
6
2
8
7
6
5
C2
33u
C1
100n
3
C8
1u
47k
R2
R5
15k
10n
C5
C9
10u
VOUT =
0.8V x (Rtop + Rbottom)/Rbottom
+
5V
3
J5
2
D1
3 1
2
X.X
X.X
DES.
DATE
1
4
14
B
DATE
SHEET
REV.
VER.
A
B
C
D
{3,13}
XX-XXX-XX
XX-XXX-XX
TP7
Derek 11-Oct-10
Derek 10-JUN-10
TP6
TP5
TP4
TP3
VDDNF
{14}
VBAT
VDDIOP1
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
POWER SUPPLY
3V3
5V
2
VDDISI
SIP2
JP4
VDDIOP0
1/1
MODIF.
SCALE
REV
B
A
TP2
TP1
VDDIOP1
L17
220ohm at 100MHz
1
2
VDDIOP0
L16
220ohm at 100MHz
1
2
VDDANA
L2
220ohm at 100MHz
1
2
C4
100n
3V3
L1
220ohm at 100MHz
1
2
BAT54CLT1G
AT91SAM9x5-EK
D2
Red
470R
R3
3V3
1
1
4-66
2
11115A–ATARM–27-Jul-11
2
5
Evaluation Kit Hardware
Evaluation Kit (EK) User Guide
A
B
C
PA16
PA20
PA19
{3}
{3}
{3}
PA2
PA11
{3}
{3}
{3,7}
PA12
PA4
PA3
{3,6,14} PA13
{3,7}
{3}
PD14
PA17
{3}
{3}
PA18
PA15
PD15
{3}
{3}
{3}
5
RR2
1
2
3
4
RR1
1
2
3
4
27R
8
7
6
5
27R
8
7
6
5
4
68k 68k 68k 68k
R10 R11 R12 R13
SIP2
JP6
2
1
2
3
4
8 RR5
7 27R
6
5
RR4 27R
1
8
2
7
3
6
4
5
68k 68k 68k 68k
R15 R16 R17 R18
4
RR4,RR5 near SODIMM place
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
(MCI1_CK)
(MCI1_DA1)
(MCI1_DA0)
(MCI1_WP)
(MCI1_CD)
1
RR1,RR2 near SODIMM place
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
(MCI0_CK)
(MCI0_DA1)
(MCI0_DA0)
(MCI0_CD)
R9
10k
VDDNF
VDDIOP0
R14
10k
3
VDDNF
C11
100n
VDDIOP0
8
7
6
5
Evaluation Kit (EK) User Guide
3
3V3
1
2
3
4
D
5
C12
100n
RR3
10k
SW1
9
J6
10
8 SW2
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
9
CD
WP
GND
GND
SH
SH
10
11
12
13
14
15
1/1
MODIF.
SCALE
REV
B
A
DES.
DATE
2
1
SHEET
5
14
B
DATE
XX-XXX-XX
XX-XXX-XX
REV.
VER.
Derek 11-Oct-10 X.X
Derek 10-JUN-10 X.X
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
HSMCI
AT91SAM9x5-EK
7SDCN-B0-0101-F
DAT1
DAT0
VSS
CLK
VDD
VSS
CMD
DAT3
DAT2
J7
11
12
13
14
SD/MMCPlus CARD INTERFACE - MCI1
PJS008-2110-0
Micro SD
1
SD/MMC CARD INTERFACE - MCI0
2
A
B
C
D
Evaluation Kit Hardware
11115A–ATARM–27-Jul-11
4-67
11115A–ATARM–27-Jul-11
4-68
A
B
C
D
5
5
PA9
{3,7}
PA5
PA6
{3}
{3}
CANRX0
3
2
1
Y
2
4
6
8
10
12
14
16
18
20
CANRX1
VDDIOP0
CANTX1
4
R35
1
3
5
7
9
11
13
15
17
19
DNP
100k
R47
R52
R56
R55
R82
1
3
5
7
9
DNP
100k
R49
0R
0R
0R
0R
0R
DNP
100k
R48
DNP
DNP
DNP
DNP
0R
0R
R33
R37
10k
0R
10k
R32
10k
VDDIOP0
R20
R54
DNP
100k
R46
VDDIOP0
PD16
ZB_IRQ1
SPI1_NPCS1
SPI1_MISO
VDDIOP0
BR20-H
J9
VDDIOP0
ICE INTERFACE
{12} ZB_RSTN
{3,5,14}
PA13
{3,7,14}
PA0
{3,14}
PA21
4
5
SN74LVC1G126DBV
GND
A
OE VCC
MN19
ZIGBEE INTERFACE
PA10
SEL_CAN
{3,7}
{7}
CANTX0
R21
(only for SAM9X35/SAM9X25)
CAN INTERFACE
4
GND
VCC
CANH
CANL
2
3
7
6
GND
VCC
CANH
CANL
2
3
7
6
R58
0R
DNP
R51
R50
DNP
HD2X05
2
4
6
8
10
0R
0R
C26
2.2n
0R
0R
3
2
C21
10u
120R
R34
120R
R19
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
2
1
JP10
C27 DNP DNP
2.2u
{3}
{3}
{3}
{3}
{3}
{3}
{3,10,11,13}
3V3
ZB_IRQ0
PD17
SPI1_MOSI
SPI1_SPCK
C24
10u
VDDIOP0
SIP2
JP8
100n
C23
1
2
VDDIOP0
SIP2
JP7
C20
100n
1
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
DNP
DNP
C25
15p
R53
R57
SN65HVD234DR
R
EN
D
RS
MN6
SN65HVD234DR
R
EN
D
RS
MN5
J10
4
5
1
8
4
5
1
8
3
PA7
{3,14}
ZB_SLPTR {12}
PA22
{3,14}
PA23
{3,14}
3V3
5V
3V3
5V
MJM0606GE06-H
1
2
3
4
5
6
2
MJM0606GE06-H
CON3
1
2
3
4
5
6
CON2
2
CAN1
CAN0
B
A
1/1
MODIF.
SCALE
REV
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
X.X
X.X
B
REV.
VER.
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
CAN & ICE & ZIGBEE
AT91SAM9x5-EK
1
6
14
SHEET
DATE
XX-XXX-XX
XX-XXX-XX
A
B
C
D
Evaluation Kit Hardware
Evaluation Kit (EK) User Guide
A
B
C
D
5
PA3
PA1
{3,5}
{3}
0R
0R
0R
0R
R27
R28
R30
R31
RTS0
TXD0
CTS0
RXD0
R23
47k
R22
47k
VDDIOP0
PC25
PC23
DEBUG PORT
{3}
{3,14}
{3,11,14} SELCONFIG
{3,14}
PC24
{3,14}
PC22
{6}
SEL_CAN
{3,6}
PA9
PA10
4
0R
0R
R69
R70
CTS3
RXD3
{3,6}
0R
0R
R65
R66
RTS3
TXD3
47k
VDDIOP0
DRXD
R73
R71
100k
0R
0R
C36
100n
3
C3-
C3+
C2-
C2+
C1-
6
C1+
C2-
SD
3
ADM3222ARW
R2
V-
V+
GND
VCC
R1
T2
T1
MN8
1 EN
10
13
11
C3-
C3+
C2-
C2+
C1-
C1+
15
14
13
18
17
16
22
24
4
2
R1IN
R2IN
R3IN
18
9
14
8
15
7
3
16
17
ADM3312EARU
R1OUT
R2OUT
R3OUT
T1IN
T2IN
T3IN
EN
SD
V-
V+
GND
6
20
T1OUT
T2OUT
T3OUT
R1IN
R2IN
R3IN
T1OUT
T2OUT
T3OUT
VCC
MN9
4
5 C1C2+
2
10
11
12
7
8
9
5
19
21
1
23
12
JP11
SIP2
100n
C30
100n
R1OUT
R2OUT
R3OUT
T1IN
T2IN
T3IN
EN
SD
V-
V+
3
C1+
ADM3312EARU
100n
10
11
12
7
8
9
5
19
21
1
GND
VCC
MN4
C37
100n
4.7u
3
23
C35
C29
C28
R67
100k
DTXD
R60
VDDIOP0
47k
R64
100k
47k
47k
R63
100n
VDDIOP1
C18
100n
100n
4.7u
C15
C14
C13
R59
R62
47k
R24
R61
VDDIOP1
(only for SAM9G25/SAM9X25)
USART3
PA2
PA0
{3,5}
{3,6,14}
USART0
VDDIOP0
2
R72
C38
C33
15
14
13
18
17
16
22
24
4
2
20
6
R29
C19
C17
C16
100n
100n
C31
100n
R68
C39
C34
C32
CTSC0
RXDC0
RTSC0
TXDC0
CTSC3
RXDC3
RTSC3
TXDC3
PWR_EN {3,4}
0R
VDDIOP0
0R
100n
100n
100n
0R
100n
100n
100n
1
6
2
7
3
8
4
9
5
J11
J8
2
1
6
2
7
3
8
4
9
5
J12
L5
220ohm at 100MHz
1
2
EARTH_RS232
10
EARTH_RS232
1
6
2
7
3
8
4
9
5
11
2
EARTH_RS232
10
4
11
11
Evaluation Kit (EK) User Guide
1
5
B
A
1/1
MODIF.
SCALE
REV
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
X.X
X.X
B
REV.
VER.
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
US RT
USA
T & DEBUG
AT91SAM9x5-EK
1
7
14
SHEET
DATE
XX-XXX-XX
XX-XXX-XX
A
B
C
D
Evaluation Kit Hardware
11115A–ATARM–27-Jul-11
4-69
10
11115A–ATARM–27-Jul-11
4-70
5
C42
470p
1
3
2
C61
470p
1
AUDIO_GND
4
STEREO_3.5mm
J15
5
HEADPHONE
L7
220ohm at 100MHz
1
2
4
AUDIO_GND
5.6K
R91
47k
C60
C59
0R
DNP
470p
C44
C121
22p
220uF/10V
220uF/10V
AUDIO_GND
AUDIO_GND
470p
C41
AUDIO_GND
R90
47k
AUDIO_GND
5.6K
R81
R162
R164 near SODIMM
R162 near CODEC
R80
R78
5.6K
L6
220ohm at 100MHz
1
2
C62
470p
AUDIO_GND
C43
470p
L4
220ohm at 100MHz
1
2
22R DNP
L3
R74
220ohm at 100MHz
5.6K
1
2
PCK0
R164
+
A
B
C
2
PB10
4
3
STEREO_3.5mm
J13
AUDIO_GND
5
LINE_IN
{3,10}
4
3
9
VDDIOP0
C115
10u
OSC
0R
2
100n
0R
33R
28
AUDIO_GND
C117
100n
VCC_DAC
2
R88
R89
0R
0R
R77
4.7k
100n
10u
10u
100n
10u
RK
TK
TD
TF
RD
RF
PA28
PA24
PA26
PA25
PA27
PA29
AUDIO_GND
AUDIO_GND
R79
4.7k
VDDIOP0
B
A
1/1
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
{3,14}
{3,14}
MODIF.
SCALE
REV
{3}
{3}
{3}
{3}
{3}
{3}
PA30
PA31
1
X.X
X.X
SHEET
8
14
B
1
DATE
XX-XXX-XX
XX-XXX-XX
REV.
VER.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
AUDIO
AT91SAM9x5-EK
100n
10u
100n
DGND
C56
C53
10u
C51
C50
C47
C48
C46
C45
C40
IIS of Audio Interface
in Slave Mode
R86
R87
C54
VCC_DAC
VDDIOP0
TWI_addr
TWD0
TWCK0
3
4
5
6
7
16
8
14
27
1
21
22
23
24
R76
10k
CSB = 1:
addr=0011011
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
VMID
HPVDD
AVDD
DCVDD
DBVDD
MODE
CSB
SDIN
SCLK
R75
10k
MODE = 0: 2-wire
MPU mode for 9x5
TWI interface
WM8731SEDS
L18
220ohm at 100MHz
1
2
11
HPGND
C116
100n
R165
AUDIO_GND
15
AGND
LHPOUT
10
MICBIAS
MICIN
RHPOUT
17
100n 18
RLINEIN
C55
LLINEIN
1u
19
1u
20
ROUT
13
XTO
26
LOUT
XTI/MCLK
25
12
CLKOUT
MN10
Y3
12.288MHz
2
C52
3
C122
22p
C49
1
3
2
4
D
5
A
B
C
D
Evaluation Kit Hardware
+
Evaluation Kit (EK) User Guide
DIBP
{3}
A
B
DIBN
C
{3}
5
0R
R167
150pF
C71
0R
R166
0R can be replaced by
bead to improve EMI
150pF
C72
4
1
LAN0066-50
3
TX1
2
C70
47pF
4
DAA_GND
C73
100n
DVDD
DAA_GND
C66
100n
DAA_GND
C65
100n
DVDD
DIBP
DIBN
AVDD
PWR
TEST
DAA_GND
C74
100n
1
14
16
2
15
12
MN11
13
7
8
9
10
6
11
5
R93
6.81M
R99
3
1
DAA_GND
R102
110R
MMBAT42
Q3
100R
1
DAA_GND
6.81M
0805
0805
DAA_GND 100V
C68
47n
100n
237K
R94
C67
CX20548-11Z
GPIO
TXF
TXO
EIF
EIO
RXI
EIC
TAC
RAC
4
R92
D3
MMBD3004S-7-F
2
R100
3.01R
1%
1
MMBAT42 DAA_GND
Q2
C69
10n
D5 MMBD3004S-7-F
1
2
1
3
3
D
3
2
3
2
3
3
2
2
R103
9R1
1%
1206
Q4
MMBAT42
1
2
R101
3.01R
1%
1
2
L9
220ohm at 100MHz
1
L8
220ohm at 100MHz
2
1
2
1
2
4
VC
3
EP
17
3
Evaluation Kit (EK) User Guide
2
5
MMBAT42
Q5
470p
C64
470p
C63
R96
280R
1%
1206
R97
280R
1%
1206
1
2
3
4
5
6
B
A
1/1
MODIF.
SCALE
REV
DES.
DATE
9
14
B
1
DATE
SHEET
REV.
VER.
Derek 11-Oct-10 X.X XX-XXX-XX
Derek 10-JUN-10 X.X XX-XXX-XX
R98
280R
1%
1206
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SmartDAA
AT91SAM9x5-EK
RJ11
MJM0606GE06-H
R94,C68 should be placed near Pin6(RXI),
and should be no vias on the RXI Net.
R95
280R
1%
1206
TB3100M-13-F
D4
J16
1
A
B
C
D
Evaluation Kit Hardware
11115A–ATARM–27-Jul-11
4-71
DIBP
{3}
A
B
DIBN
{3}
C
D
5
0R
R167
150pF
C71
0R
R166
0R can be replaced by
bead to improve EMI
150pF
C72
4
1
LAN0066-50
3
TX1
2
C70
47pF
4
DAA_GND
C73
100n
DVDD
DAA_GND
C66
100n
DAA_GND
C65
100n
DVDD
DIBP
DIBN
AVDD
PWR
TEST
DAA_GND
C74
100n
1
14
16
2
15
12
MN11
13
7
8
9
10
6
11
5
R93
6.81M
R99
3
1
DAA_GND
R102
110R
MMBAT42
Q3
100R
1
DAA_GND
6.81M
0805
0805
DAA_GND 100V
C68
47n
100n
237K
R94
C67
CX20548-11Z
GPIO
TXF
TXO
EIF
EIO
RXI
EIC
TAC
RAC
4
R92
D3
MMBD3004S-7-F
2
R100
3.01R
1%
1
MMBAT42 DAA_GND
Q2
C69
10n
D5 MMBD3004S-7-F
1
2
1
3
3
3
3
2
3
2
4
VC
3
EP
17
3
2
2
R103
9R1
1%
1206
Q4
MMBAT42
1
2
R101
3.01R
1%
1
2
L9
220ohm at 100MHz
1
L8
220ohm at 100MHz
2
1
2
1
2
4-72
3
11115A–ATARM–27-Jul-11
2
5
MMBAT42
Q5
470p
C64
470p
C63
R96
280R
1%
1206
R97
280R
1%
1206
1
2
3
4
5
6
B
A
1/1
MODIF.
SCALE
REV
DES.
DATE
9
14
B
1
DATE
SHEET
REV.
VER.
Derek 11-Oct-10 X.X XX-XXX-XX
Derek 10-JUN-10 X.X XX-XXX-XX
R98
280R
1%
1206
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SmartDAA
AT91SAM9x5-EK
RJ11
MJM0606GE06-H
R94,C68 should be placed near Pin6(RXI),
and should be no vias on the RXI Net.
R95
280R
1%
1206
TB3100M-13-F
D4
J16
1
A
B
C
D
Evaluation Kit Hardware
Evaluation Kit (EK) User Guide
A
B
C
PB1
PB0
PB3
PB2
PB6
PB5
PB8
{3}
{3}
{3}
PB10
PB9
PB7
{3,8}
{3}
{3}
{3}
{3}
{3}
{3}
PB4
8
R219
R220
R221
E0_MDC
E0_MDIO
E0_INTR
22R
22R
22R
22R
8
7
6
5
{3,6,11,13} NRST
1
2
3
4
8
7
6
5
22R
RR18
22R
RR17
1
2
3
4
R218
E0_RX1
E0_RX0
E0_RXDV
E0_RXER
E0_TX1
E0_TX0
E0_TXEN
E0_TXCK
7
RR8
10k
JP12
VDDANA
RR7
10k
0R
3
4
RR6
10k
VDDANA
R105
VDD
OUT
8
7
6
5
1
2
3
4
{3}
VSS
50MHz
OE
8
7
6
5
1
2
3
4
2
1
Y1
10k
2
1
100n
6
40
10
15
33
44
23
30
41
L19
220ohm at 100MHz
1
2
0R
EARTH_ETH0
R117
100n
100n
C86
39
24
25
32
36
35
16
38
34
37
VDDANA
C85
1.5k
C84
R112
R108
26
27
28
29
17
18
19
20
21
0R DNP 22
42
0R
R106
C75
100n
VDDANA
6
C87
10u
10V
VDDANA
RESET
BGRESG
AGND
AGND
AGND
AVDDT
AVDDR
AVDDR
RX-
RX+
TX-
TX+
XT1
0R
5
ETH0_GND
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
DM9161AEP
R119
PWRDWN
DGND
DGND
DGND
DVDD
DVDD
DVDD
DISMDIX
MDC
MDIO
MDINTR
COL/RMII
CRS/PHYAD4
TX_ER/TXD4
RX_ER/RXD4/RPTR
RX_CLK/10BTSER
RX_DV/TESTMODE
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
REF_CLK/XT2
MN12
5
43
C79
2
100n
100n
45
48
31
11
12
13
14
47
5
6
46
ETH0_GND {3}
FULL DUPLEX
R114
6.8k
R113 0R
E0_AVDDT
9
C82
100n
C77
1
4
3
8
7
4
R171
R172
R173
RR9
10k
0R
0R
0R
2 D7
ETH0_GND
VDDANA
2
C81
10u
10V
2200R
L10
R177
ETH0_GND
C80
10u
10V
1
E0_AVDDT
4
1
0R DNP
0R DNP
0R DNP
R168
470R
VDDANA
R111
49.9R
R109
49.9R
C76
100n
C83
100n
2
1
ETH0_LED2 {3}
ETH0_LED1 {3}
ETH0_LED0 {3}
EARTH_ETH0
0R
R182
C78
100n
0R
0R
R179
R181
0R
R178
3
11
10
5
J17
1nF
DNP
DNP
DNP
DNP
DNP
75
75
ETH0_AVDDT {3}
ETH0_TX+ {3}
ETH0_TX- {3}
ETH0_RX+ {3}
ETH0_RX- {3}
6
RX-
470R
470R
8
7
5
4
3
RX+
1/1
MODIF.
SCALE
REV
B
A
R116
R115
75
75
2
TX-
VDDANA
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
EARTH_ETH0
J0026D21B
TX+
1
2
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
ETH0
AT91SAM9x5-EK
Right LED
Left LED
8 RD-
6 CT
7 RD+
2 TD-
3 CT
1 TD+
4
0R
0R
0R
0R
0R
SHEET
10
14
B
DATE
XX-XXX-XX
XX-XXX-XX
REV.
VER.
X.X
X.X
Optional PHY
Embedded on CM board
RJ45 ETHERNET CONNECTOR
R180
R183
R184
R185
R186
Place close to J17
(Only For SAM9G35/SAM9X35/SAM9G25/SAM9X25)
Optional PHY
Embedded on CM board
R174
R175
R176
Red
R110
49.9R
0R
R107
49.9R
3
ETH0
15
R104
8
7
6
5
1
2
3
4
7
8
7
6
5
1
2
3
4
16
9
Evaluation Kit (EK) User Guide
12
D
8
A
B
C
D
Evaluation Kit Hardware
11115A–ATARM–27-Jul-11
4-73
PC30
PC31
PC26
{3,14}
{3}
{3,14}
A
B
PC21
PC20
PC28
PC16
{3,7,14} SELCONFIG
PC29
PC19
PC18
PC27
C
{3,14}
{3,14}
{3,14}
{3,14}
{3,14}
{3,14}
{3,14}
{3,14}
1
2
3
4
1
2
3
4
E1_TXCK
5
22R
RR12
22R
RR10
8
7
6
5
8
7
6
5
E1_INTR
E1_RXER
E1_CRSDV
E1_RX0
E1_RX1
SELCONFIG
8
7
6
5
1
2
3
4
5
6
7
8
9
10
74AC244SC
GND
OE1
I0
O4
I1
O5
I2
O6
I3
O7
MN17
VCC
OE2
O0
I4
O1
I5
O2
I6
O3
I7
E1_INTR
SELCONFIG
E1_TXCK
E1_MDC
E1_MDIO
E1_INTR
20
19
18
17
16
15
14
13
12
11
VDDIOP1
E1_TXCK
E1_TX1
E1_TX0
E1_TXEN
C114 100n
VDDIOP1
E1_RXER
SELCONFIG
RR14
10k
4
{3,6,10,13} NRST
RR13
10k
RR15
10k
0R
JP13
VDDIOP1
R133
0R
47k
R134
100n
100n
C98
C99
100n
C97
1.5k
R125
3
BGRESG
AGND
AGND
AGND
AVDDT
AVDDR
AVDDR
RX-
RX+
TX-
TX+
XT1
C100
10u
10V
R136
VDDIOP1
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
DM9161AEP
L20
220ohm at 100MHz
1
2
RESET
PWRDWN
DGND
DGND
DGND
DVDD
DVDD
DVDD
DISMDIX
MDC
MDIO
MDINTR
COL/RMII
CRS/PHYAD4
TX_ER/TXD4
RX_ER/RXD4/RPTR
RX_CLK/10BTSER
RX_DV/TESTMODE
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
C88
100n
VDDIOP1
REF_CLK/XT2
MN13
3
4
EARTH_ETH1
40
10
15
33
44
23
30
41
VDDIOP1
39
24
25
32
36
35
16
38
34
37
26
27
28
29
17
18
19
20
21
0R DNP 22
42
OUT
VDD
10k
0R
2 VSS
50MHz
Y2
1 OE
R120
R122
VDDIOP1 R128
E1_CRSDV
E1_RX1
E1_RX0
R121
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
1
2
3
4
22R
RR11
8
7
6
5
1
2
3
4
3
C92
2
100n
100n
0R
45
48
31
11
12
13
14
47
5
6
46
GND_ETH1
R130
6.8k
R129 0R
E1_AVDDT
9
C95
100n
C90
1
4
3
8
7
43
2200R
L11
C93
10u
10V
1
2
2
2
R169
11
1/1
MODIF.
SCALE
REV
B
A
470R
VDDIOP1
Right LED
Left LED
75
R132
R131
75
75
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
75
2
3
6
TX-
RX+
RX-
SHEET
11
14
B
1
DATE
XX-XXX-XX
XX-XXX-XX
VDDIOP1
REV.
VER.
X.X
X.X
470R
470R
8
7
5
4
1
TX+
EARTH_ETH1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
ETH1
5
4
8 RD-
6 CT
7 RD+
2 TD-
3 CT
1nF
J18
J0026D21B
RJ45 ETHERNET CONNECTOR
1 TD+
10
AT91SAM9x5-EK
1 Red
EARTH_ETH1
FULL DUPLEX2 D8
RR16
10k
C91
100n
GND_ETH1
GND_ETH1
R127
49.9R
VDDIOP1GND_ETH1
C96
100n
E1_AVDDT
R126
49.9R
C94
10u
10V
R124
49.9R
E1_AVDDT
R123
49.9R
C89
100n
(Only For SAM9X25)
ETH1
1
16
D
2
1
4
8
7
6
5
1
2
3
4
15
4-74
9
11115A–ATARM–27-Jul-11
12
5
A
B
C
D
Evaluation Kit Hardware
Evaluation Kit (EK) User Guide
Evaluation Kit (EK) User Guide
A
B
C
J19
1 2
EARTH_USB
3 4
B1
B2
B3
B4
5
6
EARTH_USB
EARTH_USB
7
{14}
VBUS
DM
DP
ID
GND
1
2
3
4
5
G3515-09010101-00
J20
5V_INTER
USB A HOST/DEVICE INTERFACE
EARTH_USB
L21
220ohm at 100MHz
1
2
B
A
Dual USB A
A1
A2
A3
A4
SHD
D
USB HOST B&C INTERFACE
5
C109
100n
C107
100n
C105
100n
C102
100n
2
L13
2
1
L14
2
220ohm at 100MHz
1
1
2
82k
4
5V
R139
47k
(VBUS_SENSE)
+ C110 220ohm at 100MHz
33u
C111
15p
R138
L12
+ C106 220ohm at 100MHz
33u
C108
100n
L15
+ C104
33u
+ C103
33u
1
220ohm at 100MHz
4
ENA
ENB
FLGB
3V3
{3}
R140
47k
PB16
ENB
FLGB
FLGA
ENA
4
3
2
1
4
3
2
1
3
OVCUR_USB
PB17
R137
47k
{3}
USBA_DM {3}
USBA_DP {3}
EN5V_HDA#
3V3
USBC_DM {3}
USBC_DP {3}
EN5V_HDC#
PB17
USBB_DP {3}
USBB_DM {3}
EN5V_HDB#
OVCUR_USB
ACTIVE LOW
AIC1526-0GS
OUTB
GNG
IN
OUTA
MN14
FLGA
5
6
7
8
AIC1526-0GS
OUTB
GNG
IN
OUTA
(IDUSBA)
5
6
7
8
MN15
C101
100n
5V
3
LCD_DETECT# {14}
{3,14}
{3,14}
{3}
{3}
{3}
2
PD17
PD16
PD20
PD19
PD18
C118 100n
2
VDDNF
24
23
22
21
20
19
18
17
16
15
14
13
1/1
DES.
DATE
Derek 11-Oct-10
Derek 10-JUN-10
SHEET
12
14
1
B
DATE
XX-XXX-XX
XX-XXX-XX
REV.
VER.
X.X
X.X
ZB_SLPTR {6}
ZB_RSTN {6}
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
USB INTERFACE
C119 100n
EN5V_HDC#
EN5V_HDB#
EN5V_HDA#
3V3
MODIF.
SCALE
REV
B
A
SN74AVC8T245PWR
VCCA VCCB1
DIR VCCB2
A1
OE
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
GND1
B8
GND2 GND3
MN18
AT91SAM9x5-EK
1
2
3
4
5
6
7
8
9
10
11
12
1
A
B
C
D
Evaluation Kit Hardware
11115A–ATARM–27-Jul-11
4-75
4-76
A
B
C
D
VBAT
BP2
BP1
{3,14}
PB18
5
ONE_WIRE
ONE WIRE EEPROM
WAKE UP
NRST
{3,4}
PUSH BUTTON
R145
R141
100k
4
3V3
4
0R
1
2
R144
1.5k
VDDANA
R142
1.5k
NC1
NC2
NC3
NC4
DS2431P
GND
I/O
MN16
{3,6,10,11}
3
4
5
6
3
WAKE UP {3}
NRST
3
{3}
C112
100n
3V
1/1
MODIF.
SCALE
REV
B
A
C113
2.2u
JP14
DES.
DATE
2
1
SHEET
13
14
B
DATE
XX-XXX-XX
XX-XXX-XX
REV.
VER.
X.X
X.X
D6
LM4040BIM3-3.0+T
R143
1.5k
Derek 11-Oct-10
Derek 10-JUN-10
5V
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
Miscellaneous
AT91SAM9x5-EK
ADVREF
2
VDDANA
ANALOG Reference 3V
2
1
11115A–ATARM–27-Jul-11
3
5
A
B
C
D
Evaluation Kit Hardware
Evaluation Kit (EK) User Guide
Evaluation Kit (EK) User Guide
A
B
C
D
4
PC24
PC27
PC29
PB11
PB13
PB15
{3,7}
{3,11}
{3,11}
{3}
{3}
{3}
5
{3,6}
PA21
{3,6}
PA23
{3,7,11} SELCONFIG
{3,12}
PD16
PC16
PC18
PC20
PC22
PC1
PC3
PC5
PC7
PC9
PC11
{3,11}
{3,11}
{3,11}
{3,7}
{3}
{3}
{3}
{3}
{3}
{3}
{4}
VDDISI
{3,6} PA7
{3,8} PA31
DNP
0R
0R
0R
0R
R156
R158
R160
R163
R187
0R
0R
0R
22R
22R
22R
R208
R209
R210
R150
R152
R154
22R
22R
22R
22R
PB18
0R
0R
0R
22R
22R
22R
22R
22R
22R
R204
R205
R206
R207
{12} 5V_INTER
R188
R189
R190
R191
R192
R193
R147
R146
4
LCDHSYNC
SPI1_MISO
SPI1_SPCK
EN_PWRLCD
AD0_XP
AD2_YP
AD4_LR
LCDDISP
LCDVSYNC
LCDDEN
LCDDAT16
LCDDAT18
LCDDAT20
LCDDAT22
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
J21
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3
ESW-120-33-L-D
J22
ESW-115-33-L-D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
LCDDAT1
LCDDAT3
LCDDAT5
LCDDAT7
LCDDAT9
LCDDAT11
ZB_IRQ0
TWCK0
3V3
5V_INTER
ISI_D1
ISI_D3
ISI_D5
ISI_D7
ISI_D9
ISI_D11
ISI only For SAM9G25
LCD only for SAM9G15/SAM9G35/SAM9X35
5
ISI_MCK
ISI_VSYNC
ISI_HSYNC
ISI_PCK
ISI_D0
ISI_D2
ISI_D4
ISI_D6
ISI_D8
ISI_D10
R157
R159
R161
R170
R151
R153
R155
R215
R216
R217
R211
R212
R213
R214
1/1
MODIF.
SCALE
REV
B
A
0R
0R
0R
0R
0R
0R
0R
22R
22R
22R
22R
22R
22R
22R
R148
R149
R194
R195
R196
R197
R198
R199
R200
R201
R202
R203
{3}
{3}
{3,13}
{3,11}
{3,11}
{3,11}
{3}
{3,11}
{3,11}
{3,7}
PA13
PA30
PC15
PC13
PC14
PC12
PC0
PC2
PC4
PC6
PC8
PC10
DES.
DATE
2
1
SHEET
14
14
B
DATE
XX-XXX-XX
XX-XXX-XX
A
B
C
{3,5,6} D
{3,8}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
REV.
VER.
X.X
X.X
PA22
{3,6}
PA0
{3,6,7}
LCD_DETECT# {12}
PD17
{3,12}
PB12
PB14
PB18
PC26
PC28
PC30
PC17
PC19
PC21
PC23
Derek 11-Oct-10
Derek 10-JUN-10
0R
0R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
LCD & ISI
AT91SAM9x5-EK
SPI1_MOSI
SPI1_NPCS1
AD1_XM
AD3_YM
ONE_WIRE
LCDPCK
LCDHSYNC
LCDPWM
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT23
LCD/TSC
ZB_IRQ1
TWD0
LCDDAT15
LCDDAT13
LCDDAT14
LCDDAT12
LCDDAT0
LCDDAT2
LCDDAT4
LCDDAT6
LCDDAT8
LCDDAT10
LCD & ISI
2
Evaluation Kit Hardware
11115A–ATARM–27-Jul-11
4-77
Evaluation Kit Hardware
4.4
Optional Display Module (DM) Board Hardware
4.4.1
DM Board Overview
The optional DM board carries a 5.0" TFT LCD module with touch screen. The DM board also carries
four QTouch pads.
Figure 4-54. DM Board Layout
4.4.2
Equipment List
The list of the DM board components follows:
One 5.0" TFT LCD module
LCD Back light driver
3.3V regulator
QTouch device
1-Wire device
4.4.3
Function Blocks
4.4.3.1
3.3V Regulator
The DM Board features its own LDO for local power regulation. It accepts DC 5V power from a 500 mA
high-side power switch on the EK and outputs a regulated +3.3 V to most other circuits on the board.
Figure 4-55. DM Board Power Supply
5V_INTER
2
3
SELCONFIG
C12
10u
4-78
11115A–ATARM–27-Jul-11
C13
100n
3V3_LCD
MN3
1
C15
2.2u
VIN
VOUT
5
GND
EN
BY P
4
C10
10u
C11
100n
SPX3819
500mA capability
Evaluation Kit (EK) User Guide
Evaluation Kit (EK) User Guide
5'' LCD,
800(H)×RGB×480(V)
FL500WVR00-A0T
FOXLINK
PIN 45
PIN 1
J1
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C5
100n
X_RIGHT
Y _LOW
X_LEFT
Y _UP
C6
10u
3V3_LCD
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
RED6
RED5
RED4
RED3
RED2
RED1
RED0
LCDPCK
LCDDEN
LCDVSY NC
LCDHSY NC
VLED+
VLED-
RED[0..7]
GREEN[0..7]
BLUE[0..7]
R1
R2
R3
R4
BLUE2
BLUE1
BLUE0
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
R7
10n
DNP
C1
RED2
RED1
RED0
RED3
RED4
RED5
RED6
RED7
GREEN1
GREEN0
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
GREEN7
10n
DNP
C4
0R
0R
0R
0R
27R
10n
DNP
C3
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
R4 R42
R43
R3 R44
R46
R2 R47
R48
R1 R49
R50
R0 R51
R52
R53
R54
R55
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
R64
220K
DNP
R38
R37
G5 R24
R25
G4 R26
R27
G3 R28
R29
G2 R30
R32
G1 R34
R33
G0 R35
R36
R18
R20
R21
B4 R10
R8
B3 R11
R9
B2 R12
R13
B1 R14
R15
B0 R16
R17
10n
DNP
C2
LCDDAT18
LCDDAT17
LCDDAT16
LCDDAT19
LCDDAT20
LCDDAT21
LCDDAT22
LCDDAT23
LCDDAT9
LCDDAT8
LCDDAT10
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
LCDDAT2
LCDDAT1
LCDDAT0
LCDDAT3
LCDDAT4
LCDDAT5
LCDDAT6
LCDDAT7
LCDDISP
AD2_Y P
AD1_XM
AD3_Y M
AD0_XP
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
LCDDAT5
LCDDAT6
LCDDAT7
LCDDAT8
LCDDAT9
LCDDAT10
LCDDAT0
LCDDAT1
LCDDAT2
LCDDAT3
LCDDAT4
4.4.3.2
Conductors
on
TOP SIDE
M1
LED2+
LED2LED1+
LED1GND6
X1
Y1
X2
Y2
GND5
GND4
DE
VSY NC
HSY NC
STB
DOTCLK
GND3
B7
B6
B5
B4
B3
B2
B1
B0
G7
G6
G5
G4
G3
G2
G1
G0
R7
R6
R5
R4
R3
R2
R1
R0
VCC2
VCC1
GND2
GND1
Evaluation Kit Hardware
TFT LCD with Touch Panel
A 5" 800x480 LCD provides the DM with a low power display feature, back light unit and a touch panel,
similar to that used on commercial PDAs.
Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24bit data signals (8bit x RGB by default) or 16-bit data signals (5+6+5bit x RGB in option). This allows the
user to develop graphical user interfaces for a wide variety of end applications.
Warning: Never connect/disconnect the LCD display from the board while the power supply is on. Doing
so may damage both units.
Figure 4-56. LCD with Touch Panel
11115A–ATARM–27-Jul-11
4-79
Evaluation Kit Hardware
4.4.3.3
Back Light
The back light voltage is generated from a CP2122ST boost converter. It is powered directly by the DC
5V from the EK board. The back light level is controlled by a PWM signal generated from the MPU
Device processor.
Figure 4-57. Back Light Control
L1
22uH
880mA
5V_INTER
RB160M-60
60V/1A
5
4
LCDPWM
24.5V/40mA VLED+
D1
5V/217mA
C7
10u
10V
MN1
VIN
SW
GND
SHDN#
FB
C9
2.2u
50V
1
2
3
CP2122ST
300mV
VLED-
R40
10k
R41
7R5
2 x 7 LEDs Back Light
2*20mA, 24.5V
4.4.3.4
QTouch
The DM board carries a QTouch device piloted through a TWI interface. It manages four capacitive
touch buttons directly printed on the PCB.
There are dual footprints for the QTouch device, and SOIC is the default mounted one.
Figure 4-58. QTouch
3V3_LCD
MN5
C16
3V3_LCD
3V3_LCD
C14
R63 R56 R57 R58
DNPDNP
100n
9
MODE(VSS)
Thermal
21
8
4-80
11115A–ATARM–27-Jul-11
VSS
KEY 0
KEY 1
KEY 2
KEY 3
KEY 4
KEY 5
14
13
12
11
10
9
8
R65
R66
R67
R68
4.7k
4.7k
4.7k
4.7k
QT1070_SOIC
KEY 6
KEY 5
QT1070 KEY 4
NC5
DNP KEY 3
NC4
KEY 2
NC3
KEY 1
NC2
KEY 0
NC1
NC0
VSS
6
7
10
18
19
20
SCL
SDA
CHANGE
RESET
11
15
12
14
13
VDD
MODE(VSS)
SDA
RESET
CHANGE
SCL
KEY 6
VDD
MN4
10k 4.7k 4.7k 4.7k
TWCK0
TWD0
CHANGE#
RESET#
1
2
3
TWD0
RESET# 4
5
CHANGE#
6
TWCK0
7
100n
16
17
1
2
3
4
5
KEY 4
KEY 3
KEY 2
KEY 1
R59
R60
R61
R62
4.7k DNP
4.7k DNP
4.7k DNP
4.7k DNP
KEY K4
KEY K3
KEY K2
KEY K1
Evaluation Kit (EK) User Guide
Evaluation Kit Hardware
4.4.3.5
1-Wire
The DM board also uses a 1-Wire device as “firmware label” to store the information such as chip type,
manufacturer’s name, production date etc.
Figure 4-59. 1-Wire on DM
3V3_LCD
R45
4.7k
ONE_WIRE
MN2
1
2
3
4
NC1
NC2
DATA
GND
NC6
NC5
NC4
NC3
8
7
6
5
DS2433S
Evaluation Kit (EK) User Guide
4-81
11115A–ATARM–27-Jul-11
A
B
C
D
FOXLINK
4
5
CP2122ST
SHDN#
VIN
MN1
L1
22uH
880mA
SW
GND
FB
1
2
3
C13
100n
5
C15
2.2u
3
2
1
BYP
VOUT
4
5
C10
10u
RB160M-60
60V/1A
D1
PIN 1
SPX3819
500mA capability
EN
GND
VIN
MN3
2*20mA, 24.5V
2 x 7 LEDs Back Light
5V_INTER
R40
10k
C12
10u
SELCONFIG
LCDPWM
C7
10u
10V
5V/217mA
5V_INTER
FL500WVR00-A0T
5'' LCD,
800(H)×RGB×480(V)
PIN 45
Conductors
on
TOP SIDE
M1
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VLED-
VLED+
C11
100n
3V3_LCD
R41
7R5
300mV
C9
2.2u
50V
24.5V/40mA
J1
LED2+
LED2LED1+
LED1GND6
X1
Y1
X2
Y2
GND5
GND4
DE
VSYNC
HSYNC
STB
DOTCLK
GND3
B7
B6
B5
B4
B3
B2
B1
B0
G7
G6
G5
G4
G3
G2
G1
G0
R7
R6
R5
R4
R3
R2
R1
R0
VCC2
VCC1
GND2
GND1
ONE_WIRE
C5
100n
R45
4.7k
1
2
3
4
3V3_LCD
3V3_LCD
C6
10u
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
RED6
RED5
RED4
RED3
RED2
RED1
RED0
LCDPCK
4
8
7
6
5
RED[0..7]
GREEN[0..7]
BLUE[0..7]
NC6
NC5
NC4
NC3
DS2433S
NC1
NC2
DATA
GND
MN2
X_RIGHT
Y_LOW
X_LEFT
Y_UP
LCDDEN
LCDVSYNC
LCDHSYNC
VLED+
VLED-
R1
R2
R3
R4
BLUE2
BLUE1
BLUE0
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
R7
10n
DNP
C1
RED2
RED1
RED0
RED3
RED4
RED5
RED6
RED7
GREEN1
GREEN0
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
GREEN7
10n
DNP
C4
0R
0R
0R
0R
C3
10n
DNP
R18
R20
R21
R53
R54
R55
R4 R42
R43
R3 R44
R46
R2 R47
R48
R1 R49
R50
R0 R51
R52
R38
R37
G5 R24
R25
G4 R26
R27
G3 R28
R29
G2 R30
R32
G1 R34
R33
G0 R35
R36
B0
B1
B2
B3
R10
R8
R11
R9
R12
R13
R14
R15
R16
R17
27R
B4
10n
DNP
C2
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
0R
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
R64
220K
DNP
3
3
LCDDAT18
LCDDAT17
LCDDAT16
LCDDAT19
LCDDAT20
LCDDAT21
LCDDAT22
LCDDAT23
LCDDAT9
LCDDAT8
LCDDAT10
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
LCDDAT2
LCDDAT1
LCDDAT0
LCDDAT3
LCDDAT4
LCDDAT5
LCDDAT6
LCDDAT7
LCDDISP
AD2_YP
AD1_XM
AD3_YM
AD0_XP
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
LCDDAT5
LCDDAT6
LCDDAT7
LCDDAT8
LCDDAT9
LCDDAT10
LCDDAT0
LCDDAT1
LCDDAT2
LCDDAT3
LCDDAT4
3V3
10k 4.7k 4.7k 4.7k
TWCK0
TWD0
CHANGE#
RESET#
R63 R56 R57 R58
DNP DNP
3V3_LCD
0R
6
7
10
18
19
20
15
12
14
13
AD0_XP
AD2_YP
AD4_LR
J2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
NC5
NC4
NC3
NC2
NC1
NC0
QT1070
DNP
SCL
SDA
CHANGE
RESET
KEY6
KEY5
KEY4
KEY3
KEY2
KEY1
KEY0
100n
3V3_LCD
C14
TSM-120-01-L-DV-A
J3
2
0R
16
17
1
2
3
4
5
KEY4 R59
KEY3 R60
KEY2 R61
KEY1 R62
C16
LCD_DETECT R23
AD1_XM
AD3_YM
R19
LCDPWM
LCDHSYNC
LCDPCK
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT23
TWD0
LCDDAT15
LCDDAT13
LCDDAT14
LCDDAT12
LCDDAT0
LCDDAT2
LCDDAT4
LCDDAT6
LCDDAT8
LCDDAT10
TSM-115-01-L-DV-A
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
MN4
LCDDISP
LCDVSYNC
LCDDEN
LCDDAT16
LCDDAT18
LCDDAT20
LCDDAT22
5V_INTER
ZB_IRQ0
TWCK0
1
3
5
7
9
11
13
15
17
LCDDAT1 19
LCDDAT3 21
LCDDAT5 23
LCDDAT7 25
LCDDAT9 27
LCDDAT11 29
0R DNP
0R DNP
CHANGE#
SELCONFIG R22
R5
R6
3V3_LCD
9
VDD
MODE(VSS)
4
VSS
8
4-82
11
11115A–ATARM–27-Jul-11
Thermal
1
2
3
4
5
6
7
VSS
KEY0
KEY1
KEY2
KEY3
KEY4
KEY5
14
13
12
11
10
9
8
B
A
1/1
MODIF.
SCALE
REV
R65
R66
R67
R68
1
KEY K1
KEY K2
KEY K3
KEY K4
DES.
DATE
1
1
B
DATE
SHEET
REV.
VER.
Derek 11-Oct-10 X.X XX-XXX-XX
Derek 10-JUN-10 X.X XX-XXX-XX
4.7k
4.7k
4.7k
4.7k
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
LCD BOARD
AT91SAM9x5-EK
XX-XXX-XX
QT1070_SOIC
VDD
MODE(VSS)
SDA
RESET
CHANGE
SCL
KEY6
MN5
4.7k DNP
4.7k DNP
4.7k DNP
4.7k DNP
TWD0
RESET#
CHANGE#
TWCK0
100n
3V3_LCD
0R
ONE_WIRE
1
A
B
C
D
4.4.4
21
5
Evaluation Kit Hardware
Schematics
Figure 4-60. DM Board Schematics
Evaluation Kit (EK) User Guide
Section 5
Revision History
5.1
Revision History
Table 5-1.
Document
Comments
11115A
First issue.
Evaluation Kit (EK) User Guide
Change
Request Ref.
5-1
11115A–ATARM–27-Jul-11
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11115A–ATARM–27-Jul-11
