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Omni
Technical Specification
3.5.1.3 SPI Bus Pin Description
Signal
Product
Pin
number
I/O
I/O
type
Reset
state
Description
Multiplexed
with
SPI1-CLK
19
O
2V8
Z
SPI Serial Clock
GPIO28
SPI1-IO
18
I/O
2V8
Z
SPI Serial input/output
GPIO29
SPI1-I
17
I
2V8
Z
SPI Serial input
GPIO30
SPI1-CS
20
O
2V8
Z
SPI Slave Enable
GPIO31
Table 14: SPI Bus Pin description
See Chapter 3.4, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and
Reset state definitions.
3.5.2 I2C Bus
3.5.2.1 Features
The I2C interface includes a clock signal (SCL) and data signal (SDA) complying with a 100Kbit/s-standard interface
(standard mode: s-mode).
3.5.2.2 Characteristics
The I²C bus is always master.
The maximum speed transfer range is 400Kbit/s (fast mode: f-mode).
For more information on the bus, see document [4] “I²C Bus Specification”, Version 2.0, Philips Semiconductor 1998
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