Download Evaluating and Programming the 29K RISC Family Third

0.83% Pipeline Latency
Total Wait:
276 cycles
(0.00001104 seconds)
–––––––––– Branch Target Cache ––––––––––
Partial hits:
0
Branch btcache access:
2418
Branch btcache hits:2143
Branch btcache hit ratio:
88.63%
–––––––––– Translation Lookaside Buffer ––––––––––
TLB access:
0
TLB hits:
0
TLB hit ratio:
0.00%
–––––––––– Bus Utilization ––––––––––
Inst Bus Utilization:
70.01%
2288 Instruction Fetches
Data Bus Utilization:
20 Loads
335 Stores
10.86%
–––––––––– Register File Spilling/Filling ––––––––––
0 Spills,
0 Fills
Opcode Histogram
ILLEGAL:
CONSTN:6
CONSTH:68
CONST:121
MTSRIM:5
CONSTHZ:
LOADL:
LOADL:
CLZ:
CLZ:
EXBYTE:
EXBYTE:
. . .
System Call Count Histogram
EXIT
1:1
GETARGS
260:1
SETVEC
289:2
. . .
–––––– M E M O R Y
S U M M A R Y ––––––
Memory Parameters for Non–banked Regions
I_SPEED: Idecode=0 Iaccess=1 Ibaccess=1
. . .
The simulator reports the total number of processor cycles simulated. Because
our example is brief, there are few User mode cycles. Most cycles are utilized by the
osboot operating system. The operating system runs in Supervisor mode and initializes the processor to run the “hello world” program in User mode. The fast memory
system has enabled the processor pipeline to be kept busy, an 8.45% idle pipeline is
reported. A breakdown of the activities contributing to pipeline stalling is shown.
Next reported is the Branch Target Cache (BTC) activity. If a processor incorporating an Instruction Cache Memory rather than a BTC had been simulated, the corresponding results would replace the BTC results shown. There were 2418 BTC accesses, of which 2143 found valid entries. This gives a hit ratio of 88.63%. Partial hits
refer to the number of BTC entries which were not fully used. This occurs when one
of the early entries in the four–entry cache block contains a jump.
Chapter 1
Architectural Overview
85