1
Download NAMC-STM1_4_manual
Transcript
NAMC-STM1/4 – Technical Reference Manual Conventions If not otherwise specified, addresses and memory maps are written in hexadecimal notation, identified by 0x. Table 1 gives a list of the abbreviations used in this document: Table 1: List of used abbreviations Abbreviation Description b B CPLD CPU DDR DMA DRAM E1 FLASH FPGA H.110 iTDM J1 LIU MCH MPC8560 µTCA PCIe PCI-X RAM ROM SDRAM SMC T1 TDM TSI TSA Bit, binary byte Complex Programmable Logic Device Central Processing Unit Dual Data Rate Direct Memory Access Dynamic RAM 2.048 Mbit G.703 Interface Reprogrammable ROM Field Programmable Gate Array Time-Slot Interchange Bus internal TDM 1,544 Mbit G.703 Interface (Japan) Line Interface Unit µTCA Carrier Hub Embedded Processor from Freescale Micro Telecommunications Computing Architecture PCI Express Extended PCI Random Access Memory Read Only Memory Synchronous Dynamic RAM Serial Communication Controller of the MPC8560 1,544 Mbit G.703 Interface (USA) Time Division Multiplex Time Slot Interchange Time Slot Assigner Version 1.3 © N.A.T. GmbH 7
