Download ADC MLN7400 User's Manual

Cost Effective
Network Processor
for TCP/IP
with ARM7TDMI™
MLN7400
Evaluation Board Manual
Version 0.20
December 31, 2003
MCS Logic Inc.
Copyright © 2003 MCS LOGIC Limited. All rights reserved
EVB7400
EVB7400
Revision History
Version
V 0.10
Date
December 30, 2003
Revision Description
First Release
User’s Manual V.0.10
2/36
Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
User’s Manual V.0.10
3/36
Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
Table of Contents
CHAPTER 1
1.1
1.2
SYSTEM REQUIREMENTS ............................................................................................................................................ 6
BOARD COMPONENTS ................................................................................................................................................ 8
CHAPTER 2
2.1
2.2
2.3
2.4
BOARD CONFIGURATION.............................................................................................. 11
ENDIAN SELECTION (SW1) ...................................................................................................................................... 11
BOOT ROM AND ROM BANK0 LENGTH SELECTION (SW2).................................................................................... 11
NAND FLASH ....................................................................................................................................................... 11
GPIO SETTING......................................................................................................................................................... 12
CHAPTER 3
3.1
3.2
INTRODUCTION.................................................................................................................. 6
SETUP EVB7400 ENVIRONMENTS ................................................................................ 13
ETHERNET 10/100 BASE-T CONNECTOR ................................................................................................................ 13
CONNECTION METHOD FOR UTP CABLE ................................................................................................................. 13
CHAPTER 4
CONNECTION CONFIGURATIONS FOR DEBUG CONSOLE.................................. 15
4.1
CONFIGURATION THE HYPER TERMINAL ................................................................................................................. 15
4.2
DOWNLOADING BINARY IMAGE AND FLASH WRITE ................................................................................................ 16
4.2.1
Downloading Binary Image ............................................................................................................................ 16
4.2.2
Flash Write...................................................................................................................................................... 19
CHAPTER 5
5.1
5.2
5.3
OPENICE32 ............................................................................................................................................................. 20
CONNECTING EVB7400 AND PC ............................................................................................................................. 20
POWERING UP THE BOARD AND OPENICE32 ........................................................................................................... 20
CHAPTER 6
6.1
6.2
OPENNICE32 INSTALLATION ....................................................................................... 20
EVB7400 1.0 SCHEMETIC AND BOM ............................................................................ 21
EVB7400 BOM....................................................................................................................................................... 21
EVB7400 SCHEMATIC ............................................................................................................................................. 24
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
List of Figures
[ F IGU R E 1 ]
EVB7400 BLOCK DIAGRAM....................................................................................................................... 6
[ F IGU R E 2 ]
MEMORY MAP .......................................................................................................................................... 7
[ F IGU R E 3 ]
BLOCK DIAGRAM (TOP VIEW) .................................................................................................................. 8
[ F IGU R E 4 ]
UTP CABLE CONNECTION...................................................................................................................... 14
[ F IGU R E 5 ]
PROPERTIES SETTING PAGE ................................................................................................................. 15
[ F IGU R E 6 ]
CHOOSE SETTING PAGE........................................................................................................................ 16
[ F IGU R E 7 ]
CONNECTING WITH OPENICE32 ............................................................................................................. 20
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
Chapter 1
Introduction
EVB7400 is a MLN7400 evaluation board and MCS-uClinux training kit that is suitable for code development and exploration of MN7400
with MCS-uClinux. It includes much of the hardware and software required completing your application development. It supports various
function related with network, communication such as IIC, SPI, UART, 10/100 Ethernet, multimedia module such as sound DAC, storage
media such as NAND FLASH memory module. Using the JTAG interface, you can debug the EVB7400 directly.
1.1
System Requirements
-. Host computer : IBM compatible PC
-. EVB7400 (Evaluation Board for MLN7400)
-. DC 5V Power
JTAG
X-Tal/Osc
UART0~4
Ethernet
PHY
(AC101L)
Boot ROM
(ROM Bank0)
10/100
Ethernet
MAC
DMA
4 Console
UARTs
1 highspeed
UART
Memory
Controller
SPI Serial
EEPROM
DAC(CS4340)
2ch GDMA
User Flash
(ROM Bank1)
IIC Serial
EEPROM
&RTC
I2C
Peripheral
Bridge
Peripheral Bus
4KBytes
Cache
M_Bus
ARM7TDMI
M_Bus I/F
PLL
SRAM
(ROM Bank2)
SPI
MIC IN
GPIOs
4 channel
ADC
4 Timers
KEY
MATRIX
NAND Flash
WDT
PCMCIA
Socket
(ROM Bank3)
DAC I/F
Interrupt
Controller
SDRAM
Status
LEDs
Eextenal
Interrupt Key
[ Fi gu re 1 ] EVB7400 BLOCK DIAGRAM
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
ADDRESS
MLN7400 MAP
EVB7400
0x000_0000 ~ 0x0FF_FFFF
ROM/Flash bank 0 (16Mbytes)
FLASH(512KB)
0x100_0000 ~ 0x1FF_FFFF
ROM/Flash bank 1 (16Mbytes)
SRAM(128KB)
0x200_0000 ~ 0x2FF_FFFF
ROM/Flash bank 2 (16Mbytes)
FLASH(2MB)
0x300_0000 ~ 0x3FF_FFFF
ROM/Flash bank 3 (16Mbytes)
PCMCIA Card
0x400_0000 ~ 0x5FF_FFFF
Cacheable SDRAM area (32Mbytes)
SDRAM 64Mbits(8Mbytes)
0x600_0000 ~ 0x600_5FFF
(Cacheable)
0x800_0000 ~ 0xEFF_FFFF
(Non-Cacheable)
0xF00_0000 ~ 0xFFF_FFFF
SFR Registers
[ Fi gu re 2 ] MEMORY MAP
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
1.2
Board Components
The arrangement of major components on the board is shown in Figure 3. The major components include:
[ Fi gu re 3 ] BLOCK DIAGRAM (TOP VIEW)
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
A Flash ROM
There is a socket(U9) which accept 512Kbyte size of 8 bit Flash Memory(AT29C010 ~ 40). This is for diaganostic program(includes all
pheriperal device driver and TCP/IP protocol stack) and BIOS(MCS-uClinux Boot loader) program.
User Flash memory(Selectable Boot ROM)
A mounted 48 TSOP type flash(AM29LV160BB), U8, is mounted for saving MCS-uClinux image. It has 2Mbytes(1M x 16bits)size. If you
want to use this for boot ROM, SW2 should be set to to X16 and U9 should be removed. (The default setting is X8)
SDRAM
SDRAM size is 8Mbytes ( 4M x 16bits)
SRAM
There is a SRAM at ROM Bank1. SRAM SIZE is 64K x 16 bits.
NAND Flash
A mounted NAND Flash ROM is provided for saving user data.
To use NAND flash, you should install and uninstall some 0 ohm register at bottom of board. Please refer to chapter 2 and Schemetic.
EEPROM(AT24C256, AT25040)
There are two EEPROM(U3, U4). One is an IIC Serial EEPROM(U3) and the other is a SPI serial EEPROM(U4).
The size of EEPROM(U3) is 32Kbytes, and the size of EEPROM(U4) is 4Kbytes.
RTC & Thermometer
There is a DS1629(U5) for RTC and thermometer check. The RTC clock is supplied by the crystal(32.768KHz)
Serial Port
There are 5 9-pin female Serial ports for serial data communiation. One is for console between the host PC and EVB7400 and others for
converter(Serial to Ethernet, Serial to wireless and so on). And there is one 9-pin mail Serial ports for High Speed UART.
Ethernet Interface
There are RJ45 connector and Ethernet Phy for network.(AC101L, 10/100 BASE-T)
AUDIO IN/OUT
There is a stereo DAC(CS4340) for AUDIO out. And MIC and AMP is connected to ADIN3(ADC channel3) for AUDIO In.
Reset Button
There is a button for system reset.
Power On/Off Switch
There is a swithch for power on/off.
LED Indicatorst
Seven LEDs are supplied on the EVB7400. Each LED shows power status, user programmable status, ethernet link and activity.
PCMCIA Socket
There is a PCMCIA Socket(J2). To use it, you should set ROM BANK3 as PCMCIA mode.
JTAG Port
One 20-pin JTAG port(J3) is supplied to connect with JTAG based Emulator.
Expansion Connectors
Seven connectors(JP2~JP8) are supplied for system expansion. They contain board data bus, adddress bus, external memory bank
control, IIC, SPI, and MII signals.
Key Matrix
There are 12 key buttons. They can be used ADC application.
Five buttons(SW4, SW7, SW10, SW13, SW15) are connected to ADIN0(ADC channel 0).
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EVB7400
Four buttons(SW5, SW8, SW11, SW14) are connected to ADIN1(ADC channel 1).
Three buttons(SW5, SW8, SW11, SW14) are connected to ADIN2(ADC channel 2).
External Interrrupt Key
There are two button to use external interrupts. Each button(S1,S2) is connected to External interrupt0 and 2.
External Timer0 Clock
Timer0 can be supplied by the external clock(ocsillator)
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
Board Configuration
Chapter 2
The EVB7400 is set with default configuration. You can use the board with the defualt settings direclty. However, you can also change
the settings according to your nedds.
2.1
Endian Selection (SW1)
Status
BIG
Description
BIG Endian
LITTLE
BIG
Little Endian
LITTLE
2.2
Boot ROM and ROM Bank0 length Selection (SW2)
Status
X8
Description
ROM BANK0 Size is 8 bits.
ROM BANK0 : AT29C040 512 X 8bits Flash
ROM BANK2 : AM29LV160BB 1M X 16bits Flash
X16
X8
ROM BANK 0 size is 16 bits.
ROM BANK0 : AM29LV160BB 1M X 16 bits Flash
*Note : AT29C040(U9) should be removed
X16
2.3
NAND FLASH
You can use NAND Flash through GPIO of MLN7400. To use NAND Flash you shoud install 0 ohm registance.
Refer to schementic page4.
Install Register reference
R12, R13, R14, R15, R16,
R17, R18, R19, R20, R21,
R22, R23, R24, R25, R26
Unintall Register Reference
R39, R40, R41,R42, R43,
R44, R54,R55,R56
*Note: To use NAND Flash, you can’t use SPI Interface, Console UART3 and High Speed UART(UART4)
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
2.4
GPIO Setting
<128-TQFP/ 144 -LQFP Common I/O>
PIN
GP00
GP01
GP02
GP03
GP04
GP05
GP06
GP07
GP08
GP09
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP18
GP19
GP20
GP21
GP22
GP23
GP24
GP25
GP26
Shared
CUTXD1
CURXD1
CUTXD2
CURXD2
CUTXD3
CURXD3
CUTXD4
CURXD4
nBE[0]
nBE[1]
TOUT[0]
TOUT[1]
TX_ERR
NTRST
ECSN2
ECSN3/CE1#
SPIMISO
SPIMOSI
SPICLK
EXINT0
EXINT1
EXT_UCLK
REG#/DLRCK
CE2#/DBCK
IORD#/DMCK
IOWR#/DDATA
ENWAIT
Initial
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
S,0
S,I
S,O
S,O
N,I
N,I
N,I
N,I
N,I
N,I
N,I
S,O
N,I
N,I
N,I
Board Setting
UART1
UART1
UART2
UART2
UART3/NFWEN
UART3/NFWRN
UART4/NFALEN
UART4/NFCLEN
SRAM(nBE0)
SRAM(nBE1)
Timer0 TOUT0
SPI SS#
LED 0
JTAG(nTRST)
SRAM(ECSN2)
PCMCIA(CE1#)
SPI MISO/NFCEN
SPI MOSI/NFRDN
SPI Clock/NFRBN
Ext Int0 Test
PCMCIA IRQ
LED 1
PCMCIA REG#/DLRCK
PCMCIA CE2#/DBCK
PCMCIA IORD#DMCK
PCMCIA IOWR#/DDATA
PCMCIA ENWAIT
<144 -LQFP Extended I/O>
Setting
Value
S, O
S, O
S, O
S, O
S, O
S, O
S, O
S, O
S, O
S, O
S, O
N, O
N, O
S, I
S, O
S, O
S, I
S, O
S, O
S, I
S, I
N, O
S, O
S, O
S, O
S, O
S, O
PIN
GP27
GP28
GP29
GP30
GP31
GP32(0)
GP33(1)
GP34(2)
GP35(3)
GP36(4)
GP37(5)
GP38(6)
GP39(7)
GP40(8)
GP41(9)
GP42(10)
Shared
EXT_TCLK0
EXT_TCLK1
EXT_TCLK2
HUARTnDCD4
HUARTnCTS4
HUARTnRTS4
HUARTnDSR4
HUARTnDTR4
EXINT2
EXINT3
TOUT[2]
TOUT[3]
DLRCK
DBCK
DMCK
DDATA
Initial
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
N,I
Board Setting
Ext Timer0 Clk
LED 2
LED 3
NFIO0
NFIO1
NFIO2
NFIO3
NFIO4
Ext Int2 Test
NFIO5
NFIO6
NFIO7
DLRCK
DBCK
DMCK
DDATA
S : Special
N : Noraml
I : Input
O : Output
1) GP22 ~GP25 는 7400P 의 경우 PCMCIA 와 DAC 을
선택적으로 사용
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
Setting
Value
S, I
N, O
N, O
N, I
N, I
N, I
N, I
N, I
S, I
N, I
N, I
N, I
S, O
S, O
S, O
S, O
EVB7400
Chapter 3
3.1
Setup EVB7400 Environments
Ethernet 10/100 BASE-T Connector
Same connector and pin for both 10Base-T and 100 Base-Tx
< At the network interface card/hubs >
< At the cables >
RJ45 female connetor at the network interface cards and hubs
RJ45 male connector at the cable
Pin
1
2
3
4
5
6
7
8
Name
TX+
TXRX+
N/C
N/C
RXN/C
N/C
Descriptions
Tranmit Data+
Tranmit DataReceive Data+
Not Connected
Not Connected
Receive DataNot Connected
Not Connected
NOTE : TX & RX are swapped on hub
3.2
Connection Method for UTP Cable
RJ45 pins on EVB7400 is defined to Adapter side. So, you straight connect EVB7400 to hub through UTP cable. In this case, between
the EVB7400 and the Hub, the pin numbers correspond to each other.
Between the EVB7400 and the NIC which is on the Host PC, you have to connect each other through UTP cable which is crossover
patch cord.
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
[ Fi gu re 4 ]
UTP CABLE CONNECTION
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
Chapter 4
4.1
Connection Configurations for Debug Console
Configuration the Hyper Terminal
To configure the Hyper Terminal, which is a Windows utility program for serial communications, refer to following steps:
1.
2.
3.
Run the Hyper Terminal program
-. Window 95/98/2000/XP start tool bar -> Program -> Accessories -> Hyper Terminal Group
-> Double click Hyperterm.exe -> Enter a connection name -> Select a icon -> Click OK.
Select COM Port to communicate with EVB7400 board.
-. Choose COM1 or COM2 as the serial communication port and click OK.
Set the serial port properties
-. Bits per second: 57600 bps
-. Data Bits : 8 bits
-. Stop Bits : 1
-. Flow control : None
4.
Select the Properties from the File menu
5.
Choose Setting Page.
[ Fi gu re 5 ] PROPERTIES SETTING PAGE
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EVB7400
[ Fi gu re 6 ] CHOOSE SETTING PAGE
6.
7.
4.2
Re-connect Hyper Terminal to run at new properties
Disconnect : Call -> Disconnect
Connect: Call -> Call
Power-On Reset or push the reset button on EVB7400 board
Now, the diagnostic program menu is showed on the Hyper Terminal
Downloading Binary Image and Flash Write
4.2.1
Downloading Binary Image
You can download a binary image file through the serial cable to target without an emulator.
1.
Type “ f ” to download user program to EVM7400 on Diagnostic program main menu.
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EVB7400
2.
Type “8” at Flash Program Menu and type address to download.
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
3.
select the Send File from the Transfer menu
File Name : Select the file name, which you want too download.
Protocol : Select the Xmodem or 1K Xmodem.
4.
Click Ok.
Then, the file that you selected will be downloaded.
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EVB7400
4.2.2 Flash Write
You can write downloaded binary image at User flash memory(AM29LV160BB, U8).
Type “2” to write an executable binary file at User Flash memory.
Then, you can execute your image by changing Boot Rom selection switch(SW2) to X16(default is X8).
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
Chapter 5
5.1
Opennice32 Installation
OPENice32
The OPENice32 can also be connected with the EVB7400 as a debugging system for software applications development. OPENice32 is
a JTAG-based, nonintrusive, debugging system for ARM-based controllers or processors. JTAG provides the interface between a
debugger and the ARM-based controller development board.
To use the OPENice32, the following additional equipment are required:
- OPENice32
- 14-way ribbon cable
- 9-pin RS232 cable or parallel cable
- 5 V DC (Max. 3A) power supply
5.2
Connecting EVB7400 and PC
The OPENice32 should be connected to the EVB7400's JTAG Port (J3) via a 20-way cable, and to the host PC via a 9-pin RS232 serial
or parallel cable.
To power on the OPENice32, DC 5 V power supply is
required.
EVB7400
[ Fi gu re 7 ] CONNECTING WITH OPENICE32
5.3
Powering up the Board and OPENice32
We recommend that you power on the EVB7400 before the OPENice32 is powered on. In this way, the system initialization and memory
configuration for EVB7400 performed by the Boot Code can be completed first.
Otherwise, it may cause the failure of code download via JTAG.
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
EVB7400 1.0 Schemetic and BOM
Chapter 6
6.1
EVB7400 BOM
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PART NO
MLN7400
MLN7400P
AT24C256
AT25040
DS1629
K6R1016V1D
K4S641632
AM29LV160BB
AT29C040A
AC101L
H1102
MAX3232
74LVC14
74LV08
AMS1086
MAX4468EKA
CS4340
K9F2808-YCB0
Xtal_osc 10MHz
GEOMETRY
144LQFP
128TQFP
8 SOIC
8 SOIC
8 SOIC
44TSOP
54TSOP
48TSOP
32DIP
48 TQFP
8pin SOT23
16 SOIC
48 TSOP
Half
COUNT
1
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
20
Xtal_osc 25MHz
Half
1
21
Crystal 32.768KHz
22
Crystal 10MHz
23
24
25
26
Xtal_oxc 1MHz
Battery
Battery Connector
PushButton SW
DIP(cylinder
1
type)
DIP(ATS Holder 1
type)
Half
1
CR2032
1
1
15
27
28
29
30
31
32
DPDT SW
Power Toggle SW
1N4004
1N4148
LED
PCMCIA 68Pin Con
33
34
35
36
37
RJ-45
HEADER 10X2
POWER JACK
MIC IN JACK
AUDIO OUT JACK
16 SOIC
3pin DIP
DIP
SMD
3
1
2
1
5
1
1
1
1
1
1
DESCRIPTION
Microprocessor
Microprocessor
EEPROM(IIC)
EEPROM(SPI)
RTC
SRAM
SDRAM
Flash
Flash
PHY
Transformer
RS232
Regulator
AMP
Stereo DAC
NAND Flash
Xtal-Oscillator
(System CLK)
Xtal-Oscillator
(PHY CLK)
Crystal(RTC)
Crystal
(System CLK)
Test CLK
3V coin Battery
REFERENCE
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12, U13, U14
U15
U16
U17
U18
U20
U21
X2
Vendor
MCS Logic
MCS Logic
Atmel
Atmel
Dallas
Samsung
Samsung
AMD
Atmel
Altima
PULSE
MAXIM
semtech
MAXIM
CRYSTAL
Samsung
Y2
Y1
X1
X3
BT1
Reset, ExtInt
S1,S2,S3,SW4,SW5,
SW6,SW7,SW8,SW9,SW10,SW11,
SW12,SW13,SW14,
SW15
SW1,SW2,SW16
A12AP
SW3
NKK
Diode
D1,D2
Diode
D3
D4,D5,D6,D7,D8
ICM-C68H-S112- J2
JST
400N1
J1
JTAG
J3
DC5V PWR
J4
J5
J6
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Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
38
39
40
DB9 FEMAIL
DB9 MAIL
HEADER 13X2
5
1
4
41
42
43
44
HEADER 24X2
HEADER 4X2
HEADER 6X2
HEADER 1
1
1
1
7
UART0~4
HUART Option
DATA, MII,
ADDRESS,
MEMORY
GPIO heaser
IIC & SPI
HUART header
Test Pin
45
46
Beads(100Mhz)
0
2012
0603(1608)
1
68
L
R
47
48
0
33
1206(3216)
0603(1608)
4
12
R
R
59
50
51
52
53
54
55
56
57
58
49.9
75
100
270
330
390
500
560
820
1K
0603(1608)
0603(1608)
0603(1608)
0603(1608)
0603(1608)
0603(1608)
0603(1608)
0603(1608)
0603(1608)
0603(1608)
4
5
1
3
5
3
2
4
1
10
R
R
R
R
R
R
R
R
R
R
59
60
61
62
2K
3K
2.2K
4.7K
0603(1608)
0603(1608)
0603(1608)
0603(1608)
4
1
1
50
R
R
R
R
63
64
10K
20K
0603(1608)
0603(1608)
5
1
R
R
P1,P2,P3,P4,P5
P6
JP3,JP4,JP6,JP8
JP7
JP2
JP5
JP1,TP1,TP2,TP3,TP4
TP5, TP6
L1
R8,R9,R10,R11,R12,
R13,R14,R15,R16,R17,
R18,R19,R20,R21,R22,
R23,R24,R25,R26,R27,
R28,R29,R30,R31,R32,
R33,R34,R35,R36,R37,
R38,R39,R40,R41,R42,
R43,R44,R45,R46,R47,
R48,R49,R50,R51,R52,
R53,R54,R55,R56,R57,
R58,R59,R60,R61,R62,
R63,R72,R73,R74,R77,
R80,R176,R177,R180,R181,
R200,R201,R202
R204,R205,R206,R207
R2,R3,R5,R65,R85
R86,R87,R88,R95,R96
R97,R107
R89,R90,R91,R92
R84,R103,R104,R105,R106
R178
R155,R,156,R157
R144,145,R146,R147,R151
R158,R159,R160
R93 R94
R161,R162,R172,R174
R163
R4,R7,R79,R82,R83
R152, R153,R154,R164,R168
R66,R67,R69,R70
R179
R167
R6,R64,R68,R71,R75,
R76,R78,R81,R98,R99,
R100,R101,R108,R109,R110,R111,
R112,R113,R114,R115,R116,R117,
R118,R119,R120,R121,R122,R123,
R124,R125,R126,R127,R128,R129,
R130,R131,R132,R133,R134,R135,
R136,R137,R138,R139,R140,R141,
R142,R143,R150,R166
R102,R148,R149,R173,R175
R171
User’s Manual V.0.10
22/36
Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
65
66
67
68
100K
1M
0.01uF_2kV
0.01uF
0603(1608)
0603(1608)
DIP
0603(1608)
3
1
1
9
R
R
69
0.1uF
0603(1608)
65
C
70
1uF
0603(1608)
6
C
71
72
73
74
75
76
20pF
22pF
27pF
47pF
100pF
330pF
0603(1608)
0603(1608)
0603(1608)
0603(1608)
0603(1608)
0603(1608)
2
2
1
1
1
12
C
C
C
C
C
C
77
78
820pF
1uF
0603(1608)
SMD A(3216)
1
17
C
T/C
79
80
81
2.2uF
3.3uF
10uF
SMD A(3216)
SMD A(3216)
SMD B(3528)
2
2
8
T/C
T/C
T/C
82
83
22uF
47uF
SMD B(3528)
SMD C(6032)
1
6
T/C
T/C
84
100uF
SMD D(7343)
3
T/C
C
R165,R169,R170
R1
C56
C47,C57,C58,C59,C60,
C61,C62,C83,C87
C1,C2,C3,C4,C5,
C6,C7,C8,C9,C10,
C11,C12,C15,C17,C18,
C19,C20,C21,C22,C23,
C24,C25,C26,C27,C28,
C29,C32,C33,C34,C35,
C36,C37,C38,C39,C40,
C41,C42,C43,C44,C45,
C46,C48,C50,C52,C63,
C64,C65,C66,C79,C80,
C81,C82,C85,C89,C92,
C93,C94,C96,C97,C183,
C184,C185,C186C187,C188
C51,C53,C54,C55,C90,
C91
C13,C14
C30,C31
C49
C88
C95
C67,C68,C69,C70,C71,
C72,C73,C74,C75,C76,
C77,C78
C16
TC11,TC12,TC13,TC14,TC15TC16,
TC17,TC18,TC19,TC20TC21,TC22,
TC37,TC38,TC39
TC41, TC42
TC9,TC10
TC35,TC36
TC3,TC6,TC7,TC25,TC26,
TC28,TC29,TC34
TC8
TC1,TC2,TC4,TC5,TC23,
TC24
TC27,TC31,TC33
User’s Manual V.0.10
23/36
Copyright © 2004 MCS LOGIC Limited. All rights reserved
EVB7400
6.2
EVB7400 Schematic
User’s Manual V.0.10
24/36
Copyright © 2004 MCS LOGIC Limited. All rights reserved
1
2
3
4
5
6
7
A
A
B
B
MLN7400 Evaluation Board
C
C
D
D
E
DESIGN
CUSTOMER
MCS LOGIC
CHECK-1
E
REV.
MLN7400EV
CHECK-2
DATE
UPDATE
2003.11.18
REMARK
1
2
3
4
5
6
BLOCK DIAGRAM
SHEET
1 / 14
1
2
4
3
VCC_33
TDO
TDI
TCK
TMS
10MHz
X2
XO
1
C14
20pF
2
C184
NC
VCC
GND
OUT
4
R5
VCC_33A
GROUND
A
GROUND
33
XI
MDIO
MDC
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
MII_RXDV
MII_RXCLK
MII_RXERR
NRESET
GROUND
GROUND
GROUND
SYSCLK
0.1uF
3
10MHZ
20pF
VCC_33
ADIN0
ADIN1
ADIN2
ADIN3
VCC_33
C1
C2
C3
C4
C5
C6
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
1
C13
33
GP40_DBCK
GP39_DLRCK
A
R3
2
1K
XO
1
FILTER
33
TEST
R4
TC1
2
1M
GP42_DDATA
GP41_DMCK
CURXD0
CUTXD0
R1
X1
R2
7
SYSTEM CLOCK
OPTIONAL
XI
6
5
47uF
GROUND
GP29_EXT_TCLK2
GP16_SPIMISO
AD07
GND33_04
SDCSN
SDRASN
SDCASN
SDWEN
GP31_HUARTNCTS4
GP32_HUARTNRTS4
GROUND
E
GP08_NBE0
VDD33_04
72
71
70
69
68
67
66
65
64
63
AD12
40
AD11
39
38
37
AD10
GROUND
GP07_CURXD4
GP10_TOUT0
GP06_CUTXD4
AD06
GP05_CURXD3
GP11_TOUT1
GP04_CUTXD3
GP12_TX_ERR
AD05
GP03_CURXD2
AD04
GP02_CUTXD2
GP13_NTRST
GP01_CURXD1
GP14_ECSN2
AD00
GP00_CUTXD1
AD01
ECSN0
GP15_ECSN3
ECSN1
GP30_HUARTNDCD4
AD09
GP09_NBE1
108
0.1uF
MII_TXCLK
MII_TXEN
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
107
106
105
15 16
104
103
102
2
3
101
100
98
GP36_EXINT3
GP35_EXINT2
SDA
SCL
97
96
95
94
0.1uF
0.1uF
0.1uF
R207
0_3216
R204
0_3216
0.1uF
H1
FHOLE3.5
AGND
MII_COL
MII_CRS
99
GROUND
R206
0_3216
R205
0_3216
FGND
C
93
92
GP26_ENWAIT
GP25_IOWR*
GP24_IORD*
GP23_CE2*
GP22_REG*
GP21_EXTUCLK
GP20_EXINT1
GP19_EXINT0
GP18_SPICLK
GP17_SPIMOSI
GP16_SPIMISO
GP15_ECSN3
GP14_ECSN2
GP13_NTRST
GP12_TXERR
GP11_TOUT1
GP10_TOUT0
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
Endian Setting
VCC_33
SW1
ADDR(19)
74
73
GROUND
FGND
1
R6
4.7K
3
R7
1K
BIG
2
GP09_NBE1
D
LITTLE
4
5
6
GROUND
SW_DPDT
MLN7400_144LQFP
E
GP08_NBE0
GP07_CURXD4
GP06_CUTXD4
GP05_CURXD3
GP04_CUTXD3
GP03_CURXD2
GP02_CUTXD2
GP01_CURXD1
GP00_CUTXD1
DESIGN
CUSTOMER
MCS LOGIC
CHECK-1
REV.
MLN7400EV
CHECK-2
UPDATE
5
6
SHEET
2/14
2003.11.18
17 18 19 20
4
B
47uF
1
GP38_TOUT3
GP37_TOUT2
REMARK
1
TC2
GROUND
DATE
10 11 12 13 14
C12
2
GP17_SPIMOSI
AD08
C11
C10
C9
1
109
RX_ERR
111
112
113
114
115
110
RX_CLK
RX_DV
RX_D0
RX_D1
RX_D2
116
MDC
MDIO
RX_D3
118
119
117
GP39_DLRCK
120
VDD33_06
GND33_06
GP40_DBCK
122
123
124
125
121
XI
XO
TEST
126
TDI
TDO
128
129
127
TCK
TMS
130
CUTXD0
RESETN
132
131
CURXD0
GP41_DMCK
GP42_DDATA
133
134
PLLGND
136
137
138
135
FILTER
PLLVDD
AVREF33
139
AVDD33_00
GND33_01
GP34_HUARTNDTR4
36
GP18_SPICLK
GP33_HUARTNDSR4
35
9
VDD33_01
62
8
GP19_EXINT0
61
34
AD02
GP33_HUARTNDSR4
GP34_HUARTNDTR4
NECS1
NECS0
7
GP20_EXINT1
GND33_03
33
AD03
60
32
GP21_EXT_UCLK
59
31
5
CKE
VDD33_03
4
6
GP22_REG*
58
D
30
GP23_CE2*
SDCLK
EOEN
820pF
29
0
D15
EWEN
C16
FILTER
28
GP25_IOWR*
GP24_IORD*
EAD20_X8EN
1
27
GP29_EXTTCLK2
GP30_HUARTNDCD4
GP26_ENWAIT
D14
57
26
D13
56
25
MLN7400_144LQFP
D12
NEWE
NEOE
24
VDD33_05
EAD19_BIG
2
D11
55
23
GND33_05
EAD18
3
SCL
D10
54
21
22
D09
53
20
SDA
EAD17
19
15
GP35_EXINT2
D08
GP32_HUARTNRTS4
18
14
D00
52
13
GP36_EXINT3
51
17
GP28_EXT_TCLK1
WEN
12
RX_CRS
GP31_HUARTNCTS4
16
RX_COL
GP27_EXT_TCLK0
CASN
15
11
GND33_00
49
14
10
GP37_TOUT2
50
9
VDD33_00
RASN
ADDR(20:0)
13
GP38_TOUT3
47
SDCLK
SDCKE
12
8
D01
48
GROUND
0
TX_D3
SDCSN
C
11
TX_D2
D02
UDQM_AD16
1
2
9
10
GP27_EXTTCLK0
GP28_EXTTCLK1
10uF
C15
0.1uF
TC3
8
BEADS_100MHz
D03
46
7
LDQM_AD15
6
TX_D1
45
5
1
TX_D0
D04
GND33_02
3
2
D05
VDD33_02
4
TX_EN
44
4
TX_CLK
43
3
C8
0.1uF
D06
42
5
C7
D07
BA1_AD14
L1
2
BA0_AD13
VCC_33A
1
6
41
VCC_33
7
AGND33_00
141
140
142
DATA(15:0)
AVSS33_00
ADIN0
143
ADIN3
ADIN1
U1
ADIN2
AGND
B
144
VCC_33
Main CPU MLN7400
1
2
3
4
5
6
7
97
RX_ERR
VDD33_04
AD09
GP09_NBE(1)
94
93
92
91
90
89
88
87
86
B
VCC_33
80
79
78
77
76
75
74
73
72
71
70
69
68
67
0.1uF
0.1uF
C27
C28
1
0.1uF
C26
TC5
0.1uF
C25
47uF
0.1uF
C24
2
0.1uF
C23
1
0.1uF
C22
TC4
0.1uF
C21
47uF
0.1uF
C
GROUND
66
65
GP09_NBE1
MLN7400P_128TQFP
D
GROUND
E
ADDR(20:0)
DESIGN
CUSTOMER
MCS LOGIC
GP07_CURXD4
GP06_CUTXD4
GP05_CURXD3
GP04_CUTXD3
GP03_CURXD2
GP02_CUTXD2
GP01_CURXD1
GP00_CUTXD1
E
2
0.1uF
C20
81
C19
82
0.1uF
GP26_ENWAIT
GP25_IOWR*
GP24_IORD*
GP23_CE2*
GP22_REG*
GP21_EXTUCLK
GP20_EXINT1
GP19_EXINT0
GP18_SPICLK
GP17_SPIMOSI
GP16_SPIMISO
GP15_ECSN3
GP14_ECSN2
GP13_NTRST
GP12_TXERR
GP11_TOUT1
GP10_TOUT0
83
C18
84
0.1uF
85
GP08_NBE0
64
63
62
61
60
59
58
20
19
18
17
57
34
SDCSN
SDRASN
SDCASN
SDWEN
16
15
14
13
10
12
11
MII_TXCLK
MII_TXEN
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
MII_COL
MII_CRS
SDA
SCL
95
GP08_NBE0
AD08
GP07_CURXD4
GND33_04
GP06_CUTXD4
AD07
GP05_CURXD3
GP10_TOUT(0)
GP04_CUTXD3
AD06
GP03_CURXD2
GP11_TOUT(1)
GP02_CUTXD2
AD05
GP01_CURXD1
GP12_TX_ERR
96
C17
99
100
101
102
98
RX_CLK
RX_DV
RX_D0
RX_D1
RX_D2
RX_D3
103
104
MDC
106
107
108
109
110
111
112
113
114
105
MDIO
VDD33_06
GND33_06
XI
XO
TEST
TDO
TDI
TCK
TMS
RESETN
116
115
CUTXD0
FILTER
118
119
120
121
122
117
CURXD0
PLLGND
FILTER
PLLVDD
AVREF33
123
GP13_NTRST
AD04
33
D
AGND33_00
124
GP14_ECSN2
AD00
GP00_CUTXD1
32
AD01
56
9
GP15_ECSN3
ECSN0
31
GP16_SPIMISO
ECSN1
8
VDD33_01
GND3_01
55
30
GP17_SPIMOSI
NECS1
NECS0
7
AD02
GND33_03
29
GP18_SPICLK
54
28
6
AD03
VSS33_03
5
GP19_EXIT_0
53
27
CKE
EOEN
26
4
GP20_EXIT1
52
0
SDCLK
AD10
25
GP21_EXT_UCLK
EWEN
24
1
GP23_CE2*
D15
51
23
GP24_IORD*
GP22_REG*
50
22
GP25_IOWR*
D14
NEWE
NEOE
2
D13
EAD20_X8EN
21
D12
49
3
MLN7400P_128TQFP
D11
EAD19_BIG
19
20
GP26_ENWAIT
EAD18
18
D10
EAD17
15
VDD33_05
48
17
D09
47
16
14
GND33_05
WEN
13
D08
45
15
SCL
46
14
12
SDA
D00
CASN
11
GND33_00
RASN
13
RX_CRS
44
10
VDD33_00
SDCSN
12
RX_COL
43
9
D01
UDQM_AD16
C
11
TX_D3
42
SDCLK
SDCKE
10
8
D02
LDQM_AD15
9
0
TX_D2
40
8
TX_D1
41
7
D04
D03
GND33_22
6
1
TX_D0
39
5
2
D05
VDD33_02
4
3
TX_EN
38
4
TX_CLK
BA1_AD14
3
VCC_33
D06
BA0_AD13
5
A
D07
AD12
2
36
37
1
6
AD11
7
35
B
AVDD33_00
ADIN0
DATA(15:0)
AVSS33_00
ADIN1
125
ADIN3
ADIN2
ADIN1
ADIN0
126
127
128
ADIN3
U2
ADIN2
AGND
CURXD0
CUTXD0
NRESET
TMS
TCK
TDI
TDO
TEST
XO
SYSCLK
A
MDIO
MDC
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
MII_RXDV
MII_RXCLK
MII_RXERR
VCC_33A
CHECK-1
REV.
MLN7400EV
CHECK-2
DATE
UPDATE
REMARK
Main CPU MLN7400P 128TQFP
1
2
3
4
5
6
SHEET
3/14
2003.11.18
1
2
3
4
5
OPTIONAL
Do not install
Install to use
NAND Flash
Only use when CPU is
MLN7400P and need to use
DAC
A
GP25_IOWR*
GP24_IORD*
GP23_CE2*
GP22_REG*
GP42_DDATA
GP41_DMCK
GP40_DBCK
GP39_DLRCK
R8
0
R9
0
R10
0
R11
0
R27
0
R28
0
R29
0
R30
0
DDATA
DMCK
DBCK
DLRCK
GP38_TOUT3
GP37_TOUT2
GP36_EXINT3
GP34_HUARTNDTR4
GP33_HUARTNDSR4
GP32_HUARTNRTS4
GP31_HUARTNCTS4
GP30_HUARTNDCD4
MLN7400P
DAC I/F
DDATA
DMCK
DBCK
DLRCK
R31
0
R32
0
R33
0
R34
0
R35
0
R36
0
R37
0
R200
0
R39
0
R40
0
A
R12
0
R13
0
R14
0
R15
0
R16
0
R17
0
R18
0
R19
0
NFIO7
NFIO6
NFIO5
NFIO4
NFIO3
NFIO2
NFIO1
NFIO0
NAND
FLASH
I/F
DAC I/F
GP18_SPICLK
GP17_SPIMOSI
GP16_SPIMISO
GP07_CURXD4
GP06_CUTXD4
GP05_CURXD3
GP04_CUTXD3
B
GP26_ENWAIT
GP25_IOWR*
GP24_IORD*
GP22_REG*
GP20_EXINT1
GP23_CE2*
GP15_ECSN3
GP37_TOUT2
7
6
PCMCIA_WAIT*
PCMCIA_IOWR*
PCMCIA_IORD*
PCMCIA_REG*
PCMCIA_IRQ*
PCMCIA_CE2*
PCMCIA_CE1*
PCMCIA_RESET_GP37
PCMCIA
I/F
R20
0
R21
0
R22
0
R23
0
R24
0
R25
0
R26
0
R38
0
B
NFRBN
NFRDN
NFCEN
NFCLEN
NFALEN
NFWRN
NFWEN
JP1
R41
0
R42
0
R43
0
R44
0
R45
0
R46
0
R47
0
R48
0
GP10_TOUT0
D
R50
0
R51
0
R52
0
R53
0
LED0*
LED1*
LED2*
LED3*
JUMP
CUART
I/F
R49
LED
I/F
R55
0
R56
0
R57
0
SPI
I/F
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SS*
NTRST
X3
C185
GP18_SPICLK
GP17_SPIMOSI
GP16_SPIMISO
GP11_TOUT1
0
D
1
0
C
VCC_33
VCC_33
R54
1
VCC_33
GP13_NTRST
GP12_TXERR
GP21_EXTUCLK
GP28_EXTTCLK1
GP29_EXTTCLK2
TOUT0_TEST
R64
C
HUARTNRTS4
HUARTNCTS4
CURXD4
CUTXD4
CURXD3
CUTXD3
CURXD2
CUTXD2
CURXD1
CUTXD1
4.7K
GP32_HUARTNRTS4
GP31_HUARTNCTS4
GP07_CURXD4
GP06_CUTXD4
GP05_CURXD3
GP04_CUTXD3
GP03_CURXD2
GP02_CUTXD2
GP01_CURXD1
GP00_CUTXD1
2
NC
VCC
GND
OUT
0.1uF
GROUND
4
R65
3
33
EXT_TCLK0
R61
0
GP27_EXTTCLK0
1MHZ
GROUND
TIMER 0
EXTERNAL CLOCK
E
DESIGN
CUSTOMER
MCS LOGIC
GP14_ECSN2
GP09_NBE1
GP08_NBE0
E
R58
0
R59
0
R60
0
GP35_EXINT2
GP19_EXINT0
SRAM
I/F
NECS2
NBE1_UB
NBE0_LB
R62
0
R63
0
CHECK-1
EXTINT2
EXTINT0
REV.
MLN7400EV
CHECK-2
DATE
UPDATE
2003.11.18
REMARK
1
2
3
4
5
6
GPIO
SHEET
4/14
2
1
A
3
4
5
IIC EEPROM
6
7
A
SPI EEPROM
VCC_33
U3
3
4
VCC
A1
WP
A2
SCL
GND
SDA
B
1
SPI_SS*
VCC_33
8
2
SPI_MISO
7
6
SCL
5
C186
3
0.1uF
4
SDA
S524A40X10
VCC_33
U4
2K
2
A0
2K
1
VCC_33
R67
R66
VCC_33
*CS
SO
VCC
*HOLD
*WP
SCK
GND
SI
8
C187
7
6
0.1uF
SPI_CLK
5
SPI_MOSI
GROUND
AT25040
B
GROUND
GROUND
GROUND
GROUND
External Interrupt Test
VCC_33
VCC_33
RTC
R68
4.7K
EXTINT0
VCC_33
R70
R69
C
C
1
S1
2
U5
1
2
3
8
VDD
SCL
OSC
ALRM
X1
GND
X2
2
7
1N4004
6
EXTINT 0
1
1uF
5
1
4
D1
SDA
2
SDA
SCL
1
2K
2K
TACT_SW
TC41
GROUND
2
DS1629
Y1
D2
GROUND
1N4004
R71
1
GROUND
4.7K
EXTINT2
3
XTAL_32_768KHZ_H49S
1
2
D
S2
2
D
TACT_SW
2
TC42
EXTINT 2
1uF
0.1uF
C29
BATTERY
1
C31
22pF
BT1A
C30
22pF
2
1
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
E
GROUND
DESIGN
CUSTOMER
MCS LOGIC
CHECK-1
E
REV.
MLN7400EV
CHECK-2
UPDATE
DATE
2003.11/18
REMARK
1
2
3
4
5
6
EEPROM & RTC
SHEET
5/14
1
2
3
4
5
6
7
VCC_33
A
NC1
CS*
NC2
WE*
NC3
OE*
VCC1
39
NBE0_LB
NBE1_UB
40
VCC2
LB*
UB*
VSS1
VSS2
22
VCC_33
38
SDCLK
SDCKE
37
VDDQ4
15
1
14
53
TC6
9
43
VDDQ3
3
VDDQ1
VDDQ2
27
49
13
51
CLK
B
CKE
23
28
33
GROUND
12
19
SDCSN
SDRASN
SDCASN
SDWEN
ADDR(15)
ADDR(16)
11
34
18
17
16
R73
0
15
R74
0
39
CS*
NC
40
RAS*
CAS*
WE*
GROUND
DQML
DQMH
28
K6R1016V1D_SRAM
BANK2
14
DQ15
12
50
2
15
DQ14
11
10uF_16V
38
A14
47
48
VCC_33
0.1uF
37
14
DQ13
10
C46
13
A13
9
45
0.1uF
36
DQ11
DQ12
8
44
0.1uF
21
DQ10
4MX16_SDRAM
A12
42
C45
20
14
A11
7
0.1uF
13
12
U7
A10
13
C44
11
35
36
5
11
6
0.1uF
32
35
0
R72
4
10
C43
12
3
8
C42
11
10
DQ9
2
7
0.1uF
9
31
DQ8
A9
5
0.1uF
30
DQ7
A8
4
1
C41
I_O16
22
A7
0
VSSQ4
A15
10
DQ6
2
52
I_O15
8
A6
VSSQ3
41
A14
34
DQ5
VSSQ2
17
I_O14
33
A5
VSSQ1
6
NECS1
NEWE
NEOE
A13
29
8
9
VCC_33
DQ4
6
44
I_O13
7
A4
46
43
15
A12
6
16
DQ3
12
14
I_O12
15
A3
VSS3
42
A11
32
DQ2
VSS2
13
I_O11
7
DQ1
A2
VSS1
27
I_O10
A10
5
A1
54
26
I_O9
A9
31
14
DQ0
41
11
12
A8
6
DATA(15:0)
A0
0.1uF
25
I_O8
13
4
C39
24
I_O7
30
0.1uF
9
10
I_O6
A6
5
0.1uF
21
A5
A7
3
C38
8
I_O5
29
10
0.1uF
20
A4
4
C37
19
7
I_O4
9
2
0.1uF
6
A3
26
C36
18
I_O3
25
3
0.1uF
5
5
A2
2
1
C35
4
I_O2
0
8
C34
4
A1
24
7
0.1uF
3
3
I_O1
0.1uF
2
A0
C33
2
C32
B
1
1
23
1
C40
U6
0
0
DATA(15:0)
VDD3
ADDR(14:0)
ADDR(15:0)
VDD2
VDD1
1
A
GROUND
SDRAM BANK
C
FLASH
GROUND
C
VCC_33
AMD Flash
BANK
Selection
VCC_33
ADDR(18:0)
U9
7
5
8
27
9
26
10
23
11
25
12
4
13
28
14
29
15
3
16
2
17
30
18
1
22
NECS0
NEOE
NEWE
24
31
U8
A3
A4
DATA(15:0)
A5
A6
A7
DQ0
A8
DQ1
A9
DQ2
A10
DQ3
A11
DQ4
A12
DQ5
A13
DQ6
A14
DQ7
24
23
0
3
22
14
1
4
21
15
2
5
20
17
3
6
19
18
4
7
18
19
5
8
8
20
6
9
7
21
7
10
6
11
5
12
4
13
3
14
2
15
1
16
48
17
17
18
16
A16
A17
A18
GND
25
1
13
A15
CE*
0
2
16
OE*
WE*
19
VCC_33
AT29C040A
GROUND
BANK0
9
20 R77
R78
0
10
4.7K
15
47
14
26
NCS_AMD
NEOE
NEWE
11
R80
0
12
A1
A2
A3
A4
DATA(15:0)
A5
A6
A7
D0
A8
D1
A9
D2
A10
D3
A11
D4
A12
D5
A13
D6
A14
D7
A15
D8
A16
D9
A17
D10
A18
D11
A19
D12
A20
D13
RY_BY#
D14
BYTE_VCCQ
D15
29
0
31
1
33
2
35
3
38
4
40
5
42
6
44
7
30
8
32
9
34
10
36
11
39
12
41
13
43
14
45
15
SW2
1
X8
2
NCS_AMD
3
VCC_33
NECS2
NECS0
4
5
ADDR(20)
4.7K
R75
1K
R79
6
SW_DPDT
X16
D
GROUND
E
*WP
*CE
*OE
DESIGN
*WE
*RST
27
NRESET
28
A0
BOSIZE : 8 Bit
BOSIZE : 16Bit
4.7K
ADDR(20:0)
R76
6
32
VCC_33
VCC
7
VDD
CUSTOMER
MCS LOGIC
VSS1
8
6
A2
37
4
5
A1
46
9
13
10
3
VPP
11
2
A0
VSS2
D
12
GROUND
0
1
CHECK-1
REV.
AM29LV160BB
E
MLN7400EN
CHECK-2
BANK1
DATE
UPDATE
SHEET
6/14
2003.11.18
GROUND
1
2
3
4
REMARK
5
6
MEMORY
2
1
3
4
6
5
7
A
A
VCC_33
VCC_33
VCC_33
X1_OE
X2_OUT
NC_GND
R84
NC_VDD
0.1uF
XTAL_OSC_25MHZ
75
GROUND
C49
27pF
3
32
4
31
5
30
6
29
7
28
8
27
TDC
TCMT
TXDN
TXN
NC1
NC3
NC2
NC4
RDP
RXP
RDC
RCMT
RDN
RXN
16
1
9
15
2
10
14
3
11
13
4
12
12
5
11
6
13
10
7
14
9
8
H1102
26
R93
R94
500
J1
TXP
TXDP
VCC_25
500
C51
R92
49.9
1uF_1608
R91
49.9
C50
R90
49.9
0.1uF
R89
49.9
C53
1uF_1608
33
LED_LNK
LED_SPD
C
RJ45
25
FGND
33
C55
R103
75
R104
75
R105
75
R106
75
1
GROUND
1uF_1608
C54
PDOWN*
R101
VCC4
1
2
24
ANEN_LED3
SPD100_LED1
DUPLEX_LED2
23
22
21
14
GROUND
BURNIN*_L_LED0
TXD1
VCC3
RXP
RXN
U11
GROUND
34
10K
TXEN
GROUND
35
VCC_25
R102
SD_FXEN
TXD0
2
38
39
37
GND7
GND8
XI
XO
41
40
42
RST*
MDIO
VCC33IN
43
45
46
44
MDC
PHYAD1_RXD3
PHYAD2_RXD2
TXC
36
VCC_25
1uF_1608
R107
PHYAD3_RXD1
GND4
13
GROUND
GND5
TXER
TXD2
12
RBIAD
AC101L
PHYAD0_INTR
11
4.7K
4.7K
10
VCCPLL
GND2
20
9
ISOLATE_RXER
VCC2
19
8
GND6
18
R100
6
7
RMII_MODEL_RXC
GND3
5
TXP
TXN
17
33
VCC25OUT
GND1
REPEATER_CRS
R97
GROUND
RXDV_CRSDV
COL
4
VCC1
TXD3
33
R99
R96
R98
3
16
2
33
15
1
R95
4.7K
47
48
PHYAD4_RXD0
VCC_25
C
B
VCC_25
GROUND
4.7K
33
C52
33
R88
0.1uF
R87
PHYADCO3
PHYADCO2
PHYADCO1
PHYADCO0
TC8
33
1
33
R86
22uF
R85
U10
2
C56
VCC_25
GROUNDGROUND
4.7K
4.7K
R117
4.7K
R118
4.7K
R119
4.7K
R120
4.7K
4.7K
R113
4.7K
R114
4.7K
C57
4.7K
4.7K
R112
TC9
R110
R111
GROUND
VCCPLL
1
4.7K
0.01uF
GROUND
4.7K
R109
2.2uF
VCC_25
PHYADCO4
PHYADCO3
PHYADCO2
PHYADCO1
PHYADCO0
R108
0.01uF_2KV
VCC_25
2
LED_LNK
LED_SPD
R116
R115
MII_TXD2
MII_TXD3
MII_COL
MII_CRS
D
GROUND
VCC_25
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
MII_TXCLK
MII_TXEN
MII_TXD0
MII_TXD1
2
GROUND
NRESET
MDIO
MDC
MII_RXDV
MII_RXCLK
MII_RXERR
1
1K
1K
4.7K
GROUND
B
3
C48
C47
0.01uF
1
2
10uF
R83
R82
R81
TC7
4
0.1uF
VCC_25
C183
Y2
FGND
Place close to
pin32 0f AC101L
D
GROUNDGROUND
GROUND
GROUND
VCC_25
C66
C65
C64
C63
C62
C61
C60
C59
C58
1
DESIGN
CHECK-1
0.1uF
0.1uF
0.1uF
0.1uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
2.2uF
CUSTOMER
MCS LOGIC
2
TC10
E
E
REV.
MLN7400EV
CHECK-2
GROUND
Place close to
pins 0f AC101L
DATE
UPDATE
2003.11.18
REMARK
AC101L ETHERNET PHY
1
2
3
4
5
6
SHEET
7/14
1
3
2
4
5
6
7
UART0
P1
1
6
2
VCC_33
7
3
A
A
8
U12
R1I
4
1
5
T2O
R2O
R2I
C2+
V-
C2-
GND
TC11
2
1uF
1
14
DB9_FEMALE
2
13
GROUND
7
UART1
P2
8
1uF
6
TC14
2
1
1
6
C70
2
T1O
T2I
9
TC13
V+
T1I
R1O
10
1uF
C1-
2
7
15
MAX3232
3
330pF
12
5
C69
11
9
16
330pF
3
CUTXD0
CURXD0
CUTXD1
CURXD1
VCC
C68
C1+
330pF
1
1
C67
TC12
2
330pF
1uF
4
8
4
9
GROUND
5
B
B
DB9_FEMALE
GROUND
GROUND
UART2
P3
1
6
2
VCC_33
7
3
8
U13
4
1
5
T2O
R2O
R2I
C2+
V-
1
GND
C2-
2
TC15
1uF
1
14
DB9_FEMALE
2
13
C
GROUND
7
UART3
P4
8
1uF
6
TC18
2
1
1
6
C74
TC17
R1I
T2I
9
2
T1O
R1O
10
1uF
V+
T1I
2
5
7
MAX3232
3
330pF
12
C1-
5
C73
11
9
330pF
CUTXD2
CURXD2
CUTXD3
CURXD3
VCC
C72
1
3
C
4
C1+
16
330pF
2
1
C71
TC16
330pF
1uF
8
4
9
GROUND
5
DB9_FEMALE
GROUND
GROUND
P5
UART4
1
6
D
D
2
VCC_33
7
3
8
U14
10
9
1uF
TC21
2
4
1
5
E
C1-
V+
T1I
T1O
R1O
R1I
T2I
T2O
R2O
R2I
C2+
V-
C2-
GND
14
1uF
1
DB9_FEMALE
2
13
GROUND
7
P6
8
6
1uF
TC22
2
1
1
E
HUART
OPTION
DESIGN
MCS LOGIC
2
CHECK-1
7
15
MAX3232
CUSTOMER
6
C78
12
TC19
REV.
3
330pF
11
5
2
C77
CUTXD4
CURXD4
HUARTNRTS4
HUARTNCTS4
9
330pF
3
16
C76
1
4
VCC
C1+
330pF
2
1
C75
TC20
330pF
1uF
8
MLN7400EV
CHECK-2
4
9
GROUND
5
DATE
UPDATE
2003.11.18
DB9_MALE
GROUND
REMARK
GROUND
1
2
3
4
5
6
RS232
SHEET
8/14
2
1
3
5
4
6
7
VCC_33
ADDR(11:0)
66
11
37
12
38
13
39
14
40
15
41
0
58
7
PCMCIA_CE1*
PCMCIA_CE2*
42
9
NEOE
NEWE
PCMCIA_IORD*
PCMCIA_IOWR*
15
44
45
61
PCMCIA_REG*
67
36
59
PCMCIA_WAIT*
PCMCIA_IRQ*
D
16
57
43
62
63
60
33
D9
A23
D10
A24
D11
A25
50
53
54
55
56
D12
D13
R142
10
A22
4.7K
65
D8
49
R141
9
A21
4.7K
64
D7
48
R140
8
A20
4.7K
6
D6
47
R139
7
A19
4.7K
5
A18
D5
46
R138
6
A17
D4
B
19
4.7K
4
D3
20
R137
3
5
A16
4.7K
4
D2
14
R136
2
A15
4.7K
3
D1
13
D14
D15
RESET
C
CE1*
CE2*
OE*
WE*_PGM*
GROUND
IORO*
IOWR*
REG*
VCC_33
CD2*
CD1*
WAIT*
RDY*_IREQ*
D
VS2*
1
32
A14
TC24
2
D0
21
VS1*
BVD2*_SPKR
BVD1*_STSCHG
GND0
GND1
INPACK*
GND2
WP*_IOIS16*
GND3
68
2
31
A13
47uF
1
A12
R135
30
A11
4.7K
0
A10
1
10
A9
2
8
11
A8
R134
10
A7
4.7K
11
TC23
9
A6
47uF
12
R133
22
8
A5
4.7K
23
7
18
A4
C80
24
6
52
0.1uF
5
VPP1
R132
25
VPP2
A3
4.7K
4
A2
51
R131
4.7K
4.7K
4.7K
4.7K
4.7K
26
VCC1
4.7K
R128
R127
R126
R125
R124
R123
4.7K
4.7K
3
VCC0
A1
C79
R202
27
A0
0.1uF
PCMCIA_RESET
28
2
R130
C
0
4.7K
PCMCIA_RESET_GP37
R122
R121
VCC_33
1
17
4.7K
B
29
R129
DATA(15:0)
R201
A
J2
0
4.7K
A
35
34
1
R143
E
PCMCIA_68PIN_CONN
DESIGN
MCS LOGIC
BANK3
GROUND
CHECK-1
GROUND
4.7K
E
CUSTOMER
REV.
MLN7400EV
CHECK-2
DATE
UPDATE
2003.11.18
REMARK
GROUND
1
2
3
PCMCIA INTERFACE
4
5
6
SHEET
9/14
1
2
4
3
5
RESET SYSTEM
6
GPIO LED
VCC_33
VCC_33
NRESET
A
GROUND
R147
R146
330
4
VCC_33
330
74LVC14
3
2
330
1
GROUND
SW_RESET
LED
LED
VCC_33
B
U16
14
1
R150
B
D7
2
D6
S3
D5
14 Pin : VCC_33
7 Pin : Ground
2
1
LED
VCC_33
10uF
LED
TC25
D4
1
U15
74LVC14
10K
1
10K
U15
R145
R144
1N4148
VCC_33
0.1uF
0.1uF
D3
VCC_33
C82
R149
2
R148
RESET
C81
VCC_33
330
VCC_33
VCC_33
A
7
3
NTRST
2
GROUND
LED0*
74LV08
LED1*
14 Pin : VCC_33
7 Pin : Ground
4.7K
7
GROUND
LED2*
LED3*
1
JTAG CONNECTOR
C
VCC_33
POWER LED
TC26
10uF
2
C
J3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
VCC_33
NTRST_JTAG
TDI
TMS
TCK
GROUND
R151
3
U15
74LVC14
TDO
NRESET
NRESET
5
6
PCMCIA_RESET
330
1
4
LED
2
HEADER2X10
D
D
D8
GROUND
VCC_5
VCC_5IN
VCC_33
GROUND
SW3
1
2
2
10uF
AMS1086
DESIGN
1
C85
TC29
10uF
MCS LOGIC
100uF
E
CUSTOMER
TC31
CHECK-1
2
100uF_16V
100uF_16V
TC28
0.1uF
TC33
4
TAB
C83
1
TC27
E
2
OUT
0.01uF
SW_TOGGLE
PWR_JACK
IN
1
3
2
A3 B3
3
GND
3
U17
2
1
A2 B2
1
A1 B1
2
2
1
1
J4
REV.
MLN7400EV
CHECK-2
DATE
GROUND
GROUND
GROUND
GROUND
GROUND
UPDATE
2003.11.18
GROUND
REMARK
POWER&RESET
1
2
3
4
5
6
SHEET
10/14
1
2
4
3
DATA(15:0)
5
6
7
VCC_33
VCC_33
JP2
A
SDA
SCL
JP3
14
12
10
8
6
4
2
0
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
1
2
3
4
5
6
7
8
A
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SS*
VCC_33
HEADER2X4
15
GROUND
13
IIC & SPI
HEADER
11
9
7
5
JP5
1
GP06_CUTXD4
GP07_CURXD4
GP30_HUARTNDCD4
3
1
VCC_33
2
3
4
5
6
7
GP31_HUARTNCTS4
GP32_HUARTNRTS4
GP33_HUARTNDSR4
GP34_HUARTNDTR4
8
9
10
11
12
HEADER2X6
HEADER2X13
B
B
GROUND
GROUND
JP4
DATA
HEADER
MDC
MDIO
MII_TXCLK
MII_TXEN
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
ADDR(20:0)
JP6
20
18
16
14
12
10
C
8
6
4
2
0
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
19
17
15
9
3
1
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
MII_CRS
MII_COL
MII_RXERR
MII_RXCLK
MII_RXDV
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
VCC_33
GROUND
C
TP1
TP_040
TP2
TP_040
TP3
TP_040
TP4
TP_040
TP5
TP_040
TP6
TP_040
VCC_33
GROUND
GROUND
JP7
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
GP15_ECSN3
GP14_ECSN2
GP09_NBE1
GP08_NBE0
NEOE
NEWE
NECS1
NECS0
GROUND
GP42_DDATA
GP40_DBCK
GP38_TOUT3
GP36_EXINT3
GP34_HUARTNDTR4
GP32_HUARTNRTS4
GP30_HUARTNDCD4
GP28_EXTTCLK1
GP26_ENWAIT
GP24_IORD*
GP22_REG*
GP20_EXINT1
GP18_SPICLK
GP16_SPIMISO
GP14_ECSN2
GP12_TXERR
GP10_TOUT0
GP08_NBE0
GP06_CUTXD4
GP04_CUTXD3
GP02_CUTXD2
GP00_CUTXD1
47
48
45
46
43
44
41
42
39
40
37
38
35
36
33
34
31
32
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
4
1
2
GROUND
GROUND
GP41_DMCK
GP39_DLRCK
GP37_TOUT2
GP35_EXINT2
GP33_HUARTNDSR4
GP31_HUARTNCTS4
GP29_EXTTCLK2
GP27_EXTTCLK0
GP25_IOWR*
GP23_CE2*
GP21_EXTUCLK
GP19_EXINT0
GP17_SPIMOSI
GP15_ECSN3
GP13_NTRST
GP11_TOUT1
GP09_NBE1
GP07_CURXD4
GP05_CURXD3
GP03_CURXD2
GP01_CURXD1
D
E
DESIGN
MCS LOGIC
GP1~
ODD
GPIO
3
GROUND
4
REV.
MLN7400EV
CHECK-2
DATE
GPIO
HEADER
MEMORY
HEADER
CUSTOMER
CHECK-1
HEADER24x2
GP0~
EVEN
GPIO
HEADER2X13
2
22
19
HIGH SPEED
UART
HEADER
MII I/F
HEADER
5
JP8
1
21
GROUND
7
D
E
24
13
VCC_33
SDCKE
SDCLK
26
23
11
ADDRESS
HEADER
SDCASN
SDRASN
SDWEN
SDCSN
25
GROUND
HEADER2X13
HEADER2X13
GROUND
GROUND
UPDATE
REMARK
Test Header Pin
5
6
SHEET
11/14
2003.11.18
1
2
VCC_33A
3
5
4
6
7
VCC_33A
VCC_33A
A
A
1K
R153
1K
R154
ADIN0
1
SW5
2
TACT_SW
TACT_SW
PLAY
PGM
1
SW8
2
TACT_SW
STOP
MENU
SW10
1
2
TACT_SW
VOL_UP
SW11
2
1
TACT_SW
B
SW12
2
TACT_SW
VOL_DN
AGND
R161
R162
560
ESP
560
SKIP+
SW13
SW9
R159
2
TACT_SW
1
1
390
TACT_SW
R158
1
R157
270
2
B
2
TACT_SW
R156
R155
SW7
SW6
EQ
390
1
1
270
2
ADIN2
390
SW4
ADIN1
270
1
1K
R160
R152
2
1
TACT_SW
SW14
VCC_33A
2
TACT_SW
C188
ENTER
820
SKIP-
0.1uF
1K
100K
R165
C
VCC_33A
VCC_33A
AGND
2
TACT_SW
2
0.01uF
1
2
3
3
4
GND
OUT
INP
VCC
INN
SHDN
5
NC
MBIAS
8
7
6
ADIN3
SW16
SHDN
1
2
3
R166
4.7K
R168
1K
MUTE
Disable
4
MAX4468EKA_SOP8
C87
J5
AGND
MUTE
Enable
U18
1
2.2K
100K
R167
R169
MODE
TC34
SW15
10uF
1
R164
AGND
R163
C
5
6
AGND
SW_DPDT
2
D
1
R170
AGND
MUTE
SW
AGND
D
100K
MICIN
C88
MIC
JACK
C89
0.1uF
R171
47pF
20K
E
DESIGN
CUSTOMER
MCS LOGIC
AGND
CHECK-1
E
REV.
MLN7400EV
CHECK-2
DATE
UPDATE
REMARK
KEY MATRIX & MIC IN
1
2
3
4
5
6
SHEET
12/14
2003.11.18
3
5
4
TC35
A
3.3uF
R172
7
560
A
2
R173
1uF_1608
10K
1
6
C90
2
1
AGND
J6
B
B
TC36
R174
560
AOUTR
3
AOUTL
2
C91
1uF_1608
R175
AOUTR_S
0
AOUTL_S
VCC_33A
1
LINE_OUT_JACK
AGND
C
R176
C
3.3uF
2
10K
1
U20
DIF0
VQ
DEM0
FILT+
11
10
D
9
E
2
R178
1uF
100
1
CS4340
C92
REF_GND
0.1uF
DIF1
12
TC37
AOUTR
1uF
MCLK
13
1
8
AGND
2
D
LRCK
14
C93
7
VA
0.1uF
6
SCLK
15
TC38
5
AOUTL
1
4
MUTEC
SDATA
2
3
RST*
1uF
2
AGND
16
C94
1
0.1uF
0
TC39
NRESET
DDATA
DBCK
DLRCK
DMCK
R177
DESIGN
CUSTOMER
MCS LOGIC
CHECK-1
AGND
E
REV.
MLN7400EV
CHECK-2
AGND
AGND
AGND
AGND
DATE
UPDATE
SHEET
13/14
2003.11.18
REMARK
1
2
3
4
5
6
DAC
1
3
2
4
5
6
7
A
A
VCC_33
NAND_Flash
U21
3
4
R179
B
5
6
NFPIN6
7
NFRBN
8
NFRDN
NFCEN
100pF
VCC_33
9
10
11
C95
12
14
0.1uF
C
13
R180
16
NFCLEN
NFALEN
NFWRN
NFWEN
C96
GROUND
15
17
18
19
20
21
0
NFPIN6
GROUND
22
GROUND
23
24
D
R181
0
NC15
NC2
NC16
NC3
NC17
NC4
NC18
NC5
IO7
GND1
IO6
R_BN
IO5
REN
IO4
CEN
NC19
NC6
NC20
NC7
NC21
VCC1
VCC2
VSS1
VSS2
NC8
NC22
NC9
NC23
CLE
NC24
ALE
IO3
WEN
IO2
WPN
IO1
NC10
IO0
NC11
NC25
NC12
NC26
NC13
NC27
NC14
NC28
48
47
46
45
B
44
NFIO7
NFIO6
NFIO5
NFIO4
43
42
41
40
VCC_33
39
38
NFPIN38
37
36
35
0.1uF
3K
2
NC1
34
33
NFIO3
NFIO2
NFIO1
NFIO0
32
31
30
29
C
C97
1
28
27
GROUND
26
GROUND
25
D
K9F2808_YCB0
NFPIN38
E
DESIGN
GROUND
CUSTOMER
MCS LOGIC
CHECK-1
E
REV.
MLN7400
CHECK-2
DATE
UPDATE
SHEET
14/14
2003.11.18
REMARK
1
2
3
4
5
6
NAND FLASH