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DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
Identification
DTM64303B 128Mx64
1GB 1Rx8 PC3-10600U-9-10-A0
Performance range
Clock / Module Speed / CL-tRCD -tRP
667 MHz / PC3-10600 / 9-9-9
533 MHz / PC3-8500 / 8-8-8
400 MHz / PC3-6400 / 6-6-6
Features
Description
240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm high
DTM64303B is an Unbuffered 128Mx64
memory module, which conforms to
JEDEC's DDR3, PC3-10600 standard. The
assembly is single rank, comprised of eight
128Mx8 DDR3 Hynix SDRAMs. One 2K-bit
EEPROM is used for Serial Presence
Detect.
Both output driver strength and input
termination impedance are programmable to
maintain signal integrity on the I/O signals.
Operating Voltage: 1.5 V ±0.075
I/O Type: SSTL_15
Data Transfer Rate: 10.6 Gigabytes/sec
Data Bursts: 8 and burst chop 4 mode
ZQ Calibration for Output Driver and On-Die Termination (ODT)
Programmable ODT / Dynamic ODT during Writes
Programmable CAS Latency: 6, 8, and 9
Differential Data Strobe signals
SDRAM Addressing (Row/Col/Bank): 14/10/3
Fully RoHS Compliant
Pin Configuration
Front Side
Pin Description
Back Side
Name
Function
Data Check Bits
1 VREFDQ 31 DQ25
61 A2
91 DQ41 121 VSS
151 VSS
181 A1
211 VSS
CB[7:0]
2 VSS
32 VSS
62 VDD
92 VSS
152 DM3
182 VDD
212 DM5
DQ[63:0]
Data Bits
3
4
5
6
33 /DQS3
34 DQS3
35 VSS
36 DQ26
63 CK1 **
64 /CK1 **
65 VDD
66 VDD
93
94
95
96
153
154
155
156
183
184
185
186
213
214
215
216
DQS[8:0], /DQS[8:0]
DM[8:0]
CK[1:0], /CK[1:0]
CKE[1:0]
Differential Data Strobes
Data Mask
Differential Clock Inputs
Clock Enables
DQ0
DQ1
VSS
/DQS0
122 DQ4
/DQS5 123 DQ5
DQS5 124 VSS
VSS
125 DM0
DQ42 126 NC
NC
VSS
DQ30
DQ31
7 DQS0 37 DQ27
8 VSS
38 VSS
9 DQ2
39 CB0 **
67 VREFCA
97 DQ43 127 VSS
68 PAR_IN, NC** 98 VSS
128 DQ6
69 VDD
99 DQ48 129 DQ7
10 DQ3
11 VSS
12 DQ8
40 CB1 **
41 VSS
42 /DQS8 **
70 A10/AP
71 BA0
72 VDD
100 DQ49 130 VSS
160 VSS
101 VSS
131 DQ12 161 DM8 **
102 /DQS6 132 DQ13 162 NC
13 DQ9
43 DQS8 **
73 /WE
103 DQS6 133 VSS
14 VSS
15 /DQS1
16 DQS1
17 VSS
44 VSS
45 CB2 **
46 CB3 **
47 VSS
74 /CAS
104 VSS
75 VDD
105 DQ50
76 /S1, NC**
106 DQ51
77 ODT1, NC ** 107 VSS
18 DQ10
19 DQ11
20 VSS
48 VTT
49 VTT
50 CKE0
78 VDD
79 /S2, NC **
80 VSS
21 DQ16
51 VDD
81 DQ32
22 DQ17
23 VSS
24 /DQS2
25 DQS2
26 VSS
27 DQ18
52 BA2
82 DQ33
53 /ERR_OUT, NC** 83 VSS
54 VDD
84 /DQS4
55 A11
85 DQS4
56 A7
86 VSS
57 VDD
87 DQ34
28 DQ19
58 A5
29 VSS
30 DQ24
59 A4
60 VDD
NC
VSS
DQ46
DQ47
187 /Event, NC
188 A0
189 VDD
217 VSS
218 DQ52
219 DQ53
/CAS
/RAS
/S[1:0]
Column Address Strobe
Row Address Strobe
Chip Selects
190 BA1
191 VDD
192 /RAS
220 VSS
221 DM6
222 NC
/WE
A[15:0]
BA[2:0]
Write Enable
Address Inputs
Bank Addresses
163 VSS
193 /S0
223 VSS
ODT[1:0]
On Die Termination Inputs
164
165
166
167
194
195
196
197
224
225
226
227
DQ54
DQ55
VSS
DQ60
SA[2:0]
SCL
SDA
VSS
SPD Address
SPD Clock Input
SPD Data Input/Output
Ground
108 DQ56 138 DQ15 168 /RESET
198 /S3, NC**
109 DQ57 139 VSS
169 CKE1, NC ** 199 VSS
110 VSS
140 DQ20 170 VDD
200 DQ36
228 DQ61
229 VSS
230 DM7
VDD
VDDSPD
VREFDQ
Power
SPD EEPROM Power
Reference Voltage for DQ
111 /DQS7 141 DQ21 171 A15 **
201 DQ37
231 NC
VREFCA
Reference Voltage for CA
112 DQS7
113 VSS
114 DQ58
115 DQ59
116 VSS
117 SA0
142 VSS
143 DM2
144 NC
145 VSS
146 DQ22
147 DQ23
172
173
174
175
176
177
202
203
204
205
206
207
232
233
234
235
236
237
VTT
NC
Termination Voltage
No Connection
88 DQ35
118 SCL
148 VSS
178 A6
89 VSS
90 DQ40
119 SA2
120 VTT
149 DQ28 179 VDD
150 DQ29 180 A3
134 DM1
135 NC
136 VSS
137 DQ14
157 VSS
158 CB4 **
159 CB5 **
VDD
CK0
/CK0
VDD
CB6 **
CB7 **
VSS
NC (TEST)
A14 **
VDD
A12/ /BC
A9
VDD
A8
VDD
ODT0
A13
VDD
VSS
DM4
NC
VSS
DQ38
DQ39
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
208 VSS
238 SDA
209 DQ44
210 DQ45
239 VSS
240 VTT
** Not used
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
Page 1
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
Front view
133.35
[5.250]
9.50
[0.374]
30.00
[1.181]
17.30
[0.681]
5.00
[0.197]
5.175
[0.204]
47.00
[1.850]
71.00
[2.795]
2.50
[0.098]
123.00
[4.843]
Back view
Side view
2.72 Max
[0.107] Max
4.00 Min
[0.157] Min
1.27 ±.10
[0.0500 ±0.0040]
Notes
Tolerances on all dimensions except where otherwise
indicated are ±.13 (.005).
All dimensions are expressed: millimeters [inches]
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
Page 2
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
/S0
DMR0
DQSR0
/DQSR0
DMR4
DQSR4
/DQSR4
/DQS
DQR[7:0]
DQS
CS
/CS DM
/DQS
I/O[7:0]
DQR[39:32]
DMR1
DQSR1
/DQSR1
DQS
CS
/CS DM
/DQS
I/O[7:0]
DQR[47:40]
DMR2
DQSR2
/DQSR2
DQS
CS
/CS DM
/DQS
DQR[55:48]
I/O[7:0]
DMR3
DQSR3
/DQSR3
/CS DM
DQS
CS
/CS DM
DQS
CS
/CS DM
I/O[7:0]
DMR7
DQSR7
/DQSR7
/DQS
DQR[31:24]
DQS
CS
I/O[7:0]
DMR6
DQSR6
/DQSR6
/DQS
DQR[23:16]
/CS DM
DMR5
DQSR5
/DQSR5
/DQS
DQR[15:8]
DQS
CS
I/O[7:0]
DQS
CS
/CS DM
/DQS
I/O[7:0]
DQR[63:56]
I/O[7:0]
All 15 OHMS
DQ[63:0]
DQR[63:0]
DQS[7:0]
DQRS[7:0]
/DQS[7:0]
/DQRS[7:0]
2.2 pF
CLK0
CLK0b
DMR[7:0]
DM[7:0]
VDD
GLOBAL SDRAM CONNECTS
All 36 OHMS 100 nf
CLK0b
All 39 OHMS
BA[2:0]
CLK0
A[13:0]
/RAS
/CAS
/WE
VTT
All 39 OHMS
CKE0
ODT0
CS0
VTT
VDDSPD
VDD
VREF_DQ
VSS
VREF_CA
VTT
DECOUPLING
Serial PD
All Devices
All SDRAMs
All Devices
All SDRAMs
All SDRAMs
All 240 OHMS
ZQ
SCL
VSS
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
SERIAL PD
SDA
SA0 SA1 SA2
Page 3
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
Absolute Maximum Ratings
(Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.)
PARAMETER
Symbol
Minimum
Maximum
Unit
Temperature, non-Operating
TSTORAGE
-55
100
C
TA
0
70
C
Ambient Temperature, Operating
TCASE
0
95
C
VDD
-0.4
1.975
V
VIN,VOUT
-0.4
1.975
V
DRAM Case Temperature, Operating
Voltage on VDD relative to VSS
Voltage on Any Pin relative to VSS
Notes:
DRAM Operating Case Temperature above 85C requires 2X refresh.
Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Power Supply Voltage
Symbol
VDD
Minimum
1.425
Typical
1.5
Maximum
1.575
Unit
V
Note
I/O Reference Voltage
VREFDQ
0.49 VDD
0.50 VDD
0.51 VDD
V
1
I/O Reference Voltage
VREFCA
0.49 VDD
0.50 VDD
0.51 VDD
V
1
Notes:
1. The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may
not exceed ±1% of its DC value. For Reference VDD/2 ± 15 mV.
DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Logical High (Logic 1)
Symbol
VIH(DC)
Minimum
VREF + 0.1
Maximum
VDD
Unit
V
Logical Low (Logic 0)
VIL(DC)
VSS
VREF - 0.1
V
AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Logical High (Logic 1)
Symbol
VIH(AC)
Minimum
VREF + 0.175
Maximum
-
Unit
V
Logical Low (Logic 0)
VIL(AC)
-
VREF - 0.175
V
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
Page 4
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Differential Input Logic High
Symbol
VIH.DIFF
Minimum
+0.200
Maximum
DC:VDD AC:VDD+0.4
Unit
V
VIL.DIFF
DC:VSS AC:VSS-0.4
-0.200
V
VIX
- 0.150
+ 0.150
V
Differential Input Logic Low
Differential Input Cross Point Voltage
relative to VDD/2
Note
Capacitance (TA = 25 C, f = 100 MHz)
PARAMETER
Pin
Symbol
Minimum
Maximum
Unit
CCK
8.6
13.4
pF
pF
Input Capacitance, Clock
CK0, /CK0,
Input Capacitance, Address
BA[2:0], A[12:0], /RAS, /CAS, /WE
CI
6
10.4
Input Capacitance Control
/S0, CKE0, ODT0
CI
6
10.4
Input/Output Capacitance
DQ[63:0], DQS[8:0], /DQS[8:0],
DM[8:0]
CIO
1.5
2.5
pF
ZQ Capacitance
ZQ
CZQ
-
6
pF
DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Input Leakage Current
Symbol
Minimum
Maximum
Unit
Note
IIL
-18
+18
μA
1,2
IOL
-10
+10
μA
2,3
(Any input 0 V < VIN < VDD)
Output Leakage Current
(0V < VOUT < VDDQ)
Notes:
1) All other pins not under test = 0 V
2) Values are shown per pin
3) DQ’s, DQS, DQS and ODT are disabled
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
Page 5
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V)
PARAMETER
Operating One
Bank ActivePrecharge Current
Operating One
Bank Active-ReadPrecharge Current
Precharge PowerDown Current
Precharge PowerDown Current
Precharge Quiet
Standby Current
Precharge Standby
Current
Active Power-Down
Current
Active Standby
Current
Operating Burst
Write Current
Operating Burst
Read Current
Burst Refresh
Current
Self Refresh
Current
Operating Bank
Interleave Read
Current
Symbol
IDD0
IDD1
IDD2P
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5
IDD6
IDD7
Test Condition
Operating current : One bank ACTIVATE-to-PRECHARGE
Operating current : One bank ACTIVATE-to-READ-toPRECHARGE
Precharge power down current: (Slow exit)
Precharge power down current: (Fast exit)
Precharge quiet standby current
Precharge standby current
Active power-down current
Active standby current
Burst write operating current
Burst read operating current
Refresh current
Self-refresh temperature current: MAX TC = 85°C
All bank interleaved read current
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
Max
Value
Unit
640
mA
760
mA
80
mA
240
mA
440
mA
440
mA
240
mA
520
mA
1080
mA
1080
mA
1360
mA
80
mA
1600
mA
Page 6
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
AC Operating Conditions
PARAMETER
Symbol
Min
Max
Unit
Internal read command to first data
tAA
13.5
20
ns
CAS-to-CAS Command Delay
tCCD
4
-
tCK
tCH(avg)
0.47
0.53
tCK
tCK
1.5
1.875
ns
tCL(avg)
0.47
0.53
tCK
tDH
65
-
ps
Clock High Level Width
Clock Cycle Time
Clock Low Level Width
Data Input Hold Time after DQS Strobe
tDIPW
400
-
ps
DQS Output Access Time from Clock
tDQSCK
-255
+255
ps
Write DQS High Level Width
tDQSH
0.4
0.6
tCK(avg)
Write DQS Low Level Width
tDQSL
0.4
0.6
tCK(avg)
DQS-Out Edge to Data-Out Edge Skew
tDQSQ
-
125
ps
Data Input Setup Time Before DQS Strobe
tDS
30
-
ps
DQS Falling Edge from Clock, Hold Time
tDSH
0.2
-
tCK(avg)
DQS Falling Edge to Clock, Setup Time
tDSS
0.2
-
tCK(avg)
Clock Half Period
tHP
minimum of tCH or tCL
-
ns
Address and Command Hold Time after Clock
tIH
140
-
ps
DQ Input Pulse Width
tIS
65
-
ps
Load Mode Command Cycle Time
tMRD
4
-
tCK
DQ-to-DQS Hold
tQH
0.38
-
tCK(avg)
Active-to-Precharge Time
tRAS
36
9*tREFI
ns
Active-to-Active / Auto Refresh Time
tRC
49.5
-
ns
RAS-to-CAS Delay
tRCD
13.5
-
ns
-
7.8
μs
Address and Command Setup Time before Clock
o
o
tREFI
o
o
Average Periodic Refresh Interval 0 C < TCASE < 95 C
tREFI
-
3.9
μs
Auto Refresh Row Cycle Time
tRFC
110
-
ns
Row Precharge Time
tRP
13.5
-
ns
Read DQS Preamble Time
tRPRE
0.9
Note-1
tCK(avg)
Read DQS Postamble Time
tRPST
0.3
Note-2
tCK(avg)
Row Active to Row Active Delay
tRRD
Max(4nCK, 6ns)
-
ns
Internal Read to Precharge Command Delay
tRTP
Max(4nCK, 7.5ns)
-
ns
Average Periodic Refresh Interval 0 C < TCASE < 85 C
Write DQS Preamble Setup Time
tWPRE
0.9
-
tCK(avg)
Write DQS Postamble Time
tWPST
0.3
-
tCK(avg)
Write Recovery Time
tWR
15
-
ns
Internal Write to Read Command Delay
tWTR
Max(4nCK, 7.5ns)
-
ns
Notes:
1.
2.
The maximum preamble is bound by tLZDQS(min)
The maximum postamble is bound by tHZDQS(max)
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
Page 7
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
SERIAL PRESENCE DETECT MATRIX
Byte#
0
Function.
Value
Hex
0x92
1
Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage.
Bit 3 ~ Bit 0. SPD Bytes Used 176
Bit 6 ~ Bit 4. SPD Bytes Total 256
Bit 7. CRC Coverage - Bytes 0-116
SPD Revision.
Rev. 1.0
2
Key Byte / DRAM Device Type.
0x0B
3
Key Byte / Module Type.
DDR3 SDRAM
0x02
Bit 3 ~ Bit 0. Module Type Bit 7 ~ Bit 4. Reserved -
4
6
SDRAM Density and Banks.
Bit 3 ~ Bit 0. Total SDRAM capacity, in megabits Bit 6 ~ Bit 4. Bank Address Bits Bit 7. Reserved SDRAM Addressing.
Bit 2 ~ Bit 0. Column Address Bits Bit 5 ~ Bit 3. Row Address Bits Bit 7, 6. Reserved
Reserved.
7
Module Organization.
5
UDIMM
0
0x02
1Gb
8 banks
0
0x11
10
14
0
UNUSED
8-Bits
1-Rank
0
10
Module Memory Bus Width.
Bit 2 ~ Bit 0. Primary bus width, in bits Bit 4, Bit 3. Bus width extension, in bits Bit 7 ~ Bit 5. Reserved Fine Timebase (FTB) Dividend / Divisor.
Bit 3 ~ Bit 0. Fine Timebase (FTB) Divisor
Bit 7 ~ Bit 4. Fine Timebase (FTB) Dividend
Medium Timebase (MTB) Dividend.
11
Medium Timebase (MTB) Divisor.
12
SDRAM Minimum Cycle Time (tCKmin).
2
5
1 (MTB =
0.125ns)
8 (MTB =
0.125ns)
1.5ns
13
Reserved.
UNUSED
14
CAS Latencies Supported, Least Significant Byte.
9
Bit 0. CL = 4 Bit 1. CL = 5 Bit 2. CL = 6 Bit 3. CL = 7 Bit 4. CL = 8 Bit 5. CL = 9 Bit 6. CL = 10 Bit 7. CL = 11 15
0x00
0x01
Bit 2 ~ Bit 0. SDRAM Device Width Bit 5 ~ Bit 3. Number of Ranks Bit 7, 6. Reserved
8
0x10
CAS Latencies Supported, Most Significant Byte.
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
0x03
64-Bits
0-Bits
0
0x52
0x01
0x08
0x0C
0x00
0x34
X
X
X
0x00
Page 8
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
Bit 0. CL = 12 Bit 1. CL = 13 Bit 2. CL =14 Bit 3. CL = 15 Bit 4. CL = 16 Bit 5. CL = 17 Bit 6. CL = 18 Bit 7. Reserved.
16
Minimum CAS Latency Time (tAAmin).
13.5ns
0x6C
17
Minimum Write Recovery Time (tWRmin).
15.0ns
0x78
18
Minimum RAS# to CAS# Delay Time (tRCDmin).
13.5ns
0x6C
19
Minimum Row Active to Row Active Delay Time (tRRDmin).
6.0ns
0x30
20
Minimum Row Precharge Delay Time (tRPmin).
13.5ns
0x6C
21
Upper Nibbles for tRAS and tRC.
Bit 3 ~ Bit 0. tRAS Most Significant Nibble Bit 7 ~ Bit 4. tRC Most Significant Nibble 22
Minimum Active to Precharge Delay Time (tRASmin), Least
Significant Byte.
23
Minimum Active to Active/Refresh Delay Time (tRCmin), Least
Significant Byte.
24
Minimum Refresh Recovery Delay Time (tRFCmin), Least
Significant Byte.
25
Minimum Refresh Recovery Delay Time (tRFCmin), Most
Significant Byte.
26
Minimum Internal Write to Read Command Delay Time
(tWTRmin).
27
Minimum Internal Read to Precharge Command Delay Time
(tRTPmin).
28
Upper Nibble for tFAW.
Bit 3 ~ Bit 0. tFAW Most Significant Nibble Bit 7 ~ Bit 4. Reserved 29
Minimum Four Activate Window Delay Time (tFAWmin), Least
Significant Byte.
30
SDRAM Optional Features.
Bit 0. RZQ / 6 Bit 1. RZQ / 7 Bit 6 ~ Bit 2. Reserved Bit 7. DLL-Off Mode Support
31
SDRAM Drivers Supported.
Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh (ASR) On-die Thermal Sensor (ODTS) Readout Reserved Reserved Reserved Reserved 32-59 Reserved
60
Module Nominal Height.
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
0x11
1
1
36.0ns
0x20
49.5ns
0x8C
110.0ns
0x70
110.0ns
0x03
7.5ns
0x3C
7.5ns
0x3C
0x00
0
0
240
0xF0
0x82
X
0x05
X
X
UNUSED
0x00
0x0F
Page 9
DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
Bit 4 ~ Bit 0. Module Nominal Height max, in mm Bit 7 ~ Bit5. Reserved 61
Module Maximum Thickness.
Bit 3 ~ Bit 0. Front, in mm (baseline thickness = 1 mm) Bit 7 ~ Bit 4. Back, in mm (baseline thickness = 1 mm) 62
Reference Raw Card Used.
Bit 4 ~ Bit 0. Reference Raw Card Bit 6, Bit 5. Reference Raw Card Revision Bit 7. Reserved 63
Address Mapping from Edge Connector to DRAM.
Bit 0. Rank 1 Mapping (Registered DIMM - Reserved) Bit 7 ~ Bit 1. Reserved 64-112 Module-Specific Section
29<h<=30
0
113
114-116
117
118
119
120,121
122-125
126
127
128-131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146,147
148
149
150-175
176-255
UNUSED
UNUSED
Module-Specific Section.
Module-Specific Section
Module Manufacturer ID Code, Least Significant Byte
Module Manufacturer ID Code, Most Significant Byte
Module Manufacturing Location
Module Manufacturing Date
Module Serial Number
Cyclical Redundancy Code (CRC).
Cyclical Redundancy Code (CRC).
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Part Number
Module Revision Code
DRAM Manufacturer ID Code, Least Significant Byte
DRAM Manufacturer ID Code, Most Significant Byte
Manufacturer’s Specific Data
Open for customer use
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
0x11
1<th<=2
1<th<=2
0x00
R/C A
Rev.0
0
0x00
Standard
0
UNUSED
UNUSED
CRC
CRC
D
A
T
A
R
A
M
6
4
3
0
3
UNUSED
UNUSED
UNUSED
UNUSED
0x00
0x00
0x00
0x01
0x91
0x00
0x20
0x20
0x1F
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DTM64303B
1 GB - 240-Pin 1Rx8 Unbuffered Non-ECC DDR3 DIMM
DATARAM CORPORATION, USA Corporate Headquarters, P.O.Box 7528, Princeton, NJ 08543-7528;
Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com
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The information contained in this document has been carefully checked and is believed to be reliable. However,
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without prior written consent of Dataram.
Document 06545, Revision A, 11-May-09, Dataram Corporation © 2009
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