Download Transcend 256MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory

144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
Pin Identification
Description
The
TS32MSS64V6G
Dynamic
RAM
TS32MSS64V6G
is
a
high-density
consists
32Mx64
memory
of
8
Synchronous
module.
pieces
of
Symbol
The
CMOS
Function
A0~A12
Address inputs
BA0,BA1
Select Bank
printed circuit board. The TS32MSS64V6G is a Dual
DQ0~DQ63
Data inputs/outputs
In-Line Memory Module and is intended for mounting into
CLK0,CLK1
Clock Input
CKE0,CKE1
Clock Enable Input
/CS0,/CS1
Chip Select Input
frequencies,
/RAS
Row address strobe
programmable latencies allow the same device to be useful
/CAS
Column address strobe
/WE
Write Enable
DQM0~7
DQM
Vcc
Power Supply
Vss
Ground
16Mx16bits Synchronous DRAMs in TSOP-II 400mil
packages and a 2048 bits serial EEPROM on a 144-pin
144-pin edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock
cycle.
Range
of
operation
for a variety of high bandwidth, high performance memory
system applications.
Features
•
Burst Mode Operation.
•
Auto and Self Refresh.
•
Serial Presence Detect (SPD) with serial EEPROM
SDA
Serial Address / Data I/O
•
LVTTL compatible inputs and outputs.
SCL
Serial Clock
•
Single 3.3V ± 0.3V power supply.
•
MRS cycle with address key programs.
NC
No Connection
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
•
All inputs are sampled at the positive going edge
of the system clock.
•
•
DRAM Brand: Promos.
Operating Temperature TA: 0~70 °C
Transcend information Inc
1
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
Dimension
B
D
A
F
C
E
G
H
K
I
J
PCB : 09-6757
Transcend information Inc
Side
Millimeters
Inches
A
67.60 ± 0.200
2.661 ± 0.008
B
32.80
1.291
C
23.20
0.913
D
4.60
0.181
E
3.30
0.130
F
2.50
0.098
G
4.00
0.157
H
6.00
0.236
I
20.00
0.787
J
29.21 ± 0.200
1.150 ± 0.008
K
1.00 ± 0.100
0.039 ± 0.004
2
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
Pinouts
Pin
Pin
Pin Pin
No
Name
No Name
01
Vss
49
DQ13
03
DQ0
51
DQ14
05
DQ1
53
DQ15
07
DQ2
55
Vss
09
DQ3
57
*CB0
11
Vcc
59
*CB1
13
DQ4
61
CLK0
15
DQ5
63
Vcc
17
DQ6
65
/RAS
19
DQ7
67
/WE
21
Vss
69
/CS0
23
DQM0
71
*/CS1
25
DQM1
73
NC
27
Vcc
75
Vss
29
A0
77
*CB2
31
A1
79
*CB3
33
A2
81
Vcc
35
Vss
83
DQ16
37
DQ8
85
DQ17
39
DQ9
87
DQ18
41
DQ10
89
DQ19
43
DQ11
91
Vss
45
Vcc
93
DQ20
47
DQ12
95
DQ21
* Please refer Block Diagram
Transcend information Inc
Pin
No
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Pin
Name
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQM2
DQM3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
Pin
No
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQM4
DQM5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
Pin
No
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Pin
Name
DQ45
DQ46
DQ47
Vss
*CB4
*CB5
CKE0
Vcc
/CAS
*CKE1
*A12
*A13
*CLK1
Vss
*CB6
*CB7
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
Pin
No
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin
Name
DQ54
DQ55
Vcc
A7
BA0
Vss
*BA1
*A11
Vcc
DQM6
DQM7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
Block Diagram
/CS1
/CS0
/CS
/CS
/CS
/CS
DM0
DM
DM
DM2
DM
DM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
U1
U3
U5
U7
DM4
DM
DM
DM6
DM
DM
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS
DM1
DM
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM5
DM
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
U2
A0~A12
BA0~BA1
CKE0
CKE1
/RAS
/CAS
/WE
CK0
CK1
/CS
/CS
DM
DM3
DM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DM7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
U6
U1~U8
U1~U8
U1~U4
U5~U8
U1~U8
U1~U8
U1~U8
U1~U4
U5~U8
/CS
DM
U4
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
U8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
EEPROM
SCL
SDA
A0 A1 A2
VDD/VDDQ
U1~U8
0.1 u
Note:
1.DQ resistors :10 Ohms±5%
VSS
U1~U8
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
Transcend information Inc
4
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Operating Temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
TA
Value
-1.0~4.6
-1.0~4.6
-55~+150
8
50
0 ~ 70
Unit
V
V
°C
W
mA
°C
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70 °C)
Parameter
Symbol
Min
Typ
Max
Supply voltage
VDD
3.0
3.3
3.6
Input high voltage
VIH
2.0
3.0
VDD+0.3
Input low voltage
VIL
-0.3
0
0.8
Output high voltage
VOH
2.4
Output low voltage
VOL
0.4
Input leakage current
ILI
-10
10
Unit
V
V
V
V
V
uA
Note
1
2
IOH = -2mA
IOL = 2mA
3
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is < 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is < 3ns.
3. Any input 0V ≤ Vin ≤ VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-state output.
CAPACITANCE (VDD = 3.3V, TA = 23℃, f = 1MHz, VREF = 1.4V ± 200mV)
Parameter
Input capacitance (A0~A12, BA0~BA1)
Input capacitance (/RAS, /CAS, /WE)
Input capacitance (CKE0~CKE1)
Input capacitance (CLK0~CLK1)
Input capacitance (/CS0~CS1)
Input capacitance (DQM0~DQM7)
Data input/output capacitance (DQ0~DQ63)
Transcend information Inc
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
5
Min
25
25
15
15
15
10
10
Max
45
45
25
21
25
12
12
Unit
pF
pF
pF
pF
pF
pF
pF
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating Current
(One Bank Active)
Symbol
ICC1
Precharge Standby Current ICC2P
in power-down mode
ICC2PS
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
Test Condition
Burst Length =1
tRC≥tRC(min)
IOL=0mA
Value
Unit
Note
740
mA
1
CKE≤VIL(max), tCC=10ns
16
CKE & CLK≤VIL(max), tCC=∞
16
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 20ns
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
128
mA
112
CKE≤VIL(max), tCC=10ns
48
CKE & CLK≤VIL(max), tCC=∞
48
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 20ns
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
mA
mA
280
mA
240
ICC4
IOL= 0 mA
Page Burst
tccD = 2CLKs
860
mA
1
Refresh current
Icc5
tRC ≥ tRC(min)
1000
mA
2
Self Refresh Current
ICC6
CKE≤0.2V
24
mA
Operating Current
(Burst Mode)
Note:
Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading cap.
Transcend information Inc
6
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf=1/1
1.4
See Fig. 2
Unit
V
V
ns
V
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Row active time
Row cycle time
@Operation
Last data in to new col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
Number of valid output data
Note:
Value
15
20
20
45
100
65
1
2
1
1
Unit
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
Note
1
1
1
1
2
ea
4
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc
7
1
2
2
2
3
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
Value
Min
Max
Note
1000
ns
1
5.4
ns
1, 2
CLK cycle time
tCC
CLK to valid
output delay
tSAC
Output data
hold time
tOH
3.0
ns
2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
tCH
tCL
tSS
tSH
tSLZ
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
CLK to output in Hi-Z
tSHZ
Note:
7.5
Unit
5.4
ns
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc
8
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Refresh
Mode Register Set
Auto Refresh
Entry
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Burst Stop
Bank Selection
Both Banks
Precharge
Clock Suspend or Entry
Active Power Down
Exit
Entry
Precharge Power
Down Mode
Exit
DQM
No Operation Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
DQM
H
X
H
L
L
L
L
L
X
OP CODE
L
L
L
H
X
X
X
H
BA0,1
L
H
L
H
H
X
H
X
H
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
L
H
X
X
X
L
X
V
X
V
X
V
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
X
V
V
H
X
X
X
L
H
H
H
L
H
H
L
L
H
X
Row Address
L
Column
Address
H
(A0~A8)
L
Column
Address
H
(A0~A8)
X
V
X
X
L
H
4
4, 5
4
4, 5
6
X
X
X
X
X
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note:
1. OP Code : Operand Code
A0~A12, BA0~BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc
1,2
3
3
3
3
X
H
H
V
A10/AP A12, A11, A0~A9 Note
9
7
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
Standard Specification
Vendor Part
0
# of Bytes Written into Serial Memory
Function Described
128bytes
80
1
Total # of Bytes of S.P.D Memory
256bytes
08
2
Fundamental Memory Type
SDRAM
04
3
# of Row Addresses on this Assembly
A0~A12
0D
4
# of Column Addresses on this Assembly
A0~A8
09
5
# of Module Banks on this Assembly
2 banks
02
6
Data Width of this Assembly
64bits
40
7
Data Width Continuation
0
00
8
Voltage Interface Standard of this Assembly
LVTTL3.3V
01
9
SDRAM Cycle Time (highest CAS latency)
7.5ns
75
10
SDRAM Access from Clock (highest CL)
5.4ns
54
11
DIMM configuration type (non-parity, ECC)
DIMM
00
12
Refresh Rate Type
7.8us/Self Refresh
82
13
Primary SDRAM Width
X16
10
14
Error Checking SDRAM Width
0
00
15
Min Clock Delay Back to Back Random Address
1 clock
01
16
Burst Lengths Supported
1,2,4,8 & Full page
8F
17
Number of banks on each SDRAM device
4 bank
04
18
CAS # Latency
2&3
06
19
CS # Latency
0 clock
01
20
Write Latency
0 clock
01
21
SDRAM Module Attributes
Non Buffer
00
22
SDRAM Device Attributes : General
Prec All, Auto Prec, R/W Burst
0E
nd
23
SDRAM Cycle Time (2 highest CL)
10ns
A0
24
SDRAM Access from Clock (2nd highest CL)
6ns
60
-
00
-
00
25
rd
SDRAM Cycle Time (3 highest CL)
rd
26
SDRAM Access from Clock (3 highest CL)
27
Minimum Row Precharge Time
20ns
14
28
Minimum Row Active to Row Activate
15ns
0F
29
Minimum RAS to CAS Delay
20ns
14
30
Minimum RAS Pulse Width
45ns
2D
31
Density of Each Bank on Module
128MB
20
32
Command/Address Setup Time
1.5ns
15
33
Command/Address Hold Time
0.8ns
08
34
Data Signal Setup Time
1.5ns
15
35
Data Signal Hold Time
0.8ns
08
-
00
36-61
Superset Information
Transcend information Inc
10
144PIN PC133 Unbuffered SO-DIMM
256MB With 16MX16 CL3
TS32MSS64V6G
62
SPD Data Revision Code
VER1.2
12
63
Checksum for Bytes 0-62
BA
BA
Transcend
7F, 4F
T
54
64-71
72
Manufacturers JEDEC ID Dode per JEP-108E
Manufacturing Location
54 53 33 32 4D 53
73-90
Manufacturers Part Number
91-92
Revision Code
93-94
TS32MSS64V6G
53 36 34 56 36 47
20 20 20 20 20 20
-
0
Manufacturing Date
By Manufacturer
Variable
95-98
Assembly Serial Number
By Manufacturer
Variable
99-125
Manufacturer Specific Data
-
0
126
Intel Specification Frequency
-
64
127
Intel Specification CAS# Latency/Clock Signal Support
CL=2&3 Clock=0,1
C6
128~
Unused Storage Locations
Open
FF
Transcend information Inc
11