Download Transcend 256MB SDRAM PC133 ECC Registered Memory

168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
Description
Placement
The TS32MLR72V6F is a 16M x 72 bits Synchronous
Dynamic RAM high-density memory registered DIMM
module. The TS32MLR72V6F consists of 9pcs 16Mx8
bits Synchronous DRAMs, 2pcs drive ICs for input
control signal, 1pc PLL and a 2048 bits serial EEPROM
on
a
168-pin
printed
circuit
board.
The
TS32MLR72V6F is a Dual In-Line Memory Module and
is intended for mounting into 168-pin edge connector
A
sockets.
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible
on every clock cycle. Range of operation frequencies,
programmable latencies allow the same device to be
B
useful for a variety of high bandwidth, high performance
memory system applications.
C
Features
D
• Performance Range: PC-133
E
• Burst Mode Operation.
F
• Auto and Self Refresh.
G
• DQM Byte Masking (Read/Write)
PCB: 09-0875
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend Information Inc.
1
H
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
Pin Identification
Dimensions
Side
Millimeters
Symbol
Inches
A
133.35±0.40
5.250±0.016
B
65.67
2.585
C
23.49
0.925
D
8.89
0.350
E
15.80
F
Function
SA0~SA11
Address Input
SBA0, SBA1
Select Bank Address
SD0~SD63
Data Input / Output.
0.622
SCB0~SCB7
Check bit (data-in / data-out)
19.80
0.780
SCK0~SCK3
Clock Input.
G
29.21±0.20
1.150±0.008
H
1.27±0.10
0.050±0.004
SCKE0
Clock Enable Input.
/SCS0, SCS2
Chip Select Input.
/SRAS
Row Address Strobe
/SCAS
Column Address Strobe
/SWE
Write Enable
(Refer Placement)
SDQM0~SDQM7 Data (DQ) Mask
Transcend Information Inc.
2
SREGE
Register Enable
EA0~EA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
NC
No Connection
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
Pinouts:
Pin
Pin
Pin
Pin
No
Name
No
Name
01
Vss
43
Vss
02
SD0
44
NC
03
SD1
45
/SCS2
04
SD2
46
SDQM2
05
SD3
47
SDQM3
06
Vcc
48
NC
07
SD4
49
Vcc
08
SD5
50
NC
09
SD6
51
NC
10
SD7
52
*SCB2
11
SD8
53
*SCB3
12
Vss
54
Vss
13
SD9
55
SD16
14
SD10
56
SD17
15
SD11
57
SD18
16
SD12
58
SD19
17
SD13
59
Vcc
18
Vcc
60
SD20
19
SD14
61
NC
20
SD15
62
*Vref
21
*SCB0
63
*SCKE1
22
*SCB1
64
Vss
23
Vss
65
SD21
24
NC
66
SD22
25
NC
67
SD23
26
Vcc
68
Vss
27
/SWE
69
SD24
28
SDQM0
70
SD25
29
SDQM1
71
SD26
30
/SCS0
72
SD27
31
NC
73
Vcc
32
Vss
74
SD28
33
SA0
75
SD29
34
SA2
76
SD30
35
SA4
77
SD31
36
SA6
78
Vss
37
SA8
79
*SCLK2
38
SA10/AP
80
NC
39
SBA1
81
NC
40
Vcc
82
SDA
41
Vcc
83
SCL
42
SCLK0
84
Vcc
* Please refer Block Diagram
Transcend Information Inc.
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
3
Pin
Name
Vss
SD32
SD33
SD34
SD35
Vcc
SD36
SD37
SD38
SD39
SD40
Vss
SD41
SD42
SD43
SD44
SD45
Vcc
SD46
SD47
*SCB4
*SCB5
Vss
NC
NC
Vcc
/SCAS
SDQM4
SDQM5
*/SCS1
/SRAS
Vss
SA1
SA3
SA5
SA7
SA9
SBA0
SA11
Vcc
*SCLK1
*SA12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
SCKE0
*/SCS3
SDQM6
SDQM7
*SA13
Vcc
NC
NC
*SCB6
*SCB7
Vss
SD48
SD49
SD50
SD51
Vcc
SD52
NC
*Vref
*SREGE
Vss
SD53
SD54
SD55
Vss
SD56
SD57
SD58
SD59
Vcc
SD60
SD61
SD62
SD63
Vss
*SCLK3
NC
EA0
EA1
EA2
Vcc
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
Block Diagram
SCB0~SCB7
RDQM5
/RCS0
PCK2
/RCS0
/RCS2
/RCS2
PCK3
PCK3
/RCS0
/RCS2
CLK
/RCS0
PCK2
PCK1
PCK1
PCK2
PCK3
PCK4
PLL
CLK
SCLK0
/CS
CLK
DQM
DQ0~DQ7
A0~A11,BA0,BA1
/RAS 32Mx8
SDRAM
/CAS
/WE
CKE
RDQM1
RDQM4
EEPROM
RDQM7
/RCS2
/CS
CLK
DQM
DQ0~DQ7
A0~A11,BA0,BA1
/RAS 32Mx8
SDRAM
/CAS
/WE
CKE
PCK3
DQ0~DQ7
A0~A11,BA0,BA1
/RAS 32Mx8
SDRAM
/CAS
/WE
CKE
DQM
CLK
RDQM6
/CS
RDQM3
PCK2
DQ0~DQ7
A0~A11,BA0,BA1
/RAS 32Mx8
SDRAM
/CAS
/WE
CKE
DQ0~DQ7
A0~A11,BA0,BA1
/RAS 32Mx8
SDRAM
/CAS
/WE
CKE
DQM
CLK
/CS
DQM
CLK
/CS
RDQM2
PCK1
DQ0~DQ7
A0~A11,BA0,BA1
/RAS 32Mx8
SDRAM
/CAS
/WE
CKE
DQ0~DQ7
A0~A11,BA0,BA1
32Mx8
/RAS
SDRAM
/CAS
/WE
CKE
/CS
/RCS0
PCK1
PCK4
DQM
DQM
CLK
RDQM1
/CS
/RCS0~3
RDQM0
DQ0~DQ7
A0~A11,BA0,BA1
32Mx8
/RAS
SDRAM
/CAS
/WE
CKE
DQM
SREGE
RDQM0~7
CLK
/SCS0~SCS3
REGISTER
SDQM0~SDQM7
DQM
/SWE
SCKE0
DQ0~DQ7
A0~A11,BA0,BA1
32Mx8
/RAS
SDRAM
/CAS
/WE
CKE
/CS
RA0~RA11,RBA0,RBA1
/RRAS
/RCAS
/RWE
RCKE0
/CS
SD0~SD63
SA0~SA11,SBA0,SBA1
/SRAS
/SCAS
SCL
SCL
A0
SDA
A1
SDA
A2
EA0 EA1 EA2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend
makes no warranties, either expressed or implied, as to its accuracy and assumes no liability in connection with the
use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice.
Transcend Information Inc.
4
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply to Vss
Storage temperature
Power dissipation
Short circuit current
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
MTBF
THB
TC
Value
-1.0~4.6
-1.0~4.6
-55~+150
9
50
50
85°C/85%,
0°C ~ 125°C
Unit
V
V
°C
W
mA
year
°C-%
°C-Hr
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)
Parameter
Symbol
Typ
Max
Unit
Min
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Output high voltage
VOH
2.4
V
Output low voltage
VOL
0.4
V
Input leakage current
IIL
-10
10
uA
Note
1
2
IOH=-2mA
IOL=2mA
3
Note: 1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Transcend Information Inc.
5
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (SA0~SA11, SBA0~ SBA1)
CIN1
-
15
pF
Input capacitance (/SRAS, /SCAS, /SWE)
CIN2
-
15
pF
Input capacitance (SCKE0)
CIN3
-
15
pF
Input capacitance (SCLK0~SCLK3)
CIN4
-
23
pF
Input capacitance (/SCS0, /SCS2)
CIN5
-
15
pF
Input capacitance (SDQM0~SDQM7)
CIN6
-
15
pF
Data input/output capacitance (SD0~SD63)
COUT
-
16
pF
Data input/output capacitance (SCB0~SCB7)
COUT1
-
16
pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
CAS Latency
Operating Current
(One Bank Active)
ICC1
Precharge Standby
Current
in power-down mode
Precharge Standby
Current
in non power-down mode
ICC2P
ICC2PS
Burst Length =1
tRC≥tRC(min)
IOL=0mA
CKE≤VIL(max), tCC=10ns
CKE & CLK≤VIL(max), tCC=∞
ICC2N
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 20ns
ICC2NS
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
Active Standby Current
in power-down mode
Unit
Note
1,630
mA
1
mA
3
368
20
494
mA
128
ICC3P
CKE≤VIL(max), tCC=10ns
404
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
56
Active Standby Current
ICC3N
in non power-down mode
(One Bank Active)
ICC3NS
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 20ns
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
Operating Current
(Bust Mode)
Value
ICC4
IOL= 0 mA
Page Burst
tccD = 2CLKs
Refresh Current
ICC5
tRC≥tRC(min)
Self Refresh Current
ICC6
CKE≤0.2V
Note: 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 2 Drive Ics
4. Unless otherwise noticed, input swing level is CMOS (VIH/\VIL=VDDQ/VSSQ)
Transcend Information Inc.
6
mA
3
3
620
mA
3
227
1,610
mA
1
2,240
395
mA
mA
2
3
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf=1/1
1.4
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
Unit
V
V
ns
V
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
/RAS to /CAS delay
Row precharge time
Row cycle time
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Last data in to new col. address delay
Last data in to row precharge
Last data in to Active delay
Last data in to burst stop
Col. address to col. address delay
tCDL(min)
tRDL(min)
tDAL
tBDL(min)
tCCD(min)
Row active time
Number of valid
CAS latency=3
Value
Unit
Note
15
20
45
100
60
ns
ns
ns
us
ns
1
1
1
CLK
CLK
2
2
CLK
CLK
2
3
ea
4
1
2
2CLK+20ns
1
1
2
output data
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend Information Inc.
7
1
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
Unit
Note
ns
1
ns
1, 2
ns
1, 2
ns
ns
ns
ns
ns
3
3
3
3
2
tSHZ
CLK to output
ns
CAS latency=3
5.4
in Hi-Z
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the paremeter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
1
CLK cycle time
CAS latency=2
tCC
CLK to valid
output delay
CAS latency=2
tSAC
Output data
hold time
CAS latency=2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
Transcend Information Inc.
Value
Min
Max
7.5
1000
5.4
tOH
2.7
tCH
tCL
tSS
tSH
tSLZ
2.5
2.5
1.5
0.8
1
8
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
SIMPLIFIED TRUTH TABLE
COMMAND
Register
SCKEn-1 SCKEn /SCS /SRAS /SCAS /SWE SDQM SBA0,1 SA10/AP
Mode Register Set
Auto Refresh
Entry
Refresh
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Clock Suspend or Entry
Active Power Down
Exit
Entry
Precharge Power
Down Mode
Exit
SDQM
H
H
X
H
L
L
L
L
X
OP CODE
L
L
L
H
X
X
L
H
H
H
H
X
X
X
X
X
L
H
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
L
H
X
X
X
L
V
V
V
L
H
X
X
X
X
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
H
H
No Operation Command
H
X
X
SA0~SA9, SA11
L
H
X
X
X
L
H
H
H
X
V
Note
1,2
3
3
3
3
Row Address
L
Column
Address
H
(SA0~SA9)
L
Column
Address
H
(SA0~SA9)
X
V
L
X
H
4
4, 5
4
4, 5
6
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note:
1. OP Code : Operand Code
SA0~SA11, SBA0~SBA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. SBA0~SBA1: Bank select address.
If both SBA0 and SBA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both SBA0 is “Low” and SBA1 is “High” at read, write, row active and precharge, bank B is selected.
If both SBA0 is “High” and SBA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both SBA0 and SBA1 are “High” at read, write, row active and precharge, bank D is selected.
If SA10/AP is “High” at row precharge, SBA0 and SBA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. SDQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write SDQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read SDQM latency is 2)
Transcend Information Inc.
9
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
Serial Presence Detect Specification
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
Serial Presence Detect
Function Described
Standard Specification
# of Bytes Written into Serial Memory
128bytes
Total # of Bytes of S.P.D Memory
256bytes
Fundamental Memory Type
SDRAM
# of Row Addresses on this Assembly
13
# of Column Addresses on this Assembly
10
# of Module Banks on this Assembly
1 bank
Data Width of this Assembly
72bits
Data Width Continuation
0
Voltage Interface Standard of this Assembly
LVTTL3.3V
SDRAM Cycle Time (highest CAS latency)
7.5ns
SDRAM Access from Clock (highest CL)
5.4ns
DIMM configuration type (non-parity, ECC)
ECC
Refresh Rate Type
7.8us/Self Refresh
Primary SDRAM Width
X8
Error Checking SDRAM Width
X8
Min Clock Delay Back to Back Random Address
1 clock
Burst Lengths Supported
1,2,4,8 & Full page
Number of banks on each SDRAM device
4 bank
CAS # Latency
3
CS # Latency
0 clock
Write Latency
0 clock
SDRAM Module Attributes
Registered DQM,
address/control inputs
and on-card PLL
SDRAM Device Attributes : General
SDRAM Cycle Time (2nd highest CL)
SDRAM Access from Clock (2nd highest CL)
SDRAM Cycle Time (3rd highest CL)
SDRAM Access from Clock (3rd highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Transcend Information Inc.
10
Vendor Part
80
08
04
0D
0A
01
48
00
01
75
54
02
82
08
08
01
8F
04
06
01
01
16
Prec All, Auto Prec, R/W
Burst
0E
20ns
15ns
20ns
45ns
128MB
1.5ns
0.8ns
1.5ns
0.8ns
JEDEC2
A0
60
00
00
14
0F
14
2D
20
15
08
15
08
00
02
168PIN PC133 Registered DIMM
256MB With 32Mx8 CL3
TS32MLR72V6F
63
64-71
72
Checksum for Bytes 0-62
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
73-90
Manufacturers Part Number
91-92
93-94
95-98
99-125
126
127
128~
Revision Code
Manufacturing Date上午 09:36
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend Information Inc.
Transcend
T
TS32MLR72V6F
11
By Manufacturer
By Manufacturer
CL2 & CL=3 Clock 0
Open
CA
7F, 4F
54
54 53 33 32 4D 4C
52 37 32 56 36 46
20 20 20 20 20 20
0
Variable
Variable
0
64
86
FF