Download Transcend 256MB SDRAM 144Pin SO-DIMM PC100 Unbuffer Non-ECC Memory

144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
Description
Pin Identification
Symbol
The TS32MSS64V8D2 is a 32M bit x 64 Synchronous
Function
A0~A11
Address inputs
TS32MSS64V8D2 consists of 16 pieces of CMOS
BA0, BA1
Banks Select
4Mx8bitsx4banks Synchronous DRAMs in TSOP-II 400mil
D0~D63
Data inputs/outputs
packages, a 2048 bits serial EEPROM and a PLL on a
CLK0
Clock Input
144-pin printed circuit board. The TS32MSS64V8D2 is a
CKE0, CKE1
Clock Enable Input
Dual In-Line Memory Module and is intended for mounting
/CS0, /CS1
Chip Select Input
into 144-pin edge connector sockets.
/RAS
Row address strobe
/CAS
Column address strobe
use of system clock. I/O transactions are possible on every
/WE
Write Enable
clock cycle. Range of operation frequencies, programmable
DQM0~DQM7
DQM
latencies allow the same device to be useful for a variety of
Vcc
Power Supply
high
Vss
Ground
SDA
Serial Address / Data I/O
SCL
Serial Clock
NC
No Connection
Dynamic
RAM
high-density
memory
modules.
The
Synchronous design allows precise cycle control with the
bandwidth,
high
performance
memory
system
applications.
Features
•
Burst Mode Operation.
•
Auto and Self Refresh.
•
Serial Presence Detect (SPD) with serial EEPROM
•
LVTTL compatible inputs and outputs.
•
Single 3.3V ± 0.3V power supply.
•
MRS cycle with address key programs.
Dimensions
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the
system clock.
Transcend information Inc.
1
Side
Millimeters
Inches
A
B
C
D
E
F
G
H
I
67.60 ± 0.20
32.80
23.20
4.60
3.30
4.00
20.00
50.50 ± 0.20
1.00 ± 0.10
2.661 ± 0.008
1.291
0.913
0.181
0.130
0.157
0.787
1.988 ± 0.008
0.040 ± 0.004
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
Dimension
B
D
A
C
E
F
I
G
H
PCB: 09-7265
Pinouts
Pin
Pin
Pin Pin
No
Name
No
Name
01
Vss
49
DQ13
03
DQ0
51
DQ14
05
DQ1
53
DQ15
07
DQ2
55
Vss
09
DQ3
57
*CB0
11
Vcc
59
*CB1
13
DQ4
61
CLK0
15
DQ5
63
Vcc
17
DQ6
65
/RAS
19
DQ7
67
/WE
21
Vss
69
/CS0
23
DQM0
71
*/CS1
25
DQM1
73
NC
27
Vcc
75
Vss
29
A0
77
*CB2
31
A1
79
*CB3
33
A2
81
Vcc
35
Vss
83
DQ16
37
DQ8
85
DQ17
39
DQ9
87
DQ18
41
DQ10
89
DQ19
43
DQ11
91
Vss
45
Vcc
93
DQ20
47
DQ12
95
DQ21
* Please refer Block Diagram
Pin
No
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Pin
Name
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQM2
DQM3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
Pin
No
02
04
06
08
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Transcend information Inc.
2
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQM4
DQM5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
Pin
No
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Pin
Name
DQ45
DQ46
DQ47
Vss
*CB4
*CB5
CKE0
Vcc
/CAS
*CKE1
*A12
*A13
*CLK1
Vss
*CB6
*CB7
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
Pin
No
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin
Name
DQ54
DQ55
Vcc
A7
BA0
Vss
*BA1
*A11
Vcc
DQM6
DQM7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
Block Diagram
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
DQM0
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
DQM5
DQM7
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
/CS
CLK
CKE
REF
DQM5
PLL
CLK2
CLK02
CLK1
CLK01
CLK3
CLK03
CLK4
CLK04
DQM7
DQM6
SCL
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
DQM3
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
DQM2
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
DQM1
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM4
CLK0
DQM6
DQM
/CS
CLK
CKE
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM0
CLK04
DQM3
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM4
/CS1
CLK03
CKE1
DQM2
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
CLK02
DQM1
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
A0~A11,BA0,1
DQ0~DQ7
/RAS
/CAS 16Mx8
/WE SDRAM
DQM
A0~A11
BA0~BA1
D0~D63
/RAS
/CAS
/WE
/CS0
CLK01
CKE0
EEPROM
SCL
SDA
A0
A1
SDA
A2
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make
changes in specifications at any time without prior notice.
Transcend information Inc.
3
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Voltage on any pin relative to Vss
VIN, VOUT
-1.0~4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0~4.6
V
TSTG
-55~+150
°C
Power dissipation
PD
16
W
Short circuit current
Ios
50
mA
MTBF
50
year
Storage temperature
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
Note
Value
Unit
THB
85°C/85%, Static Stress
°C-%
TC
0°C ~ 125°C Cycling
°C
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
2. Functional operation should be restricted to recommended operating condition.
3. Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70 °C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
1,2
Input low voltage
VIL
-0.3
0
0.8
V
1,2
Output high voltage
VOH
2.4
V
IOH = -2mA
Output low voltage
VOL
0.4
V
IOL = 2mA
1.All voltages are referenced to Vss.
Note :
2.VIH may overshoot to VDD+2.0V for pulse width of <4ns with 3.3V. VIL may undershoot to -2.0V for pulse
width<4.0ns with 3.3V. Pulse width measured at 50% points with amplitude-measured peak to DC
reference.
CAPACITANCE (VDD = 3.3V, TA = 23℃, f = 1MHz, VREF = 1.4V ± 200mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A11, BA0~BA1)
CIN1
45
85
pF
Input capacitance (/RAS, /CAS, /WE)
CIN2
45
85
pF
Input capacitance (CKE0~CKE1)
CIN3
25
45
pF
Input capacitance (CLK0)
CIN4
25
21
pF
Input capacitance (/CS0~/CS1)
CIN5
25
25
pF
Input capacitance (DQM0~DQM7)
CIN6
10
15
pF
Data input/output capacitance (DQ0~DQ63)
COUT
13
18
pF
Transcend information Inc.
4
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
Burst Length =1
tRC≥tRC(min)
IOL=0mA
ICC1
Precharge Standby Current ICC2P CKE≤VIL(max), tCC=10ns
in power-down mode
ICC2PS CKE & CLK≤VIL(max), tCC=∞
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
960
32
320
ICC2NS
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
160
ICC3P
CKE≤VIL(max), tCC=10ns
80
ICC3PS CKE & CLK≤VIL(max), tCC=∞
ICC3N
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 20ns
Unit
Note
mA
1
mA
32
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 20ns
ICC2N
Precharge Standby Current
in non power-down mode
Value
mA
mA
80
480
mA
ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
ICC4
IOL= 0 mA
Page Burst
400
mA
1
1760
mA
2
32
mA
1040
tccD = 2CLKs
Refresh current
Self Refresh Current
Note:
ICC5
tRC≥tRC(min)
ICC6
CKE≤0.2V
1. Measured with outputs open.
2.Refresh period is 64ms.
3.Unless otherwise noticed, input swing level is CMOS (VIH/VIL=VDDQ/VSSQ)
Transcend information Inc.
5
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
AC OPERATING TEST CONDITIONS (VDD=3.3.0.3V, TA=0 to 70%C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
Value
Unit
Note
Row active to row active delay
tRRD(min)
20
ns
1
/RAS to /CAS delay
tRCD(min)
20
ns
1
Row precharge time
tRP(min)
20
ns
1
tRAS(min)
50
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
70
ns
1
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to Active delay
tDAL(min)
2CLK+ tRP
-
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Number of valid output data
1
ea
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
4
Row active time
Transcend information Inc.
6
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
CLK cycle time
tCC
Value
Max
10
1000
ns
1
6
ns
1, 2
tSAC
Output data
Note
Min
CLK to valid
output delay
Unit
tOH
3
ns
2
CLK high pulse width
tCH
3
ns
3
CLK low pulse width
tCL
3
ns
3
Input setup time
tSS
2
ns
3
Input hold time
tSH
1
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
hold time
CLK to output
6
tSHZ
ns
in Hi-Z
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
if tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc.
7
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Refresh
Auto Refresh
Entry
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Column
Address
Write &
Column
Address
Burst Stop
Precharge
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Clock
Entry
Suspend or
Active Power
Down
Exit
Entry
Precharge
Power
Down Mode
CKEn
/CS
/RAS
/CAS
/WE
DQM
H
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
H
X
H
L
L
H
H
L
L
L
H
L
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
X
X
X
L
H
H
H
X
BA0,1
V
X
A10/AP
A11, A0~A9
Note
1,2
3
3
3
3
Row Address
L
H
L
H
X
L
H
Column
Address
(A0~A8)
Column
Address
(A0~A8)
4
4, 5
4
4, 5
6
X
X
X
X
X
X
Exit
DQM
L
H
X
H
No Operation Command
Note:
CKEn-1
H
X
X
V
X
X
X
7
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
1. OP Code: Operand Code
A0~A11, BA0~BA1: Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc.
8
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
Function Described
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Number of Bytes Written into Serial Memory
Total Number of Bytes of S.P.D Memory
Fundamental Memory Type
Number of Row Addresses on this Assembly
Number of Column Addresses on this Assembly
Number of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
22
SDRAM Device Attributes: General
nd
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
SDRAM Cycle Time (2 highest CL)
SDRAM Access from Clock (2nd highest CL)
SDRAM Cycle Time (3rd highest CL)
SDRAM Access from Clock (3rd highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID code per JEP-108E
Manufacturing Location
73-90
Manufacturers Part Number
Standard
Specification
128bytes
256bytes
SDRAM
12
10
2 banks
64bits
0
LVTTL3.3V
10ns
6ns
DIMM
15.625us/Self Refresh
X8
0
1 clock
1,2,4,8 & Full page
4 bank
2, 3
0 clock
0 clock
Non Buffer
Prec All, Auto Prec,
R/W Burst
10ns
6ns
20ns
20ns
20ns
50ns
128MB
20ns
10ns
20ns
10ns
INTEL
17
Transcend
T
TS32MSS64V8D2
Transcend information Inc.
9
Vendor Part
80
08
04
0C
0A
02
40
00
01
A0
60
00
80
08
00
01
8F
04
06
01
01
00
0E
A0
60
00
00
14
14
14
32
20
20
10
20
10
00
12
17
7F, 4F
54
54 53 33 32 4D 53
53 36 34 56 38 44
32 20 20 20 20 20
144PIN PC100 Unbuffered SO-DIMM
256MB With 16Mx8 CL2
TS32MSS64V8D2
91-92
93-94
95-98
99-125
126
127
128~
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend information Inc.
10
By Manufactory
By Manufactory
CL=2,3 Clock 0
Open
0
Variable
Variable
0
64
C6
FF