Download Transcend 128MB SDRAM PC100 Unbuffer Non-ECC Memory

128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
Description
Dimensions
The TS16MLS64V8C2 is a 16M bit x 64 Synchronous
Side
Millimeters
Inches
Dynamic RAM high-density for PC-100 CL2. The
A
133.35±0.40
5.250±0.016
TS16MLS64V8C2 consists of 8pcs CMOS 8Mx16 bits
B
65.67
2.585
Synchronous DRAMs in TSOP-II 400mil packages
C
23.49
0.925
and a 2048 bits serial EEPROM on a 168-pin printed
D
8.89
0.350
E
3.00
0.118
F
31.75±0.20
1.250±0.008
G
19.80
0.788
H
15.80
0.622
I
1.27±0.10
0.050±0.004
circuit board. The TS16MLS64V8C2 is a Dual In-Line
Memory Module and is intended for mounting into
168-pin edge connector sockets.
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible
on every clock cycle. Range of operation frequencies,
(Refer Placement)
programmable latencies allow the same device to be
useful
for
a
variety
of
high
bandwidth,
high
Pin Identification
performance memory system applications.
Symbol
Function
A0~A11, BA0,BA1 Address input
Features
DQ0~DQ63
Data Input/Output.
• Performance Range: PC-100 CL2.
CLK0~CLK3
Clock Input..
• Conformed to JEDEC Standard 4 clocks.
CKE0, CKE1
Clock Enable Input.
• 16,777,216 words x 64 bits organization.
/CS0~/CS3
Chip Select Input.
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
• Burst Mode Operation.
• Auto and Self Refresh.
• CKE Power Down Mode.
• DQM Byte Masking (Read/Write)
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
NC
No Connection
(Refer Block Diagram AND Pinouts)
Data Scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend information Inc.
1
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
Placement
A
B
C
E
D
E
H
G
F
PCB: 09-7130
Transcend information Inc.
2
I
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
Pinouts:
Pin
No
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Pin
Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
Vss
NC
NC
Vcc
/WE
DQM0
DQM1
/CS0
NC
Vss
A0
A2
A4
A6
A8
A10
BA1
Vcc
Vcc
CLK0
Transcend information Inc.
Pin
No
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin
Name
Vss
NC
/CS2
DQM2
DQM3
NC
Vcc
NC
NC
NC
NC
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
CLK2
NC
NC
SDA
SCL
Vcc
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
CLK1
NC
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
/CS3
DQM6
DQM7
NC
Vcc
NC
NC
NC
NC
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
CLK3
NC
SA0
SA1
SA2
Vcc
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
TS16MLS64V8C2-- Block Diagram
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U4
UDQM
D28
D29
D30
D31
D27
D26
D25
D24
D60
D61
D62
D63
D59
D58
D57
D56
/CS
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM3
D56
D57
D58
D59
D63
D62
D61
D60
D24
D25
D26
D27
D31
D30
D29
D28
DQM7
LDQM
UDQM
U2
DQM6
UDQM
LDQM
/CS3
SDRAM U1~U4,U6~U9
/CAS
SDRAM U1~U4,U6~U9
CKE0
SDRAM U1~U4
CKE1
SDRAM U6~U9
DQn
Every DQpin of SDRAM
CLK2
10
/CS
UDQM
DQM7
LDQM
U9
DQM3
UDQM
LDQM
U1/U3
SDRAM U1~U4,U6~U9
/RAS
U7
DQM2
UDQM
LDQM
CLK0
A0~A12,BA0,BA1
/CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D23
D22
D21
D20
D16
D17
D18
D19
D55
D54
D53
D52
D48
D49
D50
D51
U8
DQM1
UDQM
DQM4
DQM0
LDQM
U6
/CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D11
D10
D9
D8
D12
D13
D14
D15
D44
D45
D46
D47
D43
D42
D41
D40
DQM5
/CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM6
/CS1
D3
D2
D1
D0
D4
D5
D6
D7
D36
D37
D38
D39
D35
D34
D33
D32
/CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D51
D50
D49
D48
D52
D53
D54
D55
D19
D18
D17
D16
D20
D21
D22
D23
U3
DQM5
UDQM
DQM0
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D40
D41
D42
D43
D47
D46
D45
D44
D15
D14
D13
D12
D8
D9
D10
D11
U1
/CS
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM4
D32
D33
D34
D35
D39
D38
D37
D36
D7
D6
D5
D4
D0
D1
D2
D3
/CS2
/CS
DQM2
/CS0
U2/U4
10
15pf
CLK1
15pf
U6/U8
CLK3
10
U7/U9
10
15pf
15pf
10
VDD
Two 0.33uf per
each SDRAM
VSS
VDD
To all SDRAMs
VSS
VDD
Serial
EEPROM
SCL
10k
CKE1
To all SDRAMs
0.1uf per
each SDRAM
SCL
A0
SDA
A1
SDA
A2
SA0 SA1 SA2
SDRAM U6~U9
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make
changes in specifications at any time without prior notice.
Transcend information Inc.
4
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0~4.6
V
Voltage on VDD supply to Vss
VDD, VDDQ
-1.0~4.6
V
TSTG
-55~+150
°C
Power dissipation
PD
8
W
Short circuit current
IOS
50
mA
MTBF
50
Years
Storage temperature
Mean time between failure
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, T A = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH=-2mA
Output low voltage
VOL
-
-
0.4
V
IOL=2mA
Input leakage current (Inputs)
IIL
-8
-
8
uA
3
Input leakage current (I/O pins)
IOL
-3
-
3
uA
4
Note: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
Transcend information Inc.
5
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
CAPACITANCE (TA = 25°C, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A11, BA0~ BA1)
CIN1
-
60
pF
Input capacitance (/RAS, /CAS, /WE)
CIN2
-
60
pF
Input capacitance (CKE0~CKE1)
CIN3
-
35
pF
Input capacitance (CLK0~CLK3)
CIN4
-
25
pF
Input capacitance (/CS0~/CS3)
CIN5
-
25
pF
Input capacitance (DQM0~DQM7)
CIN6
-
15
pF
Data input/output capacitance (DQ0~DQ63)
COUT
-
15
pF
Transcend information Inc.
6
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating Current
(One Bank Active)
Symbol
ICC2N
Active Standby Current
in power-down mode
ICC2NS
Unit
Note
600
mA
1
CKE≤VIL(max), tCC=15ns
8
CKE & CLK≤VIL(max), tCC=∞
8
CKE≥VIH(min), /CS≥VIH(min), tCC=15ns
Input signals are changed one time during 30ns
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
120
mA
56
Input signals are stable
CKE≤VIL(max), tCC=15ns
40
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
40
CKE≥VIH(min), /CS≥VIH(min), tCC=15ns
Input signals are changed one time during 30ns
mA
240
mA
ICC3NS
Operating Current
(Bust Mode)
ICC4
Refresh Current
ICC5
160
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
IOL= 0 mA
Page Burst
tccD = 2CLKs
Self Refresh Current
ICC6
Note 1. Measured with outputs open.
2. Refresh period is 64ms.
Transcend information Inc.
Value
ICC3P
ICC3N
Active Standby Current
in non power-down mode
(One Bank Active)
CAS Latency
Burst Length =1
tRC≥tRC(min)
IOL=0mA
ICC1
Precharge Standby Current ICC2P
in power-down mode
ICC2PS
Precharge Standby Current
in non power-down mode
Test Condition
7
3
700
2
700
mA
1
2
tRC≥tRC(min)
1600
mA
CKE≤0.2V
12
mA
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
Output
VOH (DC)=2.4V, I OH=-2mA
VOL (DC)=0.4V, I OL=2mA
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
Value
Unit
Note
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
1
1
1
1
1
2
2
2
3
CAS latency=3
20
20
20
50
100
70
1
1
1
1
2
ea
4
CAS latency=2
1
Row active to row active delay
/RAS to /CAS delay
Row precharge time
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
Row active time
Row cycle time
Last data in to new col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Number of valid
output data
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend information Inc.
8
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
Value
Min
CLK cycle time
CAS latency=3
CAS latency=2
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=3
10
tCC
Unit
Note
ns
1
ns
1, 2
ns
2
Max
1000
10
6
tSAC
CAS latency=2
6
3
tOH
CAS latency=2
3
CLK high pulse width
tCH
3
ns
3
CLK low pulse width
tCL
3
ns
3
Input setup time
tSS
2
ns
3
Input hold time
tSH
1
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
6
tSHZ
6
CAS latency=2
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend information Inc.
9
ns
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
Frequency
CAS
tRC
tRAS
TRP
tRRD
tRCD
tCCD
tCDL
tRDL
Latency
70ns
48ns
20ns
16ns
20ns
8ns
8ns
8ns
100MHz(10.0ns)
2
7
5
2
2
2
1
1
1
83MHz(12.0ns)
2
6
5
2
2
2
1
1
1
75MHz(13.0ns)
2
6
4
2
2
2
1
1
1
66MHz(15.0ns)
2
5
4
2
2
2
1
1
1
Transcend information Inc.
10
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
SIMPLIFIED TRUTH TABLE
COMMAND
Register
/CS
/RAS
/CAS
/WE
DQM
BA0,1
A10/AP
H
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
H
X
L
H
L
L
X
V
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Clock Suspend or Entry
Active
Power
Down
Exit
H
X
X
X
H
L
L
V
V
V
L
H
X
X
X
X
H
X
X
X
Entry
H
L
L
H
H
H
H
X
X
X
Refresh
Mode Register Set
CKEn-1 CKEn
Auto Refresh
Entry
Self
Exit
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Burst Stop
Precharge
Precharge Power
Down Mode
Bank Selection
Both Banks
Exit
L
H
L
DQM
No Operation Command
H
L
H
H
V
V
V
X
X
H
X
X
X
L
H
H
H
1,2
3
3
3
3
H
L
H
4, 5
Column
Address
(A0~A8)
4, 5
11
4
6
X
X
X
X
X
X
X
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note: 1. OP Code: Operand Code
A0~A11, BA0~BA1: Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc.
4
Column
Address
(A0~A8)
X
V
X
Note
Row Address
L
Auto Precharge Disable
A11,
A0~A9
7
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function Described
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
nd
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
SDRAM Cycle Time (2 highest CL)
nd
SDRAM Access from Clock (2 highest CL)
rd
SDRAM Cycle Time (3 highest CL)
rd
SDRAM Access from Clock (3 highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
73-90
Manufacturers Part Number
91-92
93-94
Revision Code
Manufacturing Date
Transcend information Inc.
Standard Specification
128bytes
256bytes
SDRAM
A0~A11
A0~A8
2 bank
64bits
0
LVTTL3.3V
10ns
6ns
None
15.625us/Self Refresh
x16
1 clock
1,2,4,8 & Full page
4 bank
3,2
0 clock
0 clock
Non Buffer
Prec All, Auto Prec, R/W
Burst
10ns
6ns
0
0
20
20
20
50
64MB
2ns
1ns
2ns
1ns
Version 1.2
Transcend
T
TS16MLS64V8C2
By Manufacturer
12
Vendor Part
80
08
04
0C
09
02
40
00
01
A0
60
00
80
10
00
01
8F
04
06
01
01
00
0E
A0
60
00
00
14
14
14
32
10
20
10
20
10
00
12
0E
7F, 4F
54
54 53 31 36 4D 4C
53 36 34 56 38 43
32 20 20 20 20 20
0
Variable
128MB 168PIN PC100 CL2
SDRAM DIMM With 8M X 16 3.3VOLT
TS16MLS64V8C2
95-98
99-125
126
127
128~
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend information Inc.
13
By Manufacturer
100MHz
CL=2,3 Clock=0~3
Open
Variable
0
64
F6
FF