Download Transcend 128MB SDRAM PC133 Unbuffer Non-ECC Memory

168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
Description
Placement
The TS16MLS64V6D is a 16M bit x 64 Synchronous
Dynamic
RAM
high-density
for
PC-133.
The
TS16MLS64V6D consists of 8pcs CMOS 16Mx8 bits
Synchronous DRAMs in TSOP-II 400mil packages and
a 2048 bits serial EEPROM on a 168-pin printed circuit
board. The TS16MLS64V6D is a Dual In-Line Memory
Module and is intended for mounting into 168-pin edge
connector sockets.
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible
A
on every clock cycle. Range of operation frequencies,
programmable latencies allow the same device to be
useful
for
a
variety
of
high
bandwidth,
high
performance memory system applications.
Features
B
• RoHs Compliant Product.
D
• Performance Range: PC-133.
• Conformed to JEDEC Standard Spec.
E
• Burst Mode Operation.
C
• Auto and Self Refresh.
• CKE Power Down Mode.
E
• DQM Byte Masking (Read/Write)
H
• Serial Presence Detect (SPD) with serial EEPROM
G
• LVTTL compatible inputs and outputs.
F
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
PCB : 09-7149
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend Information Inc.
1
I
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
Dimensions
Pin Identification
Side
Millimeters
Inches
Symbol
A
133.35±0.40
5.250±0.016
A0~A11, BA0, BA1
Address input
B
65.67000
2.585000
DQ0~DQ63
Data Input / Output.
C
23.49000
0.925000
CLK0, CLK2
Clock Input.
D
8.89000
0.350000
CKE0
Clock Enable Input.
E
3.00000
0.118000
/CS0, /CS2
Chip Select Input.
F
31.75±0.200
1.250±0.00800
G
19.8000
0.788000
/RAS
Row Address Strobe
H
15.80
0.622
/CAS
Column Address Strobe
I
1.27±0.10
0.050±0.004
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
NC
No Connection
(Refer Placement)
Transcend Information Inc.
2
Function
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
Pinouts:
Pin
Pin
Pin
Pin
No
Name
No
Name
01
Vss
43
Vss
02
DQ0
44
NC
03
DQ1
45
/CS2
04
DQ2
46
DQM2
05
DQ3
47
DQM3
06
Vcc
48
NC
07
DQ4
49
Vcc
08
DQ5
50
NC
09
DQ6
51
NC
10
DQ7
52
*CB2
11
DQ8
53
*CB3
12
Vss
54
Vss
13
DQ9
55
DQ16
14
DQ10
56
DQ17
15
DQ11
57
DQ18
16
DQ12
58
DQ19
17
DQ13
59
Vcc
18
Vcc
60
DQ20
19
DQ14
61
NC
20
DQ15
62
*Vref
21
*CB0
63
*CKE1
22
*CB1
64
Vss
23
Vss
65
DQ21
24
NC
66
DQ22
25
NC
67
DQ23
26
Vcc
68
Vss
27
/WE
69
DQ24
28
DQM0
70
DQ25
29
DQM1
71
DQ26
30
/CS0
72
DQ27
31
NC
73
Vcc
32
Vss
74
DQ28
33
A0
75
DQ29
34
A2
76
DQ30
35
A4
77
DQ31
36
A6
78
Vss
37
A8
79
*CLK2
38
A10/AP
80
NC
39
BA1
81
NC
40
Vcc
82
SDA
41
Vcc
83
SCL
42
CLK0
84
Vcc
* Please refer Block Diagram
Transcend Information Inc.
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
*CB4
*CB5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
*/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
*CLK1
*A12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
*/CS3
DQM6
DQM7
*A13
Vcc
NC
NC
*CB6
*CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
*Vref
*REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CLK3
NC
SA0
SA1
SA2
Vcc
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
Block Diagram
/CS0
CKE0
DQM0
DQM4
DQM
DQ3
DQ1
DQ2
DQ0
DQ7
DQ5
DQ6
DQ4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQM
/CS CKE
DQ35
DQ34
DQ33
DQ32
DQ39
DQ38
DQ37
DQ36
U1
DQM1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQM
/CS CKE
DQ42
DQ41
DQ43
DQ40
DQ44
DQ46
DQ47
DQ45
U2
DQM2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
/CS CKE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
DQM
DQ51
DQ50
DQ49
DQ48
DQ53
DQ54
DQ55
DQ52
U3
DQM3
U5
/CS CKE
U6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
/CS CKE
U7
DQM7
DQM
DQ24
DQ25
DQ26
DQ27
DQ30
DQ31
DQ29
DQ28
/CS CKE
DQM6
DQM
DQ19
DQ18
DQ17
DQ16
DQ23
DQ22
DQ21
DQ20
0
1
2
3
4
5
6
7
DQM5
DQM
DQ8
DQ9
DQ10
DQ11
DQ15
DQ14
DQ13
DQ12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
/CS CKE
DQM
DQ58
DQ59
DQ57
DQ56
DQ60
DQ61
DQ62
DQ63
U4
BA0
U1~U8
BA1
U1~U8
-RAS
U1~U8
-CAS
U1~U8
-WE
CLK0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
U8
VDD
U1~U8
VSS
U1~U8
U1,U2,U5,U6
EEPROM
SCL
CLK2
/CS CKE
WP
SDA
U3,U4,U7,U8
SA0 SA1 SA2
Note:
1.U1~U8 are 16Mx8 SDRAM.
2.DQ-to-I/O wiring may be changed per nibble.
3.Unless otherwise noted , resister values are 10 Ohms±5%
This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties, either
expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make
changes in specifications at any time without prior notice.
Transcend Information Inc.
4
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply to Vss
Storage temperature
Power dissipation
Short circuit current
Operating temperature
Note:
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0~4.6
-1.0~4.6
-55~+150
8
50
Unit
V
V
°C
W
mA
TA
0~70
°C
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Type
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Output high voltage
VOH
2.4
V
Output low voltage
VOL
0.4
V
Input leakage current (Inputs)
IIL
-10
10
uA
Note
1
2
IOH=-2mA
IOL=2mA
3
Note: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (TA = 25°C, f = 1MHz)
Parameter
Input capacitance (A0~A11, BA0~ BA1)
Input capacitance (/RAS, /CAS, /WE)
Input capacitance (CKE0)
Input capacitance (CLK0, CLK2)
Input capacitance (/CS0,/CS2)
Input capacitance (DQM0~DQM7)
Data input/output capacitance (DQ0~DQ63)
Transcend Information Inc.
Symbol
Min
Max
Unit
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
30
30
30
22
15
6
6
45
45
45
30
25
8
8
pF
pF
pF
pF
pF
pF
pF
5
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating Current
(One Bank Active)
Symbol
ICC1
ICC2P
Precharge Standby Current
ICC2PS
in power-down mode
ICC2N
Test Condition
Burst Length =1
tRC≥tRC(min)
IOL=0mA
CKE≤VIL(max), tCC=10ns
CKE & CLK≤VIL(max), tCC=∞
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Value
Unit
Note
960
mA
1
8
160
mA
Input signals are changed one time during 30ns
Precharge Standby Current
in non power-down mode ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
8
56
Input signals are stable
Active Standby Current
in power-down mode
ICC3P
CKE≤VIL(max), tCC=10ns
40
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
40
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
240
ICC3N
Active Standby Current
in non power-down mode
(One Bank Active)
Input signals are changed one time during 30ns
ICC3NS
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
mA
mA
160
Input signals are stable
IOL= 0 mA
Page Burst
tccD = 2CLKs
1200
ICC5
tRC≥tRC(min)
ICC6
CKE≤0.2V
Operating Current
(Bust Mode)
ICC4
Refresh Current
Self Refresh Current
mA
1
1760
mA
2
12
mA
Note: Module IDD was calculated on the basis of component IDD and can be differently measured according to
DQ loading cap.
Transcend Information Inc.
6
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf=1/1
1.4
See Fig. 2
Unit
V
V
ns
V
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
Number of valid
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
CAS latency=3
-
output data
Value
Unit
Note
15
20
20
45
100
65
1
2
1
1
2
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
1
1
1
1
1
2
2
2
3
ea
4
-
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend Information Inc.
7
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
(Value)Min
(Value)Max
Unit
Note
CLK cycle time
tCC
7.5
1000
ns
1
CLK to valid output delay
tSAC
5.4
ns
1, 2
Output data hold time
tOH
3.0
ns
2
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output
tSHZ
5.4
in Hi-Z
Note:
ns
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend Information Inc.
8
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Refresh
Auto Refresh
Entry
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
/CS
/RAS
/CAS
/WE
DQM
BA0,1
Bank Selection
Both Banks
Clock Suspend or
Entry
Active
Power
Down
Exit
Entry
Precharge Power
Down Mode
Exit
DQM
No Operation Command
A10/AP A11, A0~A9
H
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
X
L
H
L
L
X
H
X
L
H
H
L
X
X
H
L
L
H
H
L
L
H
L
L
H
L
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
H
X
H
H
H
X
H
L
X
3
3
3
3
Column
H
(A0~A9)
Column
V
Address
H
H
1,2
Address
L
H
(A0~A9)
X
V
X
Note
Row Address
L
Auto Precharge Enable
Burst Stop
Precharge
CKEn-1 CKEn
L
H
X
4
4, 5
4
4, 5
6
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note:
1. OP Code : Operand Code
A0~A11, BA0~BA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend Information Inc.
9
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
Function Described
0
1
2
3
4
5
6
7
8
9
10
11
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
12
Refresh Rate Type
13
14
15
16
17
18
19
20
21
22
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
73-90
SDRAM Cycle Time (2nd highest CL)
SDRAM Access from Clock (2nd highest CL)
SDRAM Cycle Time (3rd highest CL)
SDRAM Access from Clock (3rd highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID Code per JEP-108E
Man Manufacturers Manufacturing Location
Part Number
Standard
Specification
128bytes
256bytes
SDRAM
12
10
1 bank
64bits
0
LVTTL3.3V
7.5ns
5.4ns
None
15.625us/Self
Refresh
X8
none
1 clock
1,2,4,8 & Full page
4 bank
3
0 clock
0 clock
Non Buffer
Prec All, Auto Prec,
R/W Burst
0
0
0
0
20ns
15ns
20ns
45ns
128MB
1.5ns
0.8ns
1.5ns
0.8ns
JEDEC2
Transcend
T
TS16MLS64V6D
Transcend Information Inc.
10
Vendor Part
80
08
04
0C
0A
01
40
00
01
75
54
00
80
08
00
01
8F
04
04
01
01
00
0E
00
00
00
00
14
0F
14
2D
20
15
08
15
08
00
02
9D
7F, 4F
54
54 53 31 36 4D 4C
53 36 34 56 36 44
168Pin PC133 Unbuffered DIMM
128MB with 16Mx8 CL3
TS16MLS64V6D
91-92
93-94
95-98
99-125
126
127
128~
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
Transcend Information Inc.
11
By Manufacturer
By Manufacturer
100MHz
CL=3 Clock 0~3
Open
20 20 20 20 20 20
0
Variable
Variable
0
64
F4
FF