Download Epson S5U1C62000A Specifications

ICE CONTROL SOFTWARE ICS62XX
BR, BRR
Format
SET/RESET BREAK REGISTER CONDITION
(With guidance)
#BR
#BRR
Function
A break condition is set in the evaluation board CPU registers A, B, FLAG, X (Xp, Xh, Xl,) or
Y (Yp, Yh, Yl).
(1) BR:
A break condition is set in the target registers A, B, FLAG, X (Xp, Xh, Xl,) or Y
(Yp, Yh, Yl). The break condition in each register can be masked (a masked
register can generate a break in another register, whatever the specified value).
Break is induced when the values of each register correspond to the set values in
the internal CPU registers.
(2) BRR: Cancels a break condition set by BR command.
(3) A break set by the BR command is operative at one point. BA and BD settings can be
mixed.
(4) A BR condition can be canceled by executing the BM command.
Examples
#BR
A
B
FI
FD
FZ
FC
X
Y
X
Y
-:C
-:*
-:1
-:*
-:0
-:*
---:040
---:^
---:041
---:030
...
A hyphen (-) is displayed when a BR condition is not set
Break condition is sequentially set
...
Enter an asterisk (*) mark to indicate masking
This induces a break unrelated to the FD value
...
If a parameter is mis-set, entering the ^ key will return
the operation to the previous setting (one less than the
current setting)
A break condition set as described above, where A=C, FI=1, FZ=0, X=41, and Y=30.
#BR
A
B
FI
FD
FZ
FC
X
Y
C:
*:
1:*
*:
0:*
*:
041:042
030:*
...
Reads a previously set break condition
When no setting modification is made, hitting the
continues the operation to the next setting
key
Two break conditions where A=C and X=42 are described above.
VIII-54
EPSON
S1C62 FAMILY
DEVELOPMENT TOOL REFERENCE MANUAL