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Table 7-1. Transfer Encoding for PowerPC 604e Processor Bus Master (Continued) TT[0–4] 604e Bus Master Transaction Transaction Transaction Source 11010 Read atomic Single-beat read or burst lwarx 11110 Read with intent to modify atomic Burst stwcx. miss with valid reservation 00011 Reserved — N/A (The 604e does not snoop.) 00111 Reserved — N/A (The 604e does not snoop.) 01011 Read with no intent to cache Single-beat read or burst N/A 01111 Reserved — N/A (The 604e does not snoop.) 1xx11 Reserved — N/A (The 604e does not snoop.) 7.2.4.2 Transfer Size (TSIZ[0–2]) The transfer size (TSIZ[0–2]) signals consist of three input/output signals on the 604e. 7.2.4.2.1 Transfer Size (TSIZ[0–2])—Output Following are the state meaning and timing comments for the TSIZ[0–2] output signals on the 604e. State Meaning Asserted/Negated—For memory accesses, these signals along with TBST, indicate the data transfer size for the current bus operation, as shown in Table 7-2. Table 8-4 shows how the TSIZ signals are used with the address signals for aligned transfers. Table 8-5 shows how the TSIZ signals are used with the address signals for misaligned transfers. For I/O transfer protocol, these signals form part of the I/O transfer code; see the description in Section 7.2.4.1, “Transfer Type (TT[0–4]).” For external control instructions (eciwx and ecowx), TSIZ[0–2] are used to output bits 29–31 of the external access register (EAR), which are used to form the resource ID (TBST||TSIZ[0–2]). Timing Comments Assertion/Negation—The same as A[0–31]. High Impedance—The same as A[0–31]. 7-12 PowerPC 604e RISC Microprocessor User's Manual
