Download STD 7000 7604 TTL I/O Card USER`S MANUAL

STD 7000
7604
TTL I/O Card
USER'S MANUAL
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7604
TTL 1/0 Card
USER'S MANUAL
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7604 TTL I/O CARD USER'S MANUAL
TABLE OF CONTENTS
SECll0N 1
Product Overview
- Block Diagram
SECTION 2
Functional Description
- General Purpose Interface
SECTION 3
Mapping
SECTION 4
Address Decoder Operation
- Changing the 7604 1 s Port Address
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SECTION 5
7604 Card Environmental Specification
SECTION 6
Electrical Specifications
SECTION 7
Mechanical
SECTION 8
7604 Operating Subroutine Modules
SECTION 9
Maintenance
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7604
I/O CARD
TTL INPUT/OUTPUT CARD
This card provides 8 ports of which any number can
be input or output ports or output ports with
read back (64 I/O lines total).
.
The ports are accessed at 16-pin DIP sockets on the
card.
The output lines are TTL compatible with the ability
to drive 16 low power Schottky TTL Loads each (4
TTL loads). A reset line is available· to clear all
output ports simultaneously.
The input lines are TTL compatible with an input
rating of 4 low-power Schottky loads.
The ports are configure'd as input or output ports
simply by removing the unused Ie associated with
that port. If the input buffer is retained. output port
data may be read back into the Processor.
The 7604 decodes eight address lines with provisions for expansion and memory mapping, An oncard jumper system allows users to establish the
eight consecutive port addresses occupied by the
7604,
FEATURES
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• 8 Ports conflgurable as Input or output or output
with readback
• User selectable port address (256 port field)
~ Outputs Drive 16 low-power Schottky TTL loads
~ Provision for expansion and memory mapping
, All ICts socketed
• Single +5V operation
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2.
FUNCTIONAL
The 7604 is shipped fully populated. The card is
customized (to A input and B output ports such that
A + B =8 ports) by removing the unused input buffer
or output port latch according to the following table.
PORT NO.
Port
Port
Port
Port
Port
Port
Port
Port
OUTPUT PORTS
INPUT PORTS
IC NUMBER
IC NUMBER
U17
U19
U21
U23
U16
U18
U20
U22
U9
U11
U13
U15
U8
U10
U12
U14
0
1
2
3
4
5
6
7
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Leaving the input butfer in at output ports allows the
Processor to read back the output port data to check
for noise alteration or to use the output port as a
data register.
The 7604 provides 64 alternating data and ground lines. These signal lines can be
up to 10 feet (3.0Sm) long with proper electrical considerations. When writing to
an eight bit output port the data bus data is latched in the output port. The
output data will remain latched in that state unti 1 it is written to with new data
or the SYSRESET* signal clears the port. When reading from an 8-bit input port the
of the port lines at the time of the read is transferred to the data bus.
RESET
The SYSRESET line clears all eight output ports to zero simultaneously. On,system
power-up the SYSRESET signal clears the output ports.
stat~
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GENERAL PURPOSE INTERFACE
The 7604 is usefu 1 as a gene ra 1 purpose TTL interface ca rd. Iff 1at cab 1e or tw i sted
pair discrete wire cable assemblies are used, the ground-signal-ground of the I/O
connectors mfnimizes crosstalk between inter-system signal lines in electrically noisy
environments.
DATA BUI
-5V
BUFFER
q:7K
Qr--------t---<==~
r
OUTPUT STROBE
)
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RESEr _ _ _ __
FROM
PORT·SELECT
OECOOERS
lH9UT ST-.o&. _ _- , . J t #....
FROU OTHER CIRCUITS
TYPICAL I/O CIRCUIT
FIGURE 2
74LS244
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3.
Card Address Mapping
The 7604 Card is selected by a decoded
combination of address lines A3-A7. The user
chooses the card address combination by
connecting one jumper wire each from SX and SY to
pad matrices adjacent to U3 and U4 (see diagram).
The 7604 is shipped mapped at Hex Port Address 00.
To map the 7604 anywhere in the hexadecimal
add ress range 00 to FF, change the decoder outputs
connected to SX and SY.
Port Addresses
Address lines AO. A1 and A2 select one of eight Port
addresses. One input port and one output port
reside at each address. The RO- and WR- inputs
control the input gating and output latch functions.
~
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ADDRESS DECODER OPERATION
Refer to the schematic, Document #104483.
The 7605 uses four cascaded 74LS4Z decoders (U3, U4, US and u6) to decode address
lines AO-A7. These decoders are enabled only when 10RQ* and 10EXP* are active.
Address lines AO, AI, AZ and the WR~~ signal are used to gate the select strobes
from u6 that control the output ports. Address lines AO, AI, A2 and the RD* signal
are used to gate the select strobes from U5 that control the input ports.
CHANGING THE 7604's PORT ADDRESS
Refer to the Assembly diagram, Document #104484.
Locate decoders U3 and u4 (74LS4Z) adjacent to the STD BUS edge connector.. Each
decoder device has a dual row of pads which form decoder output select matrices.
Make one (and only one) connection to each of the matrices adjacent to U3 and u4.
The decoder jumper pads numbered as shown in Figure 3 are adjacent to the decoder
chips on the 7604. Also shown are the jumpers (at XO and YO) which produce hexadecimal
port addresses 00, 01, OZthru 07, the selections made when the card is shipped.
Card Address Selection
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FIGURE 3
imAA
The I/O address mapping and jumper selection table for eight addresses per card
shows where to place jumper straps to obtain any eight sequential port addresses
in the hexadecimal range OO-FF. Using the lower of the 2-digit hexadecimal
addresses desired, find the most significant hexadecimal address digit along the
vertical axis, and the least significant hex digit on the horizontal axis. For
example, port addresses 00, ot, 02 thru 07 are obtained by connecting jumpers
at XO and YO.
o
The only restriction that applies in address selection for the 7604 is that the
lower of the eight port addresses (00 as shipped) must occur only at every eighth
possible address; for example, the sequence 01, 02, 03 thru 08 is not allowed by
the decoder.
The pad matrices adjacent to U3 and U4 are on 0.10 inch (0.25cm) centers. The
jumper wires may be conveniently replaced by wi rewrap post if frequent address
selection changes are anticipated.
MOST
SIGNIFICANT
HEX AODR£SS
LEAST SIGNIFlc.un' HEX ADDRESS
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I I 21 3 T
1
4f 5
I •I
7
JUMptA
xo
xo
0
xo
YO
1
XO
Y2
2
Xl
YO
Xl
'1'1
3
4
5
X1
'1'2
Xl
'1'3
X2
YO
X2
'1'1
X2
'1'2
x2
'1'3
•
•
Y1
'1'3
X3
yo
X3
'1'1
7
X3
'1'2
)(3
Y3
X~
YO
X~
'1'1
t
U
'1'2
X~
(3
A
xs yo
xs '1'2
x6 yo
xs
Vl
)(5
Y3
XI;
Y1
8
C
0
E
F
x6
X7
SELECTION
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Y3
YO
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I/O Address Mapping And Jumper Selection Tables For 8 Addresses Per Card
FIGURE 4
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~----~------------------
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50
7604 CARD ENVIRONMENTAL SPECIFICATIONS
R£COMMENDED OPERATINb LIM I TS
PARAMETER
MIN
Free Ai r TemperatIJre
Humidity
CD
ABSOLUTE
TY?
MAX
25
55
0
CD
J
5
95
~ON-OPERAT'N' LIMITS
MAX
UNITS
-~O
75
°c
0
95
%AH
MIN
Non-condens i n9
,. ELECTRICAL SPECIFICATIONS
7604 GENERAL PURPOSE TTL I/O CARD ELECTRICAL TEST SPECIFICATION
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RECOMMENDED OPERATING LIMITS
MNEM.
PARAMETER
ABSOLUTE NON-OPERATING LIMITS
MIN.
TYP.
MAX.
MIN.
MAX.
UNIT
Vee
Suppl,y voltage
4.75
5.00
5.25
0.0
7.00
Volt
TA
Free air temp.
0
25
5S
-40
75
°c
USER WORST CASE ELECTRICAL
CHAR~CTERISTICS
OVER RECOMMENDED TEST LIMITS
For Input Port
&
MIN
High level input vo 1tage
Low 1eve 1 input voltage
Hysteresis (VT+ - VT-)
2.0
PARAMETER
VIH
VIL
0.2
TYP
MAX
UNIT
0.7
V
V
0.4
for Input current each port 1ine represents 4 LSTIL loads
V
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PARAMETER
-&
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UNIT
0.5
V
V
* 1 LSTTL load - O.4mA
STD BUS ELECTRICAL CHARACTERISTICS OVER RECOMMENDED TEST
ll~ITS
High l~vel output voltage .&
VOH
low level output voltaQe
VOL
Each output can drive 16 lSTTl loads*
MIN
TYP
2.7
3.5
0.35
A
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MIN
PARAMETER
ICC
SUPPLY CURRENT
TYP
MAX
450
700
STO BUS INPUT LOAD
See Figure
STD BUS OUTPUT DRIVE
See Figure
UNITS
rnA
6
6
~ Input characteristics with output chip removed.
&
Output characteristics wi th input chip installed.
~ Vee = 4.5V
IOl
= 4.5V
IOH
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Vee
= 8mA
= 400).tA
0
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7.
MECHANICAL
· Meets all STO BUS general mechanical specifications
· May require one additional card slot width for ribbon
cable access to ports (connector dependent).
· Connectors use low profile l6-pin DIP plugs with heavy
duty pins. T and B Ansley Catalog No. 609-M165H or equivalent.
mmI
r
mEl
U1
74l.S244
U16
74L5273
I~
U2
74L5244
U9
74LS244
10
U17
74LS273
Ul0
74LS244
U1I
74LS2n
'0
un
74LS244
.e
U19
74LS273
10
r
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U12
C
U20
74LS244
74LS273
U13
745244
U21
L....J
10
••
~
74L5273
'0
U22
..
74LS273
UlS
74LS244
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7604 ASSEMBLY
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BIT
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1
2
3
4
5
6
7
Input/Output Port Socket
STDI7604 EDGE CONNECTOR PIN LIST
PIN NUMBER
PIN NUMBER
OUTPUT (DRIVE)
OUTPUT (DRIVE)
INPUT (LOADING)
INPUT (LOADING)
MNEMONIC
+5 VOLTS
GROUND
-5V
MNEMONIC
1
2
4
VCC
GNO
3
6
07
1
60
06
60
05
1
1
04
1
60
5
7
8
10
12
14
60
VCC +5 VOLTS
GNO GROUND
-5V
60
1
1
03
02
01
9
11
60
60
1
13
60
1
DO
1
A7
1
A6
1
1
A5
A4
A15
16
A14
18
15
17
A13
20
19
A12
22
21
All
24
23
1
A3
Al0
26
2
A2
A9
28
25
27
A8
30
29
2
2
1
AO
WR'
RO'
MEMRO'
1
32
31
34
33
1
1
A1
lORa'
MEMEX'
36
35
MCSYNC'
STATUS 0'
38
37
REFRESH"
39
41
STATUS l'
BUSRO'
40
42
INTRa'
44
43
IOEXP'
BUSAK'
INTAK'
NMIRO'
46
45
PBAESEr
48
47
CNTAl'
50
49
CLOCK'
PCI
WAITAO'
1
SYSAESer
52
51 OUT
PCO
AUX GNO
54
AUX GNQ
AUX-V
56
53
55
IN
AUX ·V
"DeSIgnates ActIve low Level logIc
Edge Connector Pin List
FIGURE
6
• Address. Data and Control Busses meet all STD
BUS general electrical specifications except AO.
A 1 and A2 which are 2 LSTTL loads each,
o
•
8.
7604 OPERATING SUBROUTINE MODULES
This section provides flow diagrams and subroutines to operate your 7604 card.
may be used intact, or used as models to construct subroutines for a specific
These
ap~lication.
The subroutines are written in 8080-fami1y assembly code and wi 11 execute on 8080,
8085, and z80 processors. The memory addresses selected are compatible with Pro-Log's
7801 (808SA) and 7803 (Z80) processor cards. The 7604 port addresses used are
the address jumper selections made when the 7604 is shipped.
To use these subroutines in systems other than those described above, the
andlor lID port addresses may require change for compatibility.
~emory
The flow diagrams presented can be easily translated into the assembly code used by
any microprocessor since they show the steps required to achieve 76d4 operation
without reference to a particular microprocessor.
The (check bits) subroutine wi 11 compare the present input port status with the
port status from the last time that the port was read.
To use the routine the HL pointer must point to a place in memory where port
status is stored. Also, the port must be read into the accumulator before
calling the routine.
o
Upon return from the routine the location that the HL pointer was previously
set wi 11 contain new port status. Plus the next four locations will contain
change status.
Uses Registers A, Hand L
1
M
M+l
H+2
M+3
M+4
I
XX
XX
XX
Old Data
xx
Bits to Zerc
XX
Bits to One
New Data
+-Location HL was set to
Changes
Memory after Return
The (set bit) routine can set a bit or bits on an output port.
load the accumulator with the bits that should be changed.
(Input chip must be installed)
To use the routine
The (clear bit) routine can clear a bit or bits on an output port.
routine load the accumulator with the bits that should be changed.
(Input chip must be installed)
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CHECK BITS
L
SAVE 8 & C
.L
LOAD B WITH
OLD DATA
1
EXCLUSIVE "OR"
OLD DATA WitH
NEW DATE
l
STORE BITS
ITHAT CHANGED
_t
"AND" OLD DATA
WITH CHANGES
~
STORE BITS THAT
TO ZERO
~ENT
.~
"ANO" OLD DATA*
WITH CHANGES
~
STORE BITS THAT
WENT TO ONE
~
RES10RE B & C
~
RETURN
)
•
SET BITS
.It
INPUT PRESENT
STATUS
, II
"OR" IN
NEW BITS
,~
OUTPUT NEW
STATUS
~iI
C
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RETURN
CCLEAR BITS
""
INPUT PRESENT
STATUS
~Ir
MASK OFF
UNWANTED BITS
OUTPUT NEW
STATUS
,If
•
RETURN
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