1
Download SECTION 10 MEMORY CONTROLLER
Transcript
Synchronous External Master TA TS BDIP Data ADDR BURST MPC555 Memory TA TS MTS TS Address Address CSx CE OE OE WE/BE W BDIP BDIP Data Data BURST BURST Note that the memory controller’s BDIP line is used as a burst_in_progress signal. Figure 10-18 Synchronous External Master Configuration For GPCM–Handled Memory Devices MPC555 USER’S MANUAL MEMORY CONTROLLER Revised 15 September 1999 MOTOROLA 10-25
