Download 6802 Kit User`s Manual - Build Your Own Microcontroller Projects

6802 Microprocessor Kit
User's Manual
Rev 1.1, October 2015
6802 MICROPROCESSOR KIT
CONTENTS
OVERVIEW...........................................................................................4
FUNCTIONAL BLOCK DIAGARM........................................................4
HARDWARE LAYOUT...........................................................................5
KEYBOARD LAYOUT............................................................................5
HARDWARE FEATURES......................................................................8
MONITOR PROGRAM FEATURES.......................................................8
MEMORY AND I/O MAPS......................................................................9
INTERRUPT and RESET VECTORS....................................................9
GETTING STARTED..............................................................................10
HOW TO ENTER PROGRAM USING HEX CODE................................12
USER REGISTERS DISPLAY................................................................13
TEST CODE RUNNING WITH SINGLE STEPPING.............................14
HOW TO FIND OFFSET BYTE..............................................................16
GPIO1 LED.............................................................................................17
CONNECTING KIT TO TERMINAL.......................................................18
DUMP MEMORY CONTENTS...............................................................21
EXPANSION BUS HEADER..................................................................22
REP KEY...............................................................................................23
10ms TICK GENERATOR....................................................................23
RS232C PORT......................................................................................24
DATA FRAME for UART COMMUNICATION......................................25
CONNECTING LCD MODULE.............................................................25
LOGIC PROBE POWER SUPPLY........................................................26
HARDWARE SCHEMATIC, BOM.........................................................27
PCB LAYOUT........................................................................................31
MONITOR PROGRAM LISTINGS.........................................................35
OVERVIEW
The 6802 Microprocessor kit is a new design single board computer using the early 1976
Motorola 6802 microprocessor. This single board computer is a basic learning tool for
programming the 6802 with low level instructions hex code. The board has hex keypad and
7-segment display for entering the instruction hex code and test it directly. Students will
learn basic of the computer hardware and software of the 6802 easily. The 6802 is software
compatible with the 6800 microprocessor. The instructions and addressing modes of 6802
microprocessor are good for learning the basic of microprocessor operations.
FUNCTIONAL BLOCK DIAGRAM
Notes
1. UART is software control for low speed asynchronous communication.
2. The kit has 8-bit LCD module interfacing bus.
3. 100Hz Tick generator is for interrupt experiment.
4. Ports for display and keypad interfacing were built with discrete logic IC chips.
5. Memory and Port decoders are made with Programmable Logic Device, PLD. 4
HARDWARE LAYOUT
RS232C connector, DB9
male
DC jack, +9VDC
GPIO1 LED, 8-bit binary
display (address is 40H)
LCD contrast adj.
20-pin Text LCD header.
Selector for 10ms tick or
IRQ key
Important Notes
1. Plugging or removing the LCD module must be done when the kit is powered off!
2. AC adapter should provide approx. +9VDC, higher voltage will cause the voltage
regulator chip becomes hot.
3. The kit has diode protection for wrong polarity of adapter jack. If the center pin is not the
positive (+), the diode will be reverse bias, preventing wrong polarity feeding to voltage
regulator.
5
KEYBOARD LAYOUT
HEX keys
Hexadecimal number 0 to F with associated user registers, flag bits and page
zero memory $00 to $06 (use with key REG)
CPU control keys
RESET
Reset the CPU, the 6802 will get reset vector from location FFFE and FFFF
USER
User key, no connection
IRQ
Make IRQ pin to logic low, used for experimenting with interrupt process
Monitor function keys
REP
Repeat the key that pressed, must be pressed together with REP key.
INS
Insert one byte to the next location, the 256 bytes will be shifted down.
DEL
Delete one byte at current display, the next 256 bytes will be moved up.
STEP
Execute user code only single instruction and return to save CPU registers
GO
Jump from monitor program to user code
-
Decrement current display address by one
+
Increment current display address by one
PC
Set current display address with user Program Counter
REG
Display user registers, flags or page zero $00 to $06 with HEX key.
6
ACCA, Accumulator A
ACCB, Accumulator B
IX, 16-bit Index register
SP, 16-bit Stack Pointer register
--HI, upper 4-bit contents of the Condition Code registers, for Half Carry Flag
and Interrupt flag
NZVC, lower 4-bit contents of the Condition Code register, for Negative,
Zero, Overflow and Carry flags.
$00, display 16-bit data location $00 (high byte) and $01 (low byte)
$02, display 16-bit data location $02 (high byte) and $03 (low byte)
$04, display 16-bit data location $04 (high byte) and $05 (low byte)
$06, display 16-bit data location $06 (high byte) and $07 (low byte)
DATA
Set entry mode of hex keys to Data field
ADDR
Set entry mode of hex keys to Address field
COPY
Copy block of memory used with key + for Start, End, Destination and with
key GO
REL
Compute relative byte, used with key + for Start, Destination and key GO
DUMP
Display 16 bytes x 16 lines memory contents by using 2400 bit/s display
terminal.
LOAD
Load Motorola S-record or Intel hex file at 2400 bit/s using serial port
MUTE
Turn beep ON/OFF
Prg
Demonstration program 00-09, program number can be selected with key + or
-. Then press key GO to run it. Available sample programs are,
00
Rotate bit with ROLA instruction
01
Binary number counting from 00 to FF
02
BCD number counting from 00 to 99
7
03
Simple clock using 10ms tick for IRQ interrupt. SW1 must select to
Tick. Key + will clear the clock.
04
Test LCD module. Display message on the LCD display. Caution!
Plugging/removing the LCD module must do when the kit was
POWER OFF!
05-09 N/A for this version. User may add it in the monitor source code.
HARDWARE FEATURES
The hardware features:
•
•
•
•
•
•
•
•
•
•
•
CPU: Motorola 6802, NMOS 8-bit Microprocessor @1MHz clock
Memory: 32kB RAM, 16kB EPROM
Memory and I/O Decoder chip: Programmable Logic Device GAL16V8D
Display: high brightness 6-digit 7-segment LED
Keyboard: 36 keys
RS232 port: software controlled UART 2400 bit/s 8n1
Debugging LED: 8-bit GPIO1 LED at location $8000
Tick: 10ms tick produced by 89C2051 for time trigger experiment
Text LCD interface: direct CPU bus interface text LCD
Brownout reset: KIA7042 reset chip for power brownout reset
Expansion header: 40-pin header
MONITOR PROGRAM FEATURES
The MONITOR program features:
•
•
•
•
•
•
•
•
•
•
•
Simple hex code entering
Insert and Delete byte
Single step running
User registers: ACCA, ACCB, IX, SP, and Condition code registers for storing
CPU status after program execution
Page zero memory display
Easy offset byte calculation for Relative addressing mode
Copy block of memory
Motorola s-record or Intel hex file downloading
Memory dump
Beep ON/OFF
Demo programs
8
MEMORY AND I/O MAPS
The first 32kB is RAM space from 0000-7FFFH. Zero page is location 00-FFH. User Stack
space is set at 7F00H. System Stack is set at 7FFFH. User space is from 200H to 7000H.
The 6802 CPU uses memory space from 8000H-BFFFH for I/O ports. Available user I/O for
lab experiment is A000H-BFFFH. The monitor ROM is located at C000H-FFFFH
Memory mapped I/O
64kB Memory
0000H
0200H
7FFFH
8000H
9000H
C000H
8000H
8001H
8002H
8003H
System RAM
User RAM
Input/Output
16kB Monitor ROM
FFFFH
GPIO1
PORT0
PORT1
PORT2
9000H LCD command WR
9001H LCD data WR
9002H LCD command RD
9003H LCD data RD
INTERRUPT and RESET VECTORS
The vectors for RESET and Interrupts are shown below.
Vector
Description
MS
LS
$FFF8
$FFF9
IRQ
$FFFA
$FFFB
Software Interrupt
$FFFC
$FFFD
NMI
$FFFE
$FFFF
RESET
Software interrupt vector is for SWI instruction. Hex code for SWI instruction is 3FH.
User can put 3FH (SWI instruction) at the end of user program. It will generate interrupt
process, return to the monitor program that saves CPU registers to user registers. We can
examine the program running easily.
NMI is reserved for Single Step running. When press STEP key, the NMI interrupt will be
generated after user instruction was executed. The service routine is the same as software
interrupt, saving CPU registers to user registers for later checking.
IRQ is prepared for user interrupt experiment. The RAM vector, 00F8H is put the IRQ
vector in ROM. CPU will jump to location 00F8H. User can place the service routine for 9
IRQ at that location! NOT THE VECTOR ITSELF! See the program example of using
IRQ in the 6802 Programming Book.
GETTING STARTED
The kit accepts DC power supply with minimum voltage +7.5V. It draws DC current
approx. 200mA. However we can use +9VDC from any AC adapter. The example of AC
adapter is shown below.
The center pin is positive.
10
If your adapter is adjustable output voltage, try with approx. +9V. Higher voltage will make
higher power loss at the voltage regulator, 7805. Dropping voltage across 7805 is approx.
+2V. To get +5VDC for the kit, we thus need DC input >+7.5V.
When power up, we will see the cold boot message 6802 running.
6802
Press RESET it will be warm boot. When RESET key has been released it will show,
6802
11
If there is no LED light up, check the adapter polarity with multimeter.
HOW TO ENTER PROGRAM USING HEX CODE
Let us try enter HEX CODE of the example program to memory and test it. We write the
program using 6802 instructions.
Address Hex code
0200
86 01
0202
B7 80 00
Label
MAIN
Instruction
comment
LDAA #1
Load register A with 1
STAA $8000
Write A to GPIO1@ 8000H
Our test program has only two instructions.
The first instruction is LDAA #1, Load Accumulator A with 8-bit constant, 1.
This instruction has two bytes hex code i.e., 86 is LDAA #n and #n is 01.
The 2nd instruction is STAA $8000. The instruction's machine code is B7. The location of
GPIO1 is 8000, 16-bit data.
The total of hex codes for this small program is 5 bytes that are, 86, 01, B7, 80, and 00.
The first byte will be entered to location 0200. And the following bytes will be entered at
0201, 0202, 0203, 0204.
Let us see how to enter these codes into the memory.
Step 1 Press key PC, the display will show current memory address and its contents.
0200 a4
Shown the location 0200 has data A4. There are small dots at the data field indicating the
active field, ready for modifying the hex contents.
Step 2 Press key 8 and key 6. The new hex code 86 will be entered to the location 0200.
0200 86
Step 3 Press key + to increment the location from 0200 to 0201. Then enter hex key 1,
0200 0 1
12
Repeat Step 3 until completed for the last location. We can verify the hex code with key +
or key -.
To change the display location, press key ADDR. The dots will move to Address field. Any
hex key pressed will change the address.
USER REGISTERS DISPLAY
Before we test the code running, let us see how to use the user registers. User registers are
the memory block in RAM that used to save the contents of CPU registers after completing
a given program running. We can examine the user registers for checking our code running
then.
Press key REG, then press key 0, it will show Accumulator A has 14.
ACCA 14
Press key 1 for Accumulator B.
ACCb 60
Press key 2 for Index register, shown IX has 16-bit data= C0EF
c0ef ix
Press key 3 for Stack Pointer register, shown SP has 16-bit data= 7F00
7F00 SP
Press key 4 for upper half 4-bit of the Condition Code Register for Half carry flag and
Interrupt flag.
1 1 0 1 CH
13
Press key 5 for lower half 4-bit of the Condition Code Register for Negative, Zero,
Overflow and Carry flags.
1 1 0 1 CL
Press key 6, the 16-bit data at location 00 and 01 will show. Shown 16-bit data, 174C.
17 is MS byte stored at address 0000.
4C is LS byte stored at address 0001.
174c 00
Similarly for key 7, 8 and 9.
16 is MS byte stored at address 0002
164a 02
4A is LS byte stored at address 0003
0C is MS byte stored at address 0004
0c82 04
82 is LS byte stored at address 0005
84 is MS byte stored at address 0006
8454 06
54 is LS byte stored at address 0007
These (user) registers will be useful for program testing. The page zero memory display,
each 16-bit will also be useful for checking Arithmetic and logical operations. We will see
the examples in the programming book.
TEST CODE RUNNING WITH SINGLE STEPPING
Now get back to the program we have just entered. Let us take a look again.
Address Hex code
0200
86 01
0202
B7 80 00
Label
MAIN
Instruction
comment
LDAA #1
Load register A with 1
STAA $8000
Write A to GPIO1@ 8000H
We will try test the program using single step running.
14
Step 1 Press key PC. We see that the location 0200 has 86.
0200 86
Step 2 Press REG key, then key 0, to check the Accumulator A.
ACCA 14
Step 3 Press PC then STEP key. The instruction LDAA #1 will be executed.
0202 b7
The display will show next instruction to be executed, that is STAA $8000.
Step 4 Let check again register A with key REG and 0. We see that now the Accumulator A
has 01.
ACCA 0 1
Step 5 Press PC then STEP, the instruction STAA $800 will be executed. The display will
show next instruction to be executed.
0205 2e
We will see the contents of Accumulator register will be stored at GPIO1 LED!
To get back key PC to the location 0200, press RESET key, then press PC.
We see that the single step running is useful for learning the operation of each instruction.
We can check the result with user registers easily.
15
HOW TO FIND OFFSET BYTE
The offset byte is signed number using two's complement. It is the distant in number of byte
length between destination address and current Program Counter. The 6802 CPU uses it for
relative addressing of the Branch instructions. The monitor program has function key for
finding the offset byte by entering the start and destination addresses.
Let us see the example, how to find the offset byte, XX from below program.
This program will increment the Accumulator A, store it to GPIO1 LED, then branch back
to loop. The BRA LOOP instruction has machine code 20. The 2nd byte is OFFSET byte.
Address Hex code
0200
4C
0201
0204
Label
LOOP
Instruction
comment
INCA
Increment Accumulator A
B7 80 00
STAA $8000
Write A to GPIO1@ 8000H
20 XX
BRA LOOP
Jump back to loop
Suppose we have entered the hex code from beginning to the location 0204. The display
will show.
0204 20
To find the offset byte, XX, Press key REL.
0204 -s
The display address will be start location. Press key +, and enter destination address, 200.
0200 -d
Press GO, the offset byte, FA or -6 will be entered to location 0205 automatically.
0205 fa
If we count by hand, we will see that the byte length will be 6 bytes backward.
We can test this program with key STEP and REP together. We will see binary incrementing
on the GPIO1 LED. The program will jump back to loop with Branch Always instruction.
16
GPIO1 LED
The 6802 kit provides a useful 8-bit binary display. It can be used to debug the program or
code running demonstration. The I/O address is 8000H. U14 is 8-bit data latch. Logic 1 at
the output will make LED lit.
The GPIO1 LED can be used to display accumulator register easily. Let us take a look the
sample code below.
Address Hex code
0200
C6 01
0202
F7 80 00
Label
MAIN
Instruction
comment
LDAB #1
Load register B with 1
STAB $8000
Write B to GPIO1@ 8000H
The test code has only two instructions. The first instruction has two bytes machine code,
C6 and 01. The second instruction has three bytes F7, 80 and 00.
Enter the hex code to memory from 0200 to 0204. Then press PC, and execute the
instruction with single step by pressing key STEP. The 2nd press STEP key that executes
instruction STAB $8000 will make the GPIO1 LED showing the contents of register B. Try
change the load value to register B and test the code.
Another example is with JUMP instruction. The JUMP instruction will change the Program
Counter to 0200, to repeat program running. Now we use instruction that increments the
Accumulator A. After incrementing, we write register A to location of GPIO1 at 8000H. And
with JMP LOOP instruction, the program will be repeated.
17
Address Hex code
0200
4C
0201
0204
Label
LOOP
Instruction
comment
INCA
Increment Accumulator A
B7 80 00
STAA $8000
Write A to GPIO1@ 8000H
7E 02 00
JMP LOOP
Jump back to loop
Again enter the hex code to memory and test it with single step. Now press key STEP and
key REP together. Every time when instruction STAA $8000 was executed, did you see the
binary number counting up?
Note the JUMP instruction has 3 bytes hex code, but the BRA instruction has only 2 bytes.
CONNECTING 6802 KIT TO TERMINAL
For LOAD key, we can connect the 6802 kit to a terminal by RS232C cross cable. You may
download free terminal program, teraterm from this URL,
http://ttssh2.sourceforge.jp/index.html.en
RS232C cross cable
VT100 Terminal
6802 Kit
The example shows connecting laptop with COM1 port to the RS232C port of the 6802 kit.
New laptop has no COM port, we may use the USB-RS232 adapter for converting the USB
port to RS232 port.
To download Motorola s-record or Intel hex file that generated from the assembler or c
compiler, set serial port speed to 2400 bit/s, 8-data bit, no parity, no flow control, one stop
bit.
Step 1 Run teraterm, then click at Serial connection.
18
Step 2 Click setup>Serial port.
19
Step 3 Set serial port speed to 2400 and format as shown below.
Step 4 Press key LOAD, then key GO. The kit will wait for the data stream from terminal.
Step 5 On PC, Click file>Send File>LED.HEX.
20
The kit will read the hex file, write to memory, when completed if no checksum error, the
display will show the current address. The kit accepts for both Motorola s-record or Intel
hex files automatically.
DUMP MEMORY CONTENTS
With terminal connection, we can use it to display the memory contents, 256 bytes easily.
The monitor command is DUMP key. When pressed, the kit will send data stream to display
the memory contents from current program counter. In addition, the ASCII code is also
decoded for each line.
21
EXPANSION BUS HEADER
JP1, 40-pin header provides CPU bus signals for expansion or I/O interfacing. Students may
learn how to make the simple I/O port, interfacing to Analog-to-Digital Converter,
interfacing to stepper motor or AC power circuits.
22
REP KEY
REP(repeat) key, S19 is one bit active low key switch connected to bit 6 of Port 0. To test
the logic of S19, we can use instruction LDAA $0000 and check bit 6 of the accumulator
with test bit instruction. REP key is used in monitor program together with key STEP, + or –
to provide automatic repeating.
10ms TICK GENERATOR
SW1 is a selector for interrupt source between key IRQ or 10ms tick produced by 89C2051
microcontroller. Tick generator is software controlled using timer0 interrupt in the 89C2051
chip. The active low tick signal is sent to P3.7. For tick running indicator, P1.7 drives D1
LED.
23
Tick is a 10ms periodic signal for triggering the 6802 IRQ pin. When select SW1 to Tick,
the 6802 CPU can be triggered by a maskable interrupt. The 100Hz tick or 10ms tick can be
used to produce tasks that executed with multiple of tick. The 6802 kit lab look will show
how to use 10ms tick to make a digital timer.
10ms
10ms
10ms
RS232C PORT
The RS232C port is for serial communication. We can use a cross cable or null MODEM
cable to connect between the kit and terminal. The connector for both sides are DB9 female.
We may build it or buying from computer stores.
For new PC or laptop computer without the RS232 port. It
has only USB port, we may have the RS232C port by
using the USB to RS232 converter.
24
DATA FRAME for UART COMMUNICATION
Serial data that communicated between kit and terminal is asynchronous format. The 6802
kit has no UART chip, instead it uses software controlled to produce bit rate of 2400 bit/s.
The data frame is composed of start bit, 8-data bit and stop bit. For our kit, period = 1/2400
= 417 microseconds.
Since bit period is provided by machine cycle delay. Thus to send/receive serial data
correctly, all interrupts must be disabled.
CONNECTING LCD MODULE
JR1 is 20-pin header for connecting the LCD module. The example shows connecting the
16x2 lines text LCD module. R12 is a current limit resistor for back-light. R13 is trimmer
POT for contrast adjustment. The LCD module is interfaced to the 6802 bus directly. The
command and data registers are located in I/O space having address from 9000H to 9003H.
Be advised that plugging or removing the LCD module must be done when the kit is
powered off.
Text LCD module accepts ASCII codes for displaying the message on screen.
Without settings the LCD by software, no characters will be displayed. The first line will be
black line by adjusting the R13 for contrast adjustment.
25
LOGIC PROBE POWER SUPPLY
The kit provides test points TP4(+5V) and TP5(GND) for using the logic probe. Students
may learn digital logic signals with logic probe easily. The important signals are RESET
(TP2) and E clock (TP3). Tick signal, however indicated by D1 LED blinking. Logic probe
can test it at P3.7 of the 89C2051 microcontroller directly. Red clip is for +5V and Black
clip for GND.
+ 5V at TP1
GND at TP1
26
HARDWARE SCHEMATIC, PARTS LIST and PCB layout
D
+5V
C16
10uF
4.7k
R15
R5
R3
R2
TEST POINT
+5V
1k
1k
1k
+5V
+
1
TP4
+5V
TP5
1
VSS
VDD
C21
1
27pF
TP2
RESET1
HALT
NMI
IRQ
+5V
VCC
5
VCC
Y1
4MHz
E
VMA
R/W
C5
0.1uF
ROM_CE
6802
BA
E
VMA
R/W
IRQ
MR
RE
RESET
NMI
HALT
EX2
27pF
C20
U16
38
X1
39
40
6
2
4
3
36
7
37
5
34
C6
0.1uF
A0
A1
A2
A3
A4
A5
A6
A7
A[0..7]
A8
A9
A10
A11
A12
A13
A14
+5V
C7
0.1uF
U1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
0xC000-0xFFFF
Monitor Program
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
20
22
1
+5V
D0
D1
D2
D3
D4
D5
D6
D7
4
D0
D1
D2
D3
D4
D5
D6
D7
A8
A9
A10
A11
A12
A13
A14
A[0..7]
A0
A1
A2
A3
A4
A5
A6
A7
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
U2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0
D1
D2
D3
D4
D5
D6
D7
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
3
E
A0
A1
TXD
12
13
14
15
16
17
18
19
U3
P3.0/RXD
P3.1/TXD
P3.2/INTO
P3.3/INT1
P3.4/T0
P3.5/T1
XTAL1
XTAL2
RST/VPP
VCC
9
U7D
AT89C2051
QA
QB
QC
QD
QE
QF
QG
QH
J1
1
2
D[0..7]
12
13
14
15
16
17
18
19
11
ROM_CE
RAM_CE
RAM_WR
2
2
Q0
Q1
Q2
Q3
TP1
1
3
4
5
6
3
Title
Size
B
Date:
+5V
R1
680
LED
D1
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
JP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
HEADER 20X2
R6
10k
1
3
C2
10uF
Q2
1
1
VMA
E
+5V
D0
D1
D2
D3
D4
D5
D6
D7
NMI
IRQ
RESET2
RESET1
R/W
A15
A14
A13
A12
D0
D1
D2
D3
D4
D5
D6
D7
TICK
10ms Tick
SW2
IRQ
of
3
VOLTAGE DIP RESET
2
KIA7045
RESET
SW3
IRQ test switch
SW1
ESP switch
2
+5V
+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
CPU expansion connector
5
TVS5V_SOD123
D2
IRQ
U7C
VCC
6
74LS14
+5V
6802 MICROPROCESSOR KIT
Document Number
<Doc>
Saturday, September 26, 2015
Sheet
Designed by Wichit Sirichote, [email protected], (C)2015
LCD_E
PORT0
PORT1
PORT2
GPIO1
TEST POINT
TICK/2
TICK
U17
D0
D1
D2
D3
DDA
DDB
CLK
ODA
ODB
RST
74LS14
CD4076B
4
U7B
RESET2
9
10
7
1
2
15
user
SW4
RESET2
RESET1
74LS14
8
E
P3.7
P1.0/AIN0
P1.1/AIN1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
DC Input
14
13
12
11
Programmable system tick
5
4
2
3
6
7
8
9
E
1
+5V
20
RESET2
U4
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
U6
A
B
CLK
CLR
U7A
1
74HC164
1
3
4
5
6
10
11
12
13
PLD decoder logic
I
I
I
I
I
I
I
I
D3
74LS14
9
8
1
2
GAL16V8D
I/CLK
I/OE
2
1k
2
1N4007
1000uF25V
+5V
2
3
4
5
6
7
8
9
BREAK
NMI
D14
+
POWER
C4
3
R14
E
R/W
A10
A11
A12
A13
A14
A15
C11
0.1uF
VIN
U8
LM2490-5.0
1
11
1
0x0000-0x7FFF 32kB
SRAM, NVRAM
RAM_CE
20
22
27
VOUT
TEST POINT
1
TP3
RAM_WR
3
A0
A1
CE
OE
WE
E
HM62256B
A[8..14]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
C10
0.1uF
27C256
35
9
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
33
32
31
30
29
28
27
26
C3
10uF 16V
C9
0.1uF
+
CE
OE
VPP
VCCSTB
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
C8
0.1uF
4
3
1
C
B
A
GND
5
GND
2
+
C1
22uF
Rev
D
C
B
A
D
C
B
A
D0
D1
D2
D3
D4
D5
D6
D7
RESET2
5
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
+
VCC
2
3
4
5
6
7
8
9
11
1
20
1
19
18
17
16
15
14
13
12
11
20
11
1
2
3
4
5
6
7
8
9
C17
10uF
VCC
VCC
U11
1D
2D
3D
4D
5D
6D
7D
8D
LE
OE
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
0x01
74HC573
U12
1D
2D
3D
4D
5D
6D
7D
8D
LE
OE
A1
A2
A3
A4
A5
A6
A7
A8
U13
74HC573
VCC
TXD
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
G1
G2
VCC
74HC541
VCC
19
18
17
16
15
14
13
12
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
20
VCC
E
G
F
A
B
C
DP
D
4
RXD
S19
PC7 SPEAKER
PA0
PA1
PA2
PA3
PA4
PA5
PA6
C18
100nF
4
PC0
PC1
PC2
PC3
PC4
PC5
PC6
A
B
C
D
E
F
G
DP
14
16
13
3
5
11
15
7
U9
A
B
C
D
E
F
G
DP
LTC-4727JR
PC5
PC4
PC3
PC2
PC1
PC0
S1
S7
S13
S20
S26
S30
BREAK
3
S2
S8
S14
S21
S27
S31
3
S3
S9
S15
S22
S28
S32
2
14
16
13
3
5
11
15
7
U10
A
B
C
D
E
F
G
DP
S6
A
B
C
D
E
F
G
DP
S5
S12
4
S4
S11
S18
L1L2L3
LTC-4727JR
S10
S17
S25
R7
C
VCC
1
R9
330
VCC
R8
4.7k
D4
1
C
R11
10
R10
Q1
BC327
7-segment test
2
10k RESISTOR SIP 9
2
3
4
5
6
7
8
9
TONE
PA0
PA1
PA2
PA3
PA4
PA5
PA6
6802 MICROPROCESSOR KIT
Document Number
<Doc>
Saturday, September 26, 2015
1
Sheet
2
J2
4
CON3
1
2
3
L1L2L3
LS1
VCC
SPEAKER
+5V
1
of
3
Designed by Wichit Sirichote, [email protected], (C) 2015
Date:
Size
B
Title
SPEAKER
10k RESISTOR SIP 9
PC0
2
PC1
3
PC2
4
PC3
5
PC4
6
PC5
7
8
9
S16
S24
S33
S29
S23
2
DIGIT4
8
D0
D1
D2
D3
D4
D5
D6
D7
PORT2
PORT1
PORT0
+5V
5
1
3
DIGIT3
6
DIGIT2
2
DIGIT1
1
DIGIT4
8
DIGIT3
6
DIGIT2
2
DIGIT1
1
Rev
1
D
C
B
A
10
+5V
1
D0
D1
D2
D3
D4
D5
D6
D7
R13
10K
A1
A0
3
VCC
LCD_E
2
3
4
5
6
7
8
9
11
1
20
A1
VCC
U14
1D
2D
3D
4D
5D
6D
7D
8D
LE
OE
VCC
74HC573
A0
4
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
+5V
19
18
17
16
15
14
13
12
D5
D6
LED
D7
D8
D9
3
1N5236A
D13
LED
D10
8-bit Binary display LED x8
VB1
3
D11
+5V
D12
14
7
13
8
6
2
10uF 10V
C12
C14
10uF
SUB-D 9, Male (cross cable)
5
9
4
8
3
7
2
6
1
+
5
D0
D1
D2
D3
D4
D5
D6
D7
GPIO1
R12
D7
D6
D5
D4
D3
D2
D1
D0
R/W
RS
+5V
VCC
+
D0
D1
D2
D3
D4
D5
D6
D7
RESET2
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16x2 text LCD interface
JR1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CONN RECT 16
+5V
VCC
4
U15
V+
V-
T1OUT
T2OUT
R1IN
R2IN
MAX232A
C+
C1C2+
C2T1IN
T2IN
R1OUT
R2OUT
+5V
10uF
1
3
4
5
11
10
12
9
C19
100nF
C13
+
D
C
B
A
5
2
2
C15
10uF
2
RXD
TXD
Title
Size
B
6802 MICROPROCESSOR KIT
Document Number
<Doc>
Saturday, September 26, 2015
1
1
Sheet
3
of
3
Designed by Wichit Sirichote, [email protected], (C)2015
Date:
Rev
1
D
C
B
A
+
PARTS LIST
Semiconductors
U1
27C256, 32kB EPROM
U2
HM62256B, 32kB SRAM
U3
AT89C2051, 2kB Microcontroller
U4
GAL16V8D, PLD
U6
74HC164, shift register
U7
74LS14, hex inverter
U8
LM7805, voltage reguator
U10,U9 LTC-4727JR, common cathode LED
U11,U12,U14 74HC573, 8-bit Latch
U13 74HC541, tri-state buffer
U15 MAX232A, RS232 level converter
U16 6802 Motorola 8-bit Microprocessor
U17 CD4076B, D-FF
D2
TVS5V_SOD123
D3
1N4007, rectifier diode
D4
TONE, LED
D13 1N5236A, zener diode
Q1
BC327, PNP transistor
Q2
KIA7045, reset chip
Resistors (all resistors are 1/8W +/-5%)
R1 680
R2,R3,R5 1k
R8,R4 4.7k
R13,R6 10k
R11,R7 10k RESISTOR SIP 9
R9 330
R12,R10 10
Capacitors
C1 22uF electrolytic
C2,C13,C14,C15,C16,C17 10uF electrolytic
C3 10uF 16V electrolytic
C4 1000uF25V electrolytic
C5,C6,C7,C8,C9 0.1uF disc ceramic
C10,C11 0.1uF disc ceramic
C12 10uF 10V electrolytic
C19,C18 100nF disc ceramic
Additional parts
JJP1 HEADER 20X2
JR1 CONN RECT 16 text LCD connector
J1 DC Input
J2 CON3 3-pin header
LS1 SPEAKER
SW1 ESP switch
SW2 IRQ
SW3 RESET
SW4 user
S1,S2,S3,S4,S5,S6,S7,S8,
S9,S10,S11,S12,S13,S14,Tact switch
S15,S16,S17,S18,S19,S20,
S21,S22,S23,S24,S25,S26,
S27,S28,S29,S30,S31,S32,
S33
TP1,TP2,TP3 TEST POINT
TP4 +5V
TP5 GND
VB1 SUB-D 9, Male (cross cable)
Y1
4MHz Xtal
PCB double side plate through hole
LED cover Clear RED color acrylic plastic
Keyboard sticker printable SVG file
MONITOR PROGRAM LISTINGS
MON68.LST
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
2/11/2558 17:06
;
;
;
;
;
MONITOR PROGRAM FOR 6802 MICROPROCESSOR KIT
(C) COPYRIGHT 2015 BY WICHIT SIRICHOTE
Source code was translated by tasm assembler with command
d:>tasm -68 mon68.asm mon68.hex
; 12 September 2015 fix 16-bit variable allocation
;
HIGH BYTE DISPLAY
;
LOW BYTE DISPLAY+1
; 13 September 2015 test single step with 74LS164
;
8th clock will make NMI low!
;
The number of clock must be 7 after the break signal
;
has been set. So the 8th clock will make NMI low
;
User instruction will be fetched and executed at the
;
Add key INS and DEL
; 14 September 2015 provide RAM vector for IRQ at location 00F8H
;
CPU will jump to 00F8H if IRQ was triggered and Interrupt
;
mask has been cleared.
; 16 September 2015 Testing single step with 4076
;
add 4-bit D-FF 4076 to provide 4-bit shifting
;
use with RTI 10 cycles to make NMI service
; 17 September 2015 Add register display, page zero display
; 18 September 2015 test software UART at 2400 Hz, found half bit 1207
;
or 2414Hz, % error = 0.6%
;
test receive hex file
; 19 September 2015 add LCD drivers to monitor program
;
begin test monitor code in RAM @4000h
; 20 September 2015 add Motorola S record for hex file download command
;
tested with tasm -68 -g2 led.asm
; 21 September 2015 fix s-record lodaing, check number of byte include
;
s-record loading was tested with tasm -g2 option
;
add key mute for beep on/off
;
prepare to backup the source code!
; 23 September 2015 add cold/warm boot setup
; 25 September 2015 add function copy block of memory and cold message
;
add hex dump function for displaying hex contents
;
on 2400 terminal
; 28 Spetember 2015 fix rep key bouncing! when pressed together with key
;
fix ASCII printing with key DUMP
; address of the I/O ports
GPIO1
PORT0
PORT1
PORT2
.EQU
.EQU
.EQU
.EQU
DIGIT
SEG7
KIN
.EQU 8002H
.EQU 8003H
.EQU 8001H
ONE
ZERO
.EQU 30H
.EQU 0BDH
BUSY
8000H
8001H
8002H
8003H
.EQU 80H
; below LCD's registers are mapped into memory space
command_write
data_write
.EQU 9000H
.EQU 9001H
Page 1 of 40
MON68.LST
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0000
0000
0000
0000
0000
0000
0000
0000
0000
0080
0080
0080
0080
0081
0082
0083
0084
0086
0088
0089
0089
008A
008C
0092
0093
0093
0093
0093
0094
0095
0096
0096
0098
0098
009A
009B
009C
009E
00A0
00A1
00A3
00A3
00A5
00A7
00A9
00A9
00AB
00AB
00AD
00AD
00AE
00AE
00B0
00B2
00B2
00B4
00B4
00B6
00C6
00C7
00C9
00CA
00CB
00CC
00CC
00CC
00CD
00CE
00CF
00D0
00D1
00D1
00D2
00D3
00D3
00D3
2/11/2558 17:06
command_read
data_read
.EQU 9002H
.EQU 9003H
; page zero register definition
; LOCATION $00 TO $7F ARE 128 BYTES FOR USER PROGRAM USE
.DSEG
.ORG 80H
; zero page memory definitions for monitor use
REG_E
.BLOCK 1
REG_D
.BLOCK 1
REG_B
.BLOCK 1
REG_C
.BLOCK 1
HL
.BLOCK 2
; 84H = L 85H = H
DE
.BLOCK 2
REG_A
.BLOCK 1
_ERROR
BCC
BUFFER
INVALID
.BLOCK
.BLOCK
.BLOCK
.BLOCK
1
2
6
1
; ERROR FLAG FOR INTEL HEX FILE DOWNLOADING
; BYTE CHECK SUM
; 8BH - 90H PAGE ZERO DISPLAY BUFFER
; INVALID KEY HAS BEEN PRESSED FLAG BIT
; 0 VALID
; 1 INVALID
KEY
.BLOCK 1
STATE
.BLOCK 1
ZERO_FLAG .BLOCK 1
; ZERO WHEN HEX KEY PRESSED FOR ADDRESS OR
DISPLAY .BLOCK 2
USER_PC
USER_A
USER_B
USER_IX
USER_SP
USER_P
SAVE_SP
; display address
.BLOCK 2
.BLOCK 1
.BLOCK 1
.BLOCK 2
.BLOCK 2
.BLOCK 1
.BLOCK 2
; FOR SAVING CURRENT PC, ON RESET, IT SETS TO
; USER STACK POINTER
; PROGRAM STATUS REGISTER
; SAVE SYSTEM STACK
START_ADDRESS .BLOCK 2
DESTINATION .BLOCK 2
OFFSET_BYTE .BLOCK 2
; FOR OFFSET BYTE CALCULATION
; OFFSET BYTE = DESTINATION - START_ADDRESS
END_ADDRESS .BLOCK 2
COLD
; FOR COPY MEMORY FUNCTION
.BLOCK 2
; COLD BOOT OR WARM BOOT
REPDELAY .BLOCK 1
DEBUG
TEMP16
.BLOCK 2
.BLOCK 2
IX2
.BLOCK 2
; FOR PROGRAM DEBUGGING
; REGISTER 16 BITS
OFFSET
.BLOCK 2
BIN2SEG .BLOCK 16
BEEP_FREQ .BLOCK 1
BEEP_PERIOD .BLOCK 2
DEMO_NO
.BLOCK 1
MUTE
.BLOCK 1
BIT1_COUNTER .BLOCK 1
;
;
;
;
;
;
;
SEC100
SEC
MIN
HOUR
RUNSTOP
.BLOCK
.BLOCK
.BLOCK
.BLOCK
.BLOCK
; VARIABLES FOR CLOCK PROGRAM
K
J
.BLOCK 1
.BLOCK 1
1
1
1
1
1
FOR X INDEXT REGISTER USE
TABLE FOR 4-BIT BINARY TO 7-SEGMENT PATTERN
STORE BEEP FREQUENCY
STORE BEEP PERIOD LOAD WITH IX
FOR DEMO 0-9
TOGGLE MUTE FOR BEEP ON/OFF 0=BEEP ON
COUNTER FOR BIT 1 TEST
; GENERAL PURPOSE REGISTERS
Page 2 of 40
MON68.LST
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
00D3
00D3
00D3
C000
C000
C000
C000
C000
C000
C002
C005
C007
C00A
C00A
C00A
C00A
C00A
C00D
C00E
C010
C010
C010
C013
C013
C016
C018
C018
C018
C01A
C01C
C01E
C020
C020
C020
C020
C022
C024
C026
C028
C02A
C02C
C02E
C030
C030
C030
C032
C034
C036
C036
C038
C03A
C03C
C03E
C040
C042
C042
C043
C045
C045
C045
C047
C049
C04B
C04D
C04D
C04D
C050
C052
C052
C054
C056
C056
C058
C05A
C05A
C05C
2/11/2558 17:06
.CSEG
.ORG 0C000H
;
86
B7
86
B7
BF
80 02
00
80 00
START
; START ADDRESS FOR ROM
.ORG 4000H
LDAA
STAA
LDAA
STAA
; TEST IN RAM
#$BF
PORT1
#0
GPIO1
; DISABLE NMI BREAK SIGNAL
; TEST DISPLAY
; power up delay
CE 01 2C
09
26 FD
LDX #300
POWER_UP_DELAY DEX
BNE POWER_UP_DELAY
8E 7F FF
LDS #$7FFF
CE 7F 00
DF 9E
LDX #$7F00
STX USER_SP
86
97
97
97
00
8C
8D
92
; SYSTEM STACK
; STORE USER STACK
LDAA #0
STAA BUFFER
STAA BUFFER+1
STAA INVALID
; CLEAR INVALID FLAG
; INSERT 6502 TEXT
86
97
86
97
86
97
86
97
AF
91
BF
90
BD
8F
9B
8E
LDAA #0AFH
STAA BUFFER+5
LDAA #0BFH
STAA BUFFER+4
LDAA #0BDH
STAA BUFFER+3
LDAA #9BH
STAA BUFFER+2
86 00
97 94
97 95
LDAA #0
86
97
97
86
97
97
LDAA #02
STAA DISPLAY
STAA USER_PC
LDAA #0
STAA DISPLAY+1
STAA USER_PC+1
02
96
98
00
97
99
07
97 A0
96
97
96
97
96
84
97
85
STAA STATE
STAA ZERO_FLAG
; INITIAL STATE
TPA
STAA USER_P
LDAA DISPLAY
STAA HL
LDAA DISPLAY+1
STAA HL+1
CE 00 35
97 C7
LDX #35H
STAA BEEP_PERIOD
86 52
97 C6
LDAA #52H
STAA BEEP_FREQ
86 00
97 C9
LDAA #0
STAA DEMO_NO
DE AB
8C AA 55
LDX COLD
CPX #0AA55H
Page 3 of 40
MON68.LST
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
0239
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
0250
0251
0252
0253
0254
0255
0256
0257
0258
0259
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
C05F
C061
C061
C061
C061
C064
C066
C066
C068
C06A
C06A
C06C
C06F
C06F
C06F
C072
C072
C075
C075
C075
C076
C079
C079
C079
C079
C079
C079
C079
C079
C079
C079
C079
C07C
C07C
C07C
C07C
C07C
C07C
C07C
C07E
C07F
C081
C082
C082
C082
C082
C084
C085
C087
C088
C088
C088
C088
C088
C08A
C08A
C08C
C08F
C091
C091
C093
C095
C095
C097
C099
C09B
C09B
C09D
C0A0
C0A0
C0A2
C0A2
C0A2
C0A4
C0A7
C0A9
2/11/2558 17:06
27 18
BEQ SKIP_COLD
; COLD START
CE AA 55
DF AB
LDX #0AA55H
STX COLD
86 00
97 CA
LDAA #0
STAA MUTE
86 FF
B7 80 00
LDAA #0FFH
STAA GPIO1
BD C9 AD
JSR BEEP
BD CB 43
JSR DISPLAY_START_MSG
4F
B7 80 00
CLRA
STAA GPIO1
; BEEP IS ON
SKIP_COLD
;
;
7E C9 A2
LDX #TEXT3
JSR PSTR
; PRINT TEXT3 TESTING 2400 TERMINAL
JMP MAIN
;----------------------- 2400 BIT/S SOFTWARE UART --------------------------; one bit delay for 2400 bit/s UART
C6 3D
5A
26 FD
39
BIT_DELAY LDAB #61
LOOP
DECB
BNE LOOP
RTS
; 1207 TESTED WITH 55H @1MHz (4MHz xtal)
; 1.5 bit delay
C6 5C
5A
26 FD
39
BIT1_5_DELAY LDAB #92
LOOP1
DECB
BNE LOOP1
RTS
; DELAY 1.5 BIT
; SEND ASCII LETTER TO TERMINAL
; ENTRY: A
97 80
SEND_BYTE: STAA REG_E
; SAVE ACCUMULATOR
86 3F
B7 80 02
8D EB
LDAA #3FH
; start bit is zero
STAA PORT1
BSR BIT_DELAY
; delay one bit
86 08
97 81
LDAA #8
STAA REG_D
96 80
84 01
27 07
86 BF
B7 80 02
20 07
86 3F
B7 80 02
20 00
; 8-data bit wil be sent
CHK_BIT:
LDAA REG_E
ANDA #1
BEQ SEND_ZERO
LDAA #0BFH
STAA PORT1
BRA NEXT_BIT
SEND_ZERO: LDAA #3FH
STAA PORT1
BRA NEXT_BIT
Page 4 of 40
MON68.LST
0305
0306
0307
0308
0309
0310
0311
0312
0313
0314
0315
0316
0317
0318
0319
0320
0321
0322
0323
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334
0335
0336
0337
0338
0339
0340
0341
0342
0343
0344
0345
0346
0347
0348
0349
0350
0351
0352
0353
0354
0355
0356
0357
0358
0359
0360
0361
0362
0363
0364
0365
0366
0367
0368
0369
0370
0371
0372
0373
0374
0375
0376
0377
0378
0379
0380
C0A9
C0AB
C0AB
C0AE
C0B1
C0B3
C0B3
C0B5
C0B8
C0BA
C0BA
C0BB
C0BB
C0BB
C0BB
C0BB
C0BB
C0BB
C0BE
C0C0
C0C2
C0C2
C0C4
C0C4
C0C6
C0C8
C0CA
C0CC
C0CC
C0CC
C0CC
C0CF
C0D1
C0D3
C0D3
C0D5
C0D7
C0D9
C0DB
C0DB
C0DD
C0DF
C0E1
C0E3
C0E3
C0E5
C0E5
C0E8
C0E8
C0EB
C0ED
C0ED
C0EF
C0EF
C0F1
C0F1
C0F2
C0F2
C0F2
C0F2
C0F2
C0F2
C0F2
C0F2
C0F2
C0F2
C0F2
C0F4
C0F7
C0F9
C0FC
C0FD
C0FD
C0FD
C0FD
C0FD
2/11/2558 17:06
8D D1
NEXT_BIT:
BSR BIT_DELAY
74 00 80
7A 00 81
26 E2
LSR REG_E
DEC REG_D
BNE CHK_BIT
86 BF
B7 80 02
8D C2
LDAA #0BFH
STAA PORT1
BSR BIT_DELAY
39
RTS
; RECEIVE BYTE FROM 2400 BIT/S TERMINAL
; EXIT: A
B6 80 01
84 80
26 F9
CIN
LDAA PORT0
ANDA #80H
BNE CIN
8D BE
86
97
86
97
07
81
00
80
B6 80 01
84 80
26 08
BSR BIT1_5_DELAY
LDAA
STAA
LDAA
STAA
#7
REG_D
#0
REG_E
CHK_BIT_RX
LDAA PORT0
ANDA #80H
BNE BIT_IS_ONE
96
84
97
20
80
7F
80
08
LDAA REG_E
ANDA #7FH
STAA REG_E
BRA NEXT_BIT_RX
96
8A
97
20
80
80
80
00
BIT_IS_ONE LDAA REG_E
ORAA #80H
STAA REG_E
BRA NEXT_BIT_RX
8D 97
NEXT_BIT_RX
BSR BIT_DELAY
74 00 80
LSR REG_E
7A 00 81
26 DF
DEC REG_D
BNE CHK_BIT_RX
8D 8D
BSR BIT_DELAY
96 80
LDAA REG_E
39
RTS
CR
LF
EOS
; CENTER OF STOP BIT
.EQU 0DH
.EQU 0AH
.EQU 0
;NEW LINE
; PRINT CR, LF
86
BD
86
BD
39
0D
C0 88
0A
C0 88
NEW_LINE
LDAA #0DH
JSR SEND_BYTE
LDAA #0AH
JSR SEND_BYTE
RTS
; WRITE NIBBLE TO TERMINAL
84 0F
OUT1X
ANDA #0FH
Page 5 of 40
MON68.LST
0381
0382
0383
0384
0385
0386
0387
0388
0389
0390
0391
0392
0393
0394
0395
0396
0397
0398
0399
0400
0401
0402
0403
0404
0405
0406
0407
0408
0409
0410
0411
0412
0413
0414
0415
0416
0417
0418
0419
0420
0421
0422
0423
0424
0425
0426
0427
0428
0429
0430
0431
0432
0433
0434
0435
0436
0437
0438
0439
0440
0441
0442
0443
0444
0445
0446
0447
0448
0449
0450
0451
0452
0453
0454
0455
0456
C0FF
C0FF
C101
C103
C105
C107
C10A
C10B
C10B
C10B
C10C
C10C
C10D
C10E
C10F
C110
C110
C110
C110
C113
C114
C117
C118
C118
C118
C118
C11A
C11C
C11C
C11C
C11F
C121
C123
C123
C125
C127
C127
C129
C12C
C12E
C131
C131
C133
C136
C138
C13B
C13B
C13B
C13D
C13D
C13F
C13F
C142
C142
C144
C147
C147
C149
C14A
C14C
C14C
C14F
C14F
C151
C151
C151
C151
C151
C151
C153
C155
C155
C157
C157
C159
C159
2/11/2558 17:06
8B
81
2D
8B
BD
39
30
3A
02
07
C0 88
36
OUT1X1
RTS
OUT2X
ADDA #30H
CMPA #3AH
BLT OUT1X1
ADDA #7
JSR SEND_BYTE
PSHA
44
44
44
44
LSRA
LSRA
LSRA
LSRA
;
BD C0 FD
32
BD C0 FD
39
STAA GPIO1
JSR OUT1X
PULA
JSR OUT1X
RTS
; PRINT LINE OF MEMORY POINTED TO HL
86 10
97 D2
PRINT_LINE
LDAA #16
STAA J
PRINT_LINE1
BD C0 F2
86 10
97 83
JSR NEW_LINE
LDAA #16
STAA REG_C
DE 84
DF B0
LDX HL
STX TEMP16
; FOR ASCII PRINTING
96
BD
96
BD
84
C1 0B
85
C1 0B
LDAA HL
JSR OUT2X
LDAA HL+1
JSR OUT2X
86
BD
86
BD
3A
C0 88
20
C0 88
LDAA #':'
JSR SEND_BYTE
LDAA #' '
JSR SEND_BYTE
DE 84
PRINT_LINE2
A6 00
LDX HL
LDAA 0,X
BD C1 0B
JSR OUT2X
86 20
BD C0 88
LDAA #' '
JSR SEND_BYTE
DE 84
08
DF 84
7A 00 83
26 EA
LDX HL
INX
STX HL
DEC REG_C
BNE PRINT_LINE2
;----------------------------------; PRINT ASCII CODE
86 10
97 83
LDAA #16
STAA REG_C
PRINT_IT1
DE B0
LDX TEMP16
A6 00
LDAA 0,X
81 20
CMPA #20H
Page 6 of 40
MON68.LST
0457
0458
0459
0460
0461
0462
0463
0464
0465
0466
0467
0468
0469
0470
0471
0472
0473
0474
0475
0476
0477
0478
0479
0480
0481
0482
0483
0484
0485
0486
0487
0488
0489
0490
0491
0492
0493
0494
0495
0496
0497
0498
0499
0500
0501
0502
0503
0504
0505
0506
0507
0508
0509
0510
0511
0512
0513
0514
0515
0516
0517
0518
0519
0520
0521
0522
0523
0524
0525
0526
0527
0528
0529
0530
0531
0532
C15B
C15D
C15D
C15F
C15F
C162
C162
C164
C165
C167
C167
C16A
C16C
C16C
C16C
C16C
C16F
C171
C171
C171
C172
C172
C172
C174
C176
C176
C176
C178
C17A
C17A
C17D
C17D
C180
C180
C182
C184
C187
C187
C188
C188
C188
C188
C188
C188
C188
C188
C188
C18A
C18D
C190
C193
C195
C195
C198
C199
C19B
C19C
C19C
C19C
C19C
C19C
C19C
C19C
C19C
C19C
C19C
C19F
C19F
C1A1
C1A1
C1A3
C1A5
C1A5
C1A7
C1A9
C1AB
2/11/2558 17:06
2C 02
BGE
86 2E
LDAA #'.'
BD C0 88
PRINT_IT
PRINT_IT
JSR SEND_BYTE
DE B0
08
DF B0
LDX TEMP16
INX
STX TEMP16
7A 00 83
26 E9
DEC REG_C
BNE PRINT_IT1
;---------------------------------
7A 00 D2
26 AB
DEC J
BNE PRINT_LINE1
39
RTS
86 FF
97 CA
KEY_DUMP
LDAA #$FF
STAA MUTE
DE 96
DF 84
LDX DISPLAY
STX HL
BD C1 18
JSR PRINT_LINE
BD C0 F2
JSR NEW_LINE
DE 84
DF 96
BD C4 06
LDX HL
STX DISPLAY
JSR STILL_DATA
39
RTS
;TURN BEEP OFF
;------------------------------SOFTWARE UART -----------------------96
B7
BD
7C
20
00
80 00
C1 95
00 00
F3
CE 27 10
09
26 FD
39
LOOP2
LDAA $0
STAA GPIO1
JSR DELAY
INC $0
BRA LOOP2
DELAY
DELAY1
LDX #10000
DEX
BNE DELAY1
RTS
; CONVERT LOW NIBBLE IN ACCUMULATOR TO 7-SEGMENT PATTERN
; ENTRY: A
; EXIT: A
NIBBLE_7SEG
CE CB FB
LDX
#SEGTAB
DF B0
STX
TEMP16
9B B1
97 B1
ADDA TEMP16+1
STAA TEMP16+1
86 00
99 B0
97 B0
LDAA #0
ADCA TEMP16
STAA TEMP16
Page 7 of 40
MON68.LST
0533
0534
0535
0536
0537
0538
0539
0540
0541
0542
0543
0544
0545
0546
0547
0548
0549
0550
0551
0552
0553
0554
0555
0556
0557
0558
0559
0560
0561
0562
0563
0564
0565
0566
0567
0568
0569
0570
0571
0572
0573
0574
0575
0576
0577
0578
0579
0580
0581
0582
0583
0584
0585
0586
0587
0588
0589
0590
0591
0592
0593
0594
0595
0596
0597
0598
0599
0600
0601
0602
0603
0604
0605
0606
0607
0608
C1AB
C1AD
C1AD
C1AF
C1AF
C1B0
C1B0
C1B0
C1B0
C1B0
C1B0
C1B1
C1B1
C1B3
C1B6
C1B8
C1B8
C1B9
C1B9
C1BA
C1BB
C1BC
C1BD
C1BD
C1C0
C1C2
C1C2
C1C3
C1C3
C1C3
C1C3
C1C3
C1C3
C1C4
C1C7
C1C9
C1CB
C1CD
C1CF
C1D0
C1D1
C1D1
C1D1
C1D1
C1D1
C1D1
C1D1
C1D3
C1D6
C1D8
C1DA
C1DC
C1DE
C1E0
C1E3
C1E5
C1E7
C1E9
C1EB
C1EC
C1EC
C1EC
C1EC
C1EC
C1EC
C1EC
C1EE
C1F0
C1F2
C1F4
C1F6
C1F6
C1F7
C1F7
C1F7
C1F7
2/11/2558 17:06
DE B0
LDX TEMP16
A6 00
LDAA
39
RTS
0,X
; GET 7-SEGMENT PATTERN
; CONVERT BYTE TO 7-SEGMENT PATTERN
; ENTRY: A
; EXIT: DE
36
BYTE_7SEG
84 0F
BD C1 9C
97 86
PSHA
ANDA #0FH
JSR NIBBLE_7SEG
STAA DE
32
PULA
44
44
44
44
LSRA
LSRA
LSRA
LSRA
BD C1 9C
97 87
JSR NIBBLE_7SEG
STAA DE+1
39
RTS
; CONVERT BYTE TO 7-SEGMENT PATTERN AND SAVE TO DISPLAY BUFFER DATA FIELD
; ENTRY: A
36
BD
96
97
96
97
32
39
C1 B0
86
8C
87
8D
DATA_DISPLAY PSHA
; SAVE ACCUMULATOR
JSR BYTE_7SEG
LDAA DE
STAA BUFFER
LDAA DE+1
STAA BUFFER+1
PULA
RTS
; CONVERT 16-BIT ADDRESS IN HL AND SAVE IT TO ADDRESS FILED DISPLAY BUFFER
; ENTRY: HL
ADDRESS_DISPLAY
96
BD
96
97
96
97
96
BD
96
97
96
97
39
84
C1 B0
86
90
87
91
85
C1 B0
86
8E
87
8F
LDAA HL
JSR BYTE_7SEG
LDAA DE
STAA BUFFER+4
LDAA DE+1
STAA BUFFER+5
LDAA HL+1
JSR BYTE_7SEG
LDAA DE
STAA BUFFER+2
LDAA DE+1
STAA BUFFER+3
RTS
; CONVERT ASCII TO HEX
; ENTRY: A
TO_HEX
80
81
2D
84
80
39
30
10
04
DF
07
SUBA #30H
CMPA #10H
BLT ZERO_NINE
ANDA #11011111B
SUBA #7
ZERO_NINE
RTS
; CONVERT TWO ASCII LETTERS
; EXIT: A
Page 8 of 40
TO SINGLE BYTE
MON68.LST
0609
0610
0611
0612
0613
0614
0615
0616
0617
0618
0619
0620
0621
0622
0623
0624
0625
0626
0627
0628
0629
0630
0631
0632
0633
0634
0635
0636
0637
0638
0639
0640
0641
0642
0643
0644
0645
0646
0647
0648
0649
0650
0651
0652
0653
0654
0655
0656
0657
0658
0659
0660
0661
0662
0663
0664
0665
0666
0667
0668
0669
0670
0671
0672
0673
0674
0675
0676
0677
0678
0679
0680
0681
0682
0683
0684
C1F7
C1FA
C1FD
C1FE
C1FF
C200
C201
C201
C204
C204
C206
C206
C209
C20C
C20E
C20E
C20F
C20F
C20F
C211
C213
C214
C214
C214
C214
C214
C214
C214
C214
C214
C216
C218
C218
C21B
C21D
C21F
C21F
C221
C223
C223
C226
C226
C226
C226
C226
C228
C22A
C22A
C22D
C22F
C22F
C232
C232
C235
C237
C237
C23A
C23A
C23D
C23F
C23F
C242
C242
C245
C245
C247
C247
C249
C249
C24C
C24E
C250
C250
C253
C253
C255
2/11/2558 17:06
BD C0 BB
BD C1 EC
48
48
48
48
GET_HEX
JSR CIN
JSR TO_HEX
ASLA
ASLA
ASLA
ASLA
B7 80 00
STAA GPIO1
97 88
STAA REG_A
BD C0 BB
BD C1 EC
9A 88
JSR CIN
JSR TO_HEX
ORAA REG_A
39
RTS
9B 8A
97 8A
39
ADD_BCC
ADDA BCC
STAA BCC
RTS
; get hex file for both Intel and Motorola s record automatically
;
; GET_RECORD READS INTEL HEX FILE AND SAVE TO MEMORY
86 00
97 89
GET_RECORD LDAA #0
STAA _ERROR
BD C0 BB
81 3A
27 07
GET_RECORD1 JSR CIN
CMPA #':'
BEQ GET_RECORD2
81 53
26 F5
CMPA #'S'
BNE GET_RECORD1
7E C2 92
JMP GET_S_RECORD2
; if it was Motorola s record
GET_RECORD2
86 00
97 8A
LDAA #0
STAA BCC
BD C1 F7
97 83
JSR GET_HEX
STAA REG_C
BD C2 0F
JSR ADD_BCC
BD C1 F7
97 84
JSR GET_HEX
STAA HL
BD C2 0F
JSR ADD_BCC
BD C1 F7
97 85
JSR GET_HEX
STAA HL+1
BD C2 0F
JSR ADD_BCC
BD C1 F7
JSR GET_HEX
; GET NUMBER OF BYTE
81 00
CMPA #0
27 14
BEQ DATA_RECORD
BD C0 BB
81 0D
26 F9
; GET LOAD ADDRESS
WAIT_CR
JSR CIN
CMPA #0DH
BNE WAIT_CR
B7 80 00
STAA GPIO1
96 89
81 01
LDAA _ERROR
CMPA #1
Page 9 of 40
MON68.LST
0685
0686
0687
0688
0689
0690
0691
0692
0693
0694
0695
0696
0697
0698
0699
0700
0701
0702
0703
0704
0705
0706
0707
0708
0709
0710
0711
0712
0713
0714
0715
0716
0717
0718
0719
0720
0721
0722
0723
0724
0725
0726
0727
0728
0729
0730
0731
0732
0733
0734
0735
0736
0737
0738
0739
0740
0741
0742
0743
0744
0745
0746
0747
0748
0749
0750
0751
0752
0753
0754
0755
0756
0757
0758
0759
0760
C257
C259
C259
C259
C259
C259
C25C
C25C
C25C
C25D
C25D
C25D
C25D
C260
C262
C264
C264
C267
C267
C26A
C26A
C26B
C26D
C26D
C270
C272
C272
C274
C276
C277
C277
C279
C279
C279
C27C
C27C
C27E
C280
C280
C282
C284
C284
C284
C284
C284
C287
C287
C287
C287
C287
C287
C287
C287
C287
C287
C287
C287
C287
C287
C287
C289
C28B
C28B
C28B
C28B
C28B
C28B
C28E
C290
C292
C292
C292
C292
C295
C297
C299
2/11/2558 17:06
26 03
BNE NOERROR
; SHOW ERROR ON LED
; JSR OUT_OFF_RANGE
B7 80 00
STAA GPIO1
NOERROR
39
RTS
DATA_RECORD
BD C1 F7
DE 84
A7 00
JSR GET_HEX
LDX HL
STAA 0,X
BD C2 0F
JSR ADD_BCC
B7 80 00
STAA GPIO1
08
DF 84
; WRITE TO MEMORY
INX
STX HL
7A 00 83
26 EB
DEC REG_C
BNE DATA_RECORD ; UNTIL C=0
96 8A
88 FF
4C
LDAA BCC
EORA #0FFH
INCA
; ONE'S COMPLEMENT
; TWO'S COMPLEMENT
97 8A
STAA BCC
BD C1 F7
JSR GET_HEX
91 8A
27 04
CMPA BCC
BEQ SKIP11
86 01
97 89
LDAA #1
STAA _ERROR
; GET BYTE CHECK SUM
; COMPARE WITH BYTE CHECK SUM
; ERROR FLAG =1
SKIP11
7E C2 18
JMP GET_RECORD1
; NEXT LINE
; Motorola s record downloading subrouitne
;
;
;
;
;
;
;
86 00
97 89
S1 14 0200 8601B780008D034920F8CE07D00926FD39 30
S1 0A 0218 CE13880926FD39 0D
S9 03 0000 FC
14 is pair count for remaining pair
GET_S_RECORD LDAA #0
STAA _ERROR
GET_S_RECORD1
BD C0 BB
81 53
26 F9
JSR CIN
CMPA #'S'
BNE GET_S_RECORD1
GET_S_RECORD2
BD C0 BB
81 31
27 06
JSR CIN
CMPA #'1'
BEQ GET_S1
Page 10 of 40
MON68.LST
0761
0762
0763
0764
0765
0766
0767
0768
0769
0770
0771
0772
0773
0774
0775
0776
0777
0778
0779
0780
0781
0782
0783
0784
0785
0786
0787
0788
0789
0790
0791
0792
0793
0794
0795
0796
0797
0798
0799
0800
0801
0802
0803
0804
0805
0806
0807
0808
0809
0810
0811
0812
0813
0814
0815
0816
0817
0818
0819
0820
0821
0822
0823
0824
0825
0826
0827
0828
0829
0830
0831
0832
0833
0834
0835
0836
C299
C29B
C29D
C29D
C29F
C29F
C29F
C29F
C2A1
C2A3
C2A3
C2A6
C2A8
C2A8
C2AB
C2AB
C2AE
C2B0
C2B0
C2B3
C2B3
C2B6
C2B6
C2B9
C2BB
C2BB
C2BE
C2BE
C2C1
C2C1
C2C4
C2C4
C2C6
C2C6
C2C6
C2C6
C2C9
C2CB
C2CD
C2CD
C2D0
C2D0
C2D2
C2D4
C2D6
C2D6
C2D6
C2D6
C2D6
C2D9
C2D9
C2D9
C2DA
C2DA
C2DA
C2DA
C2DA
C2DD
C2DF
C2E1
C2E1
C2E4
C2E4
C2E7
C2E7
C2E8
C2EA
C2EA
C2ED
C2EF
C2EF
C2F1
C2F3
C2F5
C2F5
C2F5
2/11/2558 17:06
81 39
27 29
CMPA #'9'
BEQ END_OF_RECORD
20 EC
BRA GET_S_RECORD1
GET_S1
86 00
97 8A
LDAA #0
STAA BCC
BD C1 F7
97 83
JSR GET_HEX
STAA REG_C
BD C2 0F
JSR ADD_BCC
BD C1 F7
97 84
JSR GET_HEX
STAA HL
7A 00 83
DEC REG_C
BD C2 0F
JSR ADD_BCC
BD C1 F7
97 85
JSR GET_HEX
STAA HL+1
7A 00 83
DEC REG_C
BD C2 0F
; GET NUMBER OF pairs
; GET LOAD ADDRESS
JSR ADD_BCC
7A 00 83
DEC REG_C
; BYTE COUNT-1 FOR BCC
20 14
BRA DATA_S_RECORD
END_OF_RECORD
BD C0 BB
81 0D
26 F9
JSR CIN
CMPA #0DH
; END OF LINE 0D,0A
BNE END_OF_RECORD
B7 80 00
STAA GPIO1
96 89
81 01
26 03
LDAA _ERROR
CMPA #1
BNE NOERROR2
; SHOW ERROR ON LED
; JSR OUT_OFF_RANGE
B7 80 00
STAA GPIO1
NOERROR2
39
RTS
DATA_S_RECORD
BD C1 F7
DE 84
A7 00
JSR GET_HEX
LDX HL
STAA 0,X
BD C2 0F
JSR ADD_BCC
B7 80 00
STAA GPIO1
08
DF 84
; WRITE TO MEMORY
INX
STX HL
7A 00 83
26 EB
DEC REG_C
BNE DATA_S_RECORD ; UNTIL C=0
96 8A
88 FF
97 8A
LDAA BCC
EORA #0FFH
STAA BCC
BD C1 F7
JSR GET_HEX
; ONE'S COMPLEMENT
; GET BYTE CHECK SUM
Page 11 of 40
MON68.LST
0837
0838
0839
0840
0841
0842
0843
0844
0845
0846
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856
0857
0858
0859
0860
0861
0862
0863
0864
0865
0866
0867
0868
0869
0870
0871
0872
0873
0874
0875
0876
0877
0878
0879
0880
0881
0882
0883
0884
0885
0886
0887
0888
0889
0890
0891
0892
0893
0894
0895
0896
0897
0898
0899
0900
0901
0902
0903
0904
0905
0906
0907
0908
0909
0910
0911
0912
C2F8
C2F8
C2FA
C2FC
C2FC
C2FE
C300
C300
C300
C300
C300
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C303
C305
C307
C307
C307
C307
C309
C30B
C30B
C30D
C30F
C30F
C311
C314
C314
C316
C318
C31B
C31B
2/11/2558 17:06
91 8A
27 04
86 01
97 89
CMPA BCC
BEQ SKIP21
LDAA #1
STAA _ERROR
; COMPARE WITH BYTE CHECK SUM
; ERROR FLAG =1
SKIP21
7E C2 8B
JMP GET_S_RECORD1
; NEXT LINE
;****************************************************************************
;
; EXECUTE FUNCTIONS OR HEX KEY ENTERED
; CHECK HEX KEY OR FUNCTIONS KEY
; ENTRY: A
81 10
2C 56
KEYEXE
CMPA #10H
BGE FUNCTION_KEY
;HHHHHHHHHHHHHHH
KEY HEX ENTERED HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
97 83
96 94
STAA REG_C
LDAA STATE
81 01
26 05
CMPA #1
BNE CHK_STATE2
96 83
7E C7 15
; SAVE HEX KEY
LDAA REG_C
JMP HEX_ADDR
81 02
26 03
7E C7 4B
CHK_STATE2 CMPA #2
BNE CHK_STATE3
JMP HEX_DATA
81 03
CHK_STATE3 CMPA #3
Page 12 of 40
MON68.LST
0913
0914
0915
0916
0917
0918
0919
0920
0921
0922
0923
0924
0925
0926
0927
0928
0929
0930
0931
0932
0933
0934
0935
0936
0937
0938
0939
0940
0941
0942
0943
0944
0945
0946
0947
0948
0949
0950
0951
0952
0953
0954
0955
0956
0957
0958
0959
0960
0961
0962
0963
0964
0965
0966
0967
0968
0969
0970
0971
0972
0973
0974
0975
0976
0977
0978
0979
0980
0981
0982
0983
0984
0985
0986
0987
0988
C31D
C31F
C322
C322
C324
C326
C329
C329
C32B
C32D
C330
C330
C332
C334
C337
C337
C339
C33B
C33E
C33E
C340
C342
C345
C345
C347
C349
C34C
C34C
C34E
C350
C353
C353
C353
C353
C353
C353
C355
C358
C35A
C35C
C35C
C35C
C35C
C35C
C35C
C35C
C35C
C35C
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35D
C35F
C361
2/11/2558 17:06
26 03
7E C7 6B
BNE CHK_STATE5
JMP HEX_REG
81 05
26 03
7E C8 9C
CHK_STATE5 CMPA #5
BNE CHK_STATE6
JMP HEX_REL
81 06
26 03
7E C8 A8
CHK_STATE6 CMPA #6
BNE CHK_STATE7
JMP HEX_REL6
81 07
26 03
7E C8 D8
CHK_STATE7 CMPA #7
BNE CHK_STATE8
JMP HEX_SEND_FILE
81 08
26 03
7E C8 D9
CHK_STATE8
81 1E
26 03
7E C8 B4
CHK_STATE9
81 1F
26 03
7E C8 C0
CHK_STATE10 CMPA #31
BNE CHK_STATE11
JMP HEX_COPY32
81 20
26 03
7E C8 CC
CHK_STATE11 CMPA #32
BNE CHK_STATE12
JMP HEX_COPY33
CMPA #8
BNE CHK_STATE9
JMP HEX_SEND_FILE2
CMPA #30
BNE CHK_STATE10
JMP HEX_COPY31
CHK_STATE12
96
B7
86
97
83
80 00
01
92
LDAA REG_C
STAA GPIO1
LDAA #1
STAA INVALID
; INVALID KEY PRESSED
; HEX KEY WAS PRESSED
39
RTS
;FFFFFFFFFFFFFFFFFFFFFF FUNCTION KEY FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
FUNCTION_KEY
81 19
26 03
7E C3 CE
CMPA #19H
BNE CHK_FUNC1
JMP KEY_ADDR
; KEY ADDR
Page 13 of 40
MON68.LST
0989
0990
0991
0992
0993
0994
0995
0996
0997
0998
0999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
C364
C364
C366
C368
C36B
C36B
C36B
C36B
C36D
C36F
C372
C372
C374
C376
C379
C379
C37B
C37D
C380
C380
C382
C384
C387
C387
C389
C38B
C38E
C38E
C390
C392
C395
C395
C397
C399
C39C
C39C
C39E
C3A0
C3A3
C3A3
C3A3
C3A5
C3A7
C3AA
C3AA
C3AC
C3AE
C3B1
C3B1
C3B3
C3B5
C3B8
C3B8
C3B8
C3BA
C3BC
C3BF
C3BF
C3C1
C3C3
C3C6
C3C6
C3C8
C3CA
C3CD
C3CD
C3CD
C3CD
C3CD
C3CE
C3CE
C3CE
C3CE
C3D0
C3D2
C3D2
2/11/2558 17:06
81 14
26 03
7E C3 FE
CHK_FUNC1 CMPA #14H
; KEY DATA
BNE CHK_FUNC2
JMP KEY_DATA
81 10
26 03
7E C4 70
CHK_FUNC2 CMPA #10H
; KEY +
BNE CHK_FUNC3
JMP KEY_INC
81 11
26 03
7E C5 0A
CHK_FUNC3 CMPA #11H
; KEY BNE CHK_FUNC4
JMP KEY_DEC
81 18
26 03
7E C4 41
CHK_FUNC4
81 1B
26 03
7E C4 55
CHK_FUNC5
81 12
26 03
7E C5 33
CHK_FUNC6
81 1D
26 03
7E C6 79
CHK_FUNC7
81 1F
26 03
7E C6 8D
CHK_FUNC8
81 13
26 03
7E C6 36
CHK_FUNC9 CMPA #13H
BNE CHK_FUNC10
JMP KEY_STEP
81 16
26 03
7E C6 0D
CHK_FUNC10 CMPA #16H
BNE CHK_FUNC11
JMP KEY_INS
81 17
26 03
7E C6 26
CHK_FUNC11 CMPA #17H
BNE CHK_FUNC12
JMP KEY_DEL
81 15
26 03
7E C6 E3
CHK_FUNC12 CMPA #15H
BNE CHK_FUNC13
JMP KEY_DEMO
; CHANGE SBR KEY TO DEMO
81 1A
26 03
7E C6 FD
CHK_FUNC13 CMPA #1AH
BNE CHK_FUNC14
JMP KEY_MUTE
; TURN BEEP ON/OFF
81 1C
26 03
7E C7 01
CHK_FUNC14 CMPA #1CH
;
BNE CHK_FUNC15
JMP KEY_COPY
81 1E
26 03
7E C1 72
CHK_FUNC15 CMPA #1EH
BNE CHK_FUNC16
JMP KEY_DUMP
CMPA #18H
BNE CHK_FUNC5
JMP KEY_PC
CMPA #1BH
BNE CHK_FUNC6
JMP KEY_REG
CMPA #12H
BNE CHK_FUNC7
JMP KEY_GO
CMPA #1DH
BNE CHK_FUNC8
JMP KEY_REL
CMPA #1FH
BNE CHK_FUNC9
JMP KEY_DOWNLOAD_HEX
CHK_FUNC16
39
86 01
97 94
86 00
RTS
;--------------------------------------------------------KEY_ADDR
LDAA #1
STAA STATE
; STAATE =1 FOR ADDRESS MODE
LDAA #0
Page 14 of 40
MON68.LST
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
C3D4
C3D6
C3D6
C3D6
C3D9
C3D9
C3DB
C3DD
C3DF
C3DF
C3E1
C3E3
C3E5
C3E5
C3E7
C3E9
C3EB
C3EB
C3ED
C3EF
C3F1
C3F1
C3F3
C3F5
C3F7
C3F7
C3F9
C3FB
C3FD
C3FD
C3FE
C3FE
C3FE
C3FE
C400
C402
C402
C404
C406
C406
C409
C409
C40B
C40D
C40F
C40F
C411
C413
C415
C415
C417
C419
C41B
C41B
C41D
C41F
C421
C421
C423
C425
C427
C427
C429
C42B
C42D
C42D
C42E
C42E
C42E
C42E
C42E
C42E
C42E
C430
C432
C434
2/11/2558 17:06
97 95
STAA ZERO_FLAG
STILL_ADDRESS
BD C4 2E
JSR READ_MEMORY
96 91
8A 40
97 91
LDAA BUFFER+5
ORAA #40H
STAA BUFFER+5
96 90
8A 40
97 90
LDAA BUFFER+4
ORAA #40H
STAA BUFFER+4
96 8F
8A 40
97 8F
LDAA BUFFER+3
ORAA #40H
STAA BUFFER+3
96 8E
8A 40
97 8E
LDAA BUFFER+2
ORAA #40H
STAA BUFFER+2
96 8D
84 BF
97 8D
LDAA BUFFER+1
ANDA #~40H
STAA BUFFER+1
96 8C
84 BF
97 8C
LDAA BUFFER
ANDA #~40H
STAA BUFFER
39
RTS
;---------------------------------------------------------
86 02
97 94
86 00
97 95
BD C4 2E
KEY_DATA
LDAA #2
STAA STATE
; STATE =2 FOR DATA MODE
LDAA #0
STAA ZERO_FLAG
STILL_DATA
JSR READ_MEMORY
96 91
84 BF
97 91
LDAA BUFFER+5
ANDA #~40H
STAA BUFFER+5
96 90
84 BF
97 90
LDAA BUFFER+4
ANDA #~40H
STAA BUFFER+4
96 8F
84 BF
97 8F
LDAA BUFFER+3
ANDA #~40H
STAA BUFFER+3
96 8E
84 BF
97 8E
LDAA BUFFER+2
ANDA #~40H
STAA BUFFER+2
96 8D
8A 40
97 8D
LDAA BUFFER+1
ORAA #40H
STAA BUFFER+1
96 8C
8A 40
97 8C
LDAA BUFFER
ORAA #40H
STAA BUFFER
39
RTS
; READ MEMORY
READ_MEMORY
96
97
96
97
96
84
97
85
LDAA DISPLAY
STAA HL
LDAA DISPLAY+1
STAA HL+1
Page 15 of 40
MON68.LST
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
C436
C439
C439
C43B
C43D
C43D
C43D
C43D
C440
C441
C441
C441
C441
C441
C441
C441
C443
C445
C445
C447
C449
C449
C44B
C44D
C44F
C451
C451
C454
C455
C455
C455
C455
C455
C457
C459
C459
C45B
C45D
C45F
C461
C463
C465
C467
C469
C46B
C46D
C46F
C46F
C470
C470
C470
C470
C470
C472
C474
C476
C476
C479
C47B
C47D
C47F
C481
C483
C483
C483
C486
C487
C487
C487
C487
C487
C487
C489
C48B
C48D
C48D
2/11/2558 17:06
BD C1 D1
JSR ADDRESS_DISPLAY
DE 84
A6 00
LDX
HL
LDAA 0,X
;STAA GPIO1
BD C1 C3
39
JSR DATA_DISPLAY
RTS
; KEY PC, SET CURRENT USER ADDRESS
86 02
97 94
KEY_PC
LDAA #2
STAA STATE
; STAATE =2 FOR DATA MODE
86 00
97 95
LDAA #0
STAA ZERO_FLAG
96
97
96
97
LDAA USER_PC
STAA DISPLAY
LDAA USER_PC+1
STAA DISPLAY+1
; JSR READ_MEMORY
JSR STILL_DATA
RTS
98
96
99
97
BD C4 06
39
; KEY REGISTER
; SET STATE TO 3 FOR REGISTER INPUT WITH HEX KEY
86 03
97 94
86
97
86
97
86
97
86
97
86
97
97
03
91
8F
90
BE
8F
00
8E
00
8D
8C
39
KEY_REG
LDAA
STAA
LDAA
STAA
LDAA
STAA
STAA
LDAA
STAA
STAA
LDAA #3
STAA STATE
; STAATE = 3 FOR REGISTER DISPLAY
#3
BUFFER+5
#8FH
BUFFER+4
#0BEH
BUFFER+3
LDAA #0
BUFFER+2
#0
BUFFER+1
BUFFER
RTS
; INCREMENT CURRENT ADDRESS BY ONE
;
96 94
81 14
26 11
7C
96
81
2D
86
97
KEY_INC
00 C9
C9
0A
04
00
C9
INC DEMO_NO
LDAA DEMO_NO
CMPA #10
BLT SKIP_INC2
LDAA #0
STAA DEMO_NO
BD C1 C3
39
SKIP_INC2
96 94
81 05
27 4D
SKIP_INC1
81 07
LDAA STATE
CMPA #20
BNE SKIP_INC1
JSR DATA_DISPLAY
RTS
LDAA STATE
CMPA #5
BEQ REL_KEY_PRESSED
CMPA #7
Page 16 of 40
MON68.LST
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
C48F
C491
C491
C491
C493
C495
C495
C497
C499
C499
C499
C499
C499
C499
C49B
C49D
C49D
C49F
C4A1
C4A1
C4A1
C4A3
C4A4
C4A6
C4A6
C4A6
C4A6
C4A9
C4AA
C4AA
C4AA
C4AA
C4AA
C4AA
C4AA
C4AA
C4AA
C4AC
C4AE
C4AE
C4B0
C4B2
C4B4
C4B6
C4B6
C4B9
C4BB
C4BD
C4BF
C4C1
C4C2
C4C2
C4C2
C4C2
C4C2
C4C2
C4C2
C4C2
C4C4
C4C6
C4C6
C4C8
C4CA
C4CC
C4CE
C4CE
C4D1
C4D3
C4D5
C4D7
C4D9
C4DA
C4DA
C4DA
C4DA
C4DA
2/11/2558 17:06
27 61
BEQ SEND_INC1
81 1E
27 2D
CMPA #30
BEQ COPY_KEY_PRESSED
81 1F
27 11
CMPA #31
BEQ COPY_KEY_PRESSED1
; NORMAL INCREMENT CURRENT ADDRESS BY ONE
86 02
97 94
86 00
97 95
DE 96
08
DF 96
BD C4 06
39
LDAA #2
STAA STATE
; STATE =2 FOR DATA MODE
LDAA #0
STAA ZERO_FLAG
LDX DISPLAY
INX
STX DISPLAY
; JSR READ_MEMORY
JSR STILL_DATA
RTS
COPY_KEY_PRESSED1
; Save ENDING address
DE 96
DF A9
LDX DISPLAY
STX END_ADDRESS
86
97
86
97
20
94
00
95
LDAA #32
STAA STATE
LDAA #0
STAA ZERO_FLAG
BD
86
97
86
97
39
C3 D6
B3
8C
02
8D
JSR STILL_ADDRESS
LDAA #0B3H
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
COPY_KEY_PRESSED
; Save start address
DE 96
DF A3
LDX DISPLAY
STX START_ADDRESS
86
97
86
97
1F
94
00
95
LDAA #31
STAA STATE
LDAA #0
STAA ZERO_FLAG
BD
86
97
86
97
39
C3 D6
8F
8C
02
8D
JSR STILL_ADDRESS
LDAA #08FH
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
REL_KEY_PRESSED
Page 17 of 40
; STATE 32 FOR KEY GO COPYING MEMORY
MON68.LST
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
C4DA
C4DA
C4DA
C4DA
C4DC
C4DE
C4DE
C4E0
C4E2
C4E4
C4E6
C4E6
C4E9
C4EB
C4ED
C4EF
C4F1
C4F2
C4F2
C4F2
C4F2
C4F2
C4F2
C4F4
C4F6
C4F6
C4F8
C4FA
C4FC
C4FE
C4FE
C501
C503
C505
C507
C509
C50A
C50A
C50A
C50A
C50A
C50A
C50A
C50A
C50A
C50A
C50A
C50C
C50E
C510
C510
C513
C515
C517
C519
C51B
C51C
C51E
C51E
C521
C521
C521
C522
C522
C522
C522
C522
C522
C522
C524
C526
C526
C528
C52A
C52A
C52A
2/11/2558 17:06
; Save start address
DE 96
DF A3
LDX DISPLAY
STX START_ADDRESS
86
97
86
97
06
94
00
95
LDAA #6
STAA STATE
LDAA #0
STAA ZERO_FLAG
BD
86
97
86
97
39
C3 D6
B3
8C
02
8D
JSR STILL_ADDRESS
LDAA #0B3H
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
SEND_INC1
DE 96
DF A3
; Save start address
LDX DISPLAY
STX START_ADDRESS
86
97
86
97
08
94
00
95
LDAA #8
STAA STATE
LDAA #0
STAA ZERO_FLAG
BD
86
97
86
97
39
C3 D6
8F
8C
02
8D
JSR STILL_ADDRESS
LDAA #08FH
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
; DECREMENT CURRENT ADDRESS BY ONE
;
96 94
81 14
26 12
7A
96
97
81
2C
4F
97
KEY_DEC
00 C9
C9
C9
00
03
DEC DEMO_NO
LDAA DEMO_NO
STAA DEMO_NO
CMPA #0
BGE SKIP_DEC2
CLRA
STAA DEMO_NO
C9
BD C1 C3
LDAA STATE
CMPA #20
BNE SKIP_DEC1
SKIP_DEC2
39
JSR DATA_DISPLAY
RTS
SKIP_DEC1
86 02
97 94
86 00
97 95
DE 96
LDAA #2
STAA STATE
; STAATE =2 FOR DATA MODE
LDAA #0
STAA ZERO_FLAG
LDX DISPLAY
Page 18 of 40
MON68.LST
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
C52C
C52D
C52F
C52F
C532
C533
C533
C533
C533
C533
C533
C533
C535
C537
C539
C539
C539
C53B
C53D
C53D
C53F
C541
C541
C543
C545
C545
C547
C549
C549
C549
C549
C54B
C54D
C54F
C552
C553
C553
C555
C557
C55A
C55B
C55B
C55D
C55F
C562
C562
C564
C566
C569
C569
C56B
C56D
C570
C570
C570
C570
C570
C570
C571
C571
C571
C574
C574
C575
C575
C575
C576
C576
C576
C576
C576
C576
C576
C579
C579
C57A
2/11/2558 17:06
09
DF 96
DEX
STX DISPLAY
; JSR READ_MEMORY
JSR STILL_DATA
RTS
BD C4 06
39
; KEY GO WRITE USER REGISTERS TO STACK AND USE RTI TO JUMP TO USER PROGRAM
;
KEY_GO
96 94
81 20
27 38
LDAA STATE
CMPA #32
BEQ GO_STATE32
81 06
27 51
CMPA #6
BEQ GO_STATE6
81 08
27 34
CMPA #8
BEQ GO_STATE8
81 0A
27 31
CMPA #10
BEQ SHORT_GO_STATE10
81 14
26 31
CMPA #20
BNE SKIP_GO1
; GO FOR COPYING DATA
; EXECUTE KEY GO STATE 20 DEMO PROGRAMS
96
81
26
BD
39
C9
04
04
CA 81
LDAA DEMO_NO
CMPA #4
BNE DEMO2
JSR DEMO_LCD
RTS
81 01
26 04
BD CA 98
39
DEMO2
CMPA #1
BNE DEMO3
JSR DEMO_LED
RTS
81 00
26 03
7E CA AA
DEMO3
CMPA #0
BNE DEMO4
JMP RUN_DOT
81 02
26 03
7E CA B4
DEMO4
CMPA #2
BNE DEMO5
JMP BCD_COUNTING
81 03
26 03
7E CA F7
DEMO5
CMPA #3
BNE DEMO6
JMP CLOCK_PGM
; CHECK SUB FUNCTION FOR STATE=20
DEMO6
39
7E C5 E3
RTS
GO_STATE32
39
39
JMP GO_COPY_MEMORY
RTS
GO_STATE8
RTS
SHORT_GO_STATE10
BD C6 B9
JSR GO_STATE10
39
RTS
Page 19 of 40
MON68.LST
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
C57A
C57A
C57A
C57A
C57A
C57A
C57A
C57A
C57A
C57A
C57A
C57C
C57C
C57C
C57C
C57E
C57E
C580
C581
C583
C584
C586
C587
C589
C58B
C58D
C58E
C58E
C58E
C58E
C58E
C58E
C58E
C58E
C58E
C58E
C590
C592
C592
C592
C592
C592
C592
C592
C594
C595
C596
C598
C598
C598
C598
C59A
C59C
C59E
C59E
C5A0
C5A2
C5A4
C5A4
C5A4
C5A4
C5A4
C5A4
C5A4
C5A4
C5A4
C5A6
C5A8
C5AA
C5AA
C5AA
C5AA
C5AC
C5AE
C5B0
C5B0
2/11/2558 17:06
SKIP_GO1
9F A1
STS SAVE_SP
; SAVE SYSTEM STACK
; NOW SWITCH TO USER STACK
9E 9E
96
36
96
36
96
06
DE
D6
96
39
97
96
A0
9C
9B
9A
LDS USER_SP
; NOW LOAD WITH USER STACK
LDAA DISPLAY+1
PSHA
LDAA DISPLAY
PSHA
LDAA USER_P
TAP
LDX USER_IX
LDAB USER_B
LDAA USER_A
RTS
; KEY GO WITH RELATIVE CALCULATION
; FIND OFFSET BYTE
GO_STATE6
DE 96
DF A5
LDX DISPLAY
STX DESTINATION
; NOW COMPUTE OFFSET_BYTE = DESTINATION - START_ADDRESS
; THE REAL PC WILL BE NEXT INTSRUCTION ADDRESS (+2 FROM BRANCH INSTRUCTION
DE A3
08
08
DF B0
LDX START_ADDRESS
INX
INX
STX TEMP16
; SAVE CURRENT PC TO TEMP16
96 A6
90 B1
97 A8
LDAA DESTINATION+1
SUBA TEMP16+1
STAA OFFSET_BYTE+1
96 A5
92 B0
97 A7
LDAA DESTINATION
SBCA TEMP16
STAA OFFSET_BYTE
;
;
;
;
96 A8
84 80
27 09
CHECK IF THE OFFSET BYTE WAS BETWEEN -128 (FF80) TO +127 (007F)
IF BIT 7 OF THE OFFSET BYTE IS 0, THE HIGH BYTE MUST BE ZERO
IF BIT 7 OF THE OFFSET BYTE IS 1, THE HIGH BYTE MUST BE FF
OTHERWISE, THE OFFSET BYTE WAS OUT OF RANGE, SHOW ERROR THEN
LDAA OFFSET_BYTE+1
ANDA #80H
BEQ CHK_OFFSET_HIGH
; CHECK HIGH BYTE MUST BE FF (-1)
96 A7
81 FF
26 18
LDAA OFFSET_BYTE
CMPA #0FFH
BNE OUT_OFF_RANGE
7E C5 B7
JMP IN_RANGE
Page 20 of 40
MON68.LST
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
C5B3
C5B3
C5B3
C5B5
C5B7
C5B7
C5B7
C5B7
C5B9
C5BA
C5BA
C5BC
C5BE
C5BE
C5C0
C5C0
C5C3
C5C3
C5C5
C5C7
C5C8
C5C8
C5C8
C5C8
C5CA
C5CC
C5CE
C5D0
C5D2
C5D4
C5D6
C5D8
C5DA
C5DC
C5DE
C5DE
C5E0
C5E2
C5E2
C5E3
C5E3
C5E3
C5E3
C5E3
C5E3
C5E3
C5E3
C5E3
C5E3
C5E5
C5E7
C5E7
C5E7
C5E9
C5EB
C5ED
C5EF
C5EF
C5EF
C5F1
C5F2
C5F4
C5F4
C5F4
C5F6
C5F7
C5F9
C5F9
C5F9
C5FB
C5FB
C5FD
C5FD
C5FD
C5FD
C5FF
2/11/2558 17:06
96 A7
26 11
CHK_OFFSET_HIGH
LDAA OFFSET_BYTE
BNE OUT_OFF_RANGE
; STORE OFFSET TO THE 2ND BYTE OF BRANCH INSTRUCTION
DE A3
08
IN_RANGE LDX START_ADDRESS
INX
96 A8
A7 00
LDAA OFFSET_BYTE+1
STAA 0,X
DF 96
STX DISPLAY
BD C4 06
JSR STILL_DATA
86 02
97 94
39
LDAA #2
STAA STATE
RTS
OUT_OFF_RANGE
86
97
86
97
86
97
86
97
86
97
97
02
91
8F
90
03
8F
03
8E
00
8D
8C
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
STAA
LDAA #2
BUFFER+5
#8FH
BUFFER+4
#3
BUFFER+3
#3
BUFFER+2
#0
BUFFER+1
BUFFER
86 02
97 94
LDAA #2
39
RTS
STAA STATE
; SERVICE KEY GO FOR COPY KEY
GO_COPY_MEMORY
DE 96
DF A5
LDX DISPLAY
STX DESTINATION
COPY1
DE
A6
DE
A7
A3
00
A5
00
LDX START_ADDRESS
LDAA 0,X
LDX DESTINATION
STAA 0,X
DE A5
08
DF A5
LDX DESTINATION
INX
STX DESTINATION
DE A3
08
DF A3
LDX START_ADDRESS
INX
STX START_ADDRESS
9C A9
CPX END_ADDRESS
26 EA
BNE COPY1
; STORE LAST BYTE AS WELL
DE A3
A6 00
LDX START_ADDRESS
LDAA 0,X
Page 21 of 40
MON68.LST
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
C601
C603
C605
C605
C605
C605
C608
C608
C60A
C60C
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60D
C60F
C610
C612
C612
C614
C614
C616
C618
C619
C619
C61A
C61C
C61C
C61C
C61E
C61E
C620
C622
C622
C625
C625
C626
C626
C626
C626
C626
C628
C628
C62A
C62A
C62C
C62E
C62F
C62F
C630
C632
C632
C632
C635
C635
C636
C636
C636
C636
2/11/2558 17:06
DE A5
A7 00
LDX DESTINATION
STAA 0,X
BD C4 06
JSR STILL_DATA
86 02
97 94
39
LDAA #2
STAA STATE
RTS
; INSERT ONE BYTE WITHIN 256 BYTES
; CURRENT LOCATION WILL BE DISPLAY+1
DE 96
08
DF 96
KEY_INS
C6 00
A6 FE
A7 FF
09
LDX DISPLAY ; GET CURRENT DISPLAY ADDRESS
INX
STX DISPLAY
LDAB #0
INSERT
LDAA 0FEH,X
STAA 0FFH,X
DEX
5A
26 F8
DECB
BNE INSERT
86 00
LDAA #0
DE 96
A7 00
LDX DISPLAY
STAA 0,X
BD C4 06
JSR STILL_DATA
39
RTS
; DELETE ONE BYTE AT CURRENT DISPLAY ADDRESS
; SHIFTED UP 256 BYTES
DE 96
KEY_DEL
C6 00
A6 01
A7 00
08
LDX DISPLAY ; GET CURRENT DISPLAY ADDRESS
LDAB #0
DELETE
LDAA 1,X
STAA 0,X
INX
5A
26 F8
DECB
BNE DELETE
BD C4 06
JSR STILL_DATA
39
RTS
; SINGLE STEP KEY
; ENABLE BREAK SIGNAL SO AT THE 8TH OF E CLOCK, THE NMI WILL PRODUCE
Page 22 of 40
MON68.LST
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
C636
C636
C636
C636
C638
C638
C638
C638
C63A
C63A
C63C
C63D
C63F
C640
C640
C642
C643
C643
C645
C646
C646
C648
C649
C649
C64B
C64C
C64C
C64E
C64F
C64F
C651
C654
C654
C654
C655
C655
C655
C655
C655
C655
C655
C655
C655
C657
C65A
C65A
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65C
C65D
C65F
C65F
C660
C662
C662
C663
C665
C665
C666
C668
2/11/2558 17:06
KEY_STEP
9F A1
STS SAVE_SP
; SAVE SYSTEM STACK
; NOW SWITCH TO USER STACK
9E 9E
LDS USER_SP
; NOW LOAD WITH USER STACK
96 97
36
96 96
36
LDAA DISPLAY+1
PSHA
LDAA DISPLAY ; PUSH PC
PSHA
96 9D
36
LDAA USER_IX+1
PSHA
96 9C
36
LDAA USER_IX
PSHA
96 9A
36
LDAA USER_A
PSHA
; PUSH A
96 9B
36
LDAA USER_B
PSHA
; PUSH B
96 A0
36
LDAA USER_P
PSHA
C6 FF
F7 80 02
LDAB #$FF
STAB PORT1
; NOW ENABLE 74LS164
3B
RTI
; 10 CYCLES
; PUSH IX
; PUSH CONDITION CODE REGISTER
NMI_SERVICE
; STAA GPIO1
86 BF
B7 80 02
LDAA #0BFH
STAA PORT1
20 00
BRA
; STOP BREAK SIGNAL
SWI_SERVICE
; RTI
; SAVE CPU REGISTERS TO USER REGISTERS
; SWI INSTRUCTION 3FH
SWI_SERVICE
;
;
;
;
;
;
;
POP
POP
POP
POP
POP
POP
POP
CC
ACCB
ACCA
IXH
IXL
PCH
PCL
32
97 A0
PULA
STAA USER_P
32
97 9B
PULA
STAA USER_B
32
97 9A
PULA
STAA USER_A
32
97 9C
PULA
STAA USER_IX
; SAVE CONDITION CODE REGISTER
Page 23 of 40
MON68.LST
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1750
1751
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1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
C668
C669
C66B
C66C
C66C
C66E
C66F
C671
C671
C671
C671
C673
C673
C675
C675
C678
C678
C679
C679
C679
C679
C67B
C67D
C67D
C67F
C681
C684
C686
C688
C68A
C68C
C68D
C68D
C68D
C68D
C68D
C68D
C68F
C691
C693
C695
C697
C699
C69B
C69D
C69F
C6A1
C6A3
C6A5
C6A7
C6A7
C6A9
C6AB
C6AB
C6AE
C6B1
C6B4
C6B4
C6B6
C6B8
C6B8
C6B9
C6B9
C6B9
C6BB
C6BE
C6BE
C6C1
C6C4
C6C4
C6C4
C6C7
C6C7
C6C9
C6CB
C6CD
2/11/2558 17:06
32
97 9D
32
PULA
STAA USER_IX+1
PULA
97 98
32
97 99
STAA USER_PC
PULA
STAA USER_PC+1
9F 9E
STS USER_SP
9E A1
LDS SAVE_SP
; RESTORE SYSTEM STACK AND GET BACK TO MONITOR
BD C4 41
JSR KEY_PC
; DISPLAY CURRENT PC
39
RTS
;--------------------------------------------------------------
86 05
97 94
86
97
BD
86
97
86
97
39
00
95
C3 D6
AE
8C
02
8D
KEY_REL
LDAA #5
STAA STATE ; STATE = 5 FOR RELATIVE BYTE CALCULATION
LDAA #0
STAA ZERO_FLAG
JSR STILL_ADDRESS
LDAA #0AEH
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
KEY_DOWNLOAD_HEX
86
97
86
97
86
97
86
97
86
97
86
97
97
B3
91
85
91
A3
90
3F
8F
B3
8E
00
8D
8C
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
STAA
#0B3H
; PRINT LOAD
BUFFER+5
#85H
BUFFER+5
#0A3H
BUFFER+4
#3FH
BUFFER+3
#0B3H
BUFFER+2
#0
BUFFER+1
BUFFER
86 0A
97 94
LDAA #10
STAA STATE
BD C9 FF
CE CB A7
BD CA 14
JSR CLR_SCREEN
LDX #DOWNLOAD
JSR PSTR
86 FF
97 CA
LDAA #$FF
STAA MUTE
39
86 01
B7 80 00
; TURN OFF BEEP
RTS
GO_STATE10
LDAA #1
STAA GPIO1
CE CB B6
BD CA 14
LDX #DOWNLOAD2
JSR PSTR
BD C2 14
JSR GET_RECORD
96 89
81 00
26 08
LDAA _ERROR
CMPA #0
BNE FOUND_ERROR
Page 24 of 40
; GET INTEL HEX FILE
MON68.LST
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
C6CD
C6D0
C6D3
C6D5
C6D5
C6D8
C6DB
C6DB
C6DB
C6DB
C6DD
C6DF
C6E2
C6E2
C6E3
C6E3
C6E3
C6E3
C6E5
C6E7
C6E7
C6E9
C6EB
C6ED
C6EF
C6EF
C6F1
C6F3
C6F5
C6F7
C6F7
C6F9
C6FC
C6FD
C6FD
C6FD
C6FD
C6FD
C6FD
C700
C701
C701
C701
C701
C703
C705
C705
C707
C709
C709
C70C
C70E
C710
C712
C714
C715
C715
C715
C715
C715
C715
C715
C715
C715
C717
C719
C71B
C71B
C71D
C71F
C721
C723
C725
C725
C726
C729
2/11/2558 17:06
CE CB D0
BD CA 14
20 06
CE CB DD
BD CA 14
LDX #COMPLETE
JSR PSTR
BRA SKIP_ERROR
FOUND_ERROR
LDX #ERROR_FOUND
JSR PSTR
SKIP_ERROR
86 02
97 94
BD C4 06
LDAA #2
39
RTS
86 14
97 94
86
97
86
97
1F
91
03
90
86
97
86
97
BE
8F
00
8E
STAA STATE
JSR STILL_DATA
KEY_DEMO
LDAA #20
; STATE 20 FOR KEY DEMO
STAA STATE
LDAA #1FH
; PRINT Prg
STAA BUFFER+5
LDAA #03H
STAA BUFFER+4
LDAA
STAA
LDAA
STAA
96 C9
BD C1 C3
39
#0BEH
BUFFER+3
#0
BUFFER+2
LDAA DEMO_NO
JSR DATA_DISPLAY
RTS
73 00 CA
39
KEY_MUTE
COM MUTE
RTS
86 1E
97 94
KEY_COPY
LDAA #30
STAA STATE
; STATE = 30
86 00
97 95
LDAA #0
STAA ZERO_FLAG
BD
86
97
86
97
39
JSR STILL_ADDRESS
LDAA #0AEH
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
C3 D6
AE
8C
02
8D
;------------------- HEX KEY FOR ADDRESS ------------------96 95
81 00
26 0A
86
97
86
97
97
HEX_ADDR
LDAA ZERO_FLAG
CMPA #0
BNE SHIFT_ADDRESS
01
95
00
96
97
LDAA #1
STAA ZERO_FLAG
LDAA #0
STAA DISPLAY
STAA DISPLAY+1
0C
79 00 97
79 00 96
SHIFT_ADDRESS CLC
ROL DISPLAY+1
ROL DISPLAY
Page 25 of 40
MON68.LST
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1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
C72C
C72C
C72D
C730
C733
C733
C734
C737
C73A
C73A
C73B
C73E
C741
C741
C743
C745
C747
C747
C747
C747
C74A
C74A
C74B
C74B
C74B
C74B
C74D
C74F
C751
C751
C753
C755
C755
C757
C759
C75B
C75B
C75D
C75F
C760
C761
C762
C763
C765
C767
C767
C767
C76A
C76B
C76B
C76B
C76B
C76B
C76B
C76B
C76D
C76F
C771
C771
C773
C773
C776
C776
C778
C77A
C77C
C77E
C780
C782
C784
C786
C787
C787
C787
C789
C78B
2/11/2558 17:06
0C
79 00 97
79 00 96
CLC
ROL DISPLAY+1
ROL DISPLAY
0C
79 00 97
79 00 96
CLC
0C
79 00 97
79 00 96
CLC
ROL DISPLAY+1
ROL DISPLAY
ROL DISPLAY+1
ROL DISPLAY
96 97
9A 83
97 97
LDAA DISPLAY+1
ORAA REG_C
STAA DISPLAY+1
; JSR READ_MEMORY
BD C3 D6
JSR STILL_ADDRESS
39
RTS
;------------------------- HEX KEY FOR DATA MODE --------------------------
96 95
81 00
26 0A
HEX_DATA
LDAA ZERO_FLAG
CMPA #0
BNE SHIFT_DATA
86 01
97 95
LDAA #1
STAA ZERO_FLAG
86 00
DE 96
A7 00
LDAA #0
DE
A6
48
48
48
48
9A
A7
96
00
LDX DISPLAY
STAA 0,X
SHIFT_DATA
83
00
BD C4 06
39
LDX
LDAA
ASLA
ASLA
ASLA
ASLA
ORAA
STAA
DISPLAY
0,X
REG_C
0,X
; JSR READ_MEMORY
JSR STILL_DATA
RTS
;************************ HEX REGSITERS DISPLAY **************************
; DISPLAY USER REGSITERS
96 83
81 00
26 16
HEX_REG
96 9A
LDAA USER_A
; STAA GPIO1
JSR DATA_DISPLAY
BD C1 C3
86
97
86
97
86
97
86
97
39
3F
8E
8D
8F
8D
90
3F
91
LDAA REG_C
CMPA #0
BNE CHK_REG1
LDAA #3FH
STAA BUFFER+2
LDAA #8DH
STAA BUFFER+3
LDAA #8DH
STAA BUFFER+4
LDAA #3FH
STAA BUFFER+5
RTS
; REGISTER ACCA
CHK_REG1
81 01
26 16
CMPA #1
BNE CHK_REG2
Page 26 of 40
MON68.LST
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
C78B
C78D
C78D
C78D
C790
C792
C794
C796
C798
C79A
C79C
C79E
C7A0
C7A1
C7A1
C7A3
C7A5
C7A5
C7A7
C7A7
C7A7
C7A9
C7A9
C7AC
C7AC
C7AE
C7B0
C7B2
C7B4
C7B5
C7B5
C7B5
C7B7
C7B9
C7B9
C7BB
C7BB
C7BD
C7BD
C7C0
C7C2
C7C4
C7C6
C7C8
C7C9
C7C9
C7C9
C7C9
C7CB
C7CD
C7CD
C7CD
C7CD
C7CF
C7D1
C7D3
C7D3
C7D5
C7D7
C7D9
C7D9
C7DB
C7DD
C7DD
C7DF
C7DF
C7E1
C7E3
C7E3
C7E5
C7E7
C7E9
C7E9
C7EB
C7ED
C7ED
2/11/2558 17:06
96 9B
BD
86
97
86
97
86
97
86
97
39
C1 C3
A7
8E
8D
8F
8D
90
3F
91
LDAA USER_B
; STAA GPIO1
JSR DATA_DISPLAY
LDAA #0A7H
STAA BUFFER+2
LDAA #8DH
STAA BUFFER+3
LDAA #8DH
STAA BUFFER+4
LDAA #3FH
STAA BUFFER+5
RTS
81 02
26 10
CHK_REG2 CMPA #2
BNE CHK_REG3
DE 9C
LDX USER_IX
; STAA GPIO1
; REGISTER ACCB
DF 84
STX HL
BD C1 D1
JSR ADDRESS_DISPLAY
86
97
86
97
39
LDAA
STAA
LDAA
STAA
30
8D
26
8C
#30H
BUFFER+1
#26H
BUFFER
RTS
81 03
26 10
CHK_REG3 CMPA #3
BNE CHK_REG4
DE 9E
LDX USER_SP
; STAA GPIO1
STX HL
DF 84
BD
86
97
86
97
39
; REGISTER IX
C1 D1
AE
8D
1F
8C
81 04
26 2F
JSR ADDRESS_DISPLAY
LDAA #0AEH
STAA BUFFER+1
LDAA #1FH
; REGISTER SP
STAA BUFFER
RTS
CHK_REG4
CMPA #4
BNE CHK_REG5
; CONDITION CODE DISPLAY FOR HIGH NIBBLE 11HI
96 A0
84 10
26 06
LDAA USER_P
ANDA #$10
BNE SHOW_BIT4
86 BD
97 8E
20 04
LDAA #ZERO
STAA BUFFER+2
BRA NEXT_BIT1
86 30
97 8E
SHOW_BIT4 LDAA #ONE
STAA BUFFER+2
96 A0
NEXT_BIT1 LDAA USER_P
84 20
26 06
ANDA #$20
BNE SHOW_BIT5
86 BD
97 8F
20 04
LDAA #ZERO
STAA BUFFER+3
BRA NEXT_BIT2
86 30
97 8F
SHOW_BIT5 LDAA #ONE
STAA BUFFER+3
86 30
NEXT_BIT2 LDAA #ONE
Page 27 of 40
MON68.LST
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2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
C7EF
C7F1
C7F3
C7F3
C7F5
C7F7
C7F9
C7FB
C7FB
C7FB
C7FC
C7FC
C7FC
C7FE
C800
C800
C800
C800
C802
C804
C806
C806
C808
C80A
C80C
C80C
C80E
C810
C810
C812
C814
C816
C816
C818
C81A
C81C
C81C
C81E
C820
C820
C822
C824
C826
C826
C828
C82A
C82C
C82C
C82E
C830
C830
C832
C834
C836
C836
C838
C83A
C83C
C83C
C83E
C840
C840
C840
C842
C844
C846
C848
C849
C849
C849
C84B
C84D
C84D
C850
C852
C854
2/11/2558 17:06
97 90
97 91
STAA BUFFER+4
STAA BUFFER+5
86
97
86
97
LDAA
STAA
LDAA
STAA
8D
8D
37
8C
39
#8DH
; STORE CH, CONDITION CODE HIGH NIBBLE
BUFFER+1
#37H
BUFFER
RTS
81 05
26 49
CHK_REG5
CMPA #5
BNE CHK_REG6
; CONDITION CODE DISPLAY FOR LOW NIBBLE NZVC
96 A0
84 80
26 06
LDAA USER_P
ANDA #$80
BNE SHOW_BIT6
86 BD
97 91
20 04
LDAA #ZERO
STAA BUFFER+5
BRA NEXT_BIT3
86 30
97 91
SHOW_BIT6 LDAA #ONE
STAA BUFFER+5
96 A0
84 04
26 06
NEXT_BIT3 LDAA USER_P
ANDA #4
BNE SHOW_BIT7
86 BD
97 90
20 04
LDAA #ZERO
STAA BUFFER+4
BRA NEXT_BIT4
86 30
97 90
SHOW_BIT7 LDAA #ONE
STAA BUFFER+4
96 A0
84 02
26 06
NEXT_BIT4 LDAA USER_P
ANDA #2
BNE SHOW_BIT8
86 BD
97 8F
20 04
LDAA #ZERO
STAA BUFFER+3
BRA NEXT_BIT5
86 30
97 8F
SHOW_BIT8 LDAA #ONE
STAA BUFFER+3
96 A0
84 01
26 06
NEXT_BIT5 LDAA USER_P
ANDA #1
BNE SHOW_BIT9
86 BD
97 8E
20 04
LDAA #ZERO
STAA BUFFER+2
BRA NEXT_BIT6
86 30
97 8E
SHOW_BIT9 LDAA #ONE
STAA BUFFER+2
NEXT_BIT6
86
97
86
97
39
8D
8D
85
8C
81 06
26 10
CE
EE
DF
BD
00 00
00
84
C1 D1
LDAA
STAA
LDAA
STAA
RTS
CHK_REG6
#8DH
BUFFER+1
#85H
BUFFER
CMPA #6
BNE CHK_REG7
LDX
LDX
STX
JSR
#0
0,X
HL
ADDRESS_DISPLAY
Page 28 of 40
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2131
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2134
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2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
C857
C857
C859
C85C
C85D
C85D
C85D
C85F
C861
C861
C864
C866
C868
C86B
C86B
C86D
C870
C871
C871
C871
C873
C875
C875
C878
C87A
C87C
C87F
C87F
C881
C884
C885
C885
C887
C889
C889
C88C
C88E
C890
C893
C893
C895
C898
C899
C899
C899
C899
C89A
C89A
C89A
C89A
C89A
C89A
C89A
C89A
C89A
C89A
C89A
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89B
C89C
2/11/2558 17:06
86 00
BD C1 C3
39
81 07
26 10
CE
EE
DF
BD
LDAA #0
JSR DATA_DISPLAY
RTS
CHK_REG7
00 02
00
84
C1 D1
LDX
LDX
STX
JSR
86 02
BD C1 C3
39
81 08
26 10
CE
EE
DF
BD
CHK_REG8
CMPA #8
BNE CHK_REG9
LDX
LDX
STX
JSR
86 04
BD C1 C3
39
CE
EE
DF
BD
#2
0,X
HL
ADDRESS_DISPLAY
LDAA #2
JSR DATA_DISPLAY
RTS
00 04
00
84
C1 D1
81 09
26 10
CMPA #7
BNE CHK_REG8
#4
0,X
HL
ADDRESS_DISPLAY
LDAA #4
JSR DATA_DISPLAY
RTS
CHK_REG9
00 06
00
84
C1 D1
CMPA #9
BNE CHK_REGA
LDX
LDX
STX
JSR
86 06
BD C1 C3
39
#6
0,X
HL
ADDRESS_DISPLAY
LDAA #6
JSR DATA_DISPLAY
RTS
CHK_REGA
39
RTS
39
RTS
39
RTS
Page 29 of 40
MON68.LST
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
C89C
C89C
C89C
C89C
C89F
C8A1
C8A3
C8A5
C8A7
C8A8
C8A8
C8A8
C8A8
C8AB
C8AD
C8AF
C8B1
C8B3
C8B4
C8B4
C8B4
C8B4
C8B4
C8B7
C8B9
C8BB
C8BD
C8BF
C8C0
C8C0
C8C0
C8C0
C8C0
C8C3
C8C5
C8C7
C8C9
C8CB
C8CC
C8CC
C8CC
C8CC
C8CF
C8D1
C8D3
C8D5
C8D7
C8D8
C8D8
C8D8
C8D8
C8D8
C8D8
C8D9
C8D9
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DA
C8DD
C8DD
C8DF
C8E1
C8E1
C8E3
2/11/2558 17:06
;-----------------------------------------------------------BD
86
97
86
97
39
C7 15
AE
8C
02
8D
HEX_REL
JSR HEX_ADDR
LDAA #0AEH
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
BD
86
97
86
97
39
C7 15
B3
8C
02
8D
HEX_REL6
JSR HEX_ADDR
LDAA #0B3H
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
HEX_COPY31
BD
86
97
86
97
39
C7 15
AE
8C
02
8D
JSR HEX_ADDR
LDAA #0AEH
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
HEX_COPY32
BD
86
97
86
97
39
C7 15
8F
8C
02
8D
JSR HEX_ADDR
LDAA #08FH
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
HEX_COPY33
BD
86
97
86
97
39
C7 15
B3
8C
02
8D
JSR HEX_ADDR
LDAA #0B3H
STAA BUFFER
LDAA #2
STAA BUFFER+1
RTS
39
HEX_SEND_FILE
RTS
39
HEX_SEND_FILE2
RTS
;
;
;
;
;
SCAN DISPLAY AND KEYBOARD
ENTRY: DISPLAY BUFFER IN PAGE 0
EXIT: KEY = -1 NO KEY PRESSED
KEY >=0 KEY POSITION
REGSITERS USED: X,A,Y
SCAN1
CE 00 8C
LDX #BUFFER
86 00
97 83
SCAN2
LDAA #0
STAA REG_C
86 FF
97 93
LDAA #-1
STAA KEY
Page 30 of 40
MON68.LST
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
C8E5
C8E5
C8E7
C8E9
C8E9
C8EB
C8ED
C8ED
C8ED
C8EF
C8EF
C8F1
C8F1
C8F3
C8F3
C8F6
C8F6
C8F8
C8FB
C8FB
C8FB
C8FB
C8FE
C8FE
C8FE
C8FE
C8FE
C8FE
C8FE
C900
C903
C903
C905
C906
C908
C908
C908
C90A
C90C
C90C
C90F
C90F
C911
C911
C911
C914
C914
C916
C916
C918
C91A
C91A
C91D
C91D
C920
C922
C922
C923
C923
C925
C926
C928
C928
C928
C92B
C92D
C92E
C92E
C92E
C930
C931
C933
C934
C934
C934
C934
2/11/2558 17:06
86 01
97 80
LDAA #1
STAA REG_E
86 06
97 84
LDAA #6
STAA HL
96 80
;to the active column.
KCOL
LDAA REG_E
88 FF
EORA #0FFH
; COMPLEMENT IT
84 BF
ANDA #0BFH
; MUST BE LOW FOR BREAK
B7 80 02
STAA DIGIT
A6 00
B7 80 03
LDAA 0,X
STAA SEG7
; automatic adjust for 1-3 segment display
BD C9 34
JSR AUTOBRIGHTNESS
;
;DELAY3
;
LDAB #$30
DECB
BNE DELAY3
86 00
B7 80 03
LDAA #0
STAA SEG7
; TURN LED OFF
C6 32
5A
26 FD
LDAB #50
DELAY10 DECB
BNE DELAY10
86 06
97 82
LDAA #6
STAA REG_B
B6 80 01
LDAA KIN
97 81
STAA
74 00 81
25 04
KROW LSR REG_D
;Rotate D 1 bit right, bit 0
;of D will be rotated into
BCS NOKEY
;carry flag.
96 83
97 93
LDAA REG_C
STAA KEY
7C 00 83
NOKEY INC REG_C
7A 00 82
26 EF
DEC REG_B
BNE KROW
08
INX
96 80
48
97 80
LDAA REG_E
ASLA
STAA REG_E
7A 00 84
26 C0
39
DEC
BNE
RTS
C6 C8
5A
26 FD
39
DEBOUNCE LDAB #200
DELAY4
DECB
BNE DELAY4
RTS
REG_D
;Increase current key-code by 1.
HL
KCOL
; ADJUST TIME ON IF EQUAL OR LESS THAN 3 BITS ON
AUTOBRIGHTNESS
Page 31 of 40
MON68.LST
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2359
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2369
2370
2371
2372
2373
2374
2375
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2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
C934
C934
C935
C937
C937
C939
C939
C93A
C93C
C93F
C93F
C93F
C940
C942
C942
C944
C944
C946
C948
C948
C94A
C94B
C94D
C94E
C94E
C94E
C94E
C94E
C94E
C950
C951
C953
C954
C954
C954
C954
C954
C954
C954
C954
C954
C954
C954
C954
C957
C959
C95B
C95D
C95D
C960
C962
C964
C964
C967
C969
C969
C969
C969
C969
C969
C96B
C96D
C96D
C970
C973
C975
C975
C975
C978
C97A
C97A
C97A
C97D
C97D
C97D
C97D
2/11/2558 17:06
5F
D7 CB
CLRB
STAB BIT1_COUNTER
C6 08
LDAB #8
49
24 03
7C 00 CB
CHECK_BIT1 ROLA
BCC _BIT1
INC BIT1_COUNTER
_BIT1
5A
26 F7
DECB
BNE CHECK_BIT1
96 CB
LDAA BIT1_COUNTER
81 03
2E 06
CMPA #3
BGT NORMAL
C6 03
5A
26 FD
39
DELAY20
; DIMMING FOR <=4 BITS THAT ON
LDAB #3
DECB
BNE DELAY20
RTS
NORMAL
C6 30
5A
26 FD
39
DELAY3
LDAB #$30
DECB
BNE DELAY3
RTS
; tested with 20h 30
;-------------------------------------------------------------------BD
96
81
27
C8 DA
93
FF
1D
B6 80 01
84 40
27 05
BD C9 2E
20 EB
SCANKEY JSR SCAN1
LDAA KEY
CMPA #-1
BEQ KEY_RELEASED
LDAA PORT0
ANDA #40H
BEQ SKIP_DISPLAY5
JSR DEBOUNCE
BRA SCANKEY
SKIP_DISPLAY5
86 14
97 AD
; IF REPEAT KEY WAS PRESSED, SLOW DOWN IT
LDAA #20
STAA REPDELAY
BD C8 DA
7A 00 AD
26 F8
DISPLAY4 JSR SCAN1
DEC REPDELAY
BNE DISPLAY4
CE 00 00
DF 92
LDX #0
STX INVALID
KEY_RELEASED
BD C9 2E
JSR DEBOUNCE
; THEN REPEAT KEY PRESS
; RESET INVALID FLAG
UNTIL_PRESS
BD C8 DA
JSR SCAN1
Page 32 of 40
MON68.LST
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2435
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2438
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2440
2441
2442
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2444
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2446
2447
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2449
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2477
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2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
C980
C982
C984
C986
C986
C989
C989
C98C
C98C
C98E
C991
C991
C993
C993
C995
C997
C997
C999
C99B
C99D
C99D
C99F
C99F
C9A1
C9A1
C9A1
C9A1
C9A2
C9A2
C9A2
C9A5
C9A5
C9A8
C9A8
C9AB
C9AB
C9AD
C9AD
C9AD
C9AD
C9AD
C9AD
C9AD
C9AD
C9AD
C9B0
C9B2
C9B4
C9B4
C9B6
C9B8
C9BA
C9BB
C9BB
C9BB
C9BB
C9BE
C9BE
C9C0
C9C3
C9C6
C9C8
C9CB
C9CE
C9CE
C9CF
C9D1
C9D1
C9D1
C9D1
C9D2
C9D2
C9D2
C9D2
C9D2
C9D2
2/11/2558 17:06
96 93
81 FF
27 F7
LDAA KEY
CMPA #-1
BEQ UNTIL_PRESS
BD C9 2E
JSR DEBOUNCE
BD C8 DA
JSR SCAN1
96 93
CE CC 0B
LDAA KEY
LDX
#KEYTAB
DF B0
STX
TEMP16
9B B1
97 B1
ADDA TEMP16+1
STAA TEMP16+1
86 00
99 B0
97 B0
LDAA #0
ADCA TEMP16
STAA TEMP16
DE B0
LDX TEMP16
A6 00
LDAA
;
39
0,X
; OPEN TABLE
STAA GPIO1
; TEST NOW A IS INTERNAL CODE
RTS
BD C9 54
MAIN
JSR SCANKEY
; scan display and keypad
BD C3 03
JSR KEYEXE
; execute key that pressed
BD C9 AD
JSR BEEP
; beep/no beep after key executed
20 F5
BRA MAIN
; repeat forever
;--------------------------------------------------------; BEEP WHEN KEY PRESSED
;
; CALIBRATED TO 523Hz
; NEW FREQUENCY 673Hz, TESTED 670Hz
B6 80 01
84 40
27 1D
BEEP
LDAA PORT0
ANDA #40H
BEQ NO_BEEP
; CHECK IF REPEAT KEY IS PRESSED, THEN NO BEEP
96 CA
81 00
27 01
39
LDAA MUTE
CMPA #0
BEQ BEEPON
RTS
; IF MUTE=1 THEN NO BEEP
LDX #35h
;
CE 00 35
BEEPON
86
B7
BD
86
B7
BD
BEEP2
LDAA #3FH
STAA PORT1
JSR BEEP_DELAY
LDAA #0BFH
STAA PORT1
JSR BEEP_DELAY
3F
80
C9
BF
80
C9
09
26 ED
02
D2
02
D2
BEEP_PERIOD
DEX
BNE BEEP2
NO_BEEP
39
C6 52
RTS
BEEP_DELAY LDAB #52H
;
#78H
Page 33 of 40
; #09BH CALIBRATED 524Hz
MON68.LST
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2510
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2512
2513
2514
2515
2516
2517
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2520
2521
2522
2523
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2525
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2527
2528
2529
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2531
2532
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2534
2535
2536
2537
2538
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2541
2542
2543
2544
2545
2546
2547
2548
2549
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2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
C9D4
C9D5
C9D7
C9D8
C9D8
C9D8
C9D8
C9D8
C9D8
C9D8
C9D8
C9D9
C9DC
C9DE
C9E0
C9E0
C9E3
C9E4
C9E6
C9E7
C9E7
C9E7
C9E7
C9E7
C9E9
C9EC
C9EE
C9F0
C9F3
C9F5
C9F7
C9F9
C9F9
C9F9
C9FB
C9FC
C9FE
C9FF
C9FF
C9FF
C9FF
C9FF
C9FF
C9FF
CA02
CA02
CA04
CA04
CA06
CA09
CA0B
CA0E
CA0E
CA10
CA11
CA13
CA14
CA14
CA14
CA14
CA14
CA14
CA14
CA16
CA18
CA18
CA19
CA19
CA19
CA19
CA1B
CA1B
CA1E
CA1E
CA20
CA21
2/11/2558 17:06
5A
26 FD
39
BEEP_LOOP DECB
BNE BEEP_LOOP
RTS
; TEST CODE
4C
B7 80 00
8D 02
20 F8
TEST
INCA
STAA GPIO1
BSR DELAY_LED
BRA TEST
CE 07 D0
09
26 FD
39
DELAY_LED LDX #2000
DELAY_LED1 DEX
BNE DELAY_LED1
RTS
; TEST BEEP
86
B7
8D
86
B7
8D
26
20
3F
80 02
0B
BF
80 02
04
F0
EE
C6 A0
5A
26 FD
39
BEEP3
LDAA #3FH
STAA PORT1
BSR BEEP_DELAY1
LDAA #0BFH
STAA PORT1
BSR BEEP_DELAY1
BNE BEEP3
BRA BEEP3
BEEP_DELAY1 LDAB #0A0H
BEEP_LOOP1 DECB
BNE BEEP_LOOP1
RTS
;
; CLEAR DISPLAY
CE 00 32
CLR_SCREEN LDX #50
DF B0
CLR_SCREEN1 STX TEMP16
86
BD
86
BD
0D
C0 88
0A
C0 88
LDAA #13
JSR SEND_BYTE
LDAA #10
JSR SEND_BYTE
DE B0
09
26 EF
39
LDX TEMP16
DEX
BNE CLR_SCREEN1
RTS
; PRINT STRING TO TERMINAL USING 2400 UART
; ENTRY: IX POINTED TO STRING
A6 00
26 01
39
PSTR
LDAA 0,X
BNE SEND_STRING
RTS
SEND_STRING
DF B2
STX IX2
BD C0 88
JSR SEND_BYTE
DE B2
08
20 F1
LDX IX2
INX
BRA PSTR
Page 34 of 40
MON68.LST
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2587
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2589
2590
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2592
2593
2594
2595
2596
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2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA23
CA24
CA27
CA29
CA2B
CA2C
CA2D
CA2D
CA2D
CA2D
CA30
CA33
CA34
CA34
CA34
CA37
CA3A
CA3B
CA3B
CA3B
CA3E
CA40
CA43
CA44
CA44
CA46
CA49
CA4B
CA4E
CA51
CA53
CA55
CA58
CA59
CA59
CA59
CA59
CA59
CA59
CA59
CA5B
CA5D
CA5F
CA62
CA63
CA63
CA65
CA67
CA69
CA6C
CA6D
CA6D
CA6E
CA6E
CA6E
CA6E
CA6E
CA6E
CA6E
2/11/2558 17:06
;-------------------- HARDWARE DRIVERS------------------------; TEXT MODE LCD DRIVERS
; wait until LCD ready bit set
36
B6 90 02
84 80
26 F9
32
39
LcdReady
ready
PSHA
LDAA command_read
ANDA #BUSY
BNE ready
; loop if busy flag = 1
PULA
RTS
LCD_command_write
BD CA 23
B7 90 00
39
JSR LcdReady
STAA command_write
RTS
BD CA 23
B7 90 01
39
LCD_data_write
BD CA 23
86 01
BD CA 2D
39
clr_screen
86
BD
86
BD
BD
86
C6
BD
39
InitLcd
38
CA
0C
CA
CA
00
00
CA
JSR LcdReady
STAA data_write
RTS
JSR LcdReady
LDAA #1
JSR LCD_command_write
RTS
2D
2D
3B
59
LDAA #38H
JSR LCD_command_write
LDAA #0CH
JSR LCD_command_write
JSR clr_screen
LDAA #0
LDAB #0
JSR goto_xy
RTS
; goto_xy(x,y)
; entry: A = x position
;
B = y position
C1
26
8B
BD
39
00
06
80
CA 2D
C1
26
8B
BD
39
01
06
C0
CA 2D
goto_xy
BNE case1
CMPB #0
ADDA #80H
JSR LCD_command_write
RTS
39
case1
CMPB #1
BNE case2
ADDA #0C0H
JSR LCD_command_write
RTS
case2
RTS
; write ASCII code to LCD at current position
; entry: A
BD CA 34
putch_lcd
JSR LCD_data_write
Page 35 of 40
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2724
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2736
CA71
CA72
CA72
CA72
CA72
CA72
CA72
CA72
CA72
CA72
CA74
CA76
CA77
CA77
CA79
CA7C
CA7E
CA7F
CA81
CA81
CA81
CA81
CA81
CA84
CA84
CA87
CA8A
CA8A
CA8C
CA8E
CA91
CA94
CA97
CA97
CA97
CA98
CA98
CA98
CA98
CA98
CA98
CA9A
CA9A
CA9D
CA9F
CAA1
CAA3
CAA3
CAA3
CAA6
CAA7
CAA9
CAAA
CAAA
CAAA
CAAA
CAAA
CAAC
CAAC
CAAF
CAB1
CAB2
CAB4
CAB4
CAB4
CAB4
CAB4
CAB6
CAB6
CAB9
CABB
CABD
CABE
CAC0
CAC0
CAC0
2/11/2558 17:06
39
RTS
; print strings on the LCD
; entry: IX pointed to string
A6 00
26 01
39
pstring
LDAA 0,X
BNE PSTRING1
RTS
DF
BD
DE
08
20
PSTRING1
STX
JSR
LDX
INX
BRA
B2
CA 6E
B2
F1
IX2
putch_lcd
IX2
pstring
; DEMO LCD 20X2 BIG LETTERS LCD
BD CA 44
DEMO_LCD
JSR InitLcd
CE CB 65
BD CA 72
LDX #TEXT1
JSR pstring
86
C6
BD
CE
BD
LDAA #0
LDAB #1
JSR goto_xy
LDX #TEXT2
JSR pstring
00
01
CA 59
CB 75
CA 72
39
RTS
; BINARY COUNTING
#1
86 00
DEMO_LED
B7
8D
8B
20
DEMOLOOP STAA GPIO1
BSR DEMODELAY
ADDA #1
BRA DEMOLOOP
80 00
04
01
F7
CE 00 00
09
26 FD
39
LDAA #0
DEMODELAY
LDX #0000
DEMODELAY1
DEX
BNE DEMODELAY1
RTS
; RUNNING DOT LED
PRM #0
86 01
RUN_DOT
LDAA #1
B7 80 00
8D F2
49
20 F8
RUN_DOT1 STAA GPIO1
BSR DEMODELAY
ROLA
BRA RUN_DOT1
; BCD COUNTING
#2
86 00
BCD_COUNTING LDAA #0
B7
8D
8B
19
20
BCD_COUNT1
80 00
E8
01
F6
STAA GPIO1
BSR DEMODELAY
ADDA #1
DAA
BRA BCD_COUNT1
Page 36 of 40
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2786
2787
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2793
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2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
CAC0
CAC0
CAC0
CAC0
CAC0
CAC0
CAC0
CAC0
CAC2
CAC4
CAC6
CAC8
CACA
CACA
CACB
CACD
CACD
CACF
CAD1
CAD2
CAD4
CAD6
CAD8
CAD8
CAD9
CADB
CADB
CADD
CADF
CAE0
CAE2
CAE4
CAE6
CAE7
CAE9
CAE9
CAEB
CAED
CAEF
CAF1
CAF3
CAF3
CAF4
CAF6
CAF6
CAF6
CAF6
CAF7
CAF7
CAF7
CAF7
CAF7
CAF7
CAF9
CAFB
CAFB
CAFD
CAFF
CB01
CB03
CB03
CB04
CB06
CB08
CB0A
CB0C
CB0E
CB0E
CB0E
CB0F
CB0F
CB0F
CB0F
CB0F
CB11
CB14
2/11/2558 17:06
; UPDATE CLOCK VARIABLES
; ENTER EVERY 10ms FROM IRQ INTERRUPT
SERVICE_IRQ
96
8B
97
81
26
CC
01
CC
64
2C
LDAA
ADDA
STAA
CMPA
BNE
SEC100
#1
SEC100
#100
EXIT_CLOCK
4F
97 CC
CLRA
STAA SEC100
96
8B
19
97
81
26
LDAA SEC
ADDA #1
DAA
STAA SEC
CMPA #60H
BNE EXIT_CLOCK
CD
01
CD
60
1E
4F
97 CD
CLRA
STAA SEC
96
8B
19
97
81
26
4F
97
CE
01
CE
LDAA MIN
ADDA #1
DAA
STAA MIN
CMPA #60H
BNE EXIT_CLOCK
CLRA
STAA MIN
96
8B
97
81
26
CF
01
CF
24
03
LDAA HOUR
ADDA #1
STAA HOUR
CMPA #24H
BNE EXIT_CLOCK
CE
60
10
4F
97 CF
CLRA
STAA HOUR
EXIT_CLOCK
3B
RTI
; CLOCK PROGRAM #3 TEST 10ms TICK MAKING CLOCK DISPLAY
86 7E
97 F8
CLOCK_PGM
LDAA #7EH
STAA $F8
; INSERT HEX CODE FOR JMP SERVICE_IRQ
86
97
86
97
CA
F9
C0
FA
LDAA
STAA
LDAA
STAA
#SERVICE_IRQ>>8
$F9
#SERVICE_IRQ&$FF
$FA
4F
97
97
97
97
97
CC
CD
CE
CF
D0
CLRA
STAA
STAA
STAA
STAA
STAA
SEC100
SEC
MIN
HOUR
RUNSTOP
0E
CLI
; ENABLE IRQ
DISPLAY_CLOCK
96 CC
BD C1 C3
LDAA SEC100
JSR DATA_DISPLAY
Page 37 of 40
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2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
CB14
CB16
CB18
CB1A
CB1C
CB1F
CB1F
CB21
CB23
CB25
CB25
CB27
CB29
CB2B
CB2B
CB2B
CB2B
CB2E
CB2E
CB30
CB32
CB34
CB34
CB36
CB38
CB38
CB39
CB3B
CB3D
CB3F
CB41
CB41
CB41
CB41
CB41
CB41
CB43
CB43
CB43
CB43
CB43
CB43
CB43
CB43
CB43
CB43
CB43
CB43
CB46
CB48
CB48
CB48
CB4A
CB4C
CB4C
CB4C
CB4C
CB4E
CB4E
CB50
CB50
CB50
CB50
CB50
CB52
CB55
CB55
CB58
CB5A
CB5A
CB5C
CB5D
CB5F
CB5F
CB62
CB64
2/11/2558 17:06
96
97
96
97
BD
CD
85
CE
84
C1 D1
LDAA SEC
STAA HL+1
LDAA MIN
STAA HL
JSR ADDRESS_DISPLAY
96 8E
8A 40
97 8E
LDAA BUFFER+2
ORAA #$40
STAA BUFFER+2
96 90
8A 40
97 90
LDAA BUFFER+4
ORAA #$40
STAA BUFFER+4
BD C8 DA
JSR SCAN1
96 93
81 FF
27 0D
LDAA KEY
CMPA #-1
BEQ SKIP_SHOW_KEY
81 21
26 09
CMPA #21H
BNE SKIP_SHOW_KEY
4F
97
97
97
97
CLRA
STAA
STAA
STAA
STAA
CC
CD
CE
CF
;
SEC100
SEC
MIN
HOUR
STAA GPIO1
SKIP_SHOW_KEY
20 CC
BRA DISPLAY_CLOCK
;
;
;
;
CHECK KEY
+
CODE
ADDR CODE
GO
CODE
PRESSED
21H
1BH
16H
DISPLAY_START_MSG
CE CB F5
DF B0
LDX #START_MSG+6
STX TEMP16
86 06
97 D1
LDAA #6
STAA K
DISPLAY_MSG1
86 20
LDAA #$20
97 D2
STAA J
DISPLAY_START1
DE B0
BD C8 DD
LDX TEMP16
JSR SCAN2
7A 00 D2
26 F6
DEC J
BNE DISPLAY_START1
DE B0
09
DF B0
LDX TEMP16
DEX
STX TEMP16
7A 00 D1
26 E8
DEC K
BNE DISPLAY_MSG1
Page 38 of 40
MON68.LST
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2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
CB64
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB65
CB6B
CB75
CB7B
CB88
CB88
CB8E
CBA7
CBA7
CBA7
CBA7
CBA7
CBA7
CBAD
CBB6
CBBC
CBD0
CBD6
CBDD
CBE3
CBEF
CBEF
CBF0
CBF1
CBF2
CBF3
CBF4
CBF5
CBF6
CBF7
CBF8
CBF9
CBFA
CBFB
CBFB
CBFB
CBFC
CBFD
CBFE
CBFF
CC00
CC01
CC02
CC03
CC04
CC05
CC06
CC07
CC08
CC09
CC0A
CC0B
CC0B
2/11/2558 17:06
39
RTS
;ssssssssssssssssssssssssss STRINGS CONSTANT sssssssssssssssssssssssssss
;
20204D6F746FTEXT1
726F6C61203638303200
4D6963726F70TEXT2
726F636573736F72204B697400
.BYTE "
Motorola 6802",0
.BYTE "Microprocessor Kit",0
0D0A36383032TEXT3
.BYTE 13,10,"6802 MICROPROCESSOR KIT V1.0",0
204D4943524F50524F434553534F52204B49542056312E3000
0D0A50726573DOWNLOAD .BYTE 13,10,"Press key GO",0
73206B657920474F00
0D0A436C6963DOWNLOAD2 .BYTE 13,10,"Click File>Send File>..",0
6B2046696C653E53656E642046696C653E2E2E00
0D0A4E6F2065COMPLETE .BYTE 13,10,"No error..",0
72726F722E2E00
0D0A43686563ERROR_FOUND .BYTE 13,10,"Checksum error!",0
6B73756D206572726F722100
00
00
9B
BD
BF
AF
00
00
00
00
00
00
START_MSG .BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE 0AFH
.BYTE
.BYTE 0
.BYTE 0
.BYTE 0
.BYTE 0
.BYTE
BD
30
9B
BA
36
AE
AF
38
BF
BE
3F
A7
8D
B3
8F
0F
SEGTAB
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
.BYTE
030H
09BH
0BAH
036H
0AEH
0AFH
038H
0BFH
0BEH
03FH
0A7H
08DH
0B3H
08FH
00FH
0
0
9BH
0BDH
0BFH
0
0
0BDH
;'1'
;'2'
;'3'
;'4'
;'5'
;'6'
;'7'
;'8'
;'9'
;'A'
;'B'
;'C'
;'D'
;'E'
;'F'
;'0'
Page 39 of 40
MON68.LST
2/11/2558 17:06
2958
CC0B
2959
CC0B
; Key-posistion-code to key-internal-code conversion table.
2960
CC0B
2961
CC0B
KEYTAB:
2962
CC0B 03
K0 .BYTE 03H ;HEX_3
2963
CC0C 07
K1 .BYTE 07H ;HEX_7
2964
CC0D 0B
K2 .BYTE 0BH ;HEX_B
2965
CC0E 0F
K3 .BYTE 0FH ;HEX_F
2966
CC0F 20
K4 .BYTE 20H ;NOT USED
2967
CC10 21
K5 .BYTE 21H ;NOT USED
2968
CC11 02
K6 .BYTE 02H ;HEX_2
2969
CC12 06
K7 .BYTE 06H ;HEX_6
2970
CC13 0A
K8 .BYTE 0AH ;HEX_A
2971
CC14 0E
K9 .BYTE 0EH ;HEX_E
2972
CC15 22
K0A .BYTE 22H ;NOT USED
2973
CC16 23
K0B .BYTE 23H ;NOT USED
2974
CC17 01
K0C .BYTE 01H ;HEX_1
2975
CC18 05
K0D .BYTE 05H ;HEX_5
2976
CC19 09
K0E .BYTE 09H ;HEX_9
2977
CC1A 0D
K0F .BYTE 0DH ;HEX_D
2978
CC1B 13
K10 .BYTE 13H ;STEP
2979
CC1C 1F
K11 .BYTE 1FH ;TAPERD
2980
CC1D 00
K12 .BYTE 00H ;HEX_0
2981
CC1E 04
K13 .BYTE 04H ;HEX_4
2982
CC1F 08
K14 .BYTE 08H ;HEX_8
2983
CC20 0C
K15 .BYTE 0CH ;HEX_C
2984
CC21 12
K16 .BYTE 12H ;GO
2985
CC22 1E
K17 .BYTE 1EH ;TAPEWR
2986
CC23 1A
K18 .BYTE 1AH ;CBR
2987
CC24 18
K19 .BYTE 18H ;PC
2988
CC25 1B
K1A .BYTE 1BH ;REG
2989
CC26 19
K1B .BYTE 19H ;ADDR
2990
CC27 17
K1C .BYTE 17H ;DEL
2991
CC28 1D
K1D .BYTE 1DH ;RELA
2992
CC29 15
K1E .BYTE 15H ;SBR
2993
CC2A 11
K1F .BYTE 11H ;2994
CC2B 14
K20 .BYTE 14H ;DATA
2995
CC2C 10
K21 .BYTE 10H ;+
2996
CC2D 16
K22 .BYTE 16H ;INS
2997
CC2E 1C
K23 .BYTE 1CH ;MOVE
2998
CC2F
2999
CC2F
3000
CC2F
3001
CC2F
; VECTOR NMI,RESET AND IRQ
3002
CC2F
3003
CC2F
3004
FFF8
.ORG 0FFF8H
3005
FFF8
3006
FFF8 00 F8
.BYTE 0,0F8H ; RELOCATE IRQ TO RAM VECTOR AT 00F8H
3007
FFFA
3008
FFFA
3009
FFFA
.ORG 0FFFAH
; SWI VECTOR
3010
FFFA
3011
FFFA C6 5C
.BYTE SWI_SERVICE>>8,SWI_SERVICE&$FF
3012
FFFC
3013
FFFC
3014
FFFC
.ORG 0FFFCH
; NMI VECTOR
3015
FFFC
3016
FFFC C6 55
.BYTE NMI_SERVICE>>8,NMI_SERVICE&$FF
3017
FFFE
3018
FFFE
3019
FFFE
.ORG 0FFFEH
3020
FFFE
3021
FFFE C0 00
.BYTE $C0,00
; RESTART
3022
0000
3023
0000
3024
0000
3025
0000
3026
0000
.END
3027
0000
3028
0000
3029
0000
tasm: Number of errors = 0
Page 40 of 40
NOTE