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Download SECTION 8 EXCEPTION PROCESSING
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Int ctl cyc1 Int ctl cyc2 Fetch Decode Execute i ii n n3 n4 n5 † * = = = = = = i n3 n2 n1 † i n4 REP n2 i* n5 NOP REP n4 NOP n4 n4 i n6 n5 n4 ii1 n6 n5 ii2 ii1 n6 n7 ii2 ii1 n8 n7 ii2 n9 n8 n7 interrupt interrupt instruction word normal instruction word REP #2 instruction instruction being repeated twice instruction that waits in the backup instruction latch interrupt rejected at this time interrupt can be reenabled at this time Figure 8-5. Example Of Interrupt Service When Interrupt Is Presented To REP Instruction 8.4 INTERRUPT SOURCES Exceptions may originate from a number of interrupt sources. The DSP96002 interrupt sources are given in Figure 8-6. The corresponding interrupt starting addresses for each interrupt source are shown. Interrupt starting addresses are internally-generated 32-bit addresses which point to the starting address of the fast interrupt service routine. The interrupt starting address for each interrupt is an address constant for minimum overhead. Motorola reserves 128 interrupt starting address locations, while 128 locations are reserved for user applications. These locations occupy the lowest 512 words of program memory space, except for Hardware Reset, which may also occupy a location in the upper range of the program memory address. If some of this space is not used, it may be used for program storage. 8.4.1 Internal Peripheral Interrupt Sources The internal peripheral interrupt sources include all of the on-chip peripheral devices (Host and DMA). Each internal interrupt source is level sensitive; i.e., each is serviced any time it is present and the interrupt is not masked. Each internal hardware source has independent enable control. 8.4.2 Hardware RESET The Hardware RESET interrupt is level sensitive and is the highest priority 3 interrupt. It is caused by as— — — — – serting the R E S E T pin. 8.4.3 External Interrupt Requests IRQA, IRQB and IRQC The IRQA, IRQB and IRQC interrupts can be programmed to be level-sensitive or edge-sensitive. Levelsensitive interrupts are not internally latched and are not automatically cleared when they are serviced; they must be cleared by other means to prevent multiple interrupts. The edge-sensitive interrupts are latched as pending on the high-to-low transition of the interrupt input and are automatically cleared when the interrupt is serviced. IRQA, IRQB and IRQC can be programmed to one of three priority levels: level 0, 1, or 2, all of MOTOROLA DSP96002 USER’S MANUAL 8-7
