Download RML 480Z Service Manual

OZ
SERVIOEMANUAL
AND t80Z
SERVICE IlANUAL
PH 13821
Copyright
e 1984 by Research Machines Limited
All rights reserved. Copies of this publication aay be IUde by
customers exclusively for their OWDuse, but otherwise no part of
it lUy
reproduced, transmittea, t:.ranscribed, stored in a
retrieval
or t:.ranslated into any language or computer
language
the prior written permission of Research
Machines Limited, Mill St. OXford, Bngland. OX2 OBW.
Tel
Oxford (0865) 249866.
Research Machines has a policy of cont.inuous development and
improvement of it.s products and services, and the right. is
reserved to revise t.his manual or to make changes in the
computer software
describes without not.ice. Research Machines
endeavour t.o ensure the accuracy of this manual and t.hat. t.he
products described perform correctly according to their
descriptions. However Research Machines Limited do not. accept
liability for
consequences of any error or OIIission.
Additional copies of this publicat.ion may be ordered from
Research Machines Limited at the address above. Please ask for
t.he title as given above.
Manual
SBCTION 1
SBCTION2
MAIN
21
Mode
8U-CJ!1a1rat~t:..!r
.ft
Read Ports
Write Ports
2.8
2.13
2 14
2.14
PCB
3.1
Ii' ._",,- -,
_,WII
SVII~8~.
3
Mode
3.1
SECTION 4
POWER
SUPPLY
4.
Mains Pilter and .~'V~•• ~~~VA
Converter
4.1
4.1
4 1
4.2
4.2
4.4
2.1
2.2
2.3
2.4
2.5
and Clocks
2.
3.1
3.2
3.3
3.4
3.5
3.6
4.1
Power
(
ref
10)
1.
2.
3.
to as
from
•
and
flows
and any
TR5 base.
•1
480Z
•
Selected
There
from
which
the resonant
current
to oscillate.
oscillates
and an
appears at the collector. C1
the base of TR2.
the emitter of TR3
then starts to conduct,
the
on C3 flows
to
C4 and
Thus TRS collector
from
, C3
C4
halfturned off)
Once a
a
1)
of this
sent to the
, the Q
no residual
the
must
some sort
memory is
the start of each address
IC 3a} is clocked into IC
scanned. As
4 is
the
state
the end
As
to all
receives a
data.
as are strobe
oscillator)
and
returned to normal when the CPU
1.2
480Z
I
•
a
r
JI'
'---,-_ ...
10
CJ
I
•...
.
3.
(I
"•
18
o
G
tI•
. ..
o
... ...u
II')
u
U
1.
....
....•
••
I
I-
MAIN
ref.
D1
1 to
1
DR
and
1.
2.1
80
480Z Main PCB
refresh the whole of memory.
.
.....
N
..
IG
2 2
480Z
Main PCB
480Z Main PCB
SHEET 2
memory map PROM that decodes
It
lines to enable RAM
as the
PAGE 1 and ZRD
a reset
0000 for its
1,
initialization, PAGE
so that in normal
isa 4 x 4-bit
that it can be altered under software
to
of
will
2.3 shows the
41
or 4
Lines
upon which
are decoded
JT to
and MA 7 define the
and
go to RAM
the
PCB. Lines MA14 and
on the main board I
and
select the
MA15 are used when 4164 (
address
16K block within
of the
16 address lines) and so
is the
256K memory if
the contents ofER to make
14 address lines
MR, KR, and
are used
8+ for 4164's), and HT
RAM ICs (
lines
2.4 shows an
valid RAM address
Address lines
to RAM
decodes the
two
bank. At the start of
to connect A7 to A13
connected to
address lines
identical and
connec~ea
started when theZ80
JV to
1:.nr ouan the
1
inhibits
is disabled
banks of RAM
disabled
refresh,
the
derived
allow 4164 ICs
every 1.5 ma.
which
to
8RFSHB which is
RT
allows each half of the 4164's to be refreshed
within the 2ms limit
The
latches GT and GV are included to overcome a
of
known as
this is the minimum time that RAS must
between
is at its limit between M1 and
where
after the
of
480Z
MaINR to
RAS
80
5
480Z
Main PCB
-'
..,
0
ft
11 t 5
••
G
•
I \
0
I
I
I
\ ......--......
,
,
•to
•
~
.
f¥"t
N
0
....0
•~
it
-o
0
0
0
o
o
.ft
GO
.6
Main PCB
..
•
N
-.
..
<
•
,••
III
.7
Main PCB
SHEET 3
describes the
onboard from
are two banks
Each bank can
are
may consist
up to
suit the different
Pour RC:>M sockets are
PROM, and
the link
associated
4
and
for the differ·ent
4
of 4 1 or 1 bank
Different firmware and _..,...........,...
A 64K
be
available to
enabled
ROM or EPROM can be
in ROM is available as
PROM.
accommodated
character
A similar
the ·character
available to the
video
4
video
It
first
Mode
divided
clock.
EOC
of
to
I
takes 64ns i.e one
out the line waveform
number
lines of
PROM, CO
the PROM receives even addresses 0 to 126.
a
area
both sides of the screen
clocks the row counter HR,
These are fed to the character
IC
character
R3 is a convenient waveform
us) for use
the reset
( sheet )
clocks
to 31 of
addesses
as
line
.8
.e.
counts 0 to
480Z Main PCB
x
2
20.48ms
4BOZ Main PCB
•o
an
•
N
!
I
t
I
4(
-
-z. "
.
•....
~
Z
K
)-
~
.",
....u
~
",
"
"
:§
j
·r
Q
2
~
0
-z
III
•...-'
......
\.
"
J,
!
u...
·r
Q
480Z
•
•
•
\D
•
Ie
Ie
N
o
"
U
I
10
U
o -
o
o
o
I
~
• 1
480Z Main PCB
.a
...5
~:
I
.,
C'J
2. 2
Main PCB
in.t.ruction
line.
An
and
additional wait.
t. a
address an
.1:1~ll9
e<sge of 4MIIz
"sheet
the
n11llber
charact.er
(
CPU can read the contents of
RAM in a
si~lar
way
1nll't.]r:UC:t..J.. 0I1~S •
the counter JPis
t.he
widt.h
t.s
to
in the
e
screen
ry
now neces.ary,
is inhibit.ed
lliiott ....... lliiott".......
eet. are mixed at
2. 3
1M
480Z Main PCB
SHEET
Read
Read
I
1,
and are thus time
•
onto the bus
3
a
data into the latch and
data strobes from the
KBDREADY
bit
read
1. KBDSTB1 goes to the CTC (sheet 6)
program
The monitor program reads
service routine and stores it in a
use
the user
•
Write
•
and 5 have latched
Write
are cleared
must not be
CTC has been set up, and so
initialization firmware. Another
is that PAGE 0 and PAGE 1 are 'low' to
its
instruction from ROMO at address
-sheet 1).
initialization this is
so
RAM is addressed at the bottom of memory. NM1EN is
programs and enables
the monitor for
(
selects the screen format
to be
sheet 4 to select one of
goes to
is a DAC the
of which can be
two fonts. Write
(sheet 6) and is available
connected to the
2
ANALOGOUT.
The S102 interface is software controlled
(read and write •
CR
monostables
2 14
41:SUZ Ma1.n
and JT2 which
• value of resistance).
read
Both
SHEET 6
The 810
to
use
used either
This
or as a
time between
Ch1
three
functions
Ch2
Is used
to
•
network
to
a
sheet
various
2. 5
480Z
PCB
OPTION
ref.
D10830, Sheets
to
The two
banks
can be linked to
to 256K.
1
Resolution
2
In modes
mixed
the
between colour
in
3.1
480Z
PCB
medium resolution,
levels).
colours can
on the RGB
SHEET 2
BY buffers the
data bus to the I I I data bus when
the HRG
active) • The direction of data is controlled
• CT is
also enabled at
time and decodes the lower two address lines to strobe
the
- RD3 WRO data stable in
BY until
4MHZafter
and
go'
WRO - WR.3 to be used as strobes.
address out via
FW and GR
X
via
a
enable the
writes,
is
memory
• bus.
The
this
the main
64 to 79
format· used
video
on
columns
column
and
is
__
t_he memory via
In medium
are paqe 1. In
LCLCK
FU
fiiiiJ'iiiO . . 'iiiO ......... )
chain.
HRG
2 is usedfo·r
PCB
and HIRES
set thelllOde
o
o
and
3.
480Z
PCB
~
~
..
-et
-'
x
Q
...
:;
~
..
•
t")
Ii.
E
b
~
I
N
....I
-- ----
3
PCB
field
100 t.o 103 are enabled
t.o LAO t.o LA3. If
LKWR is act.ivat.ed at this t.ime, dat.a lat.ched in WRO can be written to the
table.
The CPU
memory
is
or
screen is
three conditions.
3
............................ 010:3 . . . . )
In extra
dat.a is
and white
'text.'
on
read fromHRG memory
must be divided
500ns
the shift
is enabled
and clocked out at 16MHz to
action, shown in
3.4, is
PCB.
BY and DV are used to
resolution
for
of the clock
4MHZ for
value is
t.o the
value (0 to 15) may
)
.per
to
The
WRO
the
time
used as a
state while
The
data bits in
address to be
in
this address is
and OV
are disabled
FBLANK
be activated to load the
Note that
the
write lines, and must return to
and data lines are still valid.
the main PCB is
data is
used to
of data into the shift
is taken from the main PCB and
enables the CPU
access
two extra clock
FBLNK from the main PCB is
used to ae]rlel~a't.e VMEME the
memory.
aO-character mode,
to
3 6
480Z
PCB
M-,
7
I
......-"2".... ("MHZ)
I
--IJII
t
I
I
·:---,2S,..
I
I
--..aI
('MHZ.)
I
I
Higt Ra. Pixels
I
I
--..
I
!-- 2S0ns ("-'MlHZ)
I
I
3.3
HRG Modes
3.8
480Z
--
..-
-- --
,....-.
~
-----
--
-
--
---
I
-~
~
•
o
I-
ea
~
1
.•...
.. '" •
1tI)..
...
480Z
PCB
0
('III
+
Ii
~
,...
1
•
-J
~.
~
3.10
}
'"
'0
480Z
]
3.
4BOZ
5
This sheet shows two dedicated ICs and a CTC:
•
BS is an IEEE interface cont.roller,
from t.he main
for
and
all the control functions
necessary for the int.erface. Processor
are
via
the CTC channel O. The IEEE address can
as a status in HRG
o
).
and BT are int.erface buffers.
•
•
maths funct.ions with a minimum of
are
CTC channel 1.
group of
select is
CTC channels 2 and 3
every Bms
can
used as a real-time clock: Ch.2
Ch.3 counts the
of Ch. 2
1 second intervals so that the processor
counter' in main memory.
3.12
4
FILTER AND
FLYBACK CONVERTER
480Z Power
to 05 cathode
C65 to
•
which is used to turn off TR3 and bias TR2 base.
As
after
to
If there is no
off occurs is
which
circuit
drive from T2.
reliable
rises until it is
the
off, TR2 turns off due
TR1 then turns off as
next. t.urn-off
, until all the energy
int.o the
circuits
of TR2 starts to fall at a
and the
inductance,
is
via
current at which turn
t.he
rail,
is
to the breakdown
When t.urned on or off and under
the
on C6 is reduced due to decreased
collector current is
to ensure
under all conditions.
SNUBBERS
transistor
current
value
current which
diode 0131
allows
At
value due
of T2 but
is
and C11.
on C1' is
at the
maximum TR3
exceeds this value, 022 conducts and
is
fed back to the
and
The
5-volt rail
reference of
01
this
If the
low
of
be
low and the current in OC1 will be low.. This
to anincrease
power
tends to
the initial error condition. R1
and C101 are
which stabilise
an effective
risk
Loads
and
and maximum
rail are
a.re
current drawn.
of each
TYPICAL LOAD
2.5A
.2SA
.OSA
+SV
4.3
MAX
480Z Power --__
' , r - ' -...
<
o~
~-
.3•
II
~
~
+
z
..,i:
I
.,.
....
<~
--
4.4
480Z Pault
U14.~~OEI1S
Guide
480Z
SBCTION
SBCTION 2
2•
•1
2.1
2 1
2.1
2.2
Reset
.3
Interface
2.3
2.3
2.3
2.4
SBCTION 3
3.1
SBCTION 4
4.1
3
U .1.41:1 QJ~IU.I..LIJI Q
a
Pault
(1)
480ZFault
Guide
1
At
one
and an internal
An
for use as a network station are also
This
LINK 480Z
the RML
is intended to
course for a basic
It serves to:
•
introduce the 480Z with a brief
block
of
circuit
•
one
•
correIators
•
with a
of
Q1agn0 se) and methods of
is unable to
software via PROMs
1
routes
flow
on fault.
conclude with
•1
and
unit, ( i.e.
Fault
2
SHTS 1..6
4MHz
the· 380Z
One 'wa.it·
STEP
•
2.1
VDUaccess
•
RAM
is controlled
two bits
the
four address bits
select which of the four banks
two bits
used to
within a
of
RAM is to
sixteen 16K pages to be
processor address space.
to
0 (see later •
•
table. This takes
addres 8 bus
5 and A 14) and
- MA17). Of these, MA16 and MA17
RAM is to be
while the
of
16K pages
any of the
any of the four 64K pages of
is controlled
vou
The VOU
for both
and
that
one 'wait' state is added to all accesses). The VOU is switchable
software control between
and 80 characters. However the
screen contents will be
on
and so the screen
should be cleared first. The VOU is
as
and
should
accessed
IN r C
OUT (C),r
OTI OTIR, INI, INIR
of
cases the
C will be the Y coordinate of the
character on the screen range
to
and the value in B
be
X coordinate (
0 to
Character 0,0 is at the
left. The value in r
be the character
from
back
the screen. Characters 128 to 91 are dim.
KEYBOARD
is of
or released-the
will return an 8-bit number
is available for future
travel.
number has
etc
treated as
(
the REPEAT
means that when a
a character. The
the
seventh bit
bit identifies the direction of
with ASCII
SHIFT, CTRL REPEAT,
of function
software control.
one of
Characters are
and
active.
A
up and it is
and
2.2
strobe
480Z
SYSTEM
section
is one
connected to
18 identical
bit for data
80 that it
the 380Z
The data
an
filtered
cassette
the
readable in
bit
is
consists
monostables
can
read
centre
read
SERIAL
software
and
There is also a
PORT
in
8104 RS232
the
SIO
B.
Port
is
latched
380Z if the
and
In addition
bits,
Fault
Guide
CONTROL PORTS
•
map
o
188
198
lAH
20 to
24 to
CTC
•
Port 0
DIL switches
Read
Write = RAM ................
table
10-"' ..........,....
Read
Bit
Write
7
x
6
x
5
x
4
x
]
OIL
OIL
DIL
2
1
o
MA16
MAl
MA14
o
least two
the address within
•
bits in the B
table to which the
Port
Read
Network
Network
Network
Hard USERIO
Soft UHAND
Frame Blank
Blank
Bit
Write
7
Network
4
Reset
Soft URAND]
Soft UHAND2
Soft URAND
NMIEN
]
2
1
o
1
480Z Pault
•
Port
Read
Bit
JB2
JB1
JT1
JT2
8102'
8102' HAND
Write
Select
ALTCHAR SET
6
5
JTRIG
'8102' TXD
4
2
1
CAS VOL
CA8MI
o
CASS IN
•
Guide
CA8WREN
Port 3
Read
Write
eTC USAGE
o
'8104
o
baud rates
2MHz
timer mode.
125KHz
Provides
and can
2
strobe
Generates
a
4
Generates
for
SIO USAGE:
,-n~!'I,n~II:I""
A
B
Network
8104' RS232 Port
5
3
Faults in
follows
480Z can be
Those
access
faults
which allow
Front
SIO
cassette.
2.
A
flow
fault
480Z Fault
Guide
··11...:.
"
on Screen
Insert RAM test PROM
address,
data buses
processor, etc.
N
.....-------~
y
Insert RAM
PROM.
Use scope to observe
test.
and
RAM
N
y
a
3.1
3.
Fault.
4
be
Use
for
Procedure
No
CP,
2. No Cassette
RAM
No Front
4.
• No
• Locks up
CONCLUSION
RAM,
on
ROM
ABUS,
areas
AU;
P.ft1(tJ-
"11
------0
",]
AU
"to
"q
~.
AI
))1 ..
tJ
1\7
''0
-----.t
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HPJ'
AS
OS '
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