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Download Altera Transceiver PHY IP Core User Guide
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UG-01080 2013.4.25 Custom PCS Word Addr Bits R/W 0x063 [31:0] R 0x064 [31:0] 0x065 Register Name 9-27 Description pma_rx_signaldetect When channel <n> =1, indicates that receive circuit for channel <n> senses the specified voltage exists at the RX input buffer. RW pma_rx_set_ locktodata When set, programs the RX CDR PLL to lock to the incoming data. Bit <n> corresponds to channel <n>. [31:0] RW pma_rx_set_locktoref When set, programs the RX CDR PLL to lock to the reference clock. Bit <n> corresponds to channel <n>. 0x066 [31:0] RO pma_rx_is_ lockedtodata When 1, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <n> corresponds to channel <n>. 0x067 [31:0] RO pma_rx_is_ lockedtoref When 1, indicates that the RX CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n>. Custom PCS Table 9-23: Custom PCS Word Addr Bits R/W 0x080 [31:0] RW [5:1] R 0x081 [0] R Register Name Lane or group number Description Specifies lane or group number for indirect addressing, which is used for all PCS control and status registers. For variants that stripe data across multiple lanes, this is the logical group number. For non-bonded applications, this is the logical lane number. rx_ This is an output from the bit slip word aligner bitslipboundaryselect which shows the number of bits slipped. out From block: Word aligner. rx_phase_comp_fifo_ error When set, indicates an RX phase compensation FIFO error. From block: RX phase Compensation FIFO 0x082 [0] RW tx_phase_comp_fifo_ error When set, indicates an TX phase compensation FIFO error. From block: TX phase Compensation FIFO Custom PHY IP Core Feedback Altera Corporation
