Download AUGH User Guide DEVELOPMENT VERSION INCOMPLETE

CHAPTER 7. HARDWARE TARGET SPECIFICATION
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techno set-chip xc7v585t
techno set-speed 3
target-freq 100M
7.3
FPGA boards
AUGH handles FPGA boards as synthesis target. Multi-FPGA boards are handled. For each FPGA
present, the board description includes:
• the FPGA reference (with speed grade, hardware resources and package),
• the position in the JTAG chain if applicable,
• the available connectivity.
The description of the available connectivity can include:
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the clock sources (with frequency),
the reset sources (with active state),
the UART interfaces (with recommended baudrate value and parity handling),
the rotary encoders,
the general purpose inputs and outputs (for LEDs, buttons...).
Currently board descriptions are declared with plugins. Descriptions of custom boards can be
handled with custom plugins.
Currently the plugin "xilinx" declares the description of the board XUPV5.
Example of command-line parameters to target a board:
-board xupv5
Corresponding commands for the command interpreter:
techno set-board xupv5