Download Texas Instruments TVP5154EVM User's Manual

TVP5154EVM
User's Guide
Literature Number: SLEU069A
February 2006 – Revised July 2006
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Contents
1
Functional Description................................................................................................. 6
1.1
2
3
4
5
6
7
8
9
Board Level Description
Test Points and Jumpers........................................................................................ 7
2.2
Common Board Interface
2.3
Video Input Description.......................................................................................... 8
2.4
Video Output Description
.......................................................................................
.......................................................................................
8
8
System-Level Description ............................................................................................ 9
Required Hardware and Equipment ............................................................................... 9
Hardware Setup .......................................................................................................... 9
Software Installation .................................................................................................. 10
WinVCC Quick Start ................................................................................................... 10
WinVCC in Depth ....................................................................................................... 13
8.1
Starting WinVCC ................................................................................................ 13
8.2
WinVCC Configuration Dialog Box ........................................................................... 14
8.3
I2C System Test................................................................................................. 14
8.4
Real-Time Polling ............................................................................................... 15
8.5
Main Menu ....................................................................................................... 16
8.6
TVP5154 Property Sheets ..................................................................................... 23
Programming the TMS320DM642 ................................................................................. 25
Development and Purpose of DM642 Code ................................................................ 25
........................................................ 26
Troubleshooting ........................................................................................................ 33
10.1 Troubleshooting Guide ......................................................................................... 33
10.2 Corrective Action Dialogs ...................................................................................... 35
TVP5154EVM Schematics ........................................................................................... 37
9.2
11
.............................................................................................. 7
2.1
9.1
10
Description Overview ............................................................................................ 6
Details of the DM642 Code and Control Registers
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Table of Contents
3
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
4
TVP5154EVM Block Diagram .............................................................................................. 7
Anti-Aliasing Filter Selection................................................................................................ 8
TVP5154EVM System-Level Block Diagram ............................................................................. 9
WinVCC – I2C Configuration Screen .................................................................................... 11
Real-Time Polling Dialog .................................................................................................. 12
Decoder I2C Write and Read Enable .................................................................................... 12
WinVCC – Main Screen ................................................................................................... 12
WinVCC – System Initialization .......................................................................................... 13
WinVCC Multiple Occurrences Error Message ......................................................................... 13
WinVCC I2C Address Configuration ..................................................................................... 14
I2C System Failure ......................................................................................................... 15
Real-Time Polling Dialog .................................................................................................. 16
WinVCC – Main Screen ................................................................................................... 16
Decoder I2C Write and Read Enable .................................................................................... 17
System Initialization ........................................................................................................ 18
TVP5154 Register Map Editor ............................................................................................ 20
7311 Encoder Module Register Map Editor ............................................................................ 21
Generic I2C Register Map Editor ......................................................................................... 22
Memory Map Editor ........................................................................................................ 22
TVP5154 Property Sheets ................................................................................................ 24
DM642 Control Window ................................................................................................... 26
I2C System Failure Dialog Box ........................................................................................... 35
Corrective Action Dialog Box ............................................................................................. 35
Corrective Action Required ............................................................................................... 36
Corrective Action Required ............................................................................................... 36
I2C Error ..................................................................................................................... 37
List of Figures
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List of Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
I2C Address Selection Jumpers (I2CSEL1, JP9 and I2CSEL2, JP10)................................................ 7
Power-Down-Mode Selection Jumper (PDN, JP11) .................................................................... 7
Main Menu Summary ...................................................................................................... 16
TVP5154 Register Map Editor Controls ................................................................................. 21
Memory Map Editor Controls ............................................................................................. 23
Use of Property Sheet Controls .......................................................................................... 25
Property Sheet Button Controls .......................................................................................... 25
DM642 Control Window Controls ........................................................................................ 27
DM642 Virtual I2C Register Map ......................................................................................... 27
Decoder 1 Register ........................................................................................................ 28
Decoder 2 Register ........................................................................................................ 29
Decoder 3 Register ........................................................................................................ 30
Decoder 4 Register ........................................................................................................ 30
Decoder 1 Input Format Register ........................................................................................ 31
Decoder 2 Input Format Register ........................................................................................ 31
Decoder 3 Input Format Register ........................................................................................ 32
Decoder 4 Input Format Register ........................................................................................ 32
LED Control Register ...................................................................................................... 32
Flash Major Version Register ............................................................................................. 32
Flash Minor Version Register ............................................................................................. 32
TVP5154EVM Troubleshooting........................................................................................... 33
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List of Tables
5
User's Guide
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TVP5154EVM User's Guide
1
Functional Description
The TVP5154EVM evaluation module is a printed circuit board designed for evaluation of the TVP5154
quad video decoder. The board includes the TMS320DM642 digital signal processor (DSP) and is
designed with a 120-pin connector, which allows a connection to multiple backends; the evaluation module
(EVM) is shipped with a professional encoder module. The board is designed to provide ease of use, while
allowing full evaluation of the video decoder.
1.1
Description Overview
The TVP5154EVM uses the PC parallel port to emulate the I2C bus, which provides communication with
the TVP5154 video decoder, DM642, and the video encoder. The Windows™ Video Control Center
(WinVCC) application software that communicates with the devices via the I2C is provided on the EVM
CD-ROM.
The analog video inputs supported by the TVP5154EVM include composite video and S-video. More detail
about the video inputs is discussed in section 2.3 Video Input Description. In general, the video decoder
converts the analog video input signal into digital component data. This data and the associated clocks
from the video decoder are sent to the DM642, which provides various image capture and display modes.
The DM642 is setup in I2C slave mode and is controlled through virtual I2C registers. The video encoder
then converts the digital data from the DM642 back into analog video. The analog video outputs supported
by the EVM include composite video, S-video, and component video. These are all output simultaneously.
To experiment with the programmable features of the TVP5154 video decoder and the video encoder, the
parallel port of the TVP5154 is connected to the parallel port of a PC. WinVCC, a Windows-compatible
application provides the user interface for performing register-level and high-level control of the TVP5154
video decoder and the video encoder.
Code Composer Studio is a trademark of Texas Intruments.
All other trademarks are the property of their respective owners.
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Board Level Description
2
Board Level Description
The TVP5154EVM consists of the TVP5154EVM module and the encoder EVM module. A 4-row 120-pin
connector connects the boards. The block diagram of the EVM set is shown in Figure 1.
Figure 1. TVP5154EVM Block Diagram
2.1
Test Points and Jumpers
The TVP5154EVM was designed with test points and jumpers to help in evaluation and troubleshooting.
Each jumper is set by default in its preferred state for the TVP5154EVM. There are test points for SCL,
SDA, 3.3 V, and 1.8 V. All digital video data for each decoder core are brought out to a dual-row header,
which allows easy hookup to test equipment. The I2C address selection is made with two shunt jumpers,
which are only read after a reset or at power up. The default address is 0xB8. If the address needs to be
changed, the TVP5154 must receive a reset.
Table 1. I2C Address Selection Jumpers
(I2CSEL1, JP9 and I2CSEL2, JP10)
I2C ADDRESS
JP9
JP10
2-3
2-3
0xB8
1-2
2-3
0xBA
2-3
1-2
0xBC
1-0
1-2
0xBE
Table 2. Power-Down-Mode Selection Jumper
(PDN, JP11)
PWDN
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1-2
Normal operation
2-3
Power down
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Board Level Description
Note:
2.2
If the I2C address is changed on either the TVP5154 board or the encoder board while the
TVP5154EVM is powered up, that device will not recognize the new I2C address. The reset
button on the TVP5154EVM must be pressed and WinVCC must be reconfigured for the new
I2C address.
Common Board Interface
The TVP5154EVM uses a 4-row 120-pin connector to share common signals and the 5-V power supply
between the boards. This connection allows multiple backends to be connected to the TVP5154EVM. The
EVM package is shipped with an encoder module. This connector shares all digital video bits (Y[7:0]), all
video clocks (VS, HS, GLCO/FID, and DATACLK), 5 V, ground, I2C bus (SCL and SDA), and reset.
2.3
Video Input Description
The TVP5154EVM decoder has an analog input channel that accepts two video inputs for each decoder
core. The decoder supports a maximum input voltage range of 0.75 V, therefore, an attenuation of
one-half is needed for most input signals with a peak-to-peak variation of 1.5 V. The parallel termination
before the input to the device is 75 Ω. The two analog inputs can be connected as either two selectable
composite video inputs, or one S-video input.
The TVP5154EVM allows the user to have up to two composite inputs or one S-video input for each of the
four-channels. The EVM software sets up and controls this input selection. The S-video input uses two
connectors, one for the luma channel and one for the chroma channel.
The EVM has a resistor network on each of the inputs. These networks attenuate the signal and allow a
75-Ω resistor to ground to be placed after the anti-alias filter for termination.
Each input has an anti-alias filter that can be in-circuit or bypassed by jumpers (JP1–JP8). To select the
filter, the shunts need to be positioned to short positions 1-3 and 2-4. To bypass the filter, the shunts need
to be moved to short positions 1-2 and 3-4 as shown in Figure 2. The boards are shipped with the filter
bypassed.
Figure 2. Anti-Aliasing Filter Selection
2.4
Video Output Description
The 8-bit digital video outputs of the TVP5154 are routed to the four 32-pin headers (H2–H5), the DM642,
and finally to the 120-pin edge connector along with all video clocks on the TVP5154 module. The
encoder module connects to the 120-pin connector, and is capable of receiving digital video with or
without embedded syncs. The analog outputs of the encoder module are composite, S-video, and
component. For the user’s convenience, all of these outputs come out of the encoder module
simultaneously.
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System-Level Description
3
System-Level Description
A system-level block diagram incorporating the TVP5154 is shown in Figure 3. Typical
commercially-available test equipment is also shown. The primary features of this configuration are:
• Power is provided by a single 5-V power supply provided with the EVM and is shared between both
modules via the 120-pin connector.
• Supported analog inputs include composite video and S-video.
• Re-encoded composite video and S-video are output via the encoder module.
• Component (YPbPr) video is output via the encoder module.
• I2C bus initializes the video devices via a PC parallel port.
• The TVP5154 video decoder performance parameters may be measured with a video analyzer.
Figure 3. TVP5154EVM System-Level Block Diagram
4
Required Hardware and Equipment
The required hardware and equipment necessary to use the TVP5154EVM are:
• TVP5154EVM (provided)
• Universal 5-V power supply (provided)
• Parallel cable (provided)
• Windows-based PC with CD-ROM drive and Win95™ or later
• Composite or S-video cables for inputs
• Composite, S-video, or component cable for output
• Video sources (security camera, pattern generator, Quantum generator, DVD player, etc.)
• Display monitor that supports composite, S-video, or component video input
5
Hardware Setup
Figure 1 shows the TVP5154EVM layout and indicates the location of the power supply and the
appropriate connectors. All connectors are labeled according to their function. To prepare the EVM for
evaluation, connect the following:
1. TVP5154 module to encoder module
2. Parallel port cable from TVP5154EVM to the PC
3. Analog video sources to TVP5154EVM inputs
4. Analog video out from TVP5154EVM to monitor
5. 5-V power supply to the dc jack on the TVP5154 board. A green LED on each board should now be lit.
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Software Installation
The system comes with the anti-alias filters bypassed. To connect the filters, you must rotate the
appropriate jumpers (JP1–JP8) as described in section 2.3.
The I2C slave address can be selected with jumpers JP9 and JP10. There are four possible addresses:
B8, BA, BC, and BE. The default setting for these jumpers is for the shunt to short pins 2-3, which selects
0xB8. These are connected to pins 117 and 118, which are read at power up. If you move both the
jumpers to positions 1-2 and reset the board, the video decoder now responds to I2C slave address 0xBE.
If you choose to change the address, you must exit, restart WinVCC, and configure the software to use
the new I2C slave address.
6
Software Installation
WinVCC is a Windows application that uses the PC parallel port to emulate I2C, providing access to each
device on the I2C bus. WinVCC makes use of CMD files, a text editable file that allows preset video
setups to be programmed easily.
This feature allows the user to easily set multiple I2C registers with the press of a button. WinVCC also
has property sheets for the TVP5154, which allows the user to control the I2C registers with a GUI.
All necessary software for the TVP5154EVM is provided on the enclosed CD. Perform the following steps
to install WinVCC:
1. Explore the provided TVP5154EVM Software CD.
2. Install Port95NT.exe. This is the parallel port driver used by WinVCC. This driver must be installed and
the PC must be rebooted before WinVCC operates correctly. This does not affect normal parallel port
operation.
3. Install Setup.exe. Click Next at all prompts and click Finish to complete the installation process. This
installs WinVCC onto the PC. No reboot is required.
4. Run WinVCC.exe.
Note:
7
A shortcut to WinVCC should now be available on the desktop. WinVCC and additional
TVP5154-related documentation can also be found at Start→Programs→TVP5154EVM
Software.
WinVCC Quick Start
Perform the following steps in order to see a video output from the TVP5154EVM.
1. Once WinVCC is executed, the WinVCC Configuration screen appears, as shown in Figure 4. This
dialog box configures the I2C bus. Next to VID_DEC, select the TVP5154 and ensure the I2C address
is set to 0xB8 (default setting on EVM.) This must match the I2C ADDR jumper on the TVP5154 board.
2. Next to VID_ENC, select the 7311 Encoder and ensure the I2C address is set to 0x54 (default setting
on EVM.) This must match the I2C ADDR jumper on the encoder board.
Note:
10
If WinVCC is running and the TVP5154 or encoder board I2C address is changed, power
must be cycled on the EVM.
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WinVCC Quick Start
Figure 4. WinVCC – I2C Configuration Screen
3. Ensure that all other boxes are selected as “Not Used” and that all program options buttons are set to
ENABLE. Click OK.
4. If there are no I2C communication issues, the Real-Time Polling dialog window displays next as shown
in Figure 5. If there are I2C issues, an I2C Test Report box displays. Completely exit out of WinVCC,
double-check the parallel port cable connections, I2C address settings, cycle power on the
TVP5154EVM, and re-run WinVCC.
5. When using the TVP5154 EVM with a composite output from the 7311 encoder, it is required to disable
auto-switch polling in the Real-Time Polling dialog box by clicking on the ENABLED button. Click OK
and then the Main Control Window is seen, as shown in Figure 7.
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WinVCC Quick Start
Figure 5. Real-Time Polling Dialog
6. The TVP5154 I2C Write Enable(s) and Read Enable pop-up window is displayed as shown in Figure 6.
This is used to select which decoder or decoders (any combination of all four) will receive I2C Write
commands, and which decoder (only one) will receive I2C Read commands. Decoder 1 is Enabled by
default; enable the other three decoders by clicking on each decoder’s enable button.
Figure 6. Decoder I2C Write and Read Enable
7. Load the provided Initialization command (CMD) file into WinVCC by clicking on Tools→System
Initialization→Browse. The default directory is C:\Program Files\Texas
Instruments\TVP5154EVM\Initialization.
Figure 7. WinVCC – Main Screen
8. In the System Initialization Window (see Figure 8), click the “TVP5154 ROM – Initialize for NTSC...” or
“TVP5154 ROM – Initialize for PAL...” dataset in the window and then click the PROGRAM Device(s)
Using Selected Dataset button to initialize the TVP5154EVM.
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WinVCC in Depth
Figure 8. WinVCC – System Initialization
9. With video sources provided at the BNC connectors and the EVM output connected to a monitor, video
from the source connected to CH1 should be viewable on the display monitor.
10. The other datasets in the command file are provided to demonstrate examples of 5154 scaling
performance. Refer to the TVP5154 data sheet (SLES163) or Scaler application report for more details
on programming the TVP5154 scaler. The DM642 settings can be controlled by using the DM642
Control Window, which is found by clicking on Tools→DM642 Control. Refer to Chapter 9 for details on
programming the DM642 through this window or through the Generic I2C registers.
8
WinVCC in Depth
The following sections describe how to use Windows™ Video Control Center (WinVCC) in depth. It
discusses various features and screens that the user may encounter while evaluating the TVP5154EVM.
8.1
Starting WinVCC
The Port95NT parallel port driver must be installed before using WinVCC. WinVCC may be started by
clicking on Start→All Programs→TVP5154EVM Software→WinVCC.
If the dialog box shown in Figure 9 is displayed, it means one of two things:
• WinVCC did not run to completion the last time it ran. In this case, click OK to exit the program and
restart WinVCC.
• There is more than one instance of WinVCC running at the same time. In this case, click OK to exit the
program. Then, press CTRL-ALT-DELETE to bring up the Task Manager. Select and click End Task
on all occurrences of WinVCC or WinVCC CONFIGURATION. Then restart WinVCC.
Figure 9. WinVCC Multiple Occurrences Error Message
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WinVCC in Depth
8.2
WinVCC Configuration Dialog Box
The WinVCC Configuration dialog box (see Figure 10) should now be visible. This dialog box configures
the I2C bus on the TVP5154EVM. All settings from this dialog box are stored in the Windows registry and
are restored the next time the program is started. After initial installation, VID_DEC is set to TVP5154 and
VID_ENC is set to 7311 Encoder.
The I2C slave address for each device must match the I2C slave address selected by jumpers on the
TVP5154EVM. These jumpers are set by the factory to use 0xB8 for the TVP5154 and 0x54 for the
Encoder. It is also important to select the correct Specific Device type for the video decoder. TVP5154 and
7311 Encoder must be selected for this EVM.
All Program Options must be enabled. Disabling these options is only required if debugging a problem
with the I2C bus.
Clicking OK begins I2C communication with the selected devices.
Figure 10. WinVCC I2C Address Configuration
8.3
I2C System Test
The I2C system test of selected registers runs immediately after closing the WinVCC Configuration dialog
box with OK (unless the I2C system test program options button was disabled).
If the I2C system test passes, only a PASS message appears. If the test failed, a dialog box like the one
shown in Figure 11 appears. See Section 10, Troubleshooting, for details on how to resolve this issue.
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WinVCC in Depth
2
2
The I C system test can be run at anytime by clicking Run System I C Test in the Tools menu.
Figure 11. I2C System Failure
8.4
Real-Time Polling
Real-time polling provides polling functions that execute continuously in the background, when enabled via
the Real-Time Polling dialog. There are two polling functions. The function that applies to the TVP5154 is
VIDEO-STANDARD AUTO-SWITCH POLLING.
When the TVP5154 detects a change in the input video standard, it automatically switches to operation in
the detected standard (which includes all necessary I2C register initialization) for proper decoding of the
input video. To enable auto-switch on the TVP5154, the Set Video Standard register must be set to
auto-switch mode (Reg 0x28 = 0x00).
If the WinVCC auto-switch polling function is enabled, the detected video standard status from the
TVP5154 is polled until a change in the input video standard (or in the TVP5154 sampling mode) is
detected. When a change is detected, the video encoder is reprogrammed as needed for the detected
standard. Using this feature, the video source can change its video standard and the system displays
using the new standard, without user intervention.
When using the TVP5154 EVM with the DM642 and a composite output from the 7311 encoder, it is
required to disable auto-switch polling by clicking on the ENABLED button in the Real-Time Polling dialog
box as shown in Figure 12.
The real-time polling dialog can also be accessed once WinVCC is up and running by clicking Real-Time
Polling in the Tools menu.
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WinVCC in Depth
Figure 12. Real-Time Polling Dialog
8.5
Main Menu
After closing the real-time polling dialog, the main menu is displayed as shown in Figure 13. The menus,
which are used to operate WinVCC, are File, Edit, Tools, Window, and Help. The File menu’s only function
is Exit, which terminates the program. Table 3 summarizes the main menu contents.
Figure 13. WinVCC – Main Screen
Table 3. Main Menu Summary
MENU
16
CONTENTS
File
Exit
Edit
Register Map
TVP5154
7311 Encoder Module
Generic I2C
Memory Map
TVP5154
7311 Encoder Module
Property Sheets
TVP5154
7311 Encoder Module
Tools
System Initialization
Real-time Polling
TV Tuner Control (FQ12xx series only)
Multiple-Byte I2C Transfers
Set I2C Bit Rate
Run System I2C Test
Run Continuous I2C Test
Read VBI FIFO
Capture Live VBI Data
DM642 Control
Window
Allows selection of the active window. Multiple windows can be open at the same time.
Help
Displays program version
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WinVCC in Depth
2
The TVP5154 I C Write Enable(s) and Read Enable pop-up window is displayed as shown in Figure 14.
This is used to select which decoder or decoders (any combination of all four) will receive I2C Write
commands, and which decoder (only one) will receive I2C Read commands. Decoder 1 is Enabled by
default; enable the other three decoders by clicking on each decoder’s enable button.
Figure 14. Decoder I2C Write and Read Enable
8.5.1
System Initialization
Clicking System Initialization in the Tools menu displays the dialog box shown in Figure 15. This dialog
box provides the means for initializing the TVP5154 decoder(s) and/or video encoder for a particular video
mode, as well as programming settings for the DM642 through the Generic I2C registers. The details of
the initialization are contained in the command file (with a CMD file extension).
The command file is loaded using the Browse… button. Once the command file is opened, a text list
displays descriptions of the individual datasets contained within the command file.
Click once on the desired dataset description to select it. Click the Program Device(s) Using Selected
Dataset button to run the selected dataset, which loads the devices via the I2C bus. When the device
initialization has completed, the status indicator reads Ready.
Note:
If Ready does not display, the devices are not initialized and the I2C bus is not
communicating. See Chapter 10, Troubleshooting, for possible solutions.
Click the OK button to close the dialog box. Each time the System Initialization dialog box is closed, the
initialization file pathname and the dataset selection number are saved in the Windows registry to allow
these settings to be retained for the next time WinVCC runs.
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WinVCC in Depth
Figure 15. System Initialization
8.5.1.1
Adding a Custom Dataset
After programming the EVM via the System Initialization tool using the factory-supplied command file, you
can customize the device register settings to fit your needs. Perform the following steps to save your
custom settings:
1. Reopen the System Initialization dialog box via the Tools menu.
2. Click the Append Current Device Settings to Command File button. A dialog box requesting a
description of the new dataset appears.
3. Optionally, click the drop-down box and select one of the existing descriptions.
4. Modify the description text or type your own description.
5. Click OK. All nondefault register values from the TVP5154, DM642, and encoder are appended to the
current command file as an additional dataset.
Now, you can select your custom dataset and send it with a press of the Program… button.
By using the same procedure above with the Replace Selected Dataset with Current Device Settings
button you can overwrite an existing dataset with the current settings.
Note:
18
If editing the command file (.CMD) using a standard editor, the file must be saved as plain
text.
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WinVCC in Depth
8.5.1.2
Command Files
The command file is a text file that can be generated using any common editor; however, it must be saved
as plain text. Command files are especially useful for quickly switching between the various system
configurations. These .CMD files are unrelated to the typical Windows .CMD files.
A default command file is provided on the CD. This command file contains many examples of the desired
setups. This command file is located at:
c:\Program Files\Texas Instruments\TVP5154EVM\Initialization\
A command file can contain up to 250 datasets. A dataset is a set of register settings to initialize the
TVP5154 decoder, 7311 encoder, and/or DM642 for a particular video mode. Each dataset includes a
description that is displayed in one row of the dataset descriptions list. The register settings may be
located in the command file itself and/or may be stored in separate include file(s) (with an .INC file
extension) and be included into the command file using the INCLUDE statement.
8.5.1.3
Example Command File
An example of one dataset within a command file is shown below.
BEGIN_DATASET
DATASET_NAME,”TVP5154, Auto–switch, Stable Sync, Fast-lock, 656 Out”
// Initialize video encoder using an include file
INCLUDE, EncoderNTSC656_RTC.INC
// Program TVP5154 registers
WR_REG,VID_DEC,1,0x7F,0x00 // Reset 5154 microprocessor
WR_REG,VID_DEC,1,0x03,0x0D // Enable YCbCr outputs and syncs
WR_REG,VID_DEC,1,0x15,0x81 // Enable Stable Sync mode
WR_REG,VID_DEC,1,0x02,0x80 // Enable Fast-lock mode
END_DATASET
Each command file may contain individual write-to-register (WR_REG) commands.
• The comment indicator is the double-slash //.
• The command file is not case sensitive and ignores all white-space characters.
• All numbers can be entered as hexadecimal (beginning with 0x) or as decimal.
• Every dataset in a command file begins with BEGIN_DATASET and ends with END_DATASET. The
maximum number of datasets is 250.
• The dataset text description is entered between double quotes using the DATASET_NAME command.
The enclosed text can be up to 128 characters in length. This text appears in the System Initialization
dialog box when the command file is opened.
• The INCLUDE command inserts the contents of an include file (with an .INC file extension) in-line in
place of the INCLUDE command. Therefore, the include file must not contain the BEGIN_DATASET,
END_DATASET, and DATASET_NAME commands.
Note:
•
All included files must be located in the same directory as the command (CMD) file.
The write-to-register command is written as:
WR_REG, <DeviceFamily>, <Number of data bytes (N)>, <subaddress>, <Data1>,…, <DataN>
or
WR_REG, <Literal slave address>, <Number of data bytes (N)>, <subaddress>, <Data1>,…, <DataN>
The valid device family mnemonics are:
VID_DEC for the video decoders
VID_ENC for the video encoders
THS8200 for the THS8200 device
WinVCC translates the device family mnemonic to the slave address that was selected in the WinVCC
Configuration dialog box upon program startup. This eliminates having to edit command files if the
alternate slave address must be used.
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If the literal slave address method is used, the slave address entered is used directly. This method is
normally used for programming the video encoder.
The slave address 0x40h is used to access the DM642.
• A delay may be inserted between commands using the WAIT command, which is written as:
WAIT,<# milliseconds>
8.5.2
Register Editing
The next section describes the five available modes of register editing: TVP5154 Register Map editor,
7311 Encoder Module Register Map editor, Generic I2C Register Map editor, TVP5154 memory map
editor, and TVP5154 Property Sheets. Each of these functions can be selected from the Edit menu.
8.5.2.1
Register Map Editor
The TVP5154 Register Map editor (see Figure 16) allows the display and editing of the entire used
register space of the device within a simple scrolling text box. To open this, click on Edit Register Map in
the Edit menu and click on the device type to edit. Table 4 describes how to use each of the controls in
the TVP5154 Register Map editor.
Figure 16. TVP5154 Register Map Editor
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Table 4. TVP5154 Register Map Editor Controls
CONTROL
DEFINITION
Register Window
Scrolling text box that displays the address and data for the I2C registers that are defined for the device
Address Edit Box
Contains the I2C subaddress that will be accessed using the Write and Read buttons. Clicking on a row selects
an address, which then appears in the address edit box.
NOTE: After clicking on a row, the Data Edit box contains the data that was in the register window. The device
has not yet been read.
The address up/down arrows are used to jump to the next/previous subaddress that is defined for the device. If
an address is not defined for the device, it can still be accessed by typing the subaddress in the Address Edit
box.
Data Edit Box
Contains the data which will be written to, or was read from, the I2C subaddress.
The data up/down arrows increment/decrement the data value by 1.
Write Button
Writes the byte in the Data Edit box to the address in the Address Edit box.
The I2C register is written to whether or not the data is different from the last time the register was read.
Read Button
Reads the data from the address in the Address Edit box into the Data Edit box and the register window.
Read All Button
Reads all defined readable registers from the device and updates the register window.
Hex Button
Converts all values in the register window and address and data edit boxes to hexadecimal.
Dec Button
Converts all values in the register window and address and data edit boxes to decimal.
Close Button
Closes the dialog.
NOTE: Multiple edit register map windows can be open at the same time (one for each device). Use the
Window menu to navigate.
Loop Count
8.5.2.2
Causes subsequent write, read, or read all operations to be performed N times. N is entered as a decimal
number from 1 to 999.
Encoder Module Register Map Editor
The Encoder Module Register Map editor (see Figure 17) allows the display and editing of the video
encoder registers. This editor works like the TVP5154 Register Map editor.
To open this, click on Register Map in the Edit menu and click on 7311 Encoder Module.
Figure 17. 7311 Encoder Module Register Map Editor
8.5.2.3
Generic I2C Register Editor
The Generic I2C Register editor (see Figure 18) allows the display and editing of any device on the I2C
bus. This editor works like the TVP5154 Register Map editor, except that the I2C slave address must be
entered and the Read All button is disabled.
To open this, click on Register Map in the Edit menu and then click on Generic I2C.
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The DM642 I2C registers can be edited using I2C sub-address 0x40. See Section 9 for details about the
DM642 registers.
The video encoder module registers can be edited using I2C sub-address 0x54 (default) or 0x56 if the
alternate slave address is being used.
Figure 18. Generic I2C Register Map Editor
8.5.2.4
Memory Map Editor
The memory map editor (see Figure 19) allows the display and editing of the data memory and hardware
registers of the device, such as the scaler setting registers.
To open this, click on Memory Map in the Edit menu and click on the device type to edit. The operation of
the memory map editor controls are explained in Table 5.
Figure 19. Memory Map Editor
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Table 5. Memory Map Editor Controls
CONTROL
DEFINITION
Base Address Selector
The hardware registers use a 10-bit address internally. The base address selector allows quick entry
of the base address. The list contains base addresses for the major functional blocks of the
TVP5154.
Address Offset Edit Box
Contains the lowest byte of the 10-bit internal address. The full 10-bit address is formed by adding
the base address to the address offset. The address up/down arrows increment/decrement the
address offset by 1.
Data Edit Boxes
Contains the 16-bit data word that is written to or read from the register address. The LSB data is at
the lowest address. The data is written/read LSB first. The data up/down arrows
increment/decrement the data value by 1.
Write Button
Writes the (2) bytes in the data edit boxes starting at the 10-bit register address BASE+OFFSET.
Read Button
Reads (2) consecutive data bytes starting at the 10-bit register address BASE+OFFSET to the data
edit boxes.
Loop Count Edit Box
Causes subsequent write or read operations to be performed N times. N is entered as a decimal
number from 1 to 999.
Histogram on
Loop Count Reads
Creates a histogram of the results from the Loop Count Reads.
Close Button
Closes the dialog.
Note:
8.6
The memory map editor can remain open with other
windows. Use the Window menu to navigate.
TVP5154 Property Sheets
The property sheets represent the register data in a user-friendly format. The data is organized by
function, with each function having its own page and being selectable via tabs at the top (see Figure 20).
To open this, click on Edit Property Sheets in the Edit menu and select the device type to edit.
When the property sheet function is started or whenever the user tabs to a different page, all readable
registers in the device are read from hardware to initialize the dialog pages. Values on the page are
changed by manipulating the various dialog controls as described in Table 6.
OK, Cancel, and Apply buttons are at the bottom of each property page. These are described in Table 7.
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Figure 20. TVP5154 Property Sheets
8.6.1
Property Sheet Refresh
The property sheets are designed so that the data displayed is always current. Certain actions cause the
entire register map to be read from the device and to update the property sheets. This happens when:
• Property sheets are initially opened.
• When tabbing from one page to another.
• When Read All is clicked.
• When making the TVP5154 Property Sheets window the active window (by clicking on it).
• When making a TVP5154 Register Map editor window the active window (by clicking on it).
8.6.1.1
Auto-Update From Device
The last two items in the Property Sheet Refresh list (see section 8.6.1) are referred to as the
Auto-Update feature. Auto-Update can be disabled by setting its program option button to DISABLED.
This button is located on the initial dialog box (WinVCC Configuration).
With Auto-Update enabled (default), the user can open both the TVP5154 Property Sheets and the
TVP5154 Register Map editor at the same time. Changes made to the property sheets (and applied) are
updated in the register map window as soon as the Register Map window is clicked on. Additionally,
changes made in the TVP5154 Register Map editor are updated in the TVP5154 Property Sheets as soon
as the property sheets window is clicked on.
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Table 6. Use of Property Sheet Controls
PROPERTY SHEETS
DIALOG CONTROL
WHAT DO I DO WITH IT?
When is Hardware Updated?
Read-Only Edit Box
Read status information
N/A
Check Box
Toggle a single bit
After Apply
Drop-Down List
Select from a text list
After Apply
Edit Box
Type a number
After Apply
Edit Box with Up/Down arrows
Use up/down arrows or type a number
Up/Down arrows: Immediately
Type a number: After Apply
Slider
Slide a lever
Immediately
Pushbutton
Initiate an action
Immediately
Table 7. Property Sheet Button Controls
BUTTON
CONTROL
9
DEFINITION
OK
Writes to all writeable registers whose data has changed. A register is flagged as changed if the value to be
written is different from the value last read from that address.
Closes the dialog.
Cancel
Causes all changes made to the property page since the last Apply to be discarded. Changes made to dialog
controls with ‘immediate hardware update’ are not discarded, since they have already been changed in
hardware.
Does not write to hardware.
Closes the dialog.
Apply
Writes to all writeable registers whose data has changed. A register is flagged as changed if the value to be
written is different from the value last read from that address.
Programming the TMS320DM642
This chapter discusses how to change settings for the TMS320DM642 on this EVM. The DM642 settings
can be controlled by using the DM642 Control Window, which is found by clicking on Tools→DM642
Control, or through the Generic I2C registers.
9.1
Development and Purpose of DM642 Code
The TVP5154EVM was developed by the TI Digital Video Department, which is responsible for the
TVP5146 and TVP5150AM1 video decoders currently used on the DM642EVM released by Spectrum
Digital. The TVP5154EVM hardware and software are both based on this DM642EVM.
The TVP5154EVM was designed specifically for security customers interested in a quad video decoder.
The TVP5154EVM showcases the TVP5154 with various scaled/unscaled display modes, while making
the DM642 transparent to the customer during evaluation. This is made possible by placing the DM642
into an I2C slave mode and controlling the capture/display modes using virtual I2C registers. The entire
TVP5154EVM is controlled by a PC emulating I2C via the parallel port. By downloading the DM642 code
from flash at power up, it is not required to use Code Composer Studio™ software to program the DM642;
all relevant DM642 control registers can be accessed and controlled through a generic I2C address.
In addition to the command file provided with this EVM, additional command files to be used with TI’s EVM
control software (WinVCC) can be provided from TI to support easy programming of the TVP5154 and
DM642 registers to show the most common scaling configurations for both NTSC and PAL formats. When
using these command files or when setting the register values through a standard I2C bus interface, it is
important to enable and program the 5154 outputs before configuring the DM642 registers. The DM642
portion of the TVP5154EVM consists only of the DM642, SDRAM, and flash memory.
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Programming the TMS320DM642
9.2
Details of the DM642 Code and Control Registers
Details of the DM642 code and control registers are:
• The DM642 device address is 0x40h by default. The DM642 is setup as an I2C slave.
• The DM642 executes code on power up from the flash using the PCI GPIO to control the address
MSB.
• Virtual I2C registers are created within the DM642 in order to control the capture and display of the
scaled/unscaled data from the TVP5154 video decoder. These registers are described in Table 9.
• The virtual I2C registers support scaled and unscaled video outputs independently for each of the four
video decoders, with the option to overlay scaled video onto unscaled video, and to define the
quadrant location of each scaled channel.
• The virtual I2C registers provide easy control/access to the GPIOs currently tied to LEDs. Please refer
to the TVP5154EVM schematics for options to associate an LED on/off with a register setting.
• The DM642 is not responsible for any scaling. All video scaling is performed by the TVP5154. The
DM642 is only responsible for image capture and display.
• The DM642 virtual registers can be controlled by using the DM642 Control Window or through the
Generic I2C registers.
9.2.1
DM642 Control Window
The DM642 settings can be easily controlled by using the DM642 Control window. This window represents
the DM642 register data in a user-friendly format. The data is organized for each of the four decoders (see
Figure 21).
To open this, click on DM642 Control in the Tools menu.
Figure 21. DM642 Control Window
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Programming the TMS320DM642
When the DM642 Control window is opened, all readable registers for the device are read from software
to initialize the dialog page. Register details are given in Table 8. Values on the page are changed by
manipulating the various dialog controls as described in Table 8. The data is organized for each of the
four decoders, allowing independent control of each decoder.
Table 8. DM642 Control Window Controls
CONTROL
9.2.2
DEFINITION
Read All
Reads all defined readable registers from the device and updates the register window.
Close
Causes all changes made to the page since the last Apply to be discarded. Changes made to dialog controls
with ‘immediate register update’ are not discarded, since they have already been changed in the DM642
registers.
Does not write to registers.
Closes the dialog.
Image Capture
Enables image capture in the DM642 for that given decoder (1–4). Immediate register update.
Video Standard
Used to inform the DM642 of the input color standard for that given decoder (1–4). No change in register until
Apply is clicked.
Does not change the video standard setting for the TVP5154.
Image Size
Used to inform the DM642 of the input image size for that given decoder (1–4). No change in register until Apply
is clicked.
Actual scaling is done in the TVP5154.
Image Position
Defines the quadrant location for the input of that given decoder (1–4). Immediate register update.
Apply
Immediately changes DM642 registers for input image size and input color standard for that given decoder
(1–4).
Enables TVP5154 scaler and programs correct scaling register settings into TVP5154 based on selected input
standard and image size for that given decoder (1–4).
Flash
Major/Minor
Reads the data from the Flash Version registers and writes it into the register window.
LED Control
Changes LED (1–7) status. Checked: LED is ON. Unchecked: LED is OFF. Immediate register update.
DM642 Virtual I2C Register Map
Table 9. DM642 Virtual I2C Register Map
ADDRESS
DATA (DEFAULT)
Decoder 1 Register
REGISTER DESCRIPTION
00h
02h
Decoder 2 Register
01h
12h
Decoder 3 Register
02h
22h
Decoder 4 Register
03h
32h
Decoder 1 Input Format Register
04h
01h
Decoder 2 Input Format Register
05h
01h
Decoder 3 Input Format Register
06h
01h
Decoder 4 Input Format Register
07h
01h
LED Control
08h
00h
Flash Version: Major
09h
01h
Flash Version: Minor
0Ah
00h
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9.2.3
DM642 Virtual I2C Register Details
Table 10. Decoder 1 Register
Address
00h
Default
02h
7
6
5
Reserved
Capture Size
4
3
2
1
Capture
Enable
Position
Bit 2
Bit 1
Bit 0
Unscaled
0
0
0
QSIF – 176 × 120
0
0
1
SIF – 352 × 240 (1/4 NTSC)
(default)
0
1
0
QCIF – 176 × 144
0
1
1
CIF – 352 × 288 (1/4 PAL)
1
0
0
QVGA – 320 × 240
1
0
1
VGA – 640 × 480
1
1
0
Reserved
1
1
1
Capture Enable
Bit 3
Disable (default)
0
Enable
1
Position
Bit 5
Bit 4
Quadrant 1 (default)
0
0
Quadrant 2
0
1
Quadrant 3
1
0
Quadrant 4
1
1
0
Capture Size
Quad 1
Quad 2
Quad 3
Quad 4
Scaled capture sizes always take priority over unscaled capture sizes.
Decoder priorities are always such that Decoder 1 is the highest priority, Decoder 2 is the second highest,
etc.
For example, if Decoders 1 and 4 are scaled to 1/4 size and Decoders 2 and 3 are unscaled, this display
results:
Decoder 1 Decoder 2
Scaled
Unscaled
Decoder 2 Decoder 4
Unscaled
Scaled
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Note:
The unscaled Decoder 2 displays in both Quadrant 2 and 3 since Decoder 2 takes priority
over Decoder 3 when both are unscaled.
Table 11. Decoder 2 Register
Address
01h
Default
12h
7
6
5
Reserved
Capture Size
4
3
2
Position
Bit 2
Bit 1
Bit 0
Unscaled
0
0
0
QSIF – 176 × 120
0
0
1
SIF – 352 × 240 (1/4 NTSC)
(default)
0
1
0
QCIF – 176 × 144
0
1
1
CIF – 352 × 288 (1/4 PAL)
1
0
0
QVGA – 320 × 240
1
0
1
VGA – 640 × 480
1
1
0
Reserved
1
1
1
Capture Enable
Bit 3
Disable (default)
0
Enable
1
Position
Bit 5
Bit 4
Quadrant 1
0
0
Quadrant 2 (default)
0
1
Quadrant 3
1
0
Quadrant 4
1
1
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Capture
Enable
0
Capture Size
Quad 1
Quad 2
Quad 3
Quad 4
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Table 12. Decoder 3 Register
Address
01h
Default
22h
7
6
5
Reserved
4
3
Position
Capture Size
2
1
Capture
Enable
Bit 2
Bit 1
Bit 0
Unscaled
0
0
0
QSIF – 176 × 120
0
0
1
SIF – 352 × 240 (1/4 NTSC)
(default)
0
1
0
QCIF – 176 × 144
0
1
1
CIF – 352 × 288 (1/4 PAL)
1
0
0
QVGA – 320 × 240
1
0
1
VGA – 640 × 480
1
1
0
Reserved
1
1
1
Capture Enable
Bit 3
Disable (default)
0
Enable
1
Position
Bit 5
Bit 4
Quadrant 1
0
0
Quadrant 2
0
1
Quadrant 3 (default)
1
0
Quadrant 4
1
1
0
Capture Size
Quad 1
Quad 2
Quad 3
Quad 4
Table 13. Decoder 4 Register
Address
01h
Default
32h
7
6
5
Reserved
Capture Size
30
4
3
2
Capture
Enable
Position
Bit 2
Bit 1
Bit 0
Unscaled
0
0
0
QSIF – 176 × 120
0
0
1
SIF – 352 × 240 (1/4 NTSC)
(default)
0
1
0
QCIF – 176 × 144
0
1
1
CIF – 352 × 288 (1/4 PAL)
1
0
0
QVGA – 320 × 240
1
0
1
VGA – 640 × 480
1
1
0
Reserved
1
1
1
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0
Capture Size
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Capture Enable
Bit 3
Disable (default)
0
Enable
1
Position
Bit 5
Bit 4
Quadrant 1
0
0
Quadrant 2
0
1
Quadrant 3
1
0
Quadrant 4 (default)
1
1
Quad 1
Quad 2
Quad 3
Quad 4
Table 14. Decoder 1 Input Format Register
Address
04h
Default
01h
7
6
5
4
3
2
Reserved
Input Color Standard
Bit 2
Bit 1
Bit 0
NTSC
0
0
0
(B, D, G, H, I, N) PAL
(default)
0
0
1
Reserved
1
0
Input Color Standard
...
The Input Color Standard register is used to inform the DM642 of the input color standard for that given
decoder (1–4). The output format of the DM642 is set to the standard with the largest majority based on
Registers 04h–07h. If the number of input color standards is equal, the DM642 automatically default to
PAL output.
Table 15. Decoder 2 Input Format Register
Address
05h
Default
01h
7
6
5
4
3
2
Reserved
Input Color Standard
Bit 2
Bit 1
Bit 0
NTSC
0
0
0
(B, D, G, H, I, N) PAL
(default)
0
0
1
Reserved
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0
Input Color Standard
...
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Table 16. Decoder 3 Input Format Register
Address
06h
Default
01h
7
6
5
4
3
2
Reserved
Input Color Standard
Bit 2
Bit 1
Bit 0
NTSC
0
0
0
(B, D, G, H, I, N) PAL
(default)
0
0
1
Reserved
1
0
Input Color Standard
...
Table 17. Decoder 4 Input Format Register
Address
07h
Default
01h
7
6
5
4
3
2
Reserved
Input Color Standard
Bit 2
Bit 1
Bit 0
NTSC
0
0
0
(B, D, G, H, I, N) PAL
(default)
0
0
1
Reserved
1
0
Input Color Standard
...
Table 18. LED Control Register
Address
08h
Default
00h
7
6
5
4
3
2
1
0
Reserved
LED 7 Status
LED 6 Status
LED 5 Status
LED 4 Status
LED 3 Status
LED 2 Status
LED 1 Status
1
0
1
0
LED (1–7) Status
= 0 (LED off)
= 1 (LED on)
Table 19. Flash Major Version Register
Address
09h
Default
01h
7
6
5
4
3
2
Flash Major Version
Table 20. Flash Minor Version Register
Address
0Ah
Default
00h
7
6
5
4
3
2
Flash Minor Version
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Troubleshooting
10
Troubleshooting
This chapter discusses ways to troubleshoot the TVP5154EVM.
10.1 Troubleshooting Guide
If you are experiencing problems with the TVP5154EVM hardware or the WinVCC software, see Table 21
for available solutions.
Table 21. TVP5154EVM Troubleshooting
SYMPTOM
At startup, the error message Cannot find
DLL file DLPORTIO.DLL appears.
Blank screen
CAUSE
The parallel port driver supplied with the
EVM has not been installed.
Run Port95NT.EXE on the CD to install
the driver.
Wrong video input is selected.
Go to Edit→Property Sheets→TVP5154,
Analog Video page, select the correct
video input(s) and click Apply.
(The composite video input 1 is selected
by default.)
Source is connected to the wrong input
connector.
Connect source to the correct input
connector.
YCbCr outputs or clock output is disabled.
Go to Edit→Property Sheets→TVP5154,
Output Control page, check the enable
YCbCr outputs and enable clock outputs
check boxes and click Apply.
Wrong mode is selected for color
subcarrier genlock output.
Go to Edit→Property Sheets→TVP5154,
Synchronization page, set the Fsc control
format to RTC and click Apply.
GLCO pin is not set to output the GLCO
signal.
Go to Edit→Property Sheets→TVP5154,
Output Control page, set the drop down
box labeled FID/GLCO (pin 23) to genlock
output (GLCO) and click Apply.
Wrong YCbCr output format
Go to Edit→Property Sheets→TVP5154,
Output Control page, set the YCbCr
output format to 8-bit 4:2:2 YCbCr
w/ITU-R BT.656 embedded sync mode
and click Apply.
Auto-switch masks are not set correctly.
Go to Edit→Property Sheets→TVP5154,
Mode Selection page, uncheck all
standards to be included in auto-switch
processing and click Apply.
Video decoder is not in auto-switch mode.
Go to Edit→Property Sheets→TVP5154,
Mode Selection page, set the drop-down
box to multistandard and click Apply.
Auto-switch polling is not enabled.
Click real-time polling in the Tools menu.
Click Enable All and OK. This should be
disabled if using a composite output.
No color
Screen colors are only magenta and
green.
Video standard auto-switch does not work
on the video decoder side.
Video standard auto-switch does not work
on the video encoder side.
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Troubleshooting
Table 21. TVP5154EVM Troubleshooting (continued)
SYMPTOM
CAUSE
SOLUTION
Make sure I2C slave address jumpers on
the TVP5154 decoder module are across
pins 2 and 3.
Decoder I2C slave address is wrong.
Encoder
I2C
Slave address is hard coded to be 0x54 in
the command file. Make sure the I2C slave
address jumper on encoder module is
across pins 2 and 3.
slave address is wrong.
Parallel cable is not connected from PC
parallel port to the TVP5154 decoder
module DB25 connector.
Connect cable
EVM is not powered on.
Power supply must be plugged into a
100-V to 240-V/47-Hz to 63-Hz power
source, and the cord must be plugged into
the power connector on the EVM.
Wrong type of parallel cable.
Some parallel cables are not wired
straight through pin for pin. Use the cable
supplied with the EVM.
Device was placed in power-down mode.
Press the Reset button on the TVP5154
Decoder Module.
EVM was configured for an external I2C
master.
Reinstall 0-Ω resistors R5 and R6. Control
EVM using the PC parallel port.
PC parallel port mode is not set correctly.
DO THIS AS A LAST RESORT. Reboot
PC, enter BIOS setup program, and set
parallel port LPT1 mode (Addr 378h) to
ECP mode or bidirectional mode
(sometimes called PS/2 mode or byte
mode). If already set to one of these two
modes, switch to the other setting (see
Section 10.2).
Still no I2C communication
PC may not be capable of operating in the
required parallel port mode. This is true of
some laptop computers. Use a different
computer, preferably a desktop PC.
No I2C communication
When WinVCC is started and the WinVCC Configuration dialog box is closed with OK, the I2C system test
is performed (unless the I2C System Test program options button was disabled).
If the I2C system test fails, a dialog box (see Figure 22) appears. This example reports that a read from
TVP5154 failed, using slave address 0xB8, sub-address 0xD0. The data read was 0x78. The expected
data was 0x00.
After noting which device had a problem, click OK to continue. Next, the Corrective Action Dialog box
appears to fix the problem.
34
TVP5154EVM User's Guide
SLEU069A – February 2006 – Revised July 2006
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Troubleshooting
Figure 22. I2C System Failure Dialog Box
10.2 Corrective Action Dialogs
After closing the I2C system test report dialog box, a dialog box (see Figure 23) appears.
Figure 23. Corrective Action Dialog Box
1. If the parallel port cable is NOT connected between to PC and the TVP5154EVM, or if the EVM power
is not on:
a. Click NO.
b. The dialog box shown in Figure 23 appears instructing you to correct the problem.
c. Correct the problem.
d. Click OK to continue. The Real-Time Polling dialog appears.
SLEU069A – February 2006 – Revised July 2006
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TVP5154EVM User's Guide
35
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Troubleshooting
Figure 24. Corrective Action Required
2. If the cable is connected from the PC parallel port to the TVP5154EVM and the EVM power is on:
a. Click Yes.
b. The dialog box shown in Figure 24 appears. This dialog box appears if the PC parallel
port mode setting may need to be changed.
Note:
c.
d.
e.
f.
Only run the PC BIOS setup program if the I2C communication problem cannot be
resolved in another way (correct slave address settings, reset or power cycle the
EVM, and/or check that the device type selected was TVP5154).
Click OK to continue.
The real-time polling dialog appears. Click OK to close it and get to the main menu.
Click Exit in the File menu to exit the program.
See the troubleshooting guide in Table 21.
Figure 25. Corrective Action Required
10.2.1
Setting the PC Parallel Port Mode
Note:
Only run the PC BIOS setup program if the I2C communication problem cannot be
resolved in another way (correct slave address settings, reset or power cycle the EVM,
and/or check that the device type selected was TVP5154).
1. Restart the PC.
2. During the boot process, enter the BIOS setup program by pressing the required key (usually the initial
text screen indicates which key to press).
3. Find the place where the parallel port settings are made.
4. Set the parallel port LPT1 at address 378h to ECP mode or bidirectional mode (sometimes called PS/2
mode or byte mode). If one of these two modes is already selected, change to the opposite mode.
5. Exit and save changes.
36
TVP5154EVM User's Guide
SLEU069A – February 2006 – Revised July 2006
Submit Documentation Feedback
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TVP5154EVM Schematics
10.2.2
2
General I C Error Report
The I2C Error Report shown in Figure 26 appears when an I2C error occurs at any time other than after
the I2C system test. In this example, there is acknowledge error at slave address 0x54 (the video encoder
module). The error occurred on Read Cycle Phase 1 on the device (slave) address byte.
Figure 26. I2C Error
11
TVP5154EVM Schematics
SLEU069A – February 2006 – Revised July 2006
Submit Documentation Feedback
TVP5154EVM User's Guide
37
1
2
3
4
5
6
D
D
TVP5154EVMDVB REV 1.2
I2C
page 17 - I2C
Power
page 7 - Power
SDA
SCL
4A_IN
4B_IN
4A_IN
4B_IN
1A_OUT
1B_OUT
1A_OUT
1B_OUT
2A_OUT
2B_OUT
2A_OUT
2B_OUT
3A_OUT
3B_OUT
3A_OUT
3B_OUT
4A_OUT
4B_OUT
4A_OUT
4B_OUT
CH1_OUT[7..0]
SCKS1
SCK1
HS1
VS1
AV1
FID1
VB1
CH1_OUT[7..0]
SCKS1
CH2_OUT[7..0]
SCKS2
SCK2
HS2
VS2
AV2
FID2
VB2
CH2_OUT[7..0]
SCKS2
CH3_OUT[7..0]
SCKS3
SCK3
HS3
VS3
AV3
FID3
VB3
CH3_OUT[7..0]
SCKS3
CH4_OUT[7..0]
SCKS4
SCK4
HS4
VS4
AV4
FID4
VB4
CH4_OUT[7..0]
SCKS4
AV1
ENC_Y[7..0]
ENC_C[7..0]
ENC_Y[7..0]
ENC_C[7..0]
ENC_SCLK
ENC_HS
ENC_VS
ENC_FID
ENC_SCLK
ENC_HS
ENC_VS
ENC_FID
AV2
JTAG
page 15 - JTAG
AV3
AV4
SCL
SDA
/RESET
CH4_OUT[7..0]
SCKS4
SCK4
HS4
VS4
AV4
FID4
VB4
CH3_OUT[7..0]
SCKS3
SCK3
HS3
VS3
AV3
FID3
VB3
F&V Bit Breakout
page 12 - F&V Bit Breakout
CH2_OUT[7..0]
SCKS2
SCK2
HS2
VS2
AV2
FID2
VB2
CH1_OUT[7..0]
SCKS1
SCK1
HS1
VS1
AV1
FID1
VB1
Daughtercard Interface
page 3 - Daughtercard Interface
DSP_TDO
DSP_TDI
DSP_TMS
DSP_TCLK
DSP_TRST#
DSP_EMU[11..0]
Flash Memory
page 14 - Flash Memory
DSP_TDO
DSP_TDI
DSP_TMS
DSP_TCLK
DSP_TRST#
DSP_EMU[11..0]
TED[63..0]
TEA[22..3]
TECLKOUT1
TSDRAS#
TSDWE#
TSDCAS#
TSDCKE
TCE0#
TBE7#
TBE6#
TBE5#
TBE4#
TBE3#
TBE2#
TBE1#
TBE0#
3A_IN
3B_IN
C
SDA
SCL
/RESET
B
SDRAM
page 13 - SDRAM
TED[63..0]
TEA[22..3]
TECLKOUT1
TSDRAS#
TSDWE#
TSDCAS#
TSDCKE
TCE0#
TBE7#
TBE6#
TBE5#
TBE4#
TBE3#
TBE2#
TBE1#
TBE0#
2A_IN
2B_IN
3A_IN
3B_IN
/RESET
SCL
SDA
TCE1#
GP15_A21
GP14_A20
GP13_A19
2A_IN
2B_IN
/RESET
SCL
SDA
/RESET
TCE1#
GP15_A21
GP14_A20
GP13_A19
TSDWE#
TSDCAS#
TEA[22..3]
TED[31..0]
B
1A_IN
1B_IN
Connector
page 16 - Connector
DM642
page 4 - DM642
TVP5154
page 2 - TVP5154
1A_IN
1B_IN
CH4_OUT[7..0]
SCK4
Anti-Aliasing Filters
page 11 - Anti-Aliasing Filters
C
/RESET
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
TVP5154EVM BLOCK DIAGRAM
Size
C
Scale
FCSM No.
DWG No.
Rev
1
Sheet
1 of 17
1
2
3
4
5
6
1
2
3
4
5
6
D
D
DM642 Clocks and Reset
page 6 - DM642 Clocks and Reset
/RESET
SCL
SDA
DM642 Power Pins
page 9 - DM642 Power Pins
/RESET
SCL
SDA
DM642 Video Ports
page 5 - DM642 Video Ports
C
CH1_OUT[7..0]
SCKS1
AV1
CH1_OUT[7..0]
SCKS1
AV1
CH2_OUT[7..0]
SCKS2
AV2
CH2_OUT[7..0]
SCKS2
AV2
CH3_OUT[7..0]
SCKS3
AV3
CH3_OUT[7..0]
SCKS3
AV3
CH4_OUT[7..0]
SCKS4
AV4
CH4_OUT[7..0]
SCKS4
AV4
C
ENC_Y[7..0]
ENC_C[7..0]
ENC_Y[7..0]
ENC_C[7..0]
ENC_SCLK
ENC_HS
ENC_VS
ENC_FID
ENC_SCLK
ENC_HS
ENC_VS
ENC_FID
DM642 EMIF and JTAG
page 10 - DM642 EMIF and JTAG
B
TED[63..0]
TEA[22..3]
TED[63..0]
TEA[22..3]
TECLKOUT1
TSDCKE
TSDRAS#
TSDCAS#
TSDWE#
TCE0#
TCE1#
TBE7#
TBE6#
TBE5#
TBE4#
TBE3#
TBE2#
TBE1#
TBE0#
TECLKOUT1
TSDCKE
TSDRAS#
TSDCAS#
TSDWE#
TCE0#
TCE1#
TBE7#
TBE6#
TBE5#
TBE4#
TBE3#
TBE2#
TBE1#
TBE0#
DSP_EMU[11..0]
DSP_TDI
DSP_TDO
DSP_TMS
DSP_TCLK
DSP_TRST#
DSP_EMU[11..0]
DSP_TDI
DSP_TDO
DSP_TMS
DSP_TCLK
DSP_TRST#
B
DM642 PCI_HPI_EMAC
page 8 - DM642 PCI_HPI_EMAC
GP13_A19
GP14_A20
GP15_A21
GP13_A19
GP15_A21
GP14_A20
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
DM642 BLOCK DIAGRAM
Size
C
Scale
FCSM No.
DWG No.
Rev
1
Sheet
4 of 17
1
2
3
4
5
6
1
2
3
4
5
6
D
D
U25B
SCKS1
SCKS2
AV1
AV2
1
2
3
4
RPACK4-33
8
7
6
5
AF14
AF12
AE17
AC17
AD17
RN25
SCKS3
SCKS4
AV3
AV4
1
2
3
4
AF8
AF10
RPACK4-33
8
7
6
5
AF4
AE5
AD5
RN26
D3.3V
L1
BLM21P221SN
Y1
C2
1000pF
1
2
EN
VCC
GND
OUT
27MHz_MIH_MMD
4
R1
VP1_CLK0
VP1_CLK1
VP1_D00
VP1_D01
CLKX1/VP1_D02
VP1_CTL0
FSX1/VP1_D03
VP1_CTL1
DX1/VP1_D04
VP1_CTL2
CLKS1/VP1_D05
DR1/VP1_D06
FSR1/VP1_D07
Video Port 1 / McBSP1 / CLKR1/VP1_D08
McASP Data
VP1_D09
VP1_D10
VP1_D11
AXR0/VP1_D12
AXR1/VP1_D13
AXR2/VP1_D14
AXR3/VP1_D15
AXR4/VP1_D16
AXR5/VP1_D17
AXR6/VP1_D18
AXR7/VP1_D19
AF5
AF6
AE6
AD6
AC6
AE7
AD7
AC7
AD8
AC8
AE9
AD9
AC9
AD10
AC10
AE11
AD11
AC11
AB11
AB12
CH1_OUT[7..0]
CH1_OUT[7..0]
CH1_OUT0
CH1_OUT1
CH1_OUT2
CH1_OUT3
CH1_OUT4
CH1_OUT5
CH1_OUT6
CH1_OUT7
CH2_OUT[7..0]
CH2_OUT[7..0]
CH2_OUT0
CH2_OUT1
CH2_OUT2
CH2_OUT3
CH2_OUT4
CH2_OUT5
CH2_OUT6
CH2_OUT7
CH3_OUT[7..0]
CH3_OUT[7..0]
C
CH3_OUT0
CH3_OUT1
CH3_OUT2
CH3_OUT3
CH3_OUT4
CH3_OUT5
CH3_OUT6
CH3_OUT7
CH4_OUT[7..0]
CH4_OUT[7..0]
CH4_OUT0
CH4_OUT1
CH4_OUT2
CH4_OUT3
CH4_OUT4
CH4_OUT5
CH4_OUT6
CH4_OUT7
33
3
ENC_SCLK
ENC_HS
ENC_VS
ENC_FID
1
2
3
4
A7
A13
RPACK4-33
8
7
6
5
B8
D7
C7
VP2_CLK0
VP2_CLK1
VP2_D00
VP2_D01
VP2_D02
VP2_D03
VP2_D04
VP2_D05
VP2_D06
VP2_D07
VP2_D08
VP2_D09
VP2_D10
VP2_D11
VP2_D12
VP2_D13
VP2_D14
VP2_D15
VP2_D16
VP2_D17
VP2_D18
VP2_D19
VP2_CTL0
VP2_CTL1
VP2_CTL2
RN27
Video Port 2
TP
TP1
TP
1
B
AF18
AE18
AF17
AF16
AE16
AD16
AC16
AB16
AE15
AD15
AC15
AB15
AD14
AC14
AB14
AD13
AC13
AB13
AD12
AC12
AC1
STCLK
VIC
VDAC / GP08
C8
D8
A9
B9
C9
D9
A10
B10
C10
D10
A11
B11
C11
D11
E11
B12
C12
D12
E12
E13
ENC_Y[7..0]
ENC_Y0
ENC_Y1
ENC_Y2
ENC_Y3
ENC_Y4
ENC_Y5
ENC_Y6
ENC_Y7
ENC_C[7..0]
ENC_C0
ENC_C1
ENC_C2
ENC_C3
ENC_C4
ENC_C5
ENC_C6
ENC_C7
ENC_Y[7..0]
ENC_C[7..0]
D3.3V
R6
NO POP
TP2
TP
TP
C1
0.1uF
VP0_D00
VP0_D01
CLKX0/VP0_D02
VP0_CTL0
FSX0/VP0_D03
VP0_CTL1
DX0/VP0_D04
VP0_CTL2
CLKS0/VP0_D05
DR0/VP0_D06
FSR0/VP0_D07
Video Port 0 / McBSP0 / McASP
Control
CLKR0/VP0_D08
VP0_D09
VP0_D10
VP0_D11
ACLKR0/VP0_D12
AFSR0/VP0_D13
AHCLKR0/VP0_D14
AMUTEIN/VP0_D15
AMUTE/VP0_D16
ACLKX0/VP0_D17
AFSX0/VP0_D18
AHCLKX0/VP0_D19
1
C
VP0_CLK0
VP0_CLK1
B
PCI FREQ CONFIGURATION
R6/R27
AD1
R29
1k
TMX320DM642CGDK
MODE SELECTED
0
66MHz (DEFAULT)
1
33MHz
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
DM642 VIDEO PORT
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
5 of 17
6
1
2
D3.3V
3
4
5
6
D3.3V
L2
D3.3V
R72
150
BLM21P221SN
TP3
TP
R75
150
D
2
R61
R74
150
2
33
3
K A
C168
NO POP
50.00MHz
1
2
3
K A
OUT
R73
150
RN1
RPACK4-10k
K A
GND
4
2
VCC
1
2
EN
K A
1
2
C166
1000pF
5
6
7
8
C3
0.1uF
TP
Y2
D
4
R30
1k
R8
NO POP
PCI_EEAI
GP04
GP05
GP06
GP07
F4
F3
F2
E1
1
1
GP06
GP07
GP00 / DM641SEL
GP03 / PCIEEAI
GP01 / CLKOUT4
GP02 / CLKOUT6
D6
C6
R70 360
R71 360
EXTINT4 / GP04
EXTINT5 / GP05
EXTINT6 / GP06
EXTINT7 / GP07
TINP0
EMACEN / TOUT0
NMI
P4
1
1
TP
TP
TP
TP
TP
GP05
CLKMODE0
CLKMODE1
B4
/RESET
GP04
ECLKIN
R12
NO POP
TP9
TP
CLKIN
AA2
AE4
M5
L5
TP8
TP
1
H25
TP7
TP
1
AC2
DSP_ECLKIN
TP6
TP
1
DSP_CLKIN
TP5
TP
1
R39
10k
1
R7
NO POP
TP
4
3
2
1
U25E
1
BLUE_LED BLUE_LED BLUE_LED BLUE_LED
TP4
TP
D3.3V
TINP1
LENDIAN / TOUT1
RESET
A4
C5
EMAC_ENABLE
A5
B5
LENDIAN_MODE
D3.3V
R80
2.2k
R81
2.2k
D3.3V
L3
R31
1k
DSP_PLL_VDD
V6
Y3
C4
0.1uF
C167
1000pF
1
2
C
EN
VCC
GND
OUT
SCL0
SDA0
PLL_VDD
BLM21P221SN
E4
D3
SCL
SDA
Clocks / Interrupts / Timers / IIC
4
R3
3
25.00MHz
C
AB3
AA3
E14
AF3
33
CLKINF
AMUX1
TSTSTRB
PLL_LD
RESERVED
CLKOUTT
CLKOUTF
AD3
AC4
D3.3V
TMX320DM642CGDK
TP10
TP
X1/ICLK
X2
8
R2
7
6
S1
S0
CLK
REF
R13
33
DSP_PLL_VDD
1
D3.3V
R11
NO POP
3
GND
VDD
2
I
O
3
C169
+ 10uF
C5
0.1uF
2
R40
10k
EXCCET103U
E1
DSP_ECLKIN
5
4
NO POP
D3.3V
GND
1
TP
R10
NO POP
1
R9
NO POP
U3
C6
0.1uF
ICS512
Place all PLL external components as close to the DSP. All PLL external components must be on a single side of the board.
S1
S0
4X
100 MHz
5.33X
133.25 MHz
1
5X
125 MHz
0
2.5X
62.5 MHz
0
0
0
OPEN
0
OPEN
OPEN
MULTIPLY OUTPUT
OPEN
2X
D3.3V
R14
NO POP
EMAC_ENABLE
R32
1k
PCI_EEAI
PCI EEPROM AUTO-INIT CONFIGURATION
R15
50 MHz
NO POP
LENDIAN_MODE
B
OPEN
1
3.33X
83.25 MHz
1
0
6X
150 MHz
1
OPEN
3X
75 MHz
1
1
8X
200 MHz
R33
1k
R16/R32
MODE SELECTED
0
PCI EEPROM DISABLED(DEFAULT)
1
PCI EEPROM ENABLED; PCIEN=1
B
R16
R34
1k
NO POP
ENDIAN MODE CONFIGURATION
R15/R34
MODE SELECTED
0
BIG ENDIAN MODE
1
LITTLE ENDIAN MODE (DEFAULT)
EMAC MODE CONFIGURATION
R14/R33
MODE SELECTED
0
ETHERNET MAC DISABLED
1
ETHERNET MAC ENABLED
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
DM642 CLOCKS & RESET
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
6 of 17
6
1
2
3
4
5
6
TED16
TED17
TED18
TED19
TED20
TED21
TED22
TED23
TED24
TED25
TED26
TED27
TED28
TED29
TED30
TED31
16
15
14
13
12
11
10
9
R17
NO POP
R19
NO POP
RN5
RPACK8-33
1
2
3
4
5
6
7
8
R18
NO POP
EMIF_ECLKINSEL[1:0]
TEA19
TEA20
TEA20
0
TEA19
0
MODE SELECTED
ECLKIN( DEFAULT)
0
1
CPU CLOCK /4 EMIF CLOCK
1
0
CPU CLOCK /6 EMIF CLOCK
1
1
RESERVED
D
R20
NO POP
F25
F24
E25
E24
D25
D26
C25
C26
1
2
3
4
5
6
7
8
RN4
RPACK8-33
H24
H23
G26
G23
G25
G24
F26
F23
1
2
3
4
5
6
7
8
D21
A21
C20
B20
D20
A20
D19
C19
B24
A24
B23
B22
C22
A23
C21
B21
1
2
3
4
5
6
7
8
RN2
RPACK8-33
16
15
14
13
12
11
10
9
TED8
TED9
TED10
TED11
TED12
TED13
TED14
TED15
16
15
14
13
12
11
10
9
RPACK8-33
TED0
TED1
TED2
TED3
TED4
TED5
TED6
TED7
RN3
D
16
15
14
13
12
11
10
9
D3.3V
1
SDRAS/AOE
SDCAS/ARE
SDWE/AWE
SDCKE
SOE3
PDT
R89
4.7k
L22
ARDY
R41
10k
ECLKOUT1
ECLKOUT2
W24
HOLD
HOLDA
BUSREQ
RN14 RPACK4-33
8
7
6
5
ED56
ED57
ED58
ED59
ED60
ED61
ED62
ED63
ED48
ED49
ED50
ED51
ED52
ED53
ED54
ED55
ED40
ED41
ED42
ED43
ED44
ED45
ED46
ED47
ED32
ED33
ED34
ED35
ED36
ED37
ED38
ED39
EMIF and Emulation
TCE0#
TCE1#
TCE2#
TCE3#
J24
J25
K26
L25
R22
M22
33
33
33
33
33
33
R62
R63
R64
R65
R66
R67
TSOE3#
PDT#
J26
J23
TP13
TP
33
33
R68
R69
TECLKOUT2
TCE0#
TCE1#
TCE2#
TCE3#
PDT#
TSOE3#
TECLKOUT2
TCE0#
TCE1#
TP14
TP
TP15
TP
TP16
TP
TP17
TP
TP18
TP
C
TSDRAS#
TSDCAS#
TSDWE#
TSDCKE
TECLKOUT1
N22
P22
RN12
BE0
BE1
BE2
BE3
BE4
BE5
BE6
BE7
TP12
TP
TP
1
2
3
4
TEA[22..3]
1
K25
K24
K23
L26
TEA[22..3]
TP
RN13 RPACK4-33
8 TEA19
7 TEA20
6 TEA21
5 TEA22
1
1
2
3
4
TP
ED24
ED25
ED26
ED27
ED28
ED29
ED30
ED31
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
CE0
CE1
CE2
CE3
D3.3V
TP
TP11
TP
EMU3
EMU2
EMU1
EMU0
V26
V25
V24
U23
1
C15
B15
C14
A15
ECLKINSEL0 / EA19
ECLKINSEL1 / EA20
BOOTMODE0 / EA21
BOOTMODE1 / EA22
RPACK8-33
16 TEA11
15 TEA12
14 TEA13
13 TEA14
12 TEA15
11 TEA16
10 TEA17
9 TEA18
TP
DSP_EMU3
DSP_EMU2
DSP_EMU1
DSP_EMU0
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
1
2
3
4
5
6
7
8
1
C
EMU11
EMU10
RN7
R24
R23
T25
T24
U26
U25
U24
V23
TP
B17
D16
A17
C16
B16
D15
RPACK8-33
9 TEA3
10 TEA4
11 TEA5
12 TEA7
13 TEA6
14 TEA10
15 TEA9
16 TEA8
TP
D17
C17
DSP_EMU9
DSP_EMU8
DSP_EMU7
DSP_EMU6
DSP_EMU5
DSP_EMU4
EA11
EA12
EA13
EA14
EA15
EA16
EA17
EA18
DSP_EMU[11..0]
RN6
8
7
6
5
4
3
2
1
1
DSP_EMU11
DSP_EMU10
TMS
TRST
TDI
TDO
TCLK
EA3
EA4
EA5
EA7
EA6
EA10
EA9
EA8
1
E15
D14
A18
B18
A16
M24EA3
M23EA4
N26EA5
N24EA6
N23EA7
P26 EA8
P24 EA9
P23 EA10
TP
DSP_EMU[11..0]
DSP_TMS
DSP_TRST#
DSP_TDI
DSP_TDO
DSP_TCLK
EA03
EA04
EA05
EA06
EA07
EA08
EA09
EA10
1
DSP_TMS
DSP_TRST#
DSP_TDI
DSP_TDO
DSP_TCLK
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
U25A
L24
L23
M26
M25
R26
R25
T23
T22
1
2
3
4
5
6
7
8
RPACK8-33
16
15
14
13
12
11
10
9
TBE0#
TBE1#
TBE2#
TBE3#
TBE4#
TBE5#
TBE6#
TBE7#
AE21
AD21
AE22
AD22
AD23
AE23
AF23
AF24
AD19
AC19
AF20
AC20
AE20
AD20
AF21
AC21
AA25
AA23
AA26
Y24
Y25
Y23
Y26
W23
AD26
AD25
AC25
AC26
AB24
AB25
AB23
AA24
TMX320DM642CGDK
B
B
RPACK8-33
RPACK8-33
RN11
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
TED[63..0]
TED56
TED57
TED58
TED59
TED60
TED61
TED62
TED63
1
2
3
4
5
6
7
8
RPACK8-33
RN10
16
15
14
13
12
11
10
9
TED48
TED49
TED50
TED51
TED52
TED53
TED54
TED55
1
2
3
4
5
6
7
8
RPACK8-33
RN9
16
15
14
13
12
11
10
9
TED40
TED41
TED42
TED43
TED44
TED45
TED46
TED47
TED32
TED33
TED34
TED35
TED36
TED37
TED38
TED39
16
15
14
13
12
11
10
9
RN8
1
2
3
4
5
6
7
8
TED[63..0]
BOOT_MODE[1:0]
D3.3V
NOTE: PLACE ALL 33-OHM RESISTORS AND RESISTOR NETWORKS AS CLOSE AS POSSIBLE TO THE CORRESPONDING U25 PINS.
TEA22
TEA21
0
0
MODE SELECTED
NO BOOT (DEFAULT)
R35
R36
0
1
HPI/PCI BOOT MODE (PCIEN)
1k
1k
1
0
RESERVED
1
1
EMIF 8 BIT ROM BOOT
TEA21
TEA22
R21
NO POP
R22
NO POP
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
DM642 EMIF & JTAF
Size
C
Scale
FCSM No.
DWG No.
Rev
1
Sheet
10 of 17
1
2
3
4
5
6
1
2
3
4
6
5
D3.3V
D
D
R79
150
R42 R43 R44 R45
10k 10k 10k 10k
2
R78
150
2
2
R77
150
6
K A
K A
K A
U25D
5
7
V4
T2
M1
J2
1
1
1
BLUE_LED BLUE_LED BLUE_LED
N4
N3
N1
R3
P1
P3
R1
R2
F1
H4
C
K3
G4
GP13_A19
G3
GP15_A21
PCIEN
E2
C1
GP14_A20
R76
10k
T4
R4
P5
R5
PCBE0
PCBE1 / HDS2
PCBE2 / HR/W
PCBE3 / GP10
HD00 / AD00
HD01 / AD01
HD02 / AD02
HD03 / AD03
HD04 / AD04
HWDTHSEL / HD05 / AD05
HD06 / AD06
HD07 / AD07
HD08 / AD08
HD09 / AD09
HD10 / AD10
HD11 / AD11
HD12 / AD12
HD13 / AD13
HD14 / AD14
HD15 / AD15
MTXD0 / HD16 / AD16
MTXD1 / HD17 / AD17
MTXD2 / HD18 / AD18
MTXD3 / HD19 / AD19
MTXEN / HD20 / AD20
MCOL / HD21 / AD21
MTCLK / HD22 / AD22
HD23 / AD23
MRXD0 / HD24 / AD24
MRXD1 / HD25 / AD25
MRXD2 / HD26 / AD26
MRXD3 / HD27 / AD27
MRXDV / HD28 / AD28
MRXER / HD29 / AD29
MCRS / HD30 / AD30
MRCLK / HD31 / AD31
PFRAME / HINT
PTRDY / HHWIL
PIRDY / HRDY
PSTOP / HCNTL0
PDEVSEL / HCNTL1
PPAR / HAS
PPERR / HCS
PSERR / HDS1
PREQ / GP11
PGNT / GP12
PIDSEL / GP9
PINTA / GP13
PRST / GP15
PCIEN
Y3
AA1
Y4
Y2
W3
HWDTHSEL
Y1
W4
W2
V2
V3
V1
U4
U2
U3
U1
T3
M3
M2
M4
L2
L3
K2
L4
K1
K4
J1
J3
H2
J4
G2
H3
G1
HPI WIDTH SELECTION
HWDTHSEL
MODE SELECTED
0
16 BITS
1
32-BITS
C
PCI SELECTION
PCIEN
PCLK / GP14
MODE SELECTED
0
PCI DISABLED
1
PCI ENABLED
XSPCS
XSPDI
XSPDO / MDIO
XSPCLK / MDCLK
PCI / HPI / EMAC
B
B
TMX320DM642CGDK
D3.3V
R24
NO POP
D3.3V
HWDTHSEL
R25
NO POP
R23
NO POP
PCIEN
R37
1k
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
DM642 PCI/HPI/EMAC
A
A
Size
FCSM No.
Orcad B
Scale
1
2
3
4
DWG No.
Rev
1
Sheet
5
8 of 17
6
1
2
3
4
5
6
D
D
CORE CAPACITORS ARE 0402 SIZE
A1
A3
A6
A8
A12
A14
A19
A22
A26
B3
B6
B7
B13
B19
C2
C4
C13
C18
C23
D1
D2
D5
D13
D18
D22
D24
E3
E6
E9
E16
E18
E21
E23
E26
F5
F8
F10
F11
F13
F14
F16
F17
F19
F22
G9
G12
G15
G18
H1
H6
H21
H26
J5
J7
J20
J22
K6
K21
L1
L6
L21
M7
M13
M15
M20
N5
N6
N12
N14
N21
N25
D3.3V
DSP_CVDD
0.01uF
C20
0.01uF
C21
0.01uF
C25
C29
0.01uF
C32
0.01uF
F6
F7
F20
F21
G6
G7
G8
G10
G11
G13
G14
G16
G17
G19
G20
G21
H20
K7
K20
L7
L20
M12
M14
N7
N13
N15
N20
P7
P12
P14
P20
R13
R15
T7
T20
U7
U20
W20
Y6
Y7
Y8
Y10
Y11
Y13
Y14
Y16
Y17
Y19
Y20
Y21
AA6
AA7
AA20
AA21
0.01uF
DSP_CVDD
C13
C17
C22
C26
0.01uF
0.01uF
0.01uF
0.01uF
C30
C33
0.01uF
0.01uF
DSP_CVDD
C
C14
0.01uF
C19
0.01uF
C23
0.01uF
C27
0.01uF
DSP_CVDD
C15
0.01uF
C18
0.01uF
C24
0.01uF
C28
0.01uF
C31
C34
0.01uF
0.01uF
DSP_CVDD
C51
0.01uF
C52
0.01uF
C53
0.01uF
C54
0.01uF
C55
C56
0.01uF
0.01uF
DSP_CVDD
C170
+
10uF
C171
+
10uF
C172
+
10uF
B
D3.3V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C16
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
DSP_CVDD
0
0
H7
R6
W7
C8
C9
C10
C11
C12
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
CVDDMON
DVDDMON
VSSMON
Power and Ground
Connections
A2
A25
B1
B2
B14
B25
B26
C3
C24
D4
D23
E5
E7
E8
E10
E17
E19
E20
E22
F9
F12
F15
F18
G5
G22
H5
H22
J6
J21
K5
K22
M6
M21
N2
P25
R21
U5
U22
V21
W5
W22
W25
Y5
Y22
AA9
AA12
AA15
AA18
AB5
AB7
AB8
AB10
AB17
AB19
AB20
AB22
AC23
AD24
AE1
AE2
AE13
AE25
AE26
AF2
AF25
0.1uF
C37
C40
C43
C46
0.1uF
0.1uF
0.1uF
0.1uF
C35
C38
C41
C44
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C36
C39
C42
C45
C47
C50
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
D3.3V
D3.3V
C48
C
C49
0.1uF
D3.3V
D3.3V
C57
C59
C63
C66
C69
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
D3.3V
C58
C60
C61
C64
C67
C71
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C62
C65
C68
C70
0.1uF
0.1uF
0.1uF
0.1uF
D3.3V
B
D3.3V
C173
+
C174
+
C175
+
33uF
33uF
33uF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R90
R91
C7
D3.3V
U25C
DSP_CVDD
TMX320DM642CGDK
P2
P6
P13
P15
P21
R7
R12
R14
R20
T1
T5
T6
T21
T26
U6
U21
V5
V7
V20
V22
W1
W6
W21
W26
Y9
Y12
Y15
Y18
AA4
AA5
AA8
AA10
AA11
AA13
AA14
AA16
AA17
AA19
AA22
AB1
AB2
AB4
AB6
AB9
AB18
AB21
AB26
AC3
AC5
AC18
AC22
AC24
AD2
AD4
AD18
AE3
AE8
AE10
AE12
AE14
AE19
AE24
AF1
AF7
AF9
AF11
AF13
AF15
AF19
AF22
AF26
101562-0001
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
DM642 POWER PINS
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
9 of 17
6
1
2
3
4
5
6
D
D
TED[31..0]
TED[31..0]
D3.3V
C72
0.1uF
U4
D3.3V
R49
10k
R50
10k
R51
10k
R52
10k
GP13_A19
GP14_A20
GP15_A21
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
38
29
22
24
9
TCE1#
TSDCAS#
TSDWE#
10
D3.3V
R53
R26
10k
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
25
26
27
28
32
33
34
35
TED0
TED1
TED2
TED3
TED4
TED5
TED6
TED7
C
RDY-BY
12
CE
OE
WE
RESET
ACC
VSS1
VSS2
TEA3
TEA4
TEA5
TEA6
TEA7
TEA8
TEA9
TEA10
TEA11
TEA12
TEA13
TEA14
TEA15
TEA16
TEA17
TEA18
TEA19
TEA20
TEA21
C
/RESET
C73
0.1uF
30
31
TEA[22..3]
VCC
VCC2
TEA[22..3]
NO POP
23
39
AM29LV033C-90EI
B
B
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
FLASH MEMORY
Size
C
Scale
FCSM No.
DWG No.
Rev
1
Sheet
14 of 17
1
2
3
4
5
6
1
2
3
4
5
6
D
D
3.3V_SUPPLY
D5V
C74
0.1uF
C75
0.1uF
C76
0.1uF
C77
0.1uF
C78
0.1uF
1
1
1
TP
TP22
TP
TP
TP21
TP
TP
TP20
TP
TP
TP19
TP
1
3.3V_SUPPLY
U5
42
31
C
SCK4
CH4_OUT[7..0]
CH4_OUT[7..0]
47
CH4_OUT0
46
CH4_OUT1
44
CH4_OUT2
43
CH4_OUT3
41
CH4_OUT4
40
CH4_OUT5
38
CH4_OUT6
37
CH4_OUT7
36
35
33
32
30
29
27
26
3.3V_SUPPLY
48
1
25
24
4
10
15
21
Vcc
Vcc
Vcc
Vcc
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
7
18
D5V
U6
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
SCLK
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
2
3
4
5
6
7
8
9
10
11
12
CLK/I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
GND
VCC
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
I11
24
23
22
21
20
19
18
17
16
15
14
13
C
PALCE22V10H-10PC/5
1OE
1DIR
2OE
2DIR
GND
GND
GND
GND
GND
GND
GND
GND
28
34
39
45
SN74LVT16245BDGGR
#OE
L
L
H
B
DIR
L
H
X
OPERATION
A <--- B
A ---> B
ISOLATION
B
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
F&V BIT BREAKOUT
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
12 of 17
6
1
2
3
4
5
6
D
D
D5V
H1
1
3
5
7
9
11
SCL
SDA
SCL
SDA
HEADER 6X2
/RESET
CH1_OUT[7..0]
2
4
6
8
10
12
CH1_OUT[7..0]
H2
CH1_OUT0
CH1_OUT1
CH1_OUT2
CH1_OUT3
CH1_OUT4
CH1_OUT5
CH1_OUT6
CH1_OUT7
SCKS1
SCK1
VB1
AV1
HS1
VS1
FID1
SCKS1
SCK1
VB1
AV1
HS1
VS1
FID1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
HEADER 16X2
C
C
CH2_OUT[7..0]
CH2_OUT[7..0]
H3
CH2_OUT0
CH2_OUT1
CH2_OUT2
CH2_OUT3
CH2_OUT4
CH2_OUT5
CH2_OUT6
CH2_OUT7
SCKS2
SCK2
VB2
AV2
HS2
VS2
FID2
SCKS2
SCK2
VB2
AV2
HS2
VS2
FID2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
HEADER 16X2
CH3_OUT[7..0]
B
CH3_OUT[7..0]
H4
CH3_OUT0
CH3_OUT1
CH3_OUT2
CH3_OUT3
CH3_OUT4
CH3_OUT5
CH3_OUT6
CH3_OUT7
SCKS3
SCK3
VB3
AV3
HS3
VS3
FID3
SCKS3
SCK3
VB3
AV3
HS3
VS3
FID3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
B
HEADER 16X2
CH4_OUT[7..0]
SCKS4
SCK4
VB4
AV4
HS4
VS4
FID4
CH4_OUT[7..0]
H5
CH4_OUT0
CH4_OUT1
CH4_OUT2
CH4_OUT3
CH4_OUT4
CH4_OUT5
CH4_OUT6
CH4_OUT7
SCKS4
SCK4
VB4
AV4
HS4
VS4
FID4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
HEADER 16X2
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
DAUGHTERCARD INTERFACE
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
3 of 17
6
1
2
C81
0.1uF
C83
0.1uF
C85
0.1uF
5
6
IOVDD
C86
0.1uF
C88
0.1uF
C90
0.1uF
C92
0.1uF
C94
0.1uF
C96
0.1uF
P1
SMA_PCB_MT_MOD
R92
0
1
CH2_PLL_VDD
CH3_PLL_VDD
CH4_PLL_VDD
C80
0.1uF
C82
0.1uF
C84
0.1uF
C87
0.1uF
DVDD
C89
0.1uF
C91
0.1uF
C93
0.1uF
C95
0.1uF
R93
0
50
R101
5
4
3
2
CH1_PLL_VDD
X2
C79
0.1uF
4
X1/OSC
CH1_AVDD CH2_AVDD CH3_AVDD CH4_AVDD AVDD_REF
3
C97
0.1uF
D
R102
100k
Y4
14.31818MHz
C176
33pF
C177
33pF
CH1_D0
CH1_D1
CH1_D2
CH1_D3
CH1_D4
CH1_D5
CH1_D6
CH1_D7
CH4_AVDD
INPUT V DIVIDER NETWORK
CH3_PLL_VDD
CH3_AVDD
FOR 0-0.75V INPUT RANGE
DVDD
CH1_AVDD
REMEMBER 75ohm TERMINATION
REFP1
REFM1
X1/OSC
X2
PDN
/RESET
SCL
SDA
I2CSEL1
I2CSEL2
CH2_PLL_VDD
CH2_AVDD
R10437.4
2
CH1_A
JP5
1
R11237.4
2
BNC2
BNC_RA
1A_IN
JP2
1
1A_OUT
1B_IN
R10537.4
2
CH2_A
1B_IN
BNC6
BNC_RA
1B_OUT
1B_OUT
JP6
1
R11337.4
2
BNC3
BNC_RA
2A_IN
2A_OUT
JP3
1
2A_OUT
2B_IN
R10637.4
2
CH3_A
2B_IN
BNC7
BNC_RA
2B_OUT
JP7
1
R11437.4
2
JP4
1
3A_OUT
3B_IN
R10737.4
2
CH4_A
3B_IN
BNC8
BNC_RA
3B_OUT
JP8
1
R11537.4
2
0.1uF
CH2_B C101
0.1uF
REFM3
REFP3
CH3_A C102
0.1uF
CH3_B C103
0.1uF
CH4_B
REFM4
REFP4
4A_OUT
4B_IN
4B_IN
4
3
4A_OUT
CH2_A C100
R119
37.4
4
3
4A_IN
REFM2
REFP2
CH3_B
3B_OUT
R111
37.4
4A_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
4
3
3A_OUT
0.1uF
R118
37.4
4
3
BNC4
BNC_RA
3A_IN
0.1uF
CH1_B C99
CH2_B
2B_OUT
R110
37.4
3A_IN
CH1_A C98
4
3
3
2A_IN
U1
R117
37.4
4
R109
37.4
C
CH1_B
4
3
1A_OUT
4B_OUT
4B_OUT
CH4_A C104
0.1uF
CH4_B C105
0.1uF
AI1GND
AI1A
AI1B
PLL_VDD
PLL_GND
REFM2
REFP2
AVDD
AGND
AI2GND
AI2A
AI2B
PLL_VDD
PLL_GND
AVDD
AGND
REFM3
REFP3
AVDD
AGND
AI3GND
AI3A
AI3B
PLL_VDD
PLL_GND
REFM4
REFP4
AVDD
AGND
AI4GND
AI4A
AI4B
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
IOGND
VSYNC1/PALI1
FID1/GLCO1
CH2OUT0
CH2OUT1
CH2OUT2
CH2OUT3
CH2OUT4
CH2OUT5
CH2OUT6
CH2OUT7
SCLK2
CLK2
INT2/GPCL2/VBLK2
DGND
DVDD
IOVDD
IOGND
AVID2
HSYNC2
VSYNC2/PALI2
FID2/GLCO2
CH3OUT0
CH3OUT1
CH3OUT2
CH3OUT3
CH3OUT4
CH3OUT5
CH3OUT6
CH3OUT7
DGND
DVDD
CH2_D0
CH2_D1
CH2_D2
CH2_D3
CH2_D4
CH2_D5
CH2_D6
CH2_D7
CH2_OUT[7..0]
CH3_OUT[7..0]
SCLKS3
SCLK3
GPCL3/VBLK3
AVID3
HSYNC3
VSYNC3/PALI3
FID3/GLCO3
TMS
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
IOVDD
SCLKS3
SCLK3
GPCL3/VBLK3
AVID3
HSYNC3
VSYNC3/PALI3
FID3/GLCO3
R57
10k
IOVDD
2
JP11
/PDN
SCKS3
SCK3
VB3
AV3
HS3
VS3
FID3
B
RN22
RPACK8-33
CH4_OUT0
CH4_OUT1
CH4_OUT2
CH4_OUT3
CH4_OUT4
CH4_OUT5
CH4_OUT6
CH4_OUT7
CH4_D0
CH4_D1
CH4_D2
CH4_D3
CH4_D4
CH4_D5
CH4_D6
CH4_D7
CH4_OUT[7..0]
SCLKS4
SCLK4
GPCL4/VBLK4
AVID4
HSYNC4
VSYNC4/PALI4
FID4/GLCO4
1
PDN
SCKS3
SCK3
VB3
AV3
HS3
VS3
FID3
CH4_OUT[7..0]
RN21
SCLKS4
SCLK4
GPCL4/VBLK4
AVID4
HSYNC4
VSYNC4/PALI4
FID4/GLCO4
SCKS4
SCK4
VB4
AV4
HS4
VS4
FID4
SCKS4
SCK4
VB4
AV4
HS4
VS4
FID4
3
JP10
I2C ADR
3
I2CSEL2 2
CH3_OUT[7..0]
RPACK8-33
CH4_D0
CH4_D1
CH4_D2
CH4_D3
CH4_D4
CH4_D5
CH4_D6
CH4_D7
R56
10k
1
1
JP9
I2C ADR
3
I2CSEL1 2
RN19
RPACK8-33
CH3_OUT0
CH3_OUT1
CH3_OUT2
CH3_OUT3
CH3_OUT4
CH3_OUT5
CH3_OUT6
CH3_OUT7
CH3_D0
CH3_D1
CH3_D2
CH3_D3
CH3_D4
CH3_D5
CH3_D6
CH3_D7
RN20
POWERDOWN
R55
10k
C
SCKS2
SCK2
VB2
AV2
HS2
VS2
FID2
RPACK8-33
CH3_D0
CH3_D1
CH3_D2
CH3_D3
CH3_D4
CH3_D5
CH3_D6
CH3_D7
2-3 Powerdown
IOVDD
SCKS2
SCK2
VB2
AV2
HS2
VS2
FID2
SCLKS2
SCLK2
GPCL2/VBLK2
AVID2
HSYNC2
VSYNC2/PALI2
FID2/GLCO2
AVID2
HSYNC2
VSYNC2/PALI2
FID2/GLCO2
1-2 Normal Operation - Default
R54
10k
CH2_OUT[7..0]
RN17
SCLKS2
SCLK2
GPCL2/VBLK2
B
2-3 Base Addr 0xB8 - Default
RN18
RPACK8-33
CH2_OUT0
CH2_OUT1
CH2_OUT2
CH2_OUT3
CH2_OUT4
CH2_OUT5
CH2_OUT6
CH2_OUT7
CH2_D0
CH2_D1
CH2_D2
CH2_D3
CH2_D4
CH2_D5
CH2_D6
CH2_D7
TVP5154PNP
I2C ADDRESS SELECTION
SCKS1
SCK1
VB1
AV1
HS1
VS1
FID1
RPACK8-33
R116
37.4
4
3
R108
37.4
1A_IN
SCKS1
SCK1
VB1
AV1
HS1
VS1
FID1
SCLKS1
SCLK1
GPCL1/VBLK1
AVID1
HSYNC1
VSYNC1/PALI1
FID1/GLCO1
CH1_PLL_VDD
AGND
AVDD
REFP1
REFM1
XIN/OSC
XOUT
PDN
RESETB
SCL
SDA
I2CA0
I2CA1
DGND
DVDD
IOVDD
IOGND
CH1OUT0
CH1OUT1
CH1OUT2
CH1OUT3
CH1OUT4
CH1OUT5
CH1OUT6
CH1OUT7
SCLK1
CLK1
INT1/GPCL1/VBLK1
AVID1
HSYNC1
DGND
DVDD
IODVDD
1
BNC5
BNC_RA
PLL_VDD
PLL_GND
AGND
TMS
FID4/GLCO4
VSYNC4/PALI4
HSYNC4
AVID4
INT4/GPCL4/VBLK4
CLK4
SCLK4
IOGND
IOVDD
DVDD
DGND
CH4OUT7
CH4OUT6
CH4OUT5
CH4OUT4
CH4OUT3
CH4OUT2
CH4OUT1
CH4OUT0
FID3/GLCO3
VSYNC3/PALI3
HSYNC3
AVID3
INT4/GPCL4/VBLK4
CLK3
SCLK3
IOGND
IOVDD
JP1
CH1_OUT[7..0]
RN15
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
CH4_PLL_VDD
BNC1
BNC_RA
D
CH1_OUT[7..0]
SCLKS1
SCLK1
GPCL1/VBLK1
AVID1
HSYNC1
VSYNC1/PALI1
FID1/GLCO1
IOVDD
AVDD_REF
RN16
RPACK8-33
CH1_OUT0
CH1_OUT1
CH1_OUT2
CH1_OUT3
CH1_OUT4
CH1_OUT5
CH1_OUT6
CH1_OUT7
CH1_D0
CH1_D1
CH1_D2
CH1_D3
CH1_D4
CH1_D5
CH1_D6
CH1_D7
R58
10k
RPACK8-33
SDA
SCL
C178
1uF
C180
1uF
C181
1uF
C183
1uF
C179
C184
1uF
C186
1uF
C182
C187
1uF
C189
1uF
C185
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
1uF
REFP4
REFM4
1uF
REFP3
REFM3
1uF
REFP2
REFM2
1uF
REFP1
REFM1
R120
100
/RESET
C188
IOVDD
A
SDA
SCL
/RESET
A
TVP5154
TMS
R59
10k
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
2 of 17
6
1
2
3
4
5
6
NOTE: FILTERS DESIGNED FOR CVBS INPUTS (ADC SAMPLING RATE = 27MHz)
D
C202
8.2pF
L4
2.2uH
1A_IN
1A_OUT
C210
330pF
C204
8.2pF
L6
2.2uH
C205
8.2pF
L8
2.2uH
B
8.2pF
L9
2.2uH
8.2pF
L7
2.2uH
C213
330pF
2B_IN
2B_OUT
C217
330pF
C
C2078.2pF
L10 2.2uH
4A_IN
4A_OUT
C220
330pF
C222
330pF
C209
C224
330pF
B
8.2pF
L11 2.2uH
3B_IN
3B_OUT
C219
330pF
C206
C216
330pF
3A_OUT
C208
2.2uH
D
2A_OUT
C215
330pF
3A_IN
C218
330pF
L5
C212
330pF
1B_OUT
C214
330pF
8.2pF
2A_IN
C211
330pF
1B_IN
C
C203
4B_IN
4B_OUT
C221
330pF
C223
330pF
C225
330pF
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
ANTI-ALIASING FILTERS
A
A
Size
B
FCSM No.
Scale
1
2
3
4
DWG No.
Rev
1
Sheet
5
11 of 17
6
1
2
3
4
5
6
D
D
D3.3V
C106
C
0.1uF
R83
2.2k
C
R84
2.2k
TP23
TP
P2
U2C
5
8
9
R94
SCL
SCL
0
SN74AHC05DR
DB15
SN74AHC05DR
U2F
13
DB17
12
D3.3V
SN74AHC05DR
U2A
1
DB9
R88
2.2k
14
R87
2.2k
2
SN74AHC05DR
TP24
TP
1
TP
DB11
U2B
4
DB25F_182-25F-ND
26
U2D
6
7
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
1
27
TP
2.2k
R82
R85
2.2k
0
3
SDA
SDA
R95
R86
2.2k
SN74AHC05DR
B
B
U2E
11
10
SN74AHC05DR
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
I2C
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
17 of 17
6
1
2
3
4
5
6
D3.3V
C107
0.1uF
C109
0.1uF
C111
0.1uF
C113
0.1uF
C115
0.1uF
C117
0.1uF
C119
0.1uF
C121
0.1uF
C123
0.1uF
C125
0.1uF
C127
0.1uF
C129
0.1uF
C108
0.1uF
C110
0.1uF
C112
0.1uF
C114
0.1uF
C116
0.1uF
C118
0.1uF
C120
0.1uF
C122
0.1uF
C124
0.1uF
C126
0.1uF
C128
0.1uF
C130
0.1uF
D3.3V
D
TED[63..0]
D
TED[63..0]
D3.3V
D3.3V
U7
C
TED7
TED6
TED5
TED4
TED3
TED2
TED1
TED0
TBE0#
TSDWE#
TSDCAS#
TSDRAS#
TCE0#
TBE0#
TSDWE#
TSDCAS#
TSDRAS#
TCE0#
TEA14
TEA15
TEA16
TEA13
TEA3
TEA4
TEA5
TBE2#
TBE1#
TBE3#
TBE4#
TBE5#
TBE6#
TBE7#
TBE2#
TBE1#
TBE3#
TBE4#
TBE5#
TBE6#
TBE7#
TSDCKE
TSDCKE
TECLKOUT1
TECLKOUT1
B
TED16
TED17
TED18
TED19
TED20
TED21
TED22
TED23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VDD
D0
VDDQ
D1
D2
VSSQ
D3
D4
VDDQ
D5
D6
VSSQ
D7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
A11
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
D16
VSSQ
D17
D18
VDDQ
D19
D20
VSSQ
D21
D22
VDDQ
D23
VDD
U8
VSS
D15
VSSQ
D14
D13
VDDQ
D12
D11
VSSQ
D10
D9
VDDQ
D8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
D31
VDDQ
D30
D29
VSSQ
D28
D27
VDDQ
D26
D25
VSSQ
D24
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
TED15
TED39
TED14
TED13
TED38
TED37
TED12
TED11
TED36
TED35
TED10
TED9
TED34
TED33
TED8
TED32
TBE1#
TECLKOUT1
TSDCKE
TEA12
TEA11
TEA10
TEA9
TEA8
TEA7
TEA6
TBE3#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
TBE4#
TSDWE#
TSDCAS#
TSDRAS#
TCE0#
TEA14
TEA15
TEA16
TEA13
TEA3
TEA4
TEA5
TBE6#
TED31
TED48
TED30
TED29
TED49
TED50
TED28
TED27
TED51
TED52
TED26
TED25
TED53
TED54
TED24
TED55
MT48LC4M32B2TG-6
TEA[22..3]
VDD
D0
VDDQ
D1
D2
VSSQ
D3
D4
VDDQ
D5
D6
VSSQ
D7
NC
VDD
DQM0
/WE
/CAS
/RAS
/CS
A11
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
D16
VSSQ
D17
D18
VDDQ
D19
D20
VSSQ
D21
D22
VDDQ
D23
VDD
VSS
D15
VSSQ
D14
D13
VDDQ
D12
D11
VSSQ
D10
D9
VDDQ
D8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
D31
VDDQ
D30
D29
VSSQ
D28
D27
VDDQ
D26
D25
VSSQ
D24
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
C
TED47
TED46
TED45
TED44
TED43
TED42
TED41
TED40
TBE5#
TECLKOUT1
TSDCKE
TEA12
TEA11
TEA10
TEA9
TEA8
TEA7
TEA6
TBE7#
TED63
TED62
TED61
TED60
TED59
B
TED58
TED57
TED56
MT48LC4M32B2TG-6
TEA[22..3]
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
SDRAM
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
13 of 17
6
1
2
3
4
5
6
D
D
ROUTE TRACES AS ONE GROUP. MATCH SIGNAL LENGTH.
P3
C2
B3
C4
C5
B5
C6
B6
C7
C9
B9
C10
B10
C11
B11
C12
C13
B13
C14
XDS_EMU1
XDS_EMU0
B14
XDS_TCKRET C8
XDS_TCK
B12
XDS_TDO
B7
XDS_TDI
B4
XDS_TMS
B2
XDS_TRST#
C3
C15
C1
B15
B1
1k
B8
LOCATE R-PACK NEAR DSP
D3.3V
DSP_EMU[11..0]
DSP_EMU[11..0]
XDS_TMS
XDS_TDI
1
3
5
XDS_TDO
7
XDS_TCKRET 9
XDS_TCK
11
XDS_EMU0 13
C
XDS_TRST#
2
4
8
10
12
14
RN23RPACK8-39
DSP_EMU11
DSP_EMU10
DSP_EMU9
DSP_EMU8
DSP_EMU7
DSP_EMU6
DSP_EMU5
DSP_EMU4
H6
XDS_EMU1
DSP_EMU3
DSP_EMU2
DSP_EMU1
DSP_EMU0
HEADER 7x2, Emulation
DSP_TDO
RN24RPACK8-39
D3.3V
R38
XDS_TDI
XDS_TMS
XDS_TRST#
DSP_TDI
DSP_TMS
DSP_TRST#
EMU18
EMU17
EMU16
EMU15
EMU14
EMU13
EMU12
EMU11
EMU10
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
EMU3
EMU2
EMU1
EMU0
TCKRTN
TCLK
TDO
TDI
TMS
TRSTn
ID3
ID2
ID1
ID0
TVD
GND
GND
GND
GND
GND
GND
GND
TYPE0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TYPE1
GND
GND
GND
GND
GND
GND
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
C
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Samtec SOLC-115-02-S-Q-A
C131
0.1uF
5
D3.3V
U9
XDS_TCK
1
4
B
R4
33
2
DSP_TCLK
B
3
SN74LVC1G32DCKR
C132
0.1uF
5
D3.3V
C226
R121 100 1%
U10
1
4
18pF
R5
XDS_TCKRET
33
2
3
SN74LVC1G32DCKR
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
JTAG
Size
C
Scale
1
2
3
4
5
FCSM No.
DWG No.
Rev
1
Sheet
15 of 17
6
1
2
3
4
5
6
7
8
RESET ON POWER UP
POWER ON LED (+5V)
5V, 3.0A DC INPUT
D3.3V
D
R103
D5V
D5V
F1
D
100k
FUSE
L12
C1330.1uF
U11
R122
330
P4
PJ-002BH
2
D1
ZENER
3
2
1
LED1
GRN_LED
+ C227
47uF
C228
22uF
1
2
3
4
S1
PB
SS26
C190
1uF
HEADER 3
8
7
6
5
CONTROL
VDD
/RESIN
SENSE
CT
RESET
GND
/RESET
/RESET
/RESET
TLC7733IPWR
1
K A
H7
1
3
2
VOUT1 IS 3.3V 1A
VOUT2 IS 1.8V 2A
FB1
FERRITE
R123
249k
R96
R27
NO POP
C231
22uF
R124249k
R126
L14
1.8V_SUPPLY
EMI SUPPRESION. LOCATE NEAR EACH REGULATOR.C145
0
R97
R28
NO POP
C232
22uF
6 VIAS FROM PAD TO PLANE OR DIRECT TIE.
C142
0.1uF
0.1uF
0.039uF
1
+
CH1_AVDD
FB2
1
2
C134
C233
22uF
21
20
19
18
17
16
15
14
C258
BLM41P750SPT
+
C144
0.1uF
C146
0.1uF
10uF LESR
FERRITE
C191
C235
22uF
0.1uF
C255
47uF
C263
8200pF
C260
470pF
U13
L15
HEADER 2
J2
R127
2k 1%
71.5k 1%
C256
13
12
11
C138
POWERPAD
RT
SYNC
SS/ENA
VBIAS
VIN3
VIN2
VIN1
AGND
VSENSE
COMP
PWRGD
BOOT
TP25
TP
D3.3V
3300pF
C266
107 1%
TP
R125249k
TPS70451PWP
R129
3.74k 1%
D5V
H8
Sets Voltage
C141
0.1uF
1.8V_SUPPLY J1
JUMPER
2
C
3.3V_SUPPLY
L13
R132
R60
10k
1
2
3
4
5
10k 1%
1
C137
0.1uF
24
23
22
21
20
19
18
17
16
15
14
13
25
C230
22uF
C136
0.1uF
GND
GND
VIN1A
VOUT1A
VIN1B
VOUT1B
NC
VSENSE1/FB1
/MR
NC
/EN1
PG1
/EN2
PG2
/RESET
NC
GND
VSENSE2/FB2
VIN2A
VOUT2A
VIN2B
VOUT2B
GND
GND
PP
C229
22uF
1
2
3
4
5
6
7
8
9
10
11
12
Connect at pin 1
3.3 sq in AGND, min thermal pad
0
U12
D5V
R130
C261
C
L17 2.7uH
D3.3V
C272
0.047uF
PH1
PH2
PH3
PH4
PH5
PGND3
PGND2
PGND1
NO POP
6
7
8
9
10
+
C268
1000pF
C264
100uF
D13
C270
100 uF
MURS120T3
TPS54310PWP
1uF
0.1uF
3.3V @1.5Amp Max
2
OPTIONAL CROSS COUPLE
1.8V_SUPPLY J3
JUMPER
H9
HEADER 2
J4
C135
C234
22uF
H10
FERRITE
C192
C236
22uF
0.1uF
1.4V -> 17.4K 1%
Connect at pin 1
1.2V -> 28.0K 1%
3.3 sq in AGND, min thermal pad
1.1V -> 42.2K 1%
CH2_AVDD
FB3
1
2
1uF
0.1uF
C140
C237
22uF
HEADER 2
2
J7
C238
22uF
C193
C143
1uF
0.1uF
R134
71.5k 1%
2
C160
C257
0.1uF
0.039uF
21
20
19
18
17
L16
HEADER 2
J5
CH3_AVDD
FB5
1
2
C147
C239
22uF
H14
FERRITE
C242
22uF
0.1uF
R135
1.65k 1%
C194
C150
1
2
1uF
0.1uF
HEADER 2
C153
C245
22uF
2
J8
1
JUMPER
CH2_PLL_VDD
FB8
C197
C248
22uF
0.1uF
C259
BLM41P750SPT
FERRITE
C156
1uF
C159
0.1uF
0.1uF
+
10uF LESR
2
16
15
14
C161
0.1uF
13
12
11
D16
C274
0.01uF
MURS120T3
C273
560pF
U14
1
JUMPER
H11
MURS120T3
R128
17.4k 1%
FERRITE
0.1uF
D15
CH1_PLL_VDD
FB4
1
2
C139
1
JUMPER
D14
MURS120T3
1
2
1
JUMPER
POWERPAD
RT
SYNC
SS/ENA
VBIAS
VIN3
VIN2
VIN1
AGND
VSENSE
COMP
PWRGD
BOOT
R133
107 1%
C267
3300pF
1
2
3
4
5
D17
MURS120T3
R131
10k 1%
C262
1.4V @1.5Amp Max
L18 2.7uH
DSP_CVDD
0.047uF
PH1
PH2
PH3
PH4
PH5
PGND3
PGND2
PGND1
6
7
8
9
10
C271
C265
100uF
+
C269
1000pF
100 uF
TPS54310PWP
1
JUMPER
FB11
FERRITE
B
H12
1
2
HEADER 2
J6
CH4_AVDD
FB6
C148
C240
22uF
FERRITE
C243
22uF
0.1uF
B
H15
C195
C151
1uF
0.1uF
2
C154
C246
22uF
HEADER 2
J9
1
JUMPER
FB9
1
2
FERRITE
C249
22uF
0.1uF
POWER ESTIMATES BASED ON SPRU190
1.4V@600MHz 1.09 W 0.778A
3.3V@600MHz 0.52 W 0.157A ( no emif clk)
MEASURED CURRENT ON C6416TEB, ~0.7A@5V
CH3_PLL_VDD
C198
C157
1uF
0.1uF
2
EACH REGULATOR CAN SUPPLY UP TO 3A OF CURRENT. HOWEVER COMPONENT VALUES HAVE BEEN SELECTED FOR 1.5A OPERATION.
1
JUMPER
H13
AVDD_REF
FB7
1
2
HEADER 2
C149
C241
22uF
FERRITE
C244
22uF
0.1uF
C196
C152
1uF
0.1uF
H16
C155
C247
22uF
HEADER 2
FERRITE
C250
22uF
0.1uF
VALUES CALCULATED WITH SWIFT DESIGN TOOL 2.0.
FOLLOW TPS54310 EVM LAYOUT
CH4_PLL_VDD
FB10
1
2
C199
C158
1uF
0.1uF
TP
1
TP37
TP
TP40
TP
TP
TP34
TP
TP
TP31
TP
1
TP
TP28
DSP_CVDDTP
1
1
2
TP
1
TP39
TP
TP
TP36
TP
TP
TP33
TP
1
J11
JUMPER
TP
1
TP30
TP
TP
TP27
TP
TP
D5V
1
FERRITE
TP
FB19
FERRITE
TP38
TP
1
FB17
FERRITE
TP35
TP
1
0.1uF
TP
C164
1uF
1
C200
TP32
TP
1
C253
22uF
TP29
TP
1
FB15
TP26
D3.3V TP
TP
FERRITE
TP
FERRITE
0.1uF
FB18
FERRITE
1
C162
C251
22uF
FB16
FERRITE
1
1
2
HEADER 2
1.8V_SUPPLY
FB14
IOVDD
FB12
1
H17
TP
1
2
3.3V_SUPPLY J10
JUMPER
H18
DVDD
FB13
1
2
A
HEADER 2
C163
C252
22uF
0.1uF
A
FERRITE
C254
22uF
C201
C165
1uF
0.1uF
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
POWER
Size
D
Scale
FCSM No.
DWG No.
Rev
1
Sheet
7 of 17
1
2
3
4
5
6
7
8
1
2
3
4
5
6
D
D
D5V
D5V
D5V
D5V
P5
C
SCL
SDA
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
5V
5V
GND
GND
GND
SCL/PHI_ACK
SDA/PHI_RWW
PHI_DS/RD
PHI_CS
PHI_A1
PHI_A0
PHI_D7
PHI_D6
PHI_D5
PHI_D4
PHI_D3
PHI_D2
PHI_D1
PHI_D0
GND
CLK5/M1
FPDAT/VSYA/M2
FFRSTW/CBFLAG
FSY/HC/HSYA/~BLNK
VGAV/SYNC_T
FFIE/CCVALID
FFWE/DVALID
FFRSTWIN/~SCLK
FFRE/DIG_H
FFOE/DIG_V
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
5V
5V
GND
GND
GND
AMXCLK
ALRCLK
ASCLK
AMCLK
GND
GPIO7
GPIO6
GPIO5
GPIO4
GND
GPIO3
GPIO2
GPIO1
GPIO0
INTREQ
GPCL
GND
ITRDY
SOGOUT
VACTIVE
D_SCLK
D_RDY
D_PREF
D_HS
D_VS
/RESET
ENC_HS
R98
0
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
5V
GND
ENC_C[7..0]
GND ENC_C[7..0]
ENC_C7
RCr9
ENC_C6
RCr8
ENC_C5
RCr7
ENC_C4
RCr6
ENC_C3
RCr5
ENC_C2
RCr4
ENC_C1
RCr3
ENC_C0
RCr2
RCr1
RCr0
ENC_Y[7..0]
GND ENC_Y[7..0]
ENC_Y7
D9
ENC_Y6
D8
ENC_Y5
D7
ENC_Y4
D6
ENC_Y3
D5
ENC_Y2
D4
ENC_Y1
D3
ENC_Y0
D2
D1
D0
GND
R99 0
RESET
ENC_FID
R100 0
PALI
HSYNC
ENC_VS
AVID
PREF
ENC_SCLK
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
5V
GND
GND
BCb9
BCb8
BCb7
BCb6
BCb5
BCb4
BCb3
BCb2
BCb1
BCb0
GND
GY9
GY8
GY7
GY6
GY5
GY4
GY3
GY2
GY1
GY0
GND
FID
GLCO
VSYNC
PCLK
SCLK
C
SAMTEC_TMMS_120PIN_M_RA
B
B
TEXAS INSTRUMENTS, INC.
12500 TI BLVD
DALLAS, TEXAS 75243
A
A
CONNECTOR
Size
C
Scale
FCSM No.
DWG No.
Rev
1
Sheet
16 of 17
1
2
3
4
5
6
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