Download Life is good 42LA790W-ZA Flat Panel Television User Manual
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Internal Use Only North/Latin America Europe/Africa Asia/Oceania http://aic.lgservice.com http://eic.lgservice.com http://biz.lgservice.com LED LCD TV SERVICE MANUAL CHASSIS : LD23E MODEL : 42LM860V/W 42LM860V/W-ZB CAUTION BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL. P/NO : MFL67361006 (1206-REV00) Printed in Korea CONTENTS CONTENTS . ............................................................................................. 2 SAFETY PRECAUTIONS ......................................................................... 3 SERVICING PRECAUTIONS..................................................................... 4 SPECIFICATION........................................................................................ 6 ADJUSTMENT INSTRUCTION............................................................... 12 EXPLODED VIEW .................................................................................. 21 SCHEMATIC CIRCUIT DIAGRAM .............................................................. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes -2- LGE Internal Use Only SAFETY PRECAUTIONS IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. General Guidance Leakage Current Hot Check (See below Figure) Plug the AC cord directly into the AC outlet. An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks. It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation. If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified. When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB. Keep wires away from high voltage or high temperature parts. Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to 0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer. Leakage Current Hot Check circuit Before returning the receiver to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock. Leakage Current Cold Check(Antenna Cold Check) With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes -3- LGE Internal Use Only SERVICING PRECAUTIONS CAUTION: Before servicing receivers covered by this service manual and its supplements and addenda, read and follow the SAFETY PRECAUTIONS on page 3 of this publication. NOTE: If unforeseen circumstances create conflict between the following servicing precautions and any of the safety precautions on page 3 of this publication, always follow the safety precautions. Remember: Safety First. General Servicing Precautions 1. Always unplug the receiver AC power cord from the AC power source before; a. Removing or reinstalling any component, circuit board module or any other receiver assembly. b. Disconnecting or reconnecting any receiver electrical plug or other electrical connection. c. Connecting a test substitute in parallel with an electrolytic capacitor in the receiver. CAUTION: A wrong part substitution or incorrect polarity installation of electrolytic capacitors may result in an explosion hazard. 2. Test high voltage only by measuring it with an appropriate high voltage meter or other voltage measuring device (DVM, FETVOM, etc) equipped with a suitable high voltage probe. Do not test high voltage by "drawing an arc". 3. Do not spray chemicals on or near this receiver or any of its assemblies. 4. Unless specified otherwise in this service manual, clean electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable non-abrasive applicator; 10 % (by volume) Acetone and 90 % (by volume) isopropyl alcohol (90 % - 99 % strength) CAUTION: This is a flammable mixture. Unless specified otherwise in this service manual, lubrication of contacts in not required. 5. Do not defeat any plug/socket B+ voltage interlocks with which receivers covered by this service manual might be equipped. 6. Do not apply AC power to this instrument and/or any of its electrical assemblies unless all solid-state device heat sinks are correctly installed. 7. Always connect the test receiver ground lead to the receiver chassis ground before connecting the test receiver positive lead. Always remove the test receiver ground lead last. 8. Use with this receiver only the test fixtures specified in this service manual. CAUTION: Do not connect the test fixture ground strap to any heat sink in this receiver. Electrostatically Sensitive (ES) Devices Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive (ES) Devices. Examples of typical ES devices are integrated circuits and some field-effect transistors and semiconductor “chip” components. The following techniques should be used to help reduce the incidence of component damage caused by static by static electricity. 1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes 2. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly. 3. Use only a grounded-tip soldering iron to solder or unsolder ES devices. 4. Use only an anti-static type solder removal device. Some solder removal devices not classified as “anti-static” can generate electrical charges sufficient to damage ES devices. 5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES devices. 6. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or comparable conductive material). 7. Immediately before removing the protective material from the leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will be installed. CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions. 8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can generate static electricity sufficient to damage an ES device.) General Soldering Guidelines 1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within the range or 500 °F to 600 °F. 2. Use an appropriate gauge of RMA resin-core solder composed of 60 parts tin/40 parts lead. 3. Keep the soldering iron tip clean and well tinned. 4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle. Do not use freon-propelled spray-on cleaners. 5. Use the following unsoldering technique a. Allow the soldering iron tip to reach normal temperature. (500 °F to 600 °F) b. Heat the component lead until the solder melts. c. Quickly draw the melted solder with an anti-static, suctiontype solder removal device or with solder braid. CAUTION: Work quickly to avoid overheating the circuit board printed foil. 6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature (500 °F to 600 °F) b. First, hold the soldering iron tip and solder the strand against the component lead until the solder melts. c. Quickly move the soldering iron tip to the junction of the component lead and the printed circuit foil, and hold it there only until the solder flows onto and around both the component lead and the foil. CAUTION: Work quickly to avoid overheating the circuit board printed foil. d. Closely inspect the solder area and remove any excess or splashed solder with a small wire-bristle brush. -4- LGE Internal Use Only IC Remove/Replacement Some chassis circuit boards have slotted holes (oblong) through which the IC leads are inserted and then bent flat against the circuit foil. When holes are the slotted type, the following technique should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique as outlined in paragraphs 5 and 6 above. 3. Solder the connections. CAUTION: Maintain original spacing between the replaced component and adjacent components and the circuit board to prevent excessive component temperatures. Circuit Board Foil Repair Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit board causing the foil to separate from or "lift-off" the board. The following guidelines and procedures should be followed whenever this condition is encountered. Removal 1. Desolder and straighten each IC lead in one operation by gently prying up on the lead with the soldering iron tip as the solder melts. 2. Draw away the melted solder with an anti-static suction-type solder removal device (or with solder braid) before removing the IC. Replacement 1. Carefully insert the replacement IC in the circuit board. 2. Carefully bend each IC lead against the circuit foil pad and solder it. 3. Clean the soldered areas with a small wire-bristle brush. (It is not necessary to reapply acrylic coating to the areas). At IC Connections To repair a defective copper pattern at IC connections use the following procedure to install a jumper wire on the copper pattern side of the circuit board. (Use this technique only on IC connections). "Small-Signal" Discrete Transistor Removal/Replacement 1. Remove the defective transistor by clipping its leads as close as possible to the component body. 2. Bend into a "U" shape the end of each of three leads remaining on the circuit board. 3. Bend into a "U" shape the replacement transistor leads. 4. Connect the replacement transistor leads to the corresponding leads extending from the circuit board and crimp the "U" with long nose pliers to insure metal to metal contact then solder each connection. Power Output, Transistor Device Removal/Replacement 1. Heat and remove all solder from around the transistor leads. 2. Remove the heat sink mounting screw (if so equipped). 3. Carefully remove the transistor from the heat sink of the circuit board. 4. Insert new transistor in the circuit board. 5. Solder each transistor lead, and clip off excess lead. 6. Replace heat sink. Diode Removal/Replacement 1. Remove defective diode by clipping its leads as close as possible to diode body. 2. Bend the two remaining leads perpendicular y to the circuit board. 3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board. 4. Securely crimp each connection and solder it. 5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder. 1. Carefully remove the damaged copper pattern with a sharp knife. (Remove only as much copper as absolutely necessary). 2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern. 3. Bend a small "U" in one end of a small gauge jumper wire and carefully crimp it around the IC pin. Solder the IC connection. 4. Route the jumper wire along the path of the out-away copper pattern and let it overlap the previously scraped end of the good copper pattern. Solder the overlapped area and clip off any excess jumper wire. At Other Connections Use the following technique to repair the defective copper pattern at connections other than IC Pins. This technique involves the installation of a jumper wire on the component side of the circuit board. 1. Remove the defective copper pattern with a sharp knife. Remove at least 1/4 inch of copper, to ensure that a hazardous condition will not exist if the jumper wire opens. 2. Trace along the copper pattern from both sides of the pattern break and locate the nearest component that is directly connected to the affected copper pattern. 3. Connect insulated 20-gauge jumper wire from the lead of the nearest component on one side of the pattern break to the lead of the nearest component on the other side. Carefully crimp and solder the connections. CAUTION: Be sure the insulated jumper wire is dressed so the it does not touch components or sharp edges. Fuse and Conventional Resistor Removal/Replacement 1. Clip each fuse or resistor lead at top of the circuit board hollow stake. 2. Securely crimp the leads of replacement component around notch at stake top. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes -5- LGE Internal Use Only SPECIFICATION NOTE : Specifications and others are subject to change without notice for improvement. 1. Application range This specification is applied to the LCD TV used LD23E chassis. 3. Test method 2. Requirement for Test Each part is tested as below without special appointment. 1) Performance: LGE TV test method followed 2) Demanded other specification - Safety : CE, IEC specification - EMC : CE, IEC - Wireless : Wireless HD Specification (Option) 1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C 2) Relative Humidity: 65 % ± 10 % 3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models. 4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. 5) The receiver must be operated for about 20 minutes prior to the adjustment. 4. Model General Specification No. 1 Item Market Specification Remarks DTV & Analog (Total 37 countries) DTV(MPEG2/4,DVB-T/T2/S) Albania/Austria/Belarus/Belgium/Bosnia/Bulgaria/Croatia/ Czech/Estonia/France/Germany/Greece/Hungary/Ireland/ Italy/Kazakhstan/Latvia/Lithuania/Luxembourg/Morocco/ Netherlands/Poland/Portugal/Romania/Russia/Serbia/Slovenia/Spain/Slovakia/Switzerland/Turkey/UK/Ukraine/Denmark/Finland/Norway/Sweden EU(PAL Market-36Countries) Supported satellite : 29 satellites ABS1 75.0E/ AMOS 4.0W/ ASIASATS 105.5E/ ASTRA1LHMKR 19.2E/ ASTRA2ABD 28.2E/ ASTRA3AB 23.5E/ ASTRA4A 4.8E/ ATLANTICBIRD2 8.0W/ ATLANTICBIRD3 5.0W/ BADR 26.0E/ EUROBIRD3 33.0E/ EUROBIRD9A 9.0E/ EUTELSATW2A 10.E/ EUTELSATW3A 7.0E/ EUTELSATW4W7 36.0E/ EUTELSESAT 16.0E/ EXPRESSAM1 40.0E/ EXPRESAM3 140.0E/ EXPRESSAM33 96.5E/ HELLASAT2 39.0E/ HISPASAT1CDE 30.0W/ HOTBIRD 13.0E/ INTELSAT10&7 68.5E/ INTELSAT15 85.2E/ INTELSAT904 60.0E/ NILESAT 7.0W/ THOR 0.8W/ TURKSAT 42.0E/ YAMAL201 90.0E 2 Broadcasting system 1) PAL-BG 2) PAL-DK 3) PAL-I/I’ 4) SECAM L/L’, DK, BG, I 5) DVB-T 6) DVB-C 7) DVB-T2 8) DVB-S 9) DVB-S2 Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes DVB-S: Satellite -6- LGE Internal Use Only No. 3 Item Receiving system Specification Remarks Analog : Upper Heterodyne Digital : COFDM, QAM ► DVB-T - Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32 - Modulation : Code Rate QPSK : 1/2, 2/3, 3/4, 5/6, 7/8 16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 ► DVB-T2 - Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256, - Modulation : Code Rate QPSK : 1/2, 2/5, 2/3, 3/4, 5/6 16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6 ► DVB-C - Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s - Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM ► DVB-S/S2 - symbolrate DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s DVB-S (QPSK) : 2 ~ 45Msymbol/s - viterbi DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8 DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10 4 5 Input Voltage Screen Size AC 100 ~ 240V 50/60Hz 46.96 inches 6 7 8 Aspect Ratio Tuning System Operating Environment 16:9 9 Storage Environment 1046.68(H) x 594.02(V) x 1.5(D)mm (Typ.) FHD+240Hz 1) Temp : 0 ~ 40 deg 2) Humidity : ~ 80 % 1) Temp : -20 ~ 60 deg 2) Humidity : ~ 85 % Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes -7- LGE Internal Use Only 5. Component Video Input (Y, Cb/Pb, Cr/Pr) No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock Porposed 1 720*480 15.73 60 13.5135 SDTV ,DVD 480I 2 720*480 15.73 59.94 13.5 SDTV ,DVD 480I 3 720*480 31.50 60 27.027 SDTV 480P 4 720*480 31.47 59.94 27.0 SDTV 480P 5 1280*720 45.00 60.00 74.25 HDTV 720P 6 1280*720 44.96 59.94 74.176 HDTV 720P 7 1920*1080 33.75 60.00 74.25 HDTV 1080I 8 1920*1080 33.72 59.94 74.176 HDTV 1080I 9 1920*1080 67.500 60 148.50 HDTV 1080P 10 1920*1080 67.432 59.94 148.352 HDTV 1080P 11 1920*1080 27.000 24.000 74.25 HDTV 1080P 12 1920*1080 26.97 23.976 74.176 HDTV 1080P 13 1920*1080 33.75 30.000 74.25 HDTV 1080P 14 1920*1080 33.71 29.97 74.176 HDTV 1080P 6. RGB input (PC) No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed PC DDC 1 640*350 31.468 70.09 25.17 EGA Х 2 720*400 31.469 70.08 28.32 DOS O 3 640*480 31.469 59.94 25.17 VESA(VGA) O 4 800*600 37.879 60.31 40.00 VESA(SVGA) O 5 1024*768 48.363 60.00 65.00 VESA(XGA) O 6 1360*768 47.712 60.015 85.50 VESA (WXGA) Х 7 1920*1080 67.5 60.00 148.5 WUXGA O Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes -8- LGE Internal Use Only 7. HDMI Input No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC Proposed HDMI-PC DDC 1 720*400 31.468 70.08 28.321 Х 2 640*480 31.469 59.94 25.17 VESA O 3 800*600 37.879 60.31 40.00 VESA O 4 1024*768 48.363 60.00 65.00 VESA(XGA) O 5 1360*768 47.72 59.8 84.75 WXGA O 6 1280*1024 63.595 60.0 108.875 SXGA O 7 1920*1080 67.5 60.00 148.5 WUXGA O HDMI-DTV 1 640*480 31.469 / 31.5 59.94/ 60 25.125 2 720*480 31.469 / 31.5 59.94 / 60 3 720*576 31.25 50 4 720*576 15.625 50 5 1280*720 37.500 6 1280*720 44.96 / 45 7 1920*1080 33.72 / 33.75 59.94 / 60 8 1920*1080 28.125 50.00 26.97 / 27 23.97 / 24 9 1920*1080 10 1920*1080 1 SDTV 480P 27.00/27.03 2,3 SDTV 480P 27 17,18 SDTV 576P 27 21 SDTV 576I 50 74.25 19 HDTV 720P 59.94 / 60 74.17/74.25 4 HDTV 720P 74.17/74.25 5 HDTV 1080I 74.25 20 HDTV 1080I 74.17/74.25 32 HDTV 1080P 33 HDTV 1080P 25 11 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 34 HDTV 1080P 12 1920*1080 56.250 50 148.5 31 HDTV 1080P 13 1920*1080 67.43 / 67.5 59.94 / 60 148.35/148.50 16 HDTV 1080P 8. 3D Mode 8.1. RF Input No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode 1 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom 2 1920*1080 28.125 50 74.25 HDTV 1080I Side by Side, Top & Bottom 8.2. HDMI Input 8.2.1. HDMI 1.3 No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode 1 1280*720 45.00 60.00 74.25 HDTV 720P Side by Side, Top & Bottom 2 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom 3 1920*1080 33.75 60.00 74.25 HDTV 1080I Side by Side, Top & Bottom 4 1920*1080 28.125 50.00 74.25 HDTV 1080I Side by Side, Top & Bottom 5 1920*1080 27.00 24.00 74.25 HDTV 1080P Side by Side, Top & Bottom 6 1920*1080 33.75 30.00 74.25 HDTV 1080P Side by Side, Top & Bottom 7 1920*1080 67.50 60.00 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard, Single Frame Sequential 8 1920*1080 56.250 50 148.5 HDTV 1080P Side by Side, Top & Bottom, Checkerboard, Single Frame Sequential Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes -9- LGE Internal Use Only 8.2.2. HDMI 1.4b No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 1 640*480 31.469 / 31.5 59.94/ 60 25.125 1 2 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 3 720*576 31.25 50 27 17,18 4 720*576 15.625 50 27 21 5 1280*720 37.500 50 74.25 19 6 1280*720 44.96 / 45 59.94 / 60 74.17/74.25 4 7 1920*1080 33.72 / 33.75 59.94 / 60 74.17/74.25 5 8 1920*1080 28.125 50.00 74.25 20 9 1920*1080 26.97 / 27 23.97 / 24 74.17/74.25 32 10 1920*1080 11 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 34 12 1920*1080 56.250 50 148.5 31 13 1920*1080 67.43 / 67.5 59.94 / 60 148.35/148.50 16 25 Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes 2,3 33 - 10 - 3D input proposed mode Frame packing Line alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Line alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Line alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Field alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Line alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Line alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Field alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Field alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Line alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Line alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Frame packing Line alternative Side-by-side(Full) Top-and-Bottom Side-by-side(half) Top-and-Bottom Side-by-side(half) Top-and-Bottom Side-by-side(half) Proposed Secondary(SDTV 480P) (SDTV 480P) (SDTV 480P) Secondary(SDTV 480P) Secondary(SDTV 480P Secondary(SDTV 480P) (SDTV 480P) (SDTV 480P) Secondary(SDTV 480P) Secondary(SDTV 480P) Secondary(SDTV 576P) (SDTV 576P) (SDTV 576P) Secondary(SDTV 576P) Secondary(SDTV 576P) Secondary(SDTV 576I) (SDTV 576I (SDTV 576I Secondary(SDTV 576I) Secondary(SDTV 576I) Primary(HDTV 720P) (HDTV 720P) (HDTV 720P) Primary(HDTV 720P) Primary(HDTV 720P) Primary(HDTV 720P) (HDTV 720P) (HDTV 720P) Primary(HDTV 720P) Primary(HDTV 720P) Primary(HDTV 1080I) (HDTV 1080I) (HDTV 1080I) Secondary(HDTV 1080I) Primary(HDTV 1080I) Primary(HDTV 1080I) (HDTV 1080I) (HDTV 1080I) Secondary(HDTV 1080I) Primary(HDTV 1080I) Primary(HDTV 1080P) (HDTV 1080P) (HDTV 1080P) Primary(HDTV 1080P) Primary(HDTV 1080P) Secondary(HDTV 1080P) (HDTV 1080P) (HDTV 1080P) Secondary(HDTV 1080P) Secondary(HDTV 1080P) (HDTV 1080P) (HDTV 1080P) (HDTV 1080P) (HDTV 1080P) Secondary(HDTV 1080P) Primary(HDTV 1080P) Secondary(HDTV 1080P) Primary(HDTV 1080P) Secondary(HDTV 1080P) LGE Internal Use Only 8.3. RGB-PC Input(3D) No. 1 Resolution 1920*1080 H-freq(kHz) 67.5 V-freq.(Hz) Pixel clock(MHz) 60 148.5 3D input proposed mode Side by Side, Top & Bottom Proposed HDTV 1080P 8.4. Component Input(3D) No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock 3D input proposed mode Proposed 1 1280*720 45.00 60.00 74.25 Side by Side, Top & Bottom HDTV 720P 2 1280*720 44.96 59.94 74.176 Side by Side, Top & Bottom HDTV 720P 3 1920*1080 33.75 60.00 74.25 Side by Side, Top & Bottom HDTV 1080I 4 1920*1080 33.72 59.94 74.176 Side by Side, Top & Bottom HDTV 1080I 5 1920*1080 67.500 60 148.50 Side by Side, Top & Bottom HDTV 1080P 6 1920*1080 67.432 59.94 148.352 Side by Side, Top & Bottom HDTV 1080P 7 1920*1080 27.000 24.000 74.25 Side by Side, Top & Bottom HDTV 1080P 8 1920*1080 26.97 23.976 74.176 Side by Side, Top & Bottom HDTV 1080P 9 1920*1080 33.75 30.000 74.25 Side by Side, Top & Bottom HDTV 1080P 10 1920*1080 33.71 29.97 74.176 Side by Side, Top & Bottom HDTV 1080P 8.5. USB Input(3D) No. 1 Resolution 1920*1080 H-freq(kHz) 33.75 V-freq.(Hz) 30.000 Pixel clock(MHz) 3D input proposed mode Side by Side, Top & Bottom, Checkerboard 74.25 Proposed HDTV 1080P 8.6. DLNA Input (3D) No. 1 Resolution 1920*1080 H-freq(kHz) 33.75 V-freq.(Hz) 30.000 Pixel clock(MHz) 3D input proposed mode Side by Side, Top & Bottom, Checkerboard 74.25 Proposed HDTV 1080P ■ Remark: 3D Input mode No. 1 Side by Side L R Top & Bottom Checker board LLLLL R L Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes Single Frame Sequential R Frame Packing Line Interleaving Column Interleaving L - 11 - LGE Internal Use Only ADJUSTMENT INSTRUCTION 1. Application Range 3.1.3. Adjustment (1) Adjustment method - U sing RS-232, adjust items in the other shown in "3.1.3.3)" This specification sheet is applied to all of the LED LCD TV with LD23E chassis. (2) Adj. protocol 2. Designation Protocol (1) Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation transformer will help protect test instrument. (2) Adjustment must be done in the correct order. (3) The adjustment must be performed in the circumstance of 25 °C ± 5 °C of temperature and 65 % ± 10 % of relative humidity if there is no specific designation. (4) The input voltage of the receiver must keep AC 100-240 V~, 50/60 Hz. (5) The receiver must be operated for about 5 minutes prior to the adjustment when module is in the circumstance of over 15. Enter adj. mode Source change Begin adj. Read adj. data xb 00 04 b 00 OK04x (Adjust 480i, 1080p Comp1 ) xb 00 06 b 00 OK06x (Adjust 1920*1080 RGB) ad 00 10 OKx (Case of Success) NGx (Case of Fail) (main) ad 00 20 (main) 000000000000000000000000007c007b006dx (sub ) (Sub) 000000070000000000000000007c00830077x ad 00 21 In case of keeping module is in the circumstance of below -20 °C, it should be placed in the circumstance of above 15 °C for 3 hours. Set ACK a 00 OK00x Return adj. result In case of keeping module is in the circumstance of 0 °C, it should be placed in the circumstance of above 15 °C for 2 hours. Confirm adj. ad 00 99 NG 03 00x (Fail) NG 03 01x (Fail) NG 03 02x (Fail) OK 03 03x (Success) End adj. aa 00 90 a 00 OK90x Ref.) ADC Adj. RS232C Protocol_Ver1.0 (3) Adj. order - aa 00 00 [Enter ADC adj. mode] - xb 00 04 [Change input source to Component1 (480i& 1080p)] - ad 00 10 [Adjust 480i&1080p Comp1] - xb 00 06 [Change input source to RGB(1024*768)] - ad 00 10 [Adjust 1920*1080 RGB] - ad 00 90 End adj. [Caution] When still image is displayed for a period of 20 minutes or longer (Especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area. 3. Automatic Adjustment Command aa 00 00 3.2. M AC address D/L, CI+ key D/L, Widevine key D/L 3.1. ADC Adjustment 3.1.1. Overview ADC adjustment is needed to find the optimum black level and gain in Analog-to-Digital device and to compensate RGB deviation. Connect: PCBA Jig → RS-232C Port== PC → RS-232C Port Communication Prot connection 3.1.2. Equipment & Condition (1) USB to RS-232C Jig (2) M SPG-925 Series Pattern Generator(MSPG-925FA, pattern - 65) - Resolution :480i Comp1 1080P Comp1 1920*1080 RGB - Pattern : Horizontal 100% Color Bar Pattern - Pattern level : 0.7 ± 0.1 Vp-p - Image Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes - 12 - ▪ Com 1,2,3,4 and 115200(Baudrate) Mode check: Online Only ▪ Check the test process: DETECT → MAC → CI → Widevine → ESN ▪ Play: START ▪ Result: Ready, Test, OK or NG ▪ Printer Out (MAC Address Label) LGE Internal Use Only 3.3. LAN Inspection 3.4. LAN PORT INSPECTION(PING TEST) Connect SET → LAN port == PC → LAN Port 3.3.1. Equipment & Condition SET ▪ Each other connection to LAN Port of IP Hub and Jig PC 3.4.1. Equipment setting (1) Play the LAN Port Test PROGRAM. (2) Input IP set up for an inspection to Test Program. *IP Number : 12.12.2.2 3.4.2. LAN PORT inspection(PING TEST) (1) Play the LAN Port Test Program. (2) Connect each other LAN Port Jack. (3) Play Test (F9) button and confirm OK Message. (4) Remove LAN cable. 3.3.2. LAN inspection solution ▪ LAN Port connection with PCB ▪ Network setting at MENU Mode of TV ▪ Setting automatic IP ▪ Setting state confirmation → If automatic setting is finished, you confirm IP and MAC Address. 3.3.3. WIDEVINE key Inspection - Confirm key input data at the "IN START" MENU Mode. 3.5. Model name & Serial number Download 3.5.1. Model name & Serial number D/L Press "Power on" key of service remote control. (Baud rate : 115200 bps) ▪ Connect RS232 Signal Cable to RS-232 Jack. ▪ Write Serial number by use RS-232. ▪ Must check the serial number at Instart menu. ▪ 3.5.2. Method & notice (1) Serial number D/L is using of scan equipment. (2) Setting of scan equipment operated by Manufacturing Technology Group. (3) Serial number D/L must be conformed when it is produced in production line, because serial number D/L is mandatory by D-book 4.0 Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes - 13 - LGE Internal Use Only * Manual Download (Model Name and Serial Number) If the TV set is downloaded by OTA or service man, sometimes model name or serial number is initialized.(Not always) It is impossible to download by bar code scan, so It need Manual download. 1) Press the "Instart" key of Adjustment remote control. 2) Go to the menu "6.Model Number D/L" like below photo. 3) Input the Factory model name(ex 42LD450-TA) or Serial number like photo. 3.6.2. Check the method of CI+ key value(RS232) 1) Into the main ass’y mode(RS232: aa 00 00) CMD 1 CMD 2 A A Data 0 0 0 2) Check the mothed of CI+ key by command (RS232: ci 00 20) CMD 1 CMD 2 C I Data 0 2 0 3) Result value i 01 OK 1d1852d21c1ed5dcx CI+ Key Value 3.7. WIFI MAC ADDRESS CHECK (1) Using RS232 Command 4) Check the model name Instart menu. → Factory name displayed. (ex 47LM960V-ZB) 5) C heck the Diagnostics.(DTV country only) → Buyer model displayed. (ex 47LM960V-ZB) Transmission H-freq(kHz) V-freq.(Hz) [A][I][][Set ID][][20][Cr] [O][K][X] or [NG] (2) Check the menu on in-start 3.6. CI+ Key checking method - Check the Section 3.2 Check whether the key was downloaded or not at ‘In Start’ menu. (Refer to below). => Check the Download to CI+ Key value in LGset. 3.6.1. Check the method of CI+ Key value (1) Check the method on Instart menu (2) Check the method of RS232C Command 1) Into the main ass’y mode(RS232: aa 00 00) CMD 1 CMD 2 Data 0 A A 0 0 2) Check the key download for transmitted command (RS232: ci 00 10) CMD 1 CMD 2 C I Data 0 1 0 3) result value - normally status for download : OKx - abnormally status for download : NGx Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes - 14 - LGE Internal Use Only 4. Manual Adjustment * ADC adjustment is not needed because of OTP(Auto ADC adjustment) ▪ Reference - HDMI1 ~ HDMI4 / RGB - In the data of EDID, bellows may be different by S/W or Input mode. 4.1 EDID(The Extended Display Identification Data)/DDC(Display Data Channel) download ⓐ Product ID ⓑ Serial No: Controlled on production line. ⓒ Month, Year: Controlled on production line: ex) Monthly : ‘01’ → ‘01’ Year : ‘2012’ → ‘16’ ⓓ Model Name(Hex): LGTV ⓔ Checksum(LG TV): Changeable by total EDID data. ⓕ Vendor Specific(HDMI) 4.1.1. Overview It is a VESA regulation. A PC or a MNT will display an optimal resolution through information sharing without any necessity of user input. It is a realization of "Plug and Play". 4.1.2. Equipment - Since embedded EDID data is used, EDID download JIG, HDMI cable and D-sub cable are not need. - Adjustment remote control # HDMI 1(C/S : 9D BA) EDID Block 0, Bytes 0-127 [00H-7FH] 00 4.1.3. Download method (1) Press "ADJ" key on the Adjustment remote control then select "10.EDID D/L", By pressing "Enter" key, enter EDID D/L menu. (2) S elect "Start" button by pressing "Enter" key, HDMI1/ HDMI2/ HDMI3/ HDMI4/ RGB are writing and display OK or NG. For Analog For HDMI EDID D-sub to D-sub DVI-D to HDMI or HDMI to HDMI FF FF FF FF FF FF 00 1E 6D 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 40 81 C0 81 00 81 80 95 00 ⓐⓓ 54 A1 08 00 71 0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C 0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39 0x06 3F 1F 52 10 00 0A 20 20 20 20 20 20 01 ⓔ1 12 20 21 1C 38 2D 40 0x00 02 03 37 F1 4E 90 1F 04 13 05 0x01 22 15 01 26 15 07 50 09 57 07 E3 05 03 01 02 3A 80 18 71 0x02 14 03 ⓓ 02 ⓕ ⓕ 0x03 ⓕ 45 00 A0 5A 00 00 00 1E 01 1D 80 18 71 1C 16 0x05 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 72 51 0x06 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2 ▪ RGB 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x00 00 0x01 FF ⓒ FF FF FF FF FF 00 1E 6D 01 03 68 10 09 78 0A EE 91 A3 54 4C 99 26 ⓐ 7 8 9 A B C D E F 00 1E 6D 01 00 01 01 01 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39 60 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43 0 1 2 3 4 5 6 7 8 9 A B C D E F 02 03 37 F1 4E 10 9F 04 13 05 14 03 02 12 20 21 10 22 15 01 26 15 07 50 09 57 07 78 03 0C 00 10 00 20 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 30 10 28 10 E3 05 03 01 02 3A 80 18 71 38 2D 40 58 40 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18 71 1C 16 50 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 72 51 60 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 # HDMI 2(C/S : 9D AA) EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39 60 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43 EDID Block 1, Bytes 128-255 [80H-FFH] 0x04 2C 00 6 FF 50 00 50 ⓓ 5 FF 01 ⓑ 0x02 0F 0x07 4 FF 0F 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F ⓒ 3 FF 10 ▪ HDMI(FHD 3D, HDMI 1.4a, 3D) 00 2 FF EDID Block 1, Bytes 128-255 [80H-FFH] 4.1.4. EDID DATA 0x01 1 FF 20 00 0x00 0 00 ⓑ 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 02 03 37 F1 4E 10 9F 04 13 05 14 03 02 12 20 21 10 22 15 01 26 15 07 50 09 57 07 78 03 0C 00 20 00 20 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 30 10 28 10 E3 05 03 01 02 3A 80 18 71 38 2D 40 58 40 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18 71 1C 16 50 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 72 51 0x02 0F 50 54 A1 08 00 71 40 81 C0 81 00 81 80 95 00 0x03 90 40 A9 C0 B3 00 02 3A 80 18 71 38 2D 40 58 2C 60 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 ⓔ3 0x07 ⓓ Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes ⓓ - 15 - LGE Internal Use Only 4.2. White Balance Adjustment # HDMI 3(C/S : 9D 9A) EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39 60 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43 00 4.2.1. Overview ▪ W/B adj. Objective & How-it-works (1) Objective: To reduce each Panel's W/B deviation (2) How-it-works : When R/G/B gain in the OSD is at 192, it means the panel is at its Full Dynamic Range. In order to prevent saturation of Full Dynamic range and data, one of R/G/B is fixed at 192, and the other two is lowered to find the desired value. (3) Adjustment condition : normal temperature 1) Surrounding Temperature : 25 °C ± 5 °C 2) Warm-up time: About 5 Min 3) Surrounding Humidity : 20 % ~ 80 % EDID Block 1, Bytes 128-255 [80H-FFH 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 02 03 37 F1 4E 10 9F 04 13 05 14 03 02 12 20 21 10 22 15 01 26 15 07 50 09 57 07 78 03 0C 00 30 00 20 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 30 10 28 10 E3 05 03 01 02 3A 80 18 71 38 2D 40 58 40 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18 71 1C 16 50 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 72 51 60 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F1 # HDMI 4(C/S : 9D 8A) EDID Block 0, Bytes 0-127 [00H-7FH] 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 39 60 3F 1F 52 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 43 00 EDID Block 1, Bytes 128-255 [80H-FFH] 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 02 03 37 F1 4E 10 9F 04 13 05 14 03 02 12 20 21 10 22 15 01 26 15 07 50 09 57 07 78 03 0C 00 40 00 20 B8 2D 20 C0 0E 01 4F 3F FC 08 10 18 10 06 10 16 30 10 28 10 E3 05 03 01 02 3A 80 18 71 38 2D 40 58 40 2C 45 00 A0 5A 00 00 00 1E 01 1D 80 18 71 1C 16 51 50 20 58 2C 25 00 A0 5A 00 00 00 9E 01 1D 00 72 60 D0 1E 20 6E 28 55 00 A0 5A 00 00 00 1E 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E1 4.2.2. Equipment (1) Color Analyzer: CA-210 (LED Module : CH 14) (2) Adjustment Computer(During auto adj., RS-232C protocol is needed) (3) Adjustment Remote control (4) Video Signal Generator MSPG-925F 720p/216-Gray (Model: 217, Pattern: 78) -> Only when internal pattern is not available ▪ Color Analyzer Matrix should be calibrated using CS-1000. 4.2.3. Equipment connection MAP Co lo r Analyzer RS -232C Probe Co m p ut er RS -232C RS -232C Pat t ern Generat o r Signal Source * If TV internal pattern is used, not needed 4.2.4. Adj. Command (Protocol) <Command Format> START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP - LEN: Number of Data Byte to be sent - CMD: Command - VAL: FOS Data value - CS: Checksum of sent data - A: Acknowledge Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX] # RGB(C/S : 97) ▪ RS-232C Command used during auto-adjustment. 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 10 01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 wb 00 00 Begin White Balance adjustment 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C wb 00 10 Gain adjustment(internal white pattern) 40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 wb 00 1f Gain adjustment completed 50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A wb 00 20 Offset adjustment(internal white pattern) 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 5C wb 00 2f Offset adjustment completed wb 00 ff End White Balance adjustment (internal pattern disappears ) Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes RS-232C COMMAND [CMD ID DATA] - 16 - Explantion LGE Internal Use Only Ex) wb 00 00 -> Begin white balance auto-adj. wb 00 10 -> Gain adj. ja 00 ff -> Adj. data jb 00 c0 ... ... wb 00 1f → Gain adj. completed *(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. wb 00 ff → End white balance auto-adj. ▪ Adjustment condition and cautionary items 1) Lighting condition in surrounding area Surrounding lighting should be lower 10 lux. Try to isolate adj. area into dark surrounding. 2) Probe location : Color Analyzer(CA-210) probe should be within 10 cm and perpendicular of the module surface (80° ~ 100°) 3) Aging time - After Aging Start, Keep the Power ON status during 5 Minutes. - In case of LCD, Back-light on should be checked using no signal or Full-white pattern. ▪ Adj. Map Adj. item Cool Command (lower caseASCII) Data Range (Hex.) CMD1 MIN MAX R Gain j g CMD2 00 C0 G Gain j h 00 C0 B Gain j i 00 C0 Default (Decimal) 4.2.6. Reference(White balance adjusmtment coordinate and color temperature) ▪ Luminance : 216 Gray ▪ Standard color coordinate and temperature using CS-1000 (over 26 inch) R Cut G Cut Medium R Gain j a 00 C0 G Gain j b 00 C0 B Gain j c 00 C0 R Gain j d 00 C0 G Gain j e 00 C0 B Gain j f 00 C0 Temp ∆uv 0.269 0.273 13000 K 0.0000 0.285 0.293 9300 K 0.0000 Warm 0.313 0.329 6500 K 0.0000 ▪ Standard color coordinate and temperature using CA-210(CH 9) Coordinate Mode R Cut G Cut 4.2.5. Adj. method (1) Auto adj. method 1) Set TV in adj. mode using POWER ON key. 2) Zero calibrate probe then place it on the center of the Display. 3) Connect Cable.(RS-232C to USB) 4) Select mode in adj. Program and begin adj. 5) When adj. is complete (OK Sign), check adj. status pre mode. (Warm, Medium, Cool) 6) Remove probe and RS-232C cable to complete adj. ▪ W/B Adj. must begin as start command “wb 00 00” , and finish as end command “wb 00 ff”, and Adj. offset if need. x y Temp ∆uv Cool 0.269 ± 0.002 0.273 ± 0.002 13000K 0.0000 Medium 0.285 ± 0.002 0.293 ± 0.002 9300K 0.0000 Warm 0.313 ± 0.002 0.329 ± 0.002 6500K 0.0000 4.2.7. ALELF & EDGE LED White balance table (2) Manual adjustment. method 1) Set TV in Adj. mode using POWER ON. 2) Zero Calibrate the probe of Color Analyzer, then place it on the center of LCD module within 10 cm of the surface. 3) Press ADJ key → EZ adjust using adj. R/C → 7. WhiteBalance then press the cursor to the right(key ►). (When right key(►) is pressed 216 Gray internal pattern will be displayed) 4) One of R Gain / G Gain / B Gain should be fixed at 192, and the rest will be lowered to meet the desired value. 5) Adjustment is performed in COOL, MEDIUM, WARM 3 modes of color temperature. ▪ If internal pattern is not available, use RF input. In EZ Adj. menu 7.White Balance, you can select one of 2 Test-pattern: ON, OFF. Default is inner(ON). By selecting OFF, you can adjust using RF signal in 216 Gray pattern. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes y Cool R Cut B Cut x Medium G Cut Warm Coordinate Mode B Cut - 17 - - EDGE LED module change color coordinate because of aging time. - Apply under the color coordinate table, for compensated aging time. - ALEF(LM860*) GP4 Aging time (Min) 1 2 3 4 5 6 7 8 9 0-2 3-5 6-9 10-19 20-35 36-49 50-79 80-149 Over 150 Cool X y 269 273 293 305 292 303 291 302 288 298 286 295 285 293 283 291 282 289 281 287 Medium x y 285 293 309 323 308 321 307 320 304 316 302 313 301 311 299 309 298 308 298 306 Warm x y 313 329 330 348 330 347 329 346 326 342 324 339 322 337 321 335 320 334 319 332 LGE Internal Use Only 4.3. EYE-Q function check 4.4. Local Dimming Function Check (1) Turn on TV. (2) Press EYE key of Adjustment remote control. Step 1) Turn on TV. Step 2) At the Local Dimming mode, module Edge Backlight moving right to left Back light of IOP module moving. Step 3) Confirm the Local Dimming mode. Step 4) Press "exit" key. (3) Cover the Eye Q II sensor on the front of the using your hand and wait for 6 seconds. (4) Confirm that R/G/B value is lower than 10 of the "Raw Data (Sensor data, Back light)". If after 6 seconds, R/G/B value is not lower than 10, replace Eye Q II sensor. G 4.5. Magic Motion Remote control test (1) Equipment : RF Remote control for test, IR-KEY-Code Remote control for test (2) You must confirm the battery power of RF-Remote control before test(recommend that change the battery per every lot) (3) Sequence (test) 1) if you select the "Start(Mute)" key on the Adjustment remote control, you can pairing with the TV SET. 2) You can check the cursor on the TV Screen, when select the "OK" key on the Adjustment remote control. 3) You must remove the pairing with the TV Set by select "OK" key + "Mute" key on the Adjustment remote control for 5 seconds. (5) Remove your hand from the Eye Q II sensor and wait for 6 seconds. 4.6. 3D function test (6) Confirm that "ok" pop up. If change is not seen, replace Eye Q II sensor. (Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4]) * HDMI mode NO. 872 , pattern No.83 (1) Please input 3D test pattern like below. (2) When 3D OSD appear automatically, then select OK key. (3) Don't wear a 3D Glasses, check the picture like below. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes - 18 - LGE Internal Use Only 4.7. Wi-Fi Test 4.9. Inspection of light scattering Step 1) Turn on TV Step 2) Select Network Connection option in Network Menu. ▪ Test Method (1) Push “Power only” key. (2) Push “HDMI” hot key. (3) Inspect whether light scattering is occurred in internal black pattern or not. (4) Push “Power only” key. Step 3) Select Start Connection button in Network Connection. 4.10. Option selection per country 4.10.1. Overview Step 4) If the system finds any AP like blow PIC, it is working well. - Option selection is only done for models in Non-EU 4.10.2. Method (1) Press ADJ key on the Adj. R/C, then select Country Group Meun (2) Depending on destination, select Country Group Code 04 or Country Group EU then on the lower Country option, select US, CA, MX. Selection is done using +, - or ►◄ key. 4.11. MHL Test 4.8. LNB voltage and 22KHz tone check (only for DVB-S/S2 model) ▪ Test method (1) Set TV in Adj. mode using POWER ON. (2) Connect cable between satellite ANT and test JIG. (3) Press Yellow key(ETC+SWAP) in Adj Remote control to make LNB on. (4) Check LED light ‘ON’ at 18 V menu. (5) Check LED light ‘ON’ at 22 KHz tone menu. (6) Press Blue key(ETC+PIP INPUT) in Adj Remote control to make LNB off. (7) Check LED light ‘OFF’ at 18 V menu. (8) Check LED light ‘OFF’ at 22 KHz tone menu. ▪ Test result (1) After press LNB On key, ‘18 V LED’ and ‘22 KHz tone LED’ should be ON. (2) After press LNB OFF key, ‘18 V LED’ and ‘22 KHz tone LED’ should be OFF. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes - 19 - (1) Turn on TV (2) Select HDMI4 mode using input Menu. (3) Set MHL Zig(M1S0D3617) using MHL input, output and power cord. (4) Connect HDMI cable between MHL Zig and HDMI4 port. (5) Check LED light of Zig and Module of Set. Result) If, The LED light is green and The Module shows normal stream → OK, Else → NG LGE Internal Use Only 5. Tool Option selection ▪ Method : Press "ADJ" key on the Adjustment remote control, then select Tool option. 9. USB S/W Download(Service only) (1) Put the USB Stick to the USB socket. (2) Automatically detecting update file in USB Stick. - If your downloaded program version in USB Stick is Low, it didn't work. But your downloaded version is High, USB data is automatically detecting.(Download Version High & Power only mode, Set is automatically Download) (3) Show the message "Copying files from memory". 6. Ship-out mode check(In-stop) ▪ After final inspection, press "IN-STOP" key of the Adjustment remote control and check that the unit goes to Stand-by mode. 7. GND and Internal Pressure check 7.1. Method (1) GND & Internal Pressure auto-check preparation - Check that Power cord is fully inserted to the SET. (If loose, re-insert) (2) Perform GND & Internal Pressure auto-check - Unit fully inserted Power cord, Antenna cable and A/V arrive to the auto-check process. - Connect D-terminal to AV JACK TESTER - Auto CONTROLLER(GWS103-4) ON - Perform GND TEST - If NG, Buzzer will sound to inform the operator. - If OK, changeover to I/P check automatically. (Remove CORD, A/V form AV JACK BOX.) - Perform I/P test - If NG, Buzzer will sound to inform the operator. - If OK, Good lamp will lit up and the stopper will allow the pallet to move on to next process. (4) Updating is starting. (5) Updating Completed, The TV will restart automatically. (6) If your TV is turned on, check your updated version and Tool option. (explain the Tool option, next stage) * If downloading version is more high than your TV have, TV can lost all channel data. In this case, you have to channel recover. if all channel data is cleared, you didn’t have a DTV/ ATV test on production line. 7.2. Checkpoint ▪ TEST voltage - GND: 1.5 KV / min at 100 mA - SIGNAL: 3 KV / min at 100 mA ▪ TEST time: 1 second ▪ TEST POINT - G ND TEST = POWER CORD GND & SIGNAL CABLE METAL GND - Internal Pressure TEST = POWER CORD GND & LIVE & NEUTRAL ▪ LEAKAGE CURRENT: At 0.5 mArms * After downloading, have to adjust Tool Option again. (1) Push "IN-START" key in service remote control. (2) Select "Tool Option 1" and push "OK" key. (3) Punch in the number. (Each model has their number) 8. Audio No. Item Min Typ Max Unit Remark 9.0 10.0 12.0 W Measurement condition 1. Audio practical max Output, L/R (Distortion=10% max Output) 8.5 8.9 9.8 Vrms 2. Speaker (8Ω Impedance) 10.0 15.0 W Auto Volume :Off Audio EQ : Off Clear Voice : Off Virtual Surround:Off Measurement condition: (1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation (2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms (3) RGB PC: 1 KHz sine wave signal 0.7 Vrms Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes - 20 - LGE Internal Use Only EXPLODED VIEW IMPORTANT SAFETY NOTICE 900 Dual Play AG2 * Set + Stand * Stand Base + Body A21 A2 300 301 501 580 500 122 A22 200 A10 120 AG1 123 800 LV1 530 541 540 521 810 310 510 560 410 910 400 920 570 710 700 Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. Copyright © LG Electronics. Inc. All rights reserved. Only for training and service purposes - 21 - LGE Internal Use Only System Configuration +3.3V_NORMAL NVRAM Clock for LG1152 3 8 for DiiVA(China) VCC Write Protection WP - Low : Normal Operation - High : Write Protection 2 I2C_SDA2 HP_DET I2C_SCL2 EPHY_INT 7 VSS 3 A0’h SMARTCARD_DATA SEL_USB1 SMARTCARD_RST 4 SMARTCARD_PWR_SEL SCL 6 I2C_SCL5 SEL_USB1 SEL_USB2 SEL_USB3 1M A2 GND_2 X-TAL_2 1 SEL_USB2 R112 1 A1 4 2 A0 XIN_MAIN 24MHz X101 GND_1 X-TAL_1 C100 8pF 50V C101 8pF 50V C111 0.1uF IC102 R1EX24256BSAS0A MAIN Clock(24Mhz) SDA 5 I2C_SDA5 XO_MAIN R143 OPT 22 OPT R142 22 I2C_SCL3 SEL_USB3 SMARTCARD_VCC /RST_PHY SMARTCARD_DET SMARTCARD_CLK MOTOR_CLOSE_SW MOTOR_OPEN_SW SC_DET I2C_SDA3 MOTOR_CW DiiVA_POD_CTL MOTOR_CCW MO_SENS_TO_MAIN_UP MO_SENS_TO_MAIN_DOWN Place to LVDS Wafer EB_DATA[0-7] EB_ADDR[0-14] OPT R102 22 R103 22 R160 22 R162 22 EB_DATA[0] EB_DATA[1] EB_DATA[2] EB_DATA[3] EB_DATA[4] EB_DATA[5] EB_DATA[6] EB_DATA[7] R109 +3.3V_NORMAL 10K EB_ADDR[1] EB_ADDR[2] EB_ADDR[0] EB_ADDR[3] EB_ADDR[4] EB_ADDR[5] EB_ADDR[7] EB_ADDR[8] EB_ADDR[6] EB_ADDR[9] EB_ADDR[10] EB_ADDR[11] EB_ADDR[12] EB_ADDR[13] EB_ADDR[14] EB_BE_N0 EB_BE_N1 EB_OE_N EB_WE_N 3D_DEPTH_RESET Mhz) Mhz) Mhz) Mhz) OPTIC_SERDES_RESET OLED_TCON_RESET FPGA_LVDS_INFO USB_CTL3 is high (792/792 (672/792 (792/672 (792/792 4.7K N.C DDR DDR DDR DDR R113 Pull-UP. Main0,1/2 Main0,1/2 Main0,1/2 Main0,1/2 10K R170 FRC3_RESET DiiVA_POD_CTL 22 FRC_RESET PLL SET[1:0] ==> Internal 00 : CPU clock(1056Mhz), 01 : CPU clock(792Mhz), 10 : CPU clock(1152Mhz), 11 : CPU clock(984Mhz), FPGA_LVDS_INFO OPTIC_FPGA_RESET R151 IRB_SPI_MISO IRB_SPI_MOSI IRB_SPI_CK IRB_SPI_SS IR_B_RESET I2C_SDA1 I2C_BE_SDA1 N28 P26 P27 P28 R26 R27 R28 T26 L22 M22 N22 P22 R22 T22 U22 V22 K23 K24 K25 K26 K27 K28 L23 L24 L28 M26 N27 N26 L25 L27 L26 J23 K22 J22 U28 U26 U27 T28 T27 N23 M23 I2C_BE_SCL1 M24 I2C_SCL1 PLLSET0 M25 PLLSET1 OPT R131 U24 Y22 AA22 AB20 AB21 W22 TDI0 AB9 TDO0 PLLSET1 TMS0 PLLSET0 BOOT_MODE1 BOOT_MODE1 AB15 BOOT_MODE0 AB14 TCK0 EB_DATA0 EB_DATA1 EB_DATA2 EB_DATA3 EB_DATA4 EB_DATA5 EB_DATA6 EB_DATA7 EB_DATA8 EB_DATA9 EB_DATA10 EB_DATA11 EB_DATA12 EB_DATA13 EB_DATA14 EB_DATA15 EB_ADDR0 EB_ADDR1 EB_ADDR2 EB_ADDR3 EB_ADDR4 EB_ADDR5 EB_ADDR6 EB_ADDR7 EB_ADDR8 EB_ADDR9 EB_ADDR10 EB_ADDR11 EB_ADDR12 EB_ADDR13 EB_ADDR14 EB_BE_N0 EB_BE_N1 EB_WAIT EB_WE_N EB_OE_N EMMC_DATA4 AB8 BOOT_MODE0 EMMC_DATA3 TMS0 EMMC_DATA2 TCK0 EMMC_DATA1 TDI0 EMMC_DATA0 TDO0 100K R202 G D R134 OPT NAND_CS1 TMS1 NAND_CS0 TCK1 NAND_ALE TDI1 NAND_CLE TDO1 NAND_REN PLLSET1 NAND_WEN PLLSET0 22 R101 22 GPIO31 BOOT_MODE0 GPIO30 W24 W23 /USB_OCD3 Q100 2N7002K GPIO29 Y23 W25 EXT_INTR3/GPIO48 GPIO28 EXT_INTR2/GPIO63 GPIO27 IC100 LG1152D-B1 EXT_INTR1/GPIO62 EXT_INTR0/GPIO61 Y5 D SOC_TX S W6 BOOT_MODE0 AA6 UART1_RX Q103 2N7002K Y6 UART1_TX AB5 M_REMOTE_RX AA5 M_REMOTE_TX GPIO26 GPIO25 GPIO24 UART0_RX/GPIO49 GPIO23 UART0_TX/GPIO50 GPIO22 UART1_RX GPIO21 UART1_TX GPIO20 UART2_RX GPIO19 UART2_TX GPIO18 +5V_NORMAL AA25 IRB_SPI_CK AB25 IRB_SPI_SS S D AB24 IRB_SPI_MOSI MHL_DET Y25 AV1_CVBS_DET Q105 2N7002K OPT AA23 Y24 DTV_ATV_SELECT AA24 SPI_CS0/GPIO36 GPIO13 SPI_DI1/GPIO35 GPIO12 SPI_DO1/GPIO34 GPIO11 SPI_SCLK1/GPIO33 GPIO10 22 22 22 R105 R106 R108 E26 EMMC_DATA[5] D27 EMMC_DATA[4] D28 EMMC_DATA[3] C27 EMMC_DATA[2] C28 EMMC_DATA[1] D26 EMMC_DATA[0] P24 N25 P23 N24 P25 W5 OPTIC_SERDES_RESET W4 3D_DEPTH_RESET V6 /RST_PHY V5 OLED_TCON_RESET V4 U6 HW_OPT_9 HW_OPT_7 U5 HW_OPT_8 U4 +3.3V_NORMAL SW1 JTP-1127WEM 2 DSUB_DET T6 1 4 T5 T4 SC_DET R6 COMP1_DET R5 3 For ISP Delete PV DEBUG HW_OPT_5 R4 HW_OPT_6 P6 M_RFModule_ISP P5 HW_OPT_10 P4 M_RFModule_RESET N6 FRC_RESET N5 HW_OPT_2 N4 HW_OPT_1 N3 HW_OPT_0 M6 HW_OPT_4 AC23 +5V_NORMAL FLASH_WP /RST_HUB AC24 AE24 HW_OPT_3 AD23 HP_DET AE23 AC22 RF_SWITCH_CTL AD22 HDMI_S/W_RESET Q104 2N7002K /TU_RESET AE22 /S2_RESET BT_ANALOGTEST BT_TXR_RKL BT_USB_DM OPTIC_FPGA_RESET V7 Y4 AA4 AA2 BT_USB_DP AA1 USB_ANALOGTEST USB_TXR_RKL B25 C25 USB_DM2 B26 USB_DP2 USB_DM1 A26 A27 B27 USB_DP1 SD_DATA0/GPIO85 A25 SD_DATA1/GPIO86 SD_DATA3/GPIO72 SD_WP_N/GPIO74 SD_CD_N/GPIO75 SD_CMD/GPIO73 SD_CLK/GPIO76 SC_DATA/GPIO92 SC_RST/GPIO91 SC_VCCEN/GPIO89 SC_DETECT/GPIO93 SC_CLK/GPIO90 CAM_IOIS16_N CAM_REG_N CAM_WAIT_N CAM_VCCEN_N CAM_INPACK_N CAM_RESET CAM_IREQ_N SD_DATA2/GPIO87 C24 Zoran FRC B24 MODEL_OPT_10 A24 Not Support B23 Support C2 Tuner A23 S Tuner MODEL_OPT_9 C23 MODEL_OPT_8 C22 FrontEnd 2 R24 Not Support T23 Support T24 T2 Tuner T25 MODEL_OPT_7 U23 FrontEnd 1 DDR_Default R25 Enable V26 CP BOX V27 MODEL_OPT_6 Y28 CP BOX NON_3D_Depth_IC AA26 Reserved 3D_Depth_IC AA27 DDR AB26 3D DEPTH MODEL_OPT_5 AD2 MODEL_OPT_4 DDR Size HW_OPT_5 AA28 NON_OPTIC CAM_VS2_N UD OPTIC CAM_VS1_N FHD MODEL_OPT_3 3D Depth IC W27 MODEL_OPT_2 OPTIC I/F HW_OPT_4 CAM_CD2_N Pannel Resol HW_OPT_3 CAM_CD1_N SDA5/GPIO65 LOW W28 HIGH Y26 BackEnd 2 HW_OPT_2 Y27 SCL5/GPIO66 HW_OPT_1 CAM_CE2_N SDA4/GPIO67 SC_VCC_SEL/GPIO88 GPIO0 SCL4/GPIO68 V28 AC7 SDA3/GPIO69 CAM_CE1_N AC6 GPIO1 RMII_RXD0 I2C_SDA6 BackEnd 1 AD6 SCL3/GPIO70 RMII_RXD1 I2C_SCL6 HW_OPT_0 AE6 GPIO2 W26 I2C_SDA5 SDA2/GPIO71 AD1 I2C_SCL5 GPIO3 RMII_TXD0 1 AD5 GPIO4 SCL2/GPIO56 AD3 1 0 AE5 GPIO5 SDA1/GPIO57 AE1 1 1 AE4 SCL1/GPIO58 RMII_TXD1 0 0 AD4 GPIO6 RMII_TXEN 0 MODEL_OPT_1 AC4 SDA0/GPIO59 RMII_MDC I2C_SDA4 MODEL_OPT_0 AC5 AC3 I2C_SCL4 AB4 GPIO7 AC2 URSA5 GPIO8 SCL0/GPIO60 AB3 I2C_SDA3 GPIO9 AB6 RMII_MDIO ZORAN_FRC R121 10K DVB_S_TUNER R154 10K DVB_C2_TUNER R156 10K CP_BOX R147 10K DVB_T2_TUNER R152 10K OPT 10K R145 3D_DEPTH R140 10K OPTIC R138 10K FHD 10K I2C_SCL3 R124 GPIO14 RMII_CRS_DV I2C_SCL2 I2C_SDA2 URSA5 R110 10K SPI_SCLK0/GPIO37 RMII_REF_CLK +3.3V_NORMAL FRC_EXTERNAL R100 10K GPIO15 AB2 I2C_SDA1 LG FRC3 GPIO16 SPI_DO0/GPIO38 AB1 I2C_SCL1 NO_FRC SPI_DI0/GPIO39 SPI_CS1/GPIO32 HDMI_INT SoC internal FRC GPIO17 AB23 IRB_SPI_MISO OPT R203 100K G +3.3V_NORMAL EMMC_DATA[6] AC1 BOOT_MODE1 G OPT R133 R150 EPHY_INT /USB_OCD2 S 10K 10K 4.7K 4.7K SOC_RX ERROR_OUT EMMC_DATA[7] E27 R23 TRST_N1 SOC_RESET BOOT_MODE0 EMMC_DATA[0-7] C26 2.7K R201 V24 TDO0 +3.3V_NORMAL +5V_NORMAL EMMC_DATA5 TRST_N0 EMMC_CMD F26 5% 1/16W V25 TCK0 EMMC_CLK F27 G 10K 10K U25 TRST_N0 +3.3V_NORMAL EMMC_DATA6 PORES_N TDI0 BOOT_MODE1 EMMC_DATA7 V23 TMS0 R132 OPT R187 4.7K 4.7K R185 OPT EMMC_CMD AE3 SOC_RESET TRST_N0 BOOT_MODE1 R188 OPM1 EMMC_CLK OPM0 +3.3V_NORMAL OPT XO_MAIN EMMC_RST E28 EMMC_RST D AB17 XIN_MAIN S AB16 +3.3V_NORMAL R186 B22 EB_ADDR15/GPIO82 XO_MAIN 560 EB_ADDR16/GPIO83 R104 1% EB_ADDR17/GPIO84 A22 XIN_MAIN JTAG I/F FOR MAIN EB_CS0/GPIO77 MODE or "01" : NOR : eMMC : NAND EB_CS1/GPIO78 LOCAL_DIM_EN BOOT "11" "10" "00" EB_CS2/GPIO79 EB_CS3/GPIO64 OPT HW_OPT_6 Disable HW_OPT_7 USB_DM3 USB_DP3 USB_HUB_IC_IN_DM USB_HUB_IC_IN_DP SMARTCARD_RST SMARTCARD_DATA SMARTCARD_VCC SMARTCARD_DET SMARTCARD_PWR_SEL 10K CI CAM_REG_N P100 +3.3V_NORMAL 12507WS-04L OPT 1 2 UART1_RX OPT 22 R175 R176 22 R174 R173 RCLAMP0502BA D100 3 4 WIFI_DM UART1_TX WIFI_DP MOTOR_CW MOTOR_OPEN_SW IR_B_RESET MO_SENS_TO_MAIN_UP MOTOR_CCW MO_SENS_TO_MAIN_DOWN OPT DEBUG MOTOR_CLOSE_SW CAM_WAIT_N PCM_RST Debug R168 +3.3V_NORMAL R166 R167 I2C_SDA4 I2C_SCL4 PCM_5V_CTL I2C_SCL3 CAM_INPACK_N CAM_IREQ_N CAM_CD1_N CAM_CD2_N 10K CI 10K CI /PCM_CE2 /PCM_CE1 EPHY_RXD0 EPHY_RXD1 EPHY_TXD0 EPHY_EN I2C_SDA3 I2C_SDA6 I2C_SCL6 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes EPHY_MDC I2C_SCL2 I2C_SDA5 I2C_SCL5 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. EPHY_TXD1 I2C_SCL1 I2C_SDA2 EPHY_MDIO R183 1.2K R199 3.3K R197 3.3K R198 3.3K R196 3.3K R195 2.2K R182 2.2K R184 1.2K I2C_SDA1 EPHY_CRS_DV MODEL OPTION 8 is just for CP Box It should not be appiled at MP EPHY_REFCLK NOT_ZORAN_FRC R126 10K NON_DVB_C2_TUNER R158 10K NON_DVB_S_TUNER R155 10K NON_CP_BOX R148 10K NON_DVB_T2_TUNER R153 10K 1GByte R146 10K NON_3D DEPTH R141 10K NON_OPTIC R139 10K 10K UD R125 22 R117 R111 FRC310K OPT FRC_INTERNAL R107 10K HP_AMP_MUTE R181 3.3K Not Support (For UD) R180 3.3K Support I2C PULL UP Not Support R179 2.2K HW_OPT_10 +3.3V_NORMAL Support R178 2.2K HW_OPT_9 SMARTCARD_CLK HW_OPT_8 5 Place near Jack side LG1152 B1 MAIN & GPIO 1 LGE Internal Use Only 0.1uF 0.1uF 0.1uF 0.1uF C337 C342 C343 C346 0.1uF 0.1uF C334 0.1uF C323 C329 0.1uF 0.1uF C320 0.1uF C317 C302 10uF C326 10uF 0.1uF IC100 LG1152D-B1 Max 680mA L300 BLM18PG121SN1D ESD_LG1152 ZD301 5V 0.1uF C338 C332 10uF C370 VCC1.5V_MAIN (18) C333 0.1uF 0.1uF C369 10uF C366 10uF C359 10uF 0.1uF C305 10uF 0.1uF 0.1uF C321 C312 10uF C318 LG1152D +1.5V_DDR L305 BLM18PG121SN1D L308 BLM18PG121SN1D L302 BLM18PG121SN1D L304 BLM18PG121SN1D AVDD10_LVTX VDDC_XTAL C368 AVDD10_DEMOD +1.5V_Bypass Cap Max 35mA +1.0V_VDD AVDD10_VSB +1.0V_VDD C313 +1.0V_VDD Max 1mA +1.0V_VDD C311 Max 12mA Max 360mA VDD33 U8 U9 U10 V8 V9 On Package Decap : 0.1uF *3ea VDD33_USB V10 On Package Decap : 0.1uF *1ea J21 VCC1.5V_MAIN VCC1.5V_MAIN K21 AA10 Max 40mA R302 VREF_M0 1K 1% R300 LG1152A 1K 1% Max 40mA AA11 VREF_M1 VDD18 GND_63 N10 K16 D16 G5 G8 G9 G10 G11 G14 G15 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 J4 J5 J6 J7 AVSS25_REF GND_64 GND_XTAL GND_65 GND_1 GND_66 GND_2 GND_67 GND_3 GND_68 GND_4 GND_69 GND_5 GND_70 GND_6 GND_71 GND_7 GND_72 GND_8 GND_73 GND_9 GND_74 GND_10 GND_75 GND_11 GND_76 GND_12 GND_77 GND_13 GND_78 GND_14 GND_79 GND_15 GND_80 GND_16 GND_81 GND_17 GND_82 GND_18 GND_83 GND_19 GND_84 GND_20 GND_85 GND_21 GND_86 GND_22 GND_87 GND_23 GND_88 GND_24 GND_89 1000pF 0.1uF C350 C362 1% 1K R303 1000pF 0.1uF C300 C308 1% 0.1uF C423 Max 50mA M12 +2.5V_NORMAL M13 R304 1K 1% C351 C363 1000pF 0.1uF 1% 1K R305 0.1uF C340 0.1uF C316 C336 0.1uF 0.1uF 0.1uF C310 C306 C303 10uF 0.1uF 0.1uF 0.1uF VREF_M1 +2.5V_NORMAL VDD25_AUD Max 20mA +1.0V_VDD Max 1320mA +0.9V_VDD M14 M15 L315 BLM18PG121SN1D L322 BLM18PG121SN1D M17 N4 N5 N6 N8 N9 N11 AVSS25_REF F13 F14 L306 BLM18PG121SN1D L320 BLM15BD121SN1 AVDD10_OSPREY G15 M20 M21 M27 M28 N20 N21 P20 On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *3ea N15 P21 On Package Decap : 0.1uF *1ea N16 R20 P3 R21 +0.9V_VDD P4 P5 Max 120mA +1.8V_NORMAL +1.8V_NORMAL P15 Max 256mA Max 35mA +3.3V_NORMAL P16 +3.3V_NORMAL VDD33_HDMI +3.3V_NORMAL VDD33_XTAL VDD33_CVBS R16 L323 BLM18PG121SN1D L319 BLM18PG121SN1D R17 R18 T13 U13 GND_90 L309 BLM18PG121SN1D K10 L316 BLM18PG121SN1D L312 BLM18PG121SN1D R3 K9 VDD18 Max 1mA K11 L8 L9 L10 L11 M8 M9 M10 M11 N8 On Package Decap:0.1uF *1ea On Package Decap:0.1uF *1ea N9 N10 N11 On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *1ea P8 P9 P10 Max 31mA +1.8V_NORMAL Max 93mA L318 BLM18PG121SN1D R8 R9 L314 BLM18PG121SN1D 0.1uF R10 R11 Y7 Y8 MAIN_XTAL C304 0.1uF 0.1uF C384 C378 10uF 0.1uF +0.9V_VDD C404 C397 10uF P11 VDD18_MAIN_XTAL VDD18_LVRX C389 +1.8V_NORMAL GND_24 VDD33_5 GND_25 VDD33_6 GND_26 AVDD33_USB_1 GND_27 AVDD33_USB_2 GND_28 AVDD33_BT_USB_1 GND_29 AVDD33_BT_USB_2 GND_30 GND_31 VDD18_1 GND_32 VDD18_2 GND_33 VDD18_3 GND_34 VDD18_4 GND_35 VDD18_5 GND_36 VDD18_6 GND_37 VDD18_LTX_1 GND_38 VDD18_LTX_2 GND_39 VDD18_LTX_3 GND_40 VDD18_LTX_4 GND_41 VDD18_LVRX_1 GND_42 VDD18_LVRX_2 GND_43 VDD18_LVRX_3 GND_44 VDD18_DISPPLL GND_45 VDD18_DR3PLL GND_46 VDD18_MAIN_XTAL GND_47 GND_48 VDD15_M2_1 GND_49 VDD15_M2_2 GND_50 VDD15_M2_3 GND_51 VDD15_M2_4 GND_52 VDD15_M2_5 GND_53 VDD15_M2_6 GND_54 VDD15_M2_7 GND_55 VDD15_M2_8 GND_56 VDD15_M2_9 GND_57 VDD15_M0_1 GND_58 VDD15_M0_2 GND_59 VDD15_M0_3 GND_60 VDD15_M0_4 GND_61 VDD15_M0_5 GND_62 VDD15_M0_6 GND_63 VDD15_M0_7 GND_64 VDD15_M0_8 GND_65 VDD15_M0_9 GND_66 VDD15_M0_10 GND_67 VDD15_M0_11 GND_68 VDD15_M0_12 GND_69 VDD15_M0_13 GND_70 VDD15_M0_14 GND_71 VDD15_M0_15 GND_72 VDD15_M0_16 GND_73 VDD15_M0_17 GND_74 GND_75 VREF_M2_0 GND_76 VREF_M1_0 GND_77 VREF_M1_1 GND_78 VREF_M0_0 GND_79 VREF_M0_1 GND_80 GND_81 VDDC10_OSPREY_1 GND_82 VDDC10_OSPREY_2 GND_83 VDDC10_OSPREY_3 GND_84 VDDC10_OSPREY_4 GND_85 VDDC10_OSPREY_5 GND_86 VDDC10_OSPREY_6 GND_87 VDDC10_OSPREY_7 GND_88 VDDC10_OSPREY_8 GND_89 VDDC10_OSPREY_9 GND_90 VDDC10_OSPREY_10 GND_91 VDDC10_OSPREY_11 GND_92 GND_93 K8 Max 49mA VDD18_LVTX P13 GND_23 VDD33_4 L20 N13 N14 VDD33_3 L4 G12 AVDD10_OSPREY L321 BLM15BD121SN1 N12 VREF_M0 0.1uF GND_62 VREF_M2 VDD25_REF VDD25_COMP C349 VQPS For HDCP OTP Will be change to LOW for MP AVSS25_REF M11 H21 0.1uF GND_61 G4 H20 On Package Decap : 0.1uF *6ea Max 10mA Max 250mA M10 H19 C411 +2.5V_NORMAL M9 C324 GND_60 H18 0.1uF GND_59 VDDC_XTAL H17 C348 AVDD10_LLPLL M8 H16 0.1uF GND_58 M7 H14 C410 AVDD10_LVTX_2 M6 0.1uF GND_57 0.1uF L16 GND_56 AVDD10_LVTX_1 M5 C345 N7 AVDD10_VSB M4 H13 C395 10uF VDDC_XTAL GND_55 On Package Decap : 0.1uF *1ea C309 10uF D18 AVDD10_CVBS On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *1ea L14 G21 C315 D17 GND_54 G19 L303 BLM18PG121SN1D C341 10uF K15 VDDC10_2 MAIN_XTAL G20 C327 AVDD10_LVTX GND_53 0.1uF R15 VDDC10_1 C322 G7 C325 AVDD10_VSB L13 0.1uF G6 G18 Max 5900mA L12 C319 GND_52 0.1uF GND_51 Max 6mA L11 C314 VDD18_2 AVDD10_DEMOD +0.9V_VDD 0.1uF GND_50 G17 C353 VDD18_1 H11 G13 +0.9V_VDD 0.1uF N2 L10 H9 On Package Decap : 0.1uF *1ea C382 N1 L9 C307 10uF GND_49 C347 10uF GND_48 H8 G16 C374 10uF VDD25_LVTX_3 L8 G11 G14 C301 10uF GND_47 L7 On Package Decap : 0.1uF *2ea ESD_LG1152 ZD300 5V VDD25_LVTX_2 L6 G10 F22 0.1uF GND_46 G9 VCC1.5V_MAIN C418 GND_45 VDD25_LVTX_1 L5 G22 G8 L325 BLM18PG121SN1D C415 10uF VDD25_AUD_3 L313 BLM18PG121SN1D L324 BLM18PG121SN1D L4 0.1uF GND_44 GND_22 F9 C381 GND_43 VDD25_AUD_2 VCC1.5V_DE H10 0.1uF VDD25_AUD_1 K14 VDD25_VSB +2.5V_NORMAL VDD25_LVTX C400 GND_42 K13 +2.5V_NORMAL VDD25_CVBS +2.5V_NORMAL C371 10uF G13 VDD25_AAD Max 100mA K12 0.1uF G12 GND_41 C393 VDD18_A GND_40 VDD25_COMP_4 Max 28mA Max 250mA 0.1uF B18 VDD25_COMP_2 K11 C390 V6 GND_39 K10 0.1uF P7 VDD25_LVTX VDD25_COMP_1 K9 C407 P6 GND_38 0.1uF J16 GND_37 VDD25_COMP_3 C385 V7 VDD25_AUD AVDD25_REF K8 0.1uF R9 GND_36 OPT C416 P9 VDD25_CVBS_3 L301 BLM18PG121SN1D K7 C375 10uF R10 VDD25_COMP GND_35 0.1uF P10 VDD25_CVBS_1 B28 K6 0.1uF V13 GND_34 AA13 J28 VREF_M2 VCC1.5V_DE K5 AG1 AB12 Max 40mA Max 340mA +1.5V_DDR C405 VDD25_REF VDD25_CVBS_2 K4 C379 10uF R12 GND_33 C386 R13 VDD25_VSB C413 10uF GND_32 L15 0.1uF VDD25_CVBS VCC1.5V_DE J15 0.1uF GND_31 AH27 AA12 VDD18_MAIN_XTAL J14 C417 VDD33_XTAL VDD25_VSB J13 C419 GND_30 AG28 AA7 On Package Decap : 0.1uF *1ea On Package Decap : 0.1uF *1ea 0.1uF GND_29 AVDD33_HDMI_2 J12 VDD18_LVTX VDD18_LVRX C409 AVDD33_HDMI_1 J11 Y19 AA9 0.1uF GND_28 J10 Y18 AA8 C408 M16 AVDD33_CVBS_2 C422 10uF H16 GND_27 C414 10uF F18 GND_26 AVDD33_CVBS_1 C401 10uF R14 VDD33_XTAL VDD33_2 J9 0.1uF P14 VDD33_HDMI GND_25 C398 10uF P2 J8 VDD33_1 C403 P1 VDD18_A L326 BLM18PG121SN1D C421 10uF VDD33_CVBS R301 VDD33 1K +1.8V_NORMAL GND_21 VDD33_2 W18 W19 IC101 LG1152AN-B2 K13 VDD33_1 AF1 F28 VDDC09_1 GND_94 VDDC09_2 GND_95 VDDC09_3 GND_96 VDDC09_4 GND_97 VDDC09_5 GND_98 VDDC09_6 GND_99 VDDC09_7 GND_100 VDDC09_8 GND_101 VDDC09_9 GND_102 VDDC09_10 GND_103 VDDC09_11 GND_104 VDDC09_12 GND_105 VDDC09_13 GND_106 VDDC09_14 GND_107 VDDC09_15 GND_108 VDDC09_16 GND_109 VDDC09_17 GND_110 VDDC09_18 GND_111 VDDC09_19 GND_112 VDDC09_20 GND_113 VDDC09_21 GND_114 VDDC09_22 GND_115 VDDC09_23 GND_116 VDDC09_24 GND_117 VDD09_LTX_1 GND_118 VDD09_LTX_2 GND_119 VDD09_LTX_3 GND_120 AVDD09_DR3PLL GND_121 GND_122 H22 M303 MDS62110213 MDS62110213 ATSC M307 MDS62110213 ESD M314 MDS62110205 ESD ESD For Tuner Sensitivity / Under TUNER M310 MDS62110205 OPT VDD33 L310 BLM18PG121SN1D ESD ESD For ATSC J7 Max 48.8mA +3.3V_NORMAL J8 VDD33_USB J9 J10 MDS62110217 M311 MDS62110205 M319 +3.3V_NORMAL L317 BLM18PG121SN1D J11 J12 0.1uF MDS62110213 M306 H15 MDS62110217 MDS62110205 ALBLOCK H12 M320 0.1uF GASKET_8.0X6.0X7.5H MDS62110205 J13 J14 J15 J16 C406 M322 C402 M302 M313 GND_MAIN_XTAL H7 C396 10uF MDS62110213 MDS62110213 ESD OPT J17 J18 J19 On Package Decap : 0.1uF *1ea J20 K7 K12 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. GND_125 GND_126 G23 GND_127 GND_128 G7 0.1uF ESD ALBLOCK ESD C399 MDS62110205 SMR-T-6-6.5-8 0.1uF MDS62110205 HEATSINK MDS62110206 For secure BOOT OTP Will be change to LOW for MP C394 M317 M316 0.1uF M305 M312 M309 SP_VQPS MDS62110217 C392 MDS62110213 ESD MDS62110205 0.1uF MDS62110213 M304 MDS62110205 ESD HEATSINK C391 M301 ALBLOCK 0.1uF MDS62110213 M321 C388 ATSC M300 0.1uF MDS62110205 GND_123 GND_124 AA19 On Package Decap:0.1uF *1ea C383 M318 VDDC_MAIN_XTAL VDD18 SMD TOP FOR ESD 0.1uF M315 For Tuner Sensitivity / Under DDR M308 GASKET_8.0X6.0X7.5H C377 SMD Bottom C372 10uF For HeatSinK, AL Block / SMD Top GND_1 GND_129 GND_2 GND_130 GND_3 GND_131 GND_4 GND_132 GND_5 GND_133 GND_6 GND_134 GND_7 GND_135 GND_8 GND_136 GND_9 GND_137 GND_10 GND_138 GND_11 GND_139 GND_12 GND_140 GND_13 GND_141 GND_14 GND_142 GND_15 GND_143 GND_16 GND_144 GND_17 GND_145 GND_18 GND_146 GND_19 GND_147 GND_20 GND_148 K14 K15 K16 K17 K18 K19 K20 L7 L12 L13 L14 L15 L16 L17 L18 L19 L21 M7 M12 M13 M14 M15 M16 M17 M18 M19 N7 N12 N13 N14 N15 N16 N17 N18 N19 P7 P12 P13 P14 P15 P16 P17 P18 P19 R7 R12 R13 R14 R15 R16 R17 R18 R19 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 U7 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W20 W21 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y20 Y21 AA14 AA15 AA16 AA17 AA18 AA20 AA21 AB7 AB10 AB11 AB13 AB22 LG1152 MAIN POWER 3 11/05/31 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only C +5V_NORMAL Q506 MMBT3904(NXP) Place these close to tuner EU C510 0.1uF 16V TU_CVBS EU R527 10K B E EU R507 10K EU R593 220 EU R592 220 EU 680pF C506 OPT IC101 LG1152AN-B2 DTV_ATV_SELECT INTR_GBB INTR_HDMI1 IC500 NLASB3157DFT2G IC100 LG1152D-B1 L1 AH2 L2 AG2 L3 AF2 INTR_AFE3CH STPI_CLK INTR_HDMI1 STPI_SOP INTR_AFE3CH STPI_VAL E 100 L503 1uH SELECT SC_CVBS_IN C508 150pF 50V EU C509 150pF EU EU R614 75 1% VCC 5.5V D504 1 EU 5 2 B AUD_HMR0AMUTE EU R599 75 AUD_HMR0ALRCK OPT GND AUD_HMR0ABCK AUD_HMR0ASD4 AUD_HMR0ASD3 L504 1uH AV1_CVBS_IN 6 AUD_HMR00ARC ATV_OUT EU Q504 MMBT3906(NXP) C B1 R576 A C514 150pF 50V 50V 150pF C511 R615 75 1% 4 3 B0 AUD_HMR0ASD2 Selece = Low AUD_HMR0ASD1 DTV/MNT_VOUT Selece = High ==> A = B1 DTV/MNT_V_OUT AUD_DAC1_SCK IC101 LG1152AN-B2 R616 220CHB AUD_FS23CLK K17 K18 M2 SC_SOG_IN M1 R521 SOC_RESET EU R524 2.7K L500 U14 R572 33 C550 0.047uF T14 R573 R559 100 C551 68 C552 0.047uF V15 0.047uF U15 100 C553 0.047uF T15 33 C554 0.047uF U16 R557 33 C555 0.047uF V14 0 EU C515 100pF 50V EU 10K 10K R555 R553 V16 0.047uF R563 R530 R529 R528 T16 0.047uF 33 C556 68 C557 R575 R558 75 75 75 OPT OPT R574 R551 DTV/MNT_VOUT C607 10pF OPT C606 10pF C605 10pF 5.5V D500 OPT 5.5V D501 OPT 5.5V D502 OPT L502 Close to LG1152A V17 U17 R579 22 R580 22 R8 R11 75 C524 10pF 75 OPT C546 10pF 75 OPT OPT C528 10pF R536 68 C516 0.047uF U8 R539 33 C518 0.047uF V8 R541 68 C523 0.047uF V10 R546 33 C526 0.047uF T8 R547 0 C527 1000pF V9 0.047uF T11 R550 33 C532 0.047uF U9 R568 33 C542 0.047uF T9 R594 R600 R595 R548 R569 C531 68 C543 33 C544 C545 SC_SOG_IN R570 33 0.047uF U10 T10 1000pF 0.047uF V11 150 C538 0.047uF U11 R565 150 C539 0.047uF V12 R566 0 COMP1_Pr R567 150 AUAD_R_CH4_IN AUAD_L_CH2_IN CVBS_IN1 AUAD_R_CH2_IN CVBS_IN2 AUAD_L_CH1_IN CVBS_IN3 AUAD_R_CH1_IN CVBS_VCM CVBS_IN4 AUAD_REFN CVBS_IN5 AUAD_REFP CVBS_IN6 AUAD_VR_OUT CB_IN CB_VCM AUMI_BIAS BUF_OUT1 AUMI_IN BUF_OUT2 AUMI_COM U12 1000pF 0.047uF DDCD0_CK T12 HSYNC AUAD_L_CH5_IN V3 AUAD_R_CH5_IN V4 AUAD_L_CH4_IN T3 AUAD_R_CH4_IN U5 T5 PHY0_RXCN_0 SC1_SID PHY0_RXCP_0 BINCOM_IN PHY0_RX0N_0 B_IN PHY0_RX0P_0 GINCOM_IN PHY0_RX1N_0 G_IN PHY0_RX1P_0 SOG_IN PHY0_RX2N_0 RINCOM_IN R_IN PHY0_RX2P_0 Y1_IN SOY1_IN RFAGC PR1_IN IFAGC PB2_IN Y2_IN SOY2_IN ADC_I_INP PR2_IN ADC_I_INN 4 3 8pF C512 GND_2 100K R538 EU 1uF 25V 10K R6005 C6001 X-TAL_2 SCART_AMP_L_FB BB_TP_DATA4 BB_TP_DATA5 T6 U7 T7 T4 10K R534 2.2uF C537 U4 10K R520 2.2uF C547 2.2uF C548 V5 R6 +3.3V_NORMAL E17 R577 4.7K R578 4.7K BB_SDA_I SC_R CHB_CVBS HDMI_CLK- H17 H18 G17 G18 SC_CVBS_IN CHB_UP CHB_START HDMI_RX0- SC_G CHB_DATA1 HDMI_RX0+ SC_FB HDMI_RX1- SC_ID ATV_OUT CHB_DATA2 CHB_DATA3 DTV/MNT_V_OUT M18 CVBS_GC2 CVBS_GC1 CVBS_GC0 CVBS_UP P18 IF_AGC C115 U18 T18 JDVR_SCLK 0.1uF C116 0.1uF C117 0.1uF IF_N IF_P IF_N IF_P IF_AGC L509 C575 100pF 50V R514 C581 560pF 50V OPT C572 330pF 50V OPT 2.2uF R509 FE_TS_SYNC DAC_DATA1 FE_TS_VAL DAC_DATA2 TPI_DVB_ERR DAC_DATA3 FE_TS_DATA[0-7] DAC_DATA4 TPO_DATA[0-7] TPI_DATA[0-7] DAC_START AUAD_R_CH5_IN R515 100K TPI_ERR AAD_GC0 TPI_VAL OPTIC_GPIO1 AAD_GC1 AAD_GC2 AAD_GC4 AAD_DATA3 AAD_DATA4 AAD_DATA5 AAD_DATA6 XO_SUB AAD_DATA8 HP_LOUT_MAIN C502 EU L510 C582 330pF 50V OPT C503 2.2uF EU 2.2uF EU EU C588 330pF 50V R510 AUAD_L_CH4_IN R516 13K HSR_AP0 HP_ROUT_MAIN C604 0.01uF HSR_BM0 HSR_BP0 HSR_CM0 HSR_CLKM0 HSR_DM0 HSR_EP0 HSR_AM1 R517 C586 560pF 50V OPT 100K C505 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes HSR_CLKM1 HSR_CLKP1 HSR_EM1 2.2uF R512 13K AUAD_L_CH3_IN R518 2.2uF R513 13K AH6 G2 AG6 G3 AF6 B1 AH7 STPI_DATA AUD_HMR0AMUTE STPIO_CLK AUD_HMR0ALRCK STPIO_SOP/GPIO43 AUD_HMR0ABCK STPIO_VAL/GPIO42 AUD_HMR0ASD4 STPIO_ERR/GPIO41 AUD_HMR0ASD3 STPIO_DATA/GPIO40 AG7 A4 AH10 B4 AG10 C4 AF10 A2 AH8 D1 AF7 D2 AE8 E2 AD8 E1 AE7 F1 AD7 C529 220pF F2 B2 AC8 AG8 50V A3 AH9 C2 AF8 B3 AG9 C3 AF9 AUD_HMR0ASD1 AE9 E3 AD9 F3 AC9 D4 AE10 E4 AD10 F4 AC10 D5 AE11 E5 AD11 F5 AC11 D6 AE12 A5 AH11 B5 AG11 C5 AF11 A6 AH12 B6 AG12 C6 AF12 47 CHB AC28 AC26 AB28 33 R556 USB_CTL2 AC27 AB27 TPI_DVB_SOP/GPIO46 AUD_DAC1_LRCH TPI_DVB_VAL/GPIO45 AUD_DAC1_SCK AUD_DAC1_LRCK FE_TS_CLK TPI_DVB_ERR TPI_DVB_DATA0/GPIO44 AUD_FS25CLK TPI_DVB_DATA1 AUD_FS24CLK TPI_DVB_DATA2 AUD_FS23CLK TPI_DVB_DATA3 AUD_FS21CLK TPI_DVB_DATA4 AUD_FS20CLK TPI_DVB_DATA5 AUDCLK_OUT_SUB TPI_DVB_DATA6 AUD_DAC0_LRCK TPI_DVB_DATA7 AE28 FE_TS_SYNC AG27 FE_TS_VAL TPI_DVB_ERR AF28 AG26 FE_TS_DATA[0] AF26 FE_TS_DATA[1] AF25 FE_TS_DATA[2] AH26 FE_TS_DATA[3] AH25 FE_TS_DATA[4] AG25 FE_TS_DATA[5] AH24 FE_TS_DATA[6] AG24 FE_TS_DATA[7] FE_TS_DATA[0-7] AUD_DAC0_LRCH AUD_DAC0_SCK TPI_CLK H24 AUD_ADC_LRCH TPI_CLK AUD_ADC_SCK TPI_SOP AUD_ADC_LRCK TPI_VAL AUD_MIC_LRCH TPI_ERR AUD_MIC_SCK TPI_DATA0 TPI_DATA1 TPI_DATA2 BB_TPI_DATA0 TPI_DATA3 BB_TPI_DATA1 TPI_DATA4 BB_TPI_DATA2 TPI_DATA5 BB_TPI_DATA3 TPI_DATA6 BB_TPI_DATA4 TPI_DATA7 TPI_SOP J25 TPI_VAL J24 TPI_ERR H25 J27 TPI_DATA[0] J26 TPI_DATA[1] H28 TPI_DATA[2] H27 TPI_DATA[3] H26 TPI_DATA[4] G28 TPI_DATA[5] G27 TPI_DATA[6] G26 TPI_DATA[7] TPI_DATA[0-7] BB_TPI_DATA5 BB_TPI_DATA6 TPO_CLK D24 BB_TPI_DATA7 TPO_CLK BB_TPI_VAL TPO_SOP BB_TPI_SOP TPO_VAL BB_TPI_ERR TPO_ERR BB_TPI_CLK TPO_DATA0 TPO_DATA1 BB_SDA_I TPO_DATA2 BB_SDA_O TPO_DATA3 BB_SCL TPO_DATA4 HS_SCL TPO_DATA5 HS_SDA_I TPO_DATA6 HS_SDA_O TPO_DATA7 TPO_SOP E23 TPO_VAL D25 TPO_ERR D23 H23 TPO_DATA[0] G25 TPO_DATA[1] G24 TPO_DATA[2] F25 TPO_DATA[3] F24 TPO_DATA[4] F23 TPO_DATA[5] E25 TPO_DATA[6] E24 TPO_DATA[7] TPO_DATA[0-7] AD12 F6 AC12 D7 AE13 B7 AG13 C7 AF13 A8 AH14 B8 AG14 C8 AF14 CHB_DN CHB_UP CHB_START C1 CHB_DATA0 AUDCLK_OUT CHB_DATA1 DACLRCH CHB_DATA2 DACSLRCH/GPIO95 CHB_DATA3 DACCLFCH/GPIO94 CHB_DATA4 Close to LG1152A R581 33 AE14 F7 AC13 E7 AD13 E8 AD14 F8 AC14 Close to LG1152A R582 33 AH15 R583 AG15 33 D9 DACSCK CLK_54 CVBS_GC2 PCMI3LRCH CVBS_GC0 PCMI3SCK/GPIO80 CVBS_UP AD15 F9 AC15 C10 AF16 D10 AE16 AUD_MASTER_CLK AUD_LRCH A2 B2 100 R544 B1 100 R545 FRC3_FLASH_WP AUD_SCK AUD_LRCK OPTIC_BACK_CHANNEL C3 A4 OPTIC_GPIO1 AE2 CVBS_DN IEC958OUT FS00CLK AUD_SUBMCK R630 AD24 R598 OPT 47 R619 OPT 47 R628 OPT 22 AE25 R629 AD25 AUDCLK_TO_DIGITAL E9 R542 100 R543 A3 B3 PCMI3LRCK/GPIO81 CVBS_GC1 AUD_SUBLRCH AUD_SUBSCK/GPIO51 AF15 AE15 100 C2 DACLRCK AH13 D8 B9 CHB_ERR CHB_DATA R200 AD26 AF27 TPI_DVB_CLK/GPIO47 AUD_MIC_LRCK D3 CHB_VAL AD27 AUD_HMR0ASD2 AUD_HMR0ASD0 C1 CHB_SYNC AD28 DAC_DATA0 AC25 100 SPDIF_OUT C630 82pF 50V 47 AMP_RESET_N AUD_SUBLRCK/GPIO52 +3.3V_NORMAL DAC_DATA1 DAC_DATA2 DAC_DATA3 BTSCSEL DAC_DATA4 DTS_EN AB18 22 R596 AB19 22 R597 DTS_EN: ENABLE(’1’) (for development) DAC_START E10 AD16 F10 AC16 D11 AE17 E11 AD17 F11 AC17 D12 AE18 E12 AD18 F12 AC18 D13 AE19 E13 AD19 F13 AC19 D14 AE20 E14 AD20 F14 AC20 D15 AE21 E15 AD21 AAD_GC0 AAD_GC1 N1 AAD_GC2 TXA0N AAD_GC3 TXA0P AAD_GC4 TXA1N AAD_DATAEN TXA1P AAD_DATA0 TXA2N AAD_DATA1 TXA2P AAD_DATA2 TXACLKN AAD_DATA3 TXACLKP AAD_DATA4 TXA3N AAD_DATA5 TXA3P AAD_DATA6 TXA4N AAD_DATA7 TXA4P AAD_DATA8 TXB0N AAD_DATA9 TXB0P R9112 33 AC21 TXB1N AUPLL_CLK B10 AG16 A10 AH16 A11 AH17 B11 AG17 C12 AF18 C11 AF17 B12 AG18 A12 AH18 A13 AH19 B13 AG19 C14 AF20 C13 AF19 B14 AG20 A14 AH20 A15 AH21 B15 AG21 C16 AF22 C15 AF21 B16 AG22 A16 AH22 A17 AH23 B17 AG23 C18 AF24 C17 AF23 HSR_EP1 TXB1P TXB2N HS_RX1_AM TXB2P HS_RX1_AP TXBCLKN HS_RX1_BM TXBCLKP HS_RX1_BP TXB3N HS_RX1_CM TXB3P HS_RX1_CP TXB4N HS_RX1_CLKM TXB4P N2 P2 P1 P3 R3 R1 R2 T2 T1 T3 U3 U1 U2 V2 V1 V3 W3 W1 W2 Y2 Y1 Y3 AA3 SOC_TXA0N SOC_TXA0P SOC_TXA1N SOC_TXA1P SOC_TXA2N SOC_TXA2P SOC_TXACLKN SOC_TXACLKP SOC_TXA3N SOC_TXA3P SOC_TXA4N SOC_TXA4P SOC_TXB0N SOC_TXB0P SOC_TXB1N SOC_TXB1P SOC_TXB2N SOC_TXB2P SOC_TXBCLKN SOC_TXBCLKP SOC_TXB3N SOC_TXB3P SOC_TXB4N SOC_TXB4P HS_RX1_CLKP HS_RX1_DM HS_RX1_DP HS_RX1_EM L6 HS_RX1_EP PWM0/GPIO55 HS_RX2_AM PWM1/GPIO54 HS_RX2_AP PWM2/GPIO53 HS_RX2_BM PWM_IN L5 M4 M5 OPT EDGE_LED R631 10K R632 100 R633 100 A_DIM PWM_DIM2 PWM_DIM BPL_IN HS_RX2_BP HS_RX2_CM HS_RX2_CP HS_RX2_CLKM HS_RX2_CLKP HS_RX2_DM HS_RX2_DP HS_RX2_EM HS_RX2_EP 75K AUAD_R_CH3_IN 100K LG1152A C589 100pF 50V Place JACK Side THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HSR_CP1 HSR_DP1 R519 R609 470K EU HSR_CM1 HSR_DM1 C504 L511 75K AUAD_R_CH4_IN EU R603 C577 100pF 50V EU G1 DCO_OUT_CLK HSR_BP1 13K EU R511 AH4 F15 C603 0.01uF HSR_BM1 C576 330pF 50V EU AF5 J1 AAD_DATA9 HSR_AP1 L507 H3 AUD_HMR0ARC CHB_CLK AE26 BTSC_EN: ENABLE(’1’) (for development) HSR_EM0 13K C587 100pF 50V R608 470K C574 560pF 50V OPT 75K AG5 C9 DAC_DATA0 HSR_DP0 C501 H2 AUDCLK_OUT FE_TS_CLK HSR_CLKP0 C573 560pF 50V AH5 A9 FS00CLK AAD_DATA7 OPT H1 CVBS_DN AAD_DATA2 AUAD_L_CH5_IN AF3 A7 CLK_F54M HSR_CP0 13K AF4 K3 CHB_DATA4 SC_L_IN SC_R_IN TUNER_SIF TUNER_SIF R626 22K 2.2uF R508 AG4 J3 E6 CHB_DN CHB_DATA0 HDMI_RX2+ SPDIF_OUT_ARC F17 R627 22K C500 J2 L9DA_SDA_O SC_B HDMI_RX2- F16 L9DA_SDA_I HDMI_CLK+ HDMI_RX1+ G16 L9DA_SCL SCART_Rout E16 J17 BB_SCL HSR_AM0 L508 AV1_R_IN CHB_ERR TU_CVBS SCART_Lout R625 100 SC_R_IN 470K BB_TP_CLK BB_SDA_O AUDA_OUTL EU AV1_L_IN BB_TP_ERR TPO_CLK AAD_DATA1 2.2uF 10V EU EU R602 470K TPO_SOP CHB_VAL SCART_Rout_SOC PC_R_IN SC_L_IN BB_TP_SOP JDVR_SCLK EU L506 470K TPO_VAL CHB_DATA R624 100 PC_L_IN R607 BB_TP_VAL R5 AUDA_OUTR 470K BB_TP_DATA7 TPO_ERR AAD_DATA0 C525 R601 BB_TP_DATA6 TPI_CLK AAD_DATAEN SCART_Lout_SOC C522 TPI_SOP R7 XIN_SUB EU SCART_Lout BB_TP_DATA2 U6 T17 ADC_I_INCOM BB_TP_DATA1 BB_TP_DATA3 1M R6006 AG3 AUD_MIC_LRCK AUAD_R_CH3_IN P12 ANTCON AUD_MIC_SCK AUAD_L_CH3_IN PHY0_ARC_OUT_0 PB1_IN SCART_Rout_SOC BB_TP_DATA0 J18 SC1_FB AUD_ADC_LRCK AUD_MIC_LRCH R502 OPTIC_BACK_CHANNEL R535 C513 EU EU 100K R549 EU EU 100 T2 AAD_GC3 X-TAL_1 GND_1 SCART_AMP_R_FB 2 10K 1 8pF EU 24MHz X500 Near Place Scart AMP +12V 100K R554 EU SCART_Lout_SOC U2 Main clock for LG1152A EU 2.2uF 10V AUD_ADC_SCK DSUB_HSYNC C3626 5pF 50V OPT 25V 1uF C6006 SCART_Rout AUD_ADC_LRCH HPD0 VSYNC AUD_DAC0_SCK R501 H/NIM&CHB H/NIM&CHB DSUB_VSYNC OPT R3633 2K C540 C541 R604 1% 75 R606 1% 75 C578 10pF C579 10pF OPT OPT OPT C580 10pF R605 1% 75 R564 COMP1_Pb COMP1_Y 5.5V D506 L9A_SDA P8 P11 SC_R 100 V2 E18 DSUB_VSYNC SC_B SC_G 5.5V D505 AUAD_L_CH4_IN DDCD0_DA DSUB_HSYNC 100K R552 EU L9A_SCL AUD_DAC0_LRCH AUDA_OUTR T1 U3 AUAD_R_CH5_IN AUAD_R_CH3_IN 0.047uF AUDA_OUTL R2 AUD_DAC0_LRCK C558 1000pF OPT 2.2uF EU AUAD_L_CH3_IN 33 C549 C536 R1 AUDCLK_OUT_SUB TUNER_SIF 10uF AUD_SCART0_OUTRP 0 DSUB_B+ 5.5V D503 AUD_SCART0_OUTLN PORES_N M3 DSUB_G+ C3625 5pF 50V OPT AUDA_OUTR OPM0 AUAD_L_CH5_IN L501 OPT R3634 2K AUDA_OUTL OPM1 AUD_SCART0_OUTRN R571 DSUB_R+ U1 AUDA_BGR_OUT XTLOUT_AAD N3 NON SCART R524-*1 75 0 XTLIN_AAD 100 EU R525 C535 AUD_SCART0_OUTLP 10K EU R522 AAD_ADC_SIF VSB_AUX_XIN R4 SC_FB SC_ID XO_SUB 0.01uF P17 0.1uF EU 33 C534 0.01uF R561 N18 AUD_FS20CLK C520 EU C521 L18 0.1uF 22K 33 C533 22K R560 AAD_ADC_SIFM EU XO_SUB AUD_FS21CLK N17 XIN_SUB EU L17 XIN_SUB R531 R613 75 1% R532 OPT 680pF C517 OPT C NON SCART R525-*1 AUD_FS25CLK AUD_FS24CLK B R617 75 OPT AUD_DAC1_LRCK E Q505 CHB K2 STPI_ERR ==> A = B0 AUD_DAC1_LRCH CHB_CVBS AH3 AUD_HMR0ASD0 +5V_TU R618 220 CHB K1 47CHB AR102 AE27 INTR_GBB 2.2uF C559 OPT +5V_NORMAL LG1152D Place SOC Side LG1152 B0 MAIN AUDIO/VIDEO 3 LGE Internal Use Only IC700 H5TQ2G83BFR-PBC IC703 H5TQ2G83BFR-PBC M0_DDR_VREFCA VCC1.5V_MAIN M0_DDR_DQ7 M0_DDR_DQ8 M0_DDR_DQ9 M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15 H4 C709 0.1uF C710 0.1uF M2 C711 0.1uF M10 C712 0.1uF R730 M0_DDR_DQSU_N M0_DDR_DML VDDQ_4 RAS CAS A1 NC_S1 M0_DDR_DQ1 C21 A8 A21 C18 B21 VSS_1 VSS_2 M0_DDR_DQ6 D3 M0_DDR_DQ2 M0_DDR_DQ10 B14 E9 M0_DDR_DQ3 M0_DDR_DQ9 A16 E4 M0_DDR_DQ4 M0_DDR_DQ8 C14 C9 M0_DDR_DQ7 M0_DDR_DQ7 B17 C3 E8 M0_DDR_DQ5 C17 A15 SIGN50005 DQ1 VSS_8 DQ2 VSS_9 DQ3 VSS_10 DQ4 VSS_11 DQ5 VSS_12 M0_DDR_DQ13 F2 M0_DDR_DQ14 F10 H2 M0_DDR_DQ15 R704 240 H10 1% J8 M0_DDR_DMU A9 VSSQ_3 NC_3 VSSQ_4 NC_4 VSSQ_5 M3 N9 M4 H8 M8 K8 N4 N8 K9 J4 J2 M0_DDR_DQ10 J10 M0_DDR_DQ13 L2 M0_DDR_DQ14 L10 M0_DDR_DQ11 N2 M0_DDR_DQ15 N10 M0_DDR_DQ9 M0_DDR_DQ12 B9 G10 F4 G4 H4 E13 D12 C11 M1_DDR_DQSL_N A7 B7 M1_DDR_DQSU_N A11 C6 M1_DDR_DMU A12 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7 M1_DDR_DQ8 M1_DDR_DQ9 M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15 B11 A13 C10 B12 A10 B13 B10 A8 B4 C8 B5 B6 A5 B8 A6 M1_DDR_BA0 R707 A13 VDD_5 A14 VDD_6 M1_DDR_BA1 200 K9 M1_DDR_BA1 J4 M1_DDR_BA2 M1_DDR_CLK G8 M1_DDR_CLKN M1_DDR_CKE G10 M1_DDR_CKE K2 C713 C714 0.1uF 0.1uF C715 0.1uF C716 0.1uF M1_DDR_CLK M1_DDR_RASN G2 M1_DDR_ODT M1_DDR_CASN R708 M1_DDR_RASN M1_DDR_WEN 200 M1_DDR_CASN F4 G4 H4 M1_DDR_WEN M1_DDR_RESET_N C717 0.1uF M2 C718 0.1uF M10 C719 0.1uF VDDQ_2 CK VDDQ_3 CKE VDDQ_4 E10 RAS CAS A1 NC_S1 M1_DDR_DQSU_P M1_DDR_DQSL_N 0.1uF 1000pF M1_DDR_CLKN M1_DDR_CKE C723 0.1uF C760 0.1uF C751 0.1uF K10 M2 M10 BA1 B10 VDDQ_1 CK VDDQ_2 CK VDDQ_3 C761 0.1uF C756 0.1uF C2 E3 E10 VDDQ_4 CS ODT RAS CAS A1 NC_S1 NC_S2 D4 A11 N1 N11 NC_S4 DQS DQS B8 A8 A2 DM/TDQS VSS_1 NF/TDQS VSS_2 VSS_6 B4 C8 C3 C9 E4 E9 D3 E8 DQ0 VSS_7 DQ1 VSS_8 DQ2 VSS_9 DQ3 VSS_10 DQ4 VSS_11 DQ5 VSS_12 A9 B2 D9 F3 F9 J2 J10 L2 L10 N2 N10 DQ6 DQ7 B3 VSSQ_1 NC_1 VSSQ_2 NC_2 VSSQ_3 NC_3 VSSQ_4 NC_4 VSSQ_5 B9 C10 D2 D10 NC_5 M1_1_DDR_VREFCA R734 K4 L8 L4 K3 L9 L3 M9 M3 N9 M4 H8 M8 K8 N4 N8 A0 DDR3 2Gbit J9 VREFCA A1 A2 A3 E2 VREFDQ A4 A5 A6 H9 A3 VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 A14 VDD_6 VDD_8 K9 J4 BA0 C757 0.1uF D8 G3 C752 0.1uF G9 C753 0.1uF K2 K10 C754 0.1uF M2 M10 C755 0.1uF B10 C745 0.1uF C759 0.1uF VDD_9 BA2 G10 A10 BA1 VDDQ_1 F8 G8 VCC1.5V_MAIN 240 1% A9 J3 R740 ZQ A7 A8 CK VDDQ_2 CK VDDQ_3 CKE VDDQ_4 C2 E3 E10 H3 M1_DDR_ODT M1_DDR_RASN M1_DDR_CASN M1_DDR_WEN M1_DDR_RESET_N G2 F4 G4 H4 CS ODT RAS CAS WE A1 NC_S1 N3 RESET NC_S2 NC_S3 N11 NC_S4 C4 D4 1% M1_DDR_CLK N1 NC_S3 M1_DDR_DQSL_N M1_DDR_BA1 M1_DDR_BA2 M1_1_DDR_VREFDQ A11 NC_S2 M1_DDR_DQSL_P VCC1.5V_MAIN M1_DDR_VREFDQ C2 E3 ODT RESET M1_DDR_DQSL_P K2 VDD_9 BA0 VDD_7 M1_DDR_BA0 CS N3 M1_DDR_RESET_N R735 M1_DDR_A14 B10 VDDQ_1 CK 1K M1_DDR_A13 VCC1.5V_MAIN BA1 WE M1_DDR_CLKN 1000pF 0.1uF M1_DDR_A11 M1_DDR_A12 K10 VDD_9 M1_DDR_A9 M1_DDR_A10 H3 M1_DDR_ODT 1K 1% R726 1K 1% 1% 1K R727 G9 VDD_8 BA0 F8 M1_DDR_CLK M1_DDR_CLKN M1_DDR_DQSU_N G3 BA2 M1_DDR_CLKN 0 D8 VDD_7 M1_DDR_BA2 0 A10 C749 VDD_4 C734 VDD_3 A12/BC C730 VDD_2 A11 J3 M1_DDR_BA0 G9 DQS M1_DDR_DQSU_P DQS M1_DDR_DQSU_N D4 A11 N1 N11 NC_S4 C4 DQS DQS M1_DDR_CKE B8 M1_DDR_DML A8 M1_DDR_DML A2 DM/TDQS VSS_1 NF/TDQS M1_DDR_DMU VSS_3 10K VSS_4 M1_DDR_DQ0 VSS_5 M1_DDR_DQ1 VSS_6 M1_DDR_DQ2 M1_DDR_DQ0 M1_DDR_DQ3 M1_DDR_DQ1 M1_DDR_DQ4 M1_DDR_DQ6 M1_DDR_DQ5 M1_DDR_DQ7 M1_DDR_DQ6 M1_DDR_DQ4 M1_DDR_DQ7 M1_DDR_DQ3 M1_DDR_DQ8 M1_DDR_DQ2 M1_DDR_DQ9 M1_DDR_DQ5 B4 C8 C3 C9 E4 E9 D3 E8 DQ0 VSS_7 DQ1 VSS_8 DQ2 VSS_9 DQ3 VSS_10 DQ4 VSS_11 DQ5 VSS_12 F2 H2 M1_DDR_DQ14 H10 M1_DDR_DQ15 J8 VSSQ_2 VSSQ_3 NC_3 VSSQ_4 NC_4 VSSQ_5 VSS_5 F9 J2 M1_DDR_DQ10 J10 M1_DDR_DQ13 L2 M1_DDR_DQ14 L10 M1_DDR_DQ11 N2 M1_DDR_DQ15 N10 M1_DDR_DQ9 M1_DDR_DQ12 B9 NC_5 M2_DDR_A3 M2_DDR_A4 M2_DDR_A5 M2_DDR_A6 M2_DDR_A7 M2_DDR_A8 M2_DDR_A9 M2_DDR_A10 M2_DDR_A11 M2_DDR_A12 H6 E4 J4 D6 J5 D3 H4 J6 K5 D4 M2_DDR_A13 M2_DDR_A4 M2_DDR_A1 M2_DDR_A5 M2_DDR_A2 M2_DDR_A6 M2_DDR_A3 M2_DDR_A7 M2_DDR_A4 M2_DDR_A8 M2_DDR_A5 M2_DDR_A9 M2_DDR_A10 M2_DDR_A6 M2_DDR_A11 M2_DDR_A7 M2_DDR_A8 M2_DDR_A12 M2_DDR_A9 M2_DDR_A13 VCC1.5V_DE M2_DDR_CKE M2_DDR_BA1 H5 F4 M2_DDR_BA2 M2_DDR_A12 R743 M2_DDR_A13 R714 10K M2_DDR_BA0 M2_DDR_BA1 M2_DDR_BA2 M2_DDR_BA0 M2_DDR_RESET_N M2_DDR_BA1 M2_DDR_BA2 M2 M2_DDR_CLKN G6 F6 M2_DDR_ODT M2_DDR_RASN M2_DDR_CASN M2_DDR_CLK M3 M2_DDR_CKE G5 G4 F5 M2_DDR_WEN P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M2_DDR_A11 M2_DDR_CLKN M3 A2 K7 150 M2_DDR_RASN M2_DDR_CASN M2_CLKN M2_DDR_WEN M2_DDR_CASN M2_DDR_RESET_N M2_DDR_WEN M2_DDR_RESET_N M2_DDR_DQSL_P H3 M2_DDR_DQSU_P J1 M2_DDR_DQSU_N M2_DDR_DQSU_P M2_DDR_CLK R716 0 M2_CLK M2_DDR_DQSU_N M2_DDR_CLKN R717 0 M2_CLKN M2_DDR_DQSL_N M2_DDR_DQSU_P H1 M2_DDR_DQSL_P H2 M2_DDR_DQSL_N M2_DDR_DQSU_N M2_DDR_DQSL_P M2_DDR_DQSL_N M2_DDR_DML K3 M2_DDR_DML F2 M2_DDR_DMU M2_DDR_DMU M2_DDR_DML M2_DDR_DMU M2_DDR_DQ0 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15 M2_DDR_ZQCAL G2 K1 G3 K6 M2_DDR_DQ10 M2_DDR_DQ11 M2_DDR_DQ12 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15 R711 240 R718 1K 1% 0.1uF J2 M2_DDR_DQ8 M2_DDR_DQ9 M2_DDR_DQ9 1000pF F3 M2_DDR_DQ7 M2_DDR_DQ8 1% K2 M2_DDR_DQ6 M2_DDR_DQ6 M2_DDR_DQ7 C703 M2_DDR_DQ11 M2_DDR_DQ12 G1 M2_DDR_DQ5 M2_DDR_VREFDQ R719 M2_DDR_DQ10 J3 M2_DDR_VREFCA 1K M2_DDR_DQ9 M2_DDR_DQ4 M2_DDR_DQ5 C702 M2_DDR_DQ8 M2_DDR_DQ3 M2_DDR_DQ4 0.1uF M2_DDR_DQ7 L3 M2_DDR_DQ3 VCC1.5V_DE VCC1.5V_DE 1000pF M2_DDR_DQ6 E2 M2_DDR_DQ2 C701 M2_DDR_DQ5 M1 M2_DDR_DQ2 R712 M2_DDR_DQ4 E1 M2_DDR_DQ1 1K 1% M2_DDR_DQ3 L2 M2_DDR_DQ1 1% M2_DDR_DQ2 E3 M2_DDR_DQ0 R713 M2_DDR_DQ1 L1 1K M2_DDR_DQ0 C700 F1 DQ2 VSS_9 DQ3 VSS_10 DQ4 VSS_11 DQ5 VSS_12 K9 K1 J3 K3 L3 A3 M2_DDR_DQ10 M2_DDR_DQ11 M2_DDR_DQ12 M2_DDR_DQ13 M2_DDR_DQ14 M2_DDR_DQ15 F9 J2 J10 L2 L10 N2 N10 DQ6 DQ7 B3 VSSQ_1 NC_1 VSSQ_2 NC_2 VSSQ_3 NC_3 VSSQ_4 NC_4 VSSQ_5 B9 C10 D2 D10 NC_5 M2_DDR_VREFDQ VREFDQ A4 A5 A6 L8 ZQ R738 SIGN50000 VCC1.5V_DE 240 A7 A8 A9 B2 VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 VDD_6 A15 VDD_7 BA0 VDD_9 VDD_8 D9 G7 C722 C704 0.1uF 0.1uF K2 C705 0.1uF K8 C720 0.1uF N1 C721 0.1uF N9 R1 R9 BA1 A1 VDDQ_1 CK VDDQ_2 CK VDDQ_3 CKE VDDQ_4 VDDQ_5 CS VDDQ_6 ODT VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 WE RESET NC_2 NC_4 F3 DQSL A8 C1 C736 C737 0.1uF 0.1uF C9 C738 0.1uF D2 C739 0.1uF E9 C740 0.1uF F1 C741 0.1uF H2 C742 0.1uF H9 C743 C744 J1 NC_1 T2 G3 F3 H1 BA2 M2_CLKN M2_DDR_ODT M2_DDR_RASN VSS_8 VREFCA NC_3 D5 M2_DDR_RESET_N E8 DQ1 D9 A1 L2 R715 M2_DDR_ODT N8 J7 M2_CLK M2_DDR_CKE D3 VSS_7 B2 M2_DDR_VREFCA M8 A0 M2 M2_CLK M2_DDR_CKE M2_DDR_CLK N3 M7 10K E6 M2_DDR_BA0 E9 DQ0 A9 NC_6 IC702 H5TQ1G63DFR-PBC M2_DDR_A0 M2_DDR_A10 E4 J8 M2_DDR_A3 D2 E5 C9 H10 M2_DDR_A1 K4 C3 H2 M2_DDR_A0 D1 C8 F10 D10 M2_DDR_A2 M2_DDR_A2 B4 F2 D2 IC100 LG1152D-B1 M2_DDR_A1 VSS_6 A4 C10 NC_6 M2_DDR_A0 VSS_2 VSS_4 M1_DDR_DQ8 NC_2 VSS_1 VSS_3 B3 NC_1 A2 DM/TDQS NF/TDQS F3 VSSQ_1 A4 F10 M1_DDR_DQ13 A8 D9 DQ7 M1_DDR_DQ12 B8 B2 DQ6 M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DMU A9 VSS_2 R741 J9 L1 L9 T7 0.1uF 10uF 10V DDR3 1.5V bypass Cap - Place these caps near Memory C13 C12 M1_DDR_DQ0 VDD_1 A10/AP M1_DDR_A8 0.1uF D7 M1_DDR_RESET_N M1_DDR_DML N8 A3 A9 M1_DDR_A7 1000pF A9 R702 B9 R703 F11 M1_DDR_DQSU_P M1_DDR_A14 240 1% R736 D9 M1_DDR_WEN M1_DDR_DQSL_P M1_DDR_A13 N4 ZQ A7 A8 M1_DDR_A5 M1_DDR_A6 C750 M1_DDR_CASN M1_DDR_A13 A6 VCC1.5V_MAIN R721 H9 M1_DDR_A14 F7 D13 M1_DDR_RASN M1_DDR_A12 K8 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 A5 M1_DDR_CLK M1_DDR_CKE M1_DDR_ODT M8 E2 VREFDQ A3 A4 1K 1% M1_DDR_CLKN H8 M1_DDR_A11 M1_DDR_A12 A2 M1_DDR_A0 M1_DDR_A1 1% C7 M4 M1_DDR_A9 M1_DDR_A10 M1_DDR_RESET_N VDD_8 0.1uF 0.1uF G3 M1_1_DDR_VREFDQ M1_1_DDR_VREFCA M1_DDR_VREFCA R737 E10 M1_DDR_BA2 M1_DDR_CLK 10K M1_DDR_A11 J9 VREFCA 1K D8 E12 M1_DDR_BA1 M1_DDR_A8 M1_DDR_A10 C5 N9 M1_DDR_A8 M1_DDR_A9 C4 M1_DDR_A14 M1_DDR_BA0 R710 DDR3 2Gbit A0 A1 C735 D10 M3 M1_DDR_A7 M1_DDR_A7 VDD_6 C758 C746 D8 IC704 H5TQ2G83BFR-PBC 1000pF M1_DDR_A13 E7 M9 VDD_5 A14 A10 VCC1.5V_MAIN M1_DDR_VREFDQ 0.1uF M1_DDR_A12 M1_DDR_A6 E11 L3 M1_DDR_A6 A13 C4 M1_DDR_VREFCA C731 M1_DDR_A9 M1_DDR_A11 E8 L9 M1_DDR_A4 M1_DDR_A5 VCC1.5V_MAIN M1_DDR_A5 VDD_4 NC_6 C726 M1_DDR_A8 M1_DDR_A10 M1_DDR_A4 D11 K3 M1_DDR_A3 M1_DDR_A3 F8 VDD_3 A12/BC RESET J8 R728 M1_DDR_A7 M1_DDR_A2 M1_DDR_A2 F12 VDD_2 A11 WE H10 1K 1% M1_DDR_A5 M1_DDR_A6 M1_DDR_A1 F10 VDD_1 A10/AP N3 H2 D10 1% M1_DDR_A4 A9 CKE G2 F10 R729 M1_DDR_A3 A3 BA2 F2 D2 1K M1_DDR_A2 L4 A8 A4 C10 C727 M1_DDR_A1 L8 M1_DDR_A1 240 1% A7 F8 G8 VCC1.5V_MAIN R739 ZQ VSS_5 NC_5 K4 M1_DDR_A0 M1_DDR_A0 H9 A6 VSS_4 VCC1.5V_MAIN E9 A5 VSS_3 IC701 H5TQ2G83BFR-PBC C9 M1_DDR_A0 VREFDQ A4 J3 NC_6 IC100 LG1152D-B1 E2 A3 F9 VSSQ_1 VSSQ_2 M9 J9 VREFCA A2 F3 B3 NC_2 L3 D9 M0_DDR_DQ8 NC_1 L9 DDR3 2Gbit A1 NC_S3 DQ6 A4 M0_DDR_DQ12 A14 VSS_7 K3 B2 DQ7 M0_DDR_DQ11 B15 DQ0 L4 A0 N11 VSS_6 B4 M0_DDR_DQ1 M0_DDR_DQ6 A19 N1 VSS_5 M0_DDR_DQ5 M0_DDR_WEN A2 DM/TDQS VSS_4 C8 M0_DDR_CASN M0_DDR_RESET_N M0_DDR_DQSU_N NF/TDQS L8 H3 M0_DDR_ODT M0_DDR_RASN DQS VSS_3 M0_DDR_DQ0 M0_DDR_CKE M0_DDR_DQSU_P 10K M0_DDR_DQ4 0.1uF M0_DDR_CLK M0_DDR_CLKN DQS R742 M0_DDR_DQ3 M0_DDR_BA2 M0_1_DDR_VREFDQ NC_S4 M0_DDR_DQ2 B18 M0_DDR_BA1 A11 NC_S2 B8 M0_DDR_DML M0_DDR_CKE M0_DDR_DMU M0_DDR_DQ0 B19 D4 M0_DDR_DQSL_N 1000pF VCC1.5V_MAIN M0_DDR_VREFDQ ODT C4 M0_DDR_DQSL_P C747 M0_DDR_BA0 CS WE K4 VDD_7 E10 NC_S3 M0_DDR_DQSU_P 1% R731 M0_DDR_A14 E3 VDDQ_3 RESET 1K M0_DDR_A13 0.1uF CK C732 0.1uF 1000pF 1% M0_DDR_A12 C2 VDDQ_2 N3 M0_DDR_RESET_N 1K 1% 1K 1% R722 K2 K10 M0_DDR_A11 B10 VDDQ_1 M0_DDR_DQSL_N C15 E22 G4 M0_DDR_WEN M0_DDR_CLKN C16 M0_DDR_ZQCAL F4 M0_DDR_CASN 200 C20 M0_DDR_DQ6 0.1uF BA1 CKE G2 M0_DDR_ODT M0_DDR_RASN M0_DDR_DQSL_P M0_DDR_DMU M0_DDR_DQ4 G10 0.1uF C708 VCC1.5V_MAIN CK M0_DDR_A9 M0_DDR_A10 0.1uF C707 G9 VDD_9 BA0 BA2 G8 C706 G3 H3 M0_DDR_CLK R706 M0_DDR_RESET_N A20 C19 M0_DDR_DQ5 VDD_6 VDD_8 F8 M0_DDR_CLK M0_DDR_CLKN M0_DDR_CASN M0_DDR_DQSU_N M0_DDR_DQ3 M0_DDR_BA2 M0_DDR_CLKN M0_DDR_CLKN M0_DDR_WEN B16 M0_DDR_DQ2 J4 M0_DDR_RASN E21 D21 M0_DDR_DQSL_N M0_DDR_DQ1 D8 M0_DDR_ODT D22 B20 M0_DDR_DQ0 K9 M0_DDR_BA1 200 M0_DDR_CLK A10 VDD_5 A13 A14 M0_DDR_CKE E19 M0_DDR_DML VDD_4 J3 M0_DDR_BA0 M0_DDR_CKE M0_DDR_RESET_N M0_DDR_DQSU_P VDD_3 A12/BC M0_DDR_A7 M0_DDR_A8 1000pF 0 VDD_2 A11 M0_DDR_A6 C748 0 R701 F15 VDD_1 A10/AP R732 R700 A18 A9 M0_DDR_A5 1K 1% A17 A3 VDD_7 R705 M0_DDR_BA2 M0_DDR_WEN M0_DDR_DQSL_P N8 M0_DDR_A3 1% F17 F21 M0_DDR_ODT M0_DDR_CASN M0_DDR_A13 M0_DDR_A14 M0_DDR_BA1 M0_DDR_CKE M0_DDR_RASN N4 A8 R733 M0_DDR_CLK K8 240 1% A7 M0_DDR_CLK M0_DDR_BA0 D15 M0_DDR_BA2 M0_DDR_CLKN M8 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14 D16 H8 M0_DDR_A11 M0_DDR_A12 F18 F20 M0_DDR_BA1 M0_DDR_A9 M0_DDR_A10 M0_DDR_RESET_N M0_DDR_A11 D17 M0_DDR_A14 M0_DDR_BA0 10K M0_DDR_A10 E14 M4 ZQ C728 M0_DDR_A9 D14 N9 M0_DDR_A8 H9 A6 VCC1.5V_MAIN R720 1K M0_DDR_A12 M0_DDR_A13 R709 M0_DDR_A2 M0_DDR_A4 A5 0.1uF M0_DDR_A11 M0_DDR_A7 M0_DDR_A8 D19 VREFDQ A4 1000pF M0_DDR_A9 M0_DDR_A10 M0_DDR_A7 E15 M3 E2 A3 M0_DDR_A0 M0_DDR_A1 C729 M0_DDR_A8 M9 M0_DDR_A6 A2 R723 M0_DDR_A7 L3 M0_DDR_A5 VCC1.5V_MAIN M0_DDR_A6 F19 L9 M0_DDR_A4 M0_DDR_A5 F16 K3 M0_DDR_A3 M0_DDR_A4 D20 L4 M0_DDR_A2 M0_DDR_A3 E16 M0_1_DDR_VREFDQ M0_1_DDR_VREFCA M0_DDR_VREFCA 1K M0_DDR_A6 M0_DDR_A2 E20 J9 VREFCA C724 M0_DDR_A5 A0 A1 R724 M0_DDR_A4 L8 M0_DDR_A1 1% M0_DDR_A3 K4 M0_DDR_A0 M0_DDR_A1 E18 R725 M0_DDR_A2 M0_DDR_A0 E17 1K M0_DDR_A1 M0_1_DDR_VREFCA VCC1.5V_MAIN M0_DDR_VREFDQ C725 M0_DDR_A0 DDR3 2Gbit 1K 1% D18 C733 IC100 LG1152D-B1 NC_6 DQSL C7 B7 A9 DQSU VSS_1 DQSU VSS_2 VSS_3 E7 D3 DML VSS_4 DMU VSS_5 VSS_6 E3 F7 F2 F8 H3 H8 G2 H7 DQL0 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 VSS_12 C2 A7 A2 B8 A3 G8 J2 J8 M1 M9 P1 P9 T1 T9 B1 VSSQ_1 D7 C8 E1 DQL6 DQL7 C3 B3 DQU0 VSSQ_2 DQU1 VSSQ_3 DQU2 VSSQ_4 DQU3 VSSQ_5 DQU4 VSSQ_6 DQU5 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 B9 D1 D8 E2 E8 F9 G1 G9 1% THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LG1152 B0 MAIN DDR 4 50 LGE Internal Use Only +5V_CI_ON CI HOST I/F 5V <=> 3.3V CI_DATA[0-7] R6209 10K OPT +3.3V_NORMAL 35 1 GND 36 2 DAT3 CI_DATA[3] 37 3 DAT4 CI_DATA[4] TS_OUT4 38 4 DAT5 CI_DATA[5] CI_TS_DATA[4] R6206 10K OPT R6204 10K OPT CI_TS_DATA[5] CI_TS_DATA[6] CI_TS_DATA[7] /PCM_CE2 CI_VS1 /PCM_IORD /PCM_IOWR R6249 0 OPT PCM_RST /PCM_WAIT CI_DATA[6] DAT6 TS_OUT7 41 7 /CARD_EN1 CI_DATA[7] CI R6224 42 8 ADDR10 VS1 43 9 /O_EN IORD 44 10 ADDR11 11 ADDR10 12 ADDR8 CI_IN_TS_DATA[0] TS_IN0 47 13 ADDR13 CI_IN_TS_DATA[1] TS_IN1 48 14 ADDR14 CI_IN_TS_DATA[2] TS_IN2 49 15 /WR_EN CI_IN_TS_DATA[3] TS_IN3 50 16 /IRQA VCC 51 17 VCC 0 OPT VPP 52 18 VPP TS_IN4 53 19 TS_IN_VAL CI_IN_TS_DATA[5] TS_IN5 54 20 TS_IN_CLK CI_IN_TS_DATA[6] TS_IN6 55 21 ADDR12 CI_IN_TS_DATA[7] CI_TS_CLK PCM_INPACK DAT6 6 46 R6213 R6207 10K CI 5 45 CI_IN_TS_DATA[4] R6205 10K OPT 39 40 IOWR +5V_CI_ON R6211 10K OPT TS_OUT5 TS_IN_SYN CI_IN_TS_DATA[0-7] DIR TS_OUT6 CARD_EN2 TS_IN7 56 22 ADDR7 TS_OUT_CLK 57 23 ADDR6 22 CI_ADDR[10] CI_ADDR[11] CI_ADDR[11] CI_ADDR[9] CI_ADDR[8] CI_ADDR[13] CI_ADDR[13] CI_ADDR[14] R6243 C6205 0 0.1uF CI CI C6206 0.1uF 16V CI_ADDR[14] CI_ADDR[7] CI_ADDR[6] CI_ADDR[5] 24 ADDR5 25 ADDR4 CI_ADDR[4] 60 26 ADDR3 CI_ADDR[3] REG 0 CI TS_OUT_VAL 61 27 ADDR2 62 28 ADDR1 TS_OUT_SYN 63 29 ADDR0 TS_OUT0 64 30 DAT0 CI_DATA[0] TS_OUT1 65 31 DAT1 CI_DATA[1] TS_OUT2 66 32 DAT2 CI_DATA[2] R6215 CI 100 /CI_DET2 GND 67 33 /IO_BIT 68 34 GND PCM_INPACK /PCM_CE2 R6210 0 G2 69 33 CI AR910 A4 A5 R6217 CI_ADDR[12] A6 CI_ADDR[7] A7 CI_ADDR[5] CI_ADDR[2] CI_ADDR[0] 2 19 3 18 4 17 VCC CI 16V 0 R913 OE /PCM_CE1 5 B0 16 CI 6 15 EB_DATA[0] B1 EB_DATA[1] B2 EB_DATA[2] B3 EB_DATA[3] B4 7 14 EB_DATA[4] B5 8 13 EB_DATA[5] 9 12 B6 EB_DATA[6] B7 EB_DATA[7] CI_ADDR[6] 58 CI_TS_DATA[2] /CI_CD2 CI_DATA[4] CI_DATA[7] CI_ADDR[12] 59 CI_TS_SYNC CI_DATA[3] CI_DATA[6] CI_ADDR[1] 20 CI_DATA[5] INPACK CI_TS_DATA[1] A1 A3 OPT CI_WAIT CI_TS_DATA[0] CI_DATA[2] R6246 10K OPT /PCM_IRQA CI_RESET CI_VS1 A0 1 CI_DATA[1] /PCM_WE 22 CI R6212 33 CI_DATA[0] CI AR909 A2 R6244 10K CI 22 OPT 22 CI 22 OPT /PCM_REG +5V_CI_ON CI_ADDR[9] CI_ADDR[8] R6203 CI_TS_VAL R6245 10K OPT /PCM_OE R6202 R6200 DIR +5V_CI_ON CI_ADDR[10] R6216 IC904 74LVC245A /PCM_CE1 GND 100 /CI_DET1 CI TS_OUT3 EB_DATA[0-7] R6214 /CI_CD1 CI_TS_DATA[3] R6219 10K OPT OPT P6200 10067972-000LF CI C904 R6208 10K OPT 0.1uF +5V_CI_ON C6201 10uF 10V CI CI_DATA[0-7] C6200 0.1uF CI CI_ADDR[4] CI_DATA[0-7] CI_ADDR[3] GND CI_ADDR[2] 10 11 CI_ADDR[1] CI_ADDR[0] EB_DATA[0-7] +5V_CI_ON 10K +3.3V_NORMAL OPT IC905 74LVC1G00GW G1 OPT 1 A 2 GND 3 5 VCC IOWE=>IORD 4 Y C903 CI 16V /PCM_IORD CI_IN_TS_SYNC 0.1uF CI_IN_TS_VAL CI_IN_TS_CLK B /PCM_OE WE=>OE DIR CI AND GATE => NAND GATE 33 TPO_DATA[1] CI_IN_TS_DATA[1] TPO_DATA[2] CI_IN_TS_DATA[2] TPO_DATA[3] CI_IN_TS_DATA[3] TPO_DATA[4] CI_IN_TS_DATA[6] TPO_DATA[7] 33 TPO_VAL CI_ADDR[13] EB_ADDR[13] EB_ADDR[2] CI_ADDR[14] EB_ADDR[14] CI_ADDR[3] EB_ADDR[3] 33 EB_ADDR[5] EB_ADDR[6] CI_ADDR[7] EB_ADDR[7] CI_ADDR[8] CI_IN_TS_SYNC CI_IN_TS_VAL EB_ADDR[4] CI_ADDR[5] 33 EB_ADDR[11] BUFFER FOR 5V => 3.3V IC903 74LVC16244ADGG +5V_NORMAL 10K 10K R916 CI R915 CI 1A1 /PCM_IRQA GND_8 1A2 /CI_CD2 1A3 /CI_CD1 VCC_4 CI C905 0.1uF 16V CI C906 0.1uF 16V 2A0 AR921 CI 2A1 PCM_INPACK GND_7 CI_TS_CLK CI_TS_VAL 100 CI_TS_SYNC 2A2 2A3 3A0 AR920 CI 3A1 CI_TS_DATA[7] GND_6 CI_TS_DATA[6] CI_TS_DATA[5] CI_TS_DATA[4] 100 3A2 3A3 VCC_3 4A0 AR919 CI 4A1 CI_TS_DATA[3] GND_5 CI_TS_DATA[2] CI_TS_DATA[1] CI_TS_DATA[0] 100 4A2 4A3 3OE EB_OE_N EB_WE_N EB_BE_N1 /PCM_IORD /PCM_IOWR EB_BE_N0 EB_ADDR[9] EB_ADDR[10] CI_ADDR[11] /PCM_WAIT CI AR914 /PCM_WE EB_ADDR[8] CI_ADDR[9] 1A0 33 /PCM_OE CI AR913 CI_ADDR[10] 2OE CAM_REG_N /PCM_REG CI AR912 CI_ADDR[6] CI_IN_TS_CLK TPO_ERR EB_ADDR[12] EB_ADDR[1] CI_ADDR[2] CI AR903 TPO_SOP CI AR915 CI_ADDR[1] CI_ADDR[4] CI_IN_TS_DATA[7] AR905 CI 33 33 CI_ADDR[12] CI_IN_TS_DATA[5] TPO_DATA[6] CI AR911 EB_ADDR[0] CI_IN_TS_DATA[4] TPO_DATA[5] TPO_CLK 33 CI_ADDR[0] CI_IN_TS_DATA[0] 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 36 35 12 CI 13 14 34 15 33 16 32 17 31 18 30 19 29 20 28 21 27 22 26 23 25 24 1OE +3.3V_NORMAL C900 CI AR904 TPO_DATA[0] 0.1uF TPO_DATA[0-7] CI 16V 1Y0 1Y1 CAM_WAIT_N CAM_IREQ_N GND_1 1Y2 1Y3 VCC_1 CAM_CD2_N CAM_CD1_N TPI_CLK 2Y0 CAM_INPACK_N TPI_VAL 2Y1 CI GND_2 TPI_SOP 2Y2 AR918 75 2Y3 3Y0 TPI_DATA[7] 3Y1 TPI_DATA[6] GND_3 3Y2 TPI_DATA[5] 3Y4 TPI_DATA[4] VCC_2 75 CI AR917 4Y0 TPI_DATA[3] 4Y1 TPI_DATA[2] GND_4 4Y2 TPI_DATA[1] 4Y3 TPI_DATA[0] 4OE AR916 75 CI THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only C2307 0.1uF 16V 6 GND GND GND 7 8 9 10 3.5V 3.5V 11 12 3.5V 13 14 GND GND C2317 0.1uF 50V GND 15 16 GND/V-sync 12V 17 18 INV ON 12V 19 20 A.DIM 12V 21 22 P.DIM1 GND/P.DIM2 23 24 Err OUT L2302 +3.3V_NORMAL R2330 1K LPB R2302 100 INV_CTL POWER_DET RESET 2 1 GND C2365 0.1uF 16V PD_24V R2372 100K +24V not to RESET at 8kV ESD Q2304 MMBT3904(NXP) R2341 10K A_DIM 3 C2359 0.1uF 16V PD_+12V R2363 1.2K 1% C2346 0.1uF 50V R2376 10K OPT IC2307 D G C B PANEL_CTL R2312 100 L/DIM0_VS C2335 0.1uF 50V OPT C2339 OPT 1uF 25V 4 C2332 10uF 16V R2344 5.6K 5 3.5V CIS21J121 C2306 0.1uF 50V GND 24V L2305 CIS21J121 +3.5V_ST NCP803SN293 VCC S R2343 33K 2 3 L2303 BLM18SG121TN1D 24V R2373 100K PD_+3.5V R2366 0 5% Q2305 AO3407A OPT P2301 FW20020-24S 2 +3.5V_ST PD_+12V R2362 2.7K 1% PANEL_VCC C2328 0.1uF 50V C2326 0.01uF 50V +24V +12V +12V TYP 1450mA L2311 PWR ON 1 24V 3 +3.5V_ST Power_DET CIS21J121 Q2301 1 MMBT3906(NXP) 10K R2306 R2305 10K RL_ON PANEL_POWER +12V +3.5V_ST PD_24V IC2308 PD_24V R2364 8.2K 1% E PWM_DIM NCP803SN293 VCC PD_24V R2365 1.5K 1% 25 SMAW200-H24S2 C2360 0.1uF 16V PD_24V 3 RESET 2 1 24V-->3.48V 12V-->3.58V ST_3.5V-->3.5V GND +5V_Normal 1 +12V +5V_NORMAL MAX 1A L2310 BLM18PG121SN1D R2304 0 ERROR_OUT Tuner 1.25V REG Input LG1152 Max: 1728 mA LG1132 Max: 2000 mA R2301 10K POWER_ON/OFF1 EN 1 1% R1 VFB 2 R2308 C2371 0.1uF 16V 56K L2306 BLM18PG121SN1D VREG5 C2334 100pF 50V L2314 BLM18PG121SN1D [EP]PGND 3 7 6 VIN2 VIN VIN1 C2345 VBST 0.1uF 16V SW 14 C2354 10uF 16V L2313 6.8uH VBST R2311 10K R2 3A 5 GND C2303 0.1uF 50V R2322 22K 1% VREG5 3 4A 11 4 10 5 C2318 1uF 10V SS PGND2 PGND1 9 6 8 7 GND R2310 10K POWER_ON/OFF2_3 L2316 2uH 293 mA IC2300 AP7173-SPG-13 HF(DIODES) R2 R2315 100 1% POWER_ON/OFF2_2 R2334 10K 9 3 4 R2347 4.3K R1 1% SS 6 C2340 10uF 10V 1.5A C2324 10uF 10V EN 4 GND 5 C2331 2200pF 50V R2346 2K 1% R2 C2344 0.1uF 16V Vout=0.8*(1+R1/R2) IC2305 Vout=0.8*(1+R1/R2) DDR MAIN 1.5V 1074 mA POWER_ON/OFF2_3 C2310 0.1uF 16V R2318 10K POWER_ON/OFF2_1 PH_1 SS/TR C2329 R2342 1/16W 330K 5% 1/16W 5% 1/16W 1% VIN VSENSE NR8040T3R6N C2333 22uF 10V PVIN_2 R1 L2312 3.6uH C2341 0.1uF 16V C2337 22uF 10V 0.01uF 50V R2340 15K R2 4 11 5 10 6 9 7 8 0.1uF 16V PH_2 L2317 R1 R2 PH_1 C2302 4.7uF 16V C2350 22uF 10V C2338 100pF 50V C2363 22uF 10V OPT C2370 10uF 10V EN SS/TR COMP 50V PH_2 3A 12 +0.9V_VDD C2349 R2357 C2374 4 3 BOOT 22000pF GND_2 C2375 180pF 50V R2378 6.8K PWRGD 11 IC2302 10 TPS54319TRE 9 THERMAL 17 13 1K POWER_ON/OFF2_3 1/16W 5% 2 3 +1.5V_DDR BOOT 13 14 15 EN VIN_3 VIN_2 GND_1 2 14 C2373 C2320 10uF 10V C2347 10uF 16V 1/16W 1% R2319 R1 1 PWRGD 4700pF C2311 2200pF 50V C2353 3300pF 50V OPT 1.5K 1% C2352 10uF 10V 7 R2317 20K C2316 10uF 10V 8 COMP C2314 10uF 10V COMP 6A EN C2312 10uF 10V 6 5 OPT R23160 PH_3 5 6 4 NC_1 C2327 0.1uF 12 AGND 3 NC_2 1/16W 1% 9 7 R2382 30K FB 8 1% C2309 0.1uF 16V OPT ADUC 20S 02 010L D2350 C2304 10uF 16V 2 R2320 10K AGND C2300 10uF 16V 1 THERMAL VIN GND_1 Max 5926 mA [EP]GND 1uH 16V 1 VSENSE VIN_1 [EP]LX *NOTE 17 PGND Placed on SMD-TOP EP[GND] L2308 16 IC2301 AOZ1038PI CIS21J121 L2307 OPT L2300 BLM18PG121SN1D L2304 2uH CIS21J121 L2318 +12V 1/16W 5% PVIN_1 0.1uF 16V +3.5V_ST R2379 12K +3.3V_NORMAL RT/CLK GND_2 +0.9V_VDD C2325 R2349 10K R2339 +3.3V_NORMAL 4.7 A RT/CLK MAX L2315 R2377 100K R2381 0 4 47K 1% 2 EAN62348501 +12V R2307 C2308 2200pF 50V 1.5A FB 7 50V GND 2 VCC C2348 5 PG +5V_NORMAL R2314 3K 1% OUT 47pF 4 POWER_ON/OFF1 C2313 10uF 10V 3.9K R2321 SS C2315 0.1uF 16V 8 1 R1 1.3K 6 IN 1% 1/16W FB 50V EN 3 7 15 R2300 10K 2 Vout=0.765*(1+R1/R2) OUT THERMAL VCC 8 1 9 PG C2301 4.7uF 10V THERMAL IN 700 mA [EP] +3.3V_NORMAL C2369 22uF 10V +2.5V_NORMAL IC2303 AP7173-SPG-13 HF(DIODES) +1.8V_NORMAL [EP] L2301 BLM18PG121SN1D C2368 22uF 10V +2.5V THERMAL +3.5V_ST C2321 22pF 50V +1.0VDC EN 3. soft start +1.8V R2313 9.1K 1% C2319 3300pF 50V R2309 100K PG C2305 0.1uF OPT 1 OPT R1 SW1 Vout=0.765*(1+R1/R2) Switching freq: 700K R2 VFB 2 12 SW2 C2343 22uF 10V C2342 2200pF 50V C2336 1uF 10V 1% 4 VO 1 13 NR8040T4R7N SS C2372 0.1uF 16V 8 9 EMMC_VCCQ THERMAL R2348 10K +3.3V_TU L2319 BLM18PG121SN1D IC2306 TPS54425PWPR POWER_ON/OFF2_1 OPT +3.3V_TU_IN 3.3V_EMMC +1.8V_NORMAL L2309 BLM18PG121SN1D IC2304 TPS54327DDAR [EP]GND THERMAL +3.3V_NORMAL +1.0V_VDD +12V C2322 10uF 16V eMMC POWER 4 15 PWM_DIM2 P2300 C2330 4700pF 50V R2 Vout=0.6*(1+R1/R2) Switching freq: 400 ~ 580 Khz R2350 56K 1/16W 1% Vout=0.8*(1+R1/R2) THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 3A $ 0.145 Vout=0.827*(1+R1/R2)=1.521V LG1152 POWER LGE Internal Use Only Renesas MICOM +3.3V_NORMAL R3035 4.7K OPT For Debug 12V_EXT_PWR_DET 10K HDMI_WAUP:HDMI_INIT R3000 +3.5V_ST GND +3.5V_ST MICOM_RESET 22 (GP3_Soft touch) MHL MODEL_OPT_6 NON_GED GED P120/ANI19 KEY1 MODEL1_OPT_1 10K OPT SIDE_HP_MUTE MODEL1_OPT_4 MODEL1_OPT_3 24 23 22 P27/ANI7 21 25 20 12 19 P26/ANI6 18 26 17 R3036 MODEL1_OPT_0 27 16 +3.3V_NORMAL MODEL1_OPT_2 11 15 10K OPT POWER_ON/OFF2_1 10 For Sample Set P147/ANI18 P146 P10/SCK00/SCL00 P13/TXD2/SO20 P12/SO00/TXD0/TOOLTXD 10K P14/RXD2/SI20/SDA20 P15/PCLBUZ1/SCK20/SCL20 For JAPAN P16/TI01/TO01/INTP5 For China P17/TI02/TO02 P51/INTP2/SO11 R3019 3.3K (GP4_TOOL) NON_MHL R3037 KEY2 P70/KR0/SCK21/SCL21 PDP MODEL_OPT_5 SCART_MUTE For Japan:LNB_INIT POWER_ON/OFF2_4 P25/ANI5 MODEL1_OPT_4 MODEL1_OPT_5 +3.3V_NORMAL RL_ON P71/KR1/SI21/SDA21 IR Wafer 10Pin 37 P24/ANI4 9 P11/SI00/RXD0/TOOLRXD/SDA00 12/15Pin MODEL1_OPT_3 P41/TI07/TO07 28 POWER_ON/OFF2_3 MICOM 8 R3022 MODEL_OPT_4 MODEL1_OPT_2 P40/TOOL0 P23/ANI3 R5F100GEAFB 13 MODEL1_OPT_1 IR Wafer 38 29 IC3000 P50/INTP1/SI11/SDA11 MICOM_DIIVA R3012 10K MICOM_JAPAN R3009 10K MICOM_TOUCH_KEY R3007 10K MICOM_PDP R3005 10K MICOM_GP4_10PIN R3030 10K MICOM_MHL R3020 10K MICOM_GED R3016 10K MODEL_OPT_3 MODEL1_OPT_0 39 P22/ANI2 7 1 TOUCH_KEY R3024 P21/ANI1/AVREFM 30 6 P74/KR4/INTP8/SI01/SDA01 +3.5V_ST LCD / OLED RESET 31 1 P75/KR5/INTP9/SCK01/SCL01 MICOM MODEL OPTION MODEL_OPT_2 40 P20/ANI0/AVREFP +3.5V_ST TACT_KEY P124/XT2/EXCLKS 32 P30/INTP3/RTC1HZ/SCK11/SCL11 NON JAPAN 41 5 MODEL1_OPT_6 MODEL_OPT_1 42 P31/TI03/TO03/INTP4 EEPROM_SDA DIVA 43 P130 P72/KR2/SO21 JAPAN 44 33 P73/KR3/SO01 NON DIVA REGC 4 POWER_ON/OFF2_2 MODEL_OPT_0 45 P63 HDMI_CEC 0 46 P01/TO00/RXD1 IR MICOM MODEL OPTION 47 34 PANEL_CTL EEPROM_SCL 48 35 P62 MODEL1_OPT_5 R3018 3.3K SCART_MUTE 3 22 AMP_RESET_BY_MICOM SOC_RESET COMMERCIAL_12V_CTL 12V_EXT_PWR_DET 2 R3003 POWER_ON/OFF2_4 EXT_AMP_MUTE EXT_AMP_RESET P00/TI00/TXD1 I2C_SDA3 POWER_ON/OFF2_3 3 P140/PCLBUZ0/INTP6 P61/SDAA0 AMP_RESET_N POWER_ON/OFF2_3 1 4 36 P60/SCLA0 I2C_SCL3 POWER_ON/OFF2_2 2 POWER_ON/OFF2_4 POWER_ON/OFF! POWER_ON/OFF2_1 C3004 0.1uF 16V 10K 14 GP4 High/MID Power SEQUENCE R3033 VSS R3032 10K AMP_RESET_BY_MICOM VDD +3.3V_NORMAL P121/X1 C3001 C3000 0.1uF 13 P123/XT1 12 P137/INTP0 11 P122/X2/EXCLK 0.47uF 10 MICOM_RESET_SW SW3000 JTP-1127WEM 270K OPT 7 8 10K 6 9 LOGO_LIGHT MICOM_DEBUG +3.5V_ST 4.7M OPT R3026 MICOM_DEBUG R3023 R3027 4 MICOM_DIIVA R3025 22 for DiiVA 3 32.768KHz LOGO_LIGHT 2 MICOM_DIIVA R3001 22 MICOM_DIIVA R3002 22 X3000 1 5 C3003 /RST_DIIVA POD_WAKEUP_N FLG_POD_DR MICOM_RESET C3002 /RST_DIIVA R3014 1K P3000 12507WS-12L R3011 10K MICOM_DEBUG MICOM_DEBUG 8pF 8pF FLG_POD_DR POD_WAKEUP_N GP4_HIGH Eye Sensor Option EXT_AMP_RESET EXT_AMP_MUTE AMP_MUTE SOC_RX INV_CTL SOC_TX SOC_RESET POWER_DET LED_B/GP4_LED_R R3034 4.7K OPT COMMERCIAL_12V_CTL MICOM_NON_DIIVA R3013 10K MICOM_NON_JAPAN R3010 10K MICOM_TACT_KEY R3008 10K +3.3V_NORMAL MICOM_LCD/OLED R3006 10K MICOM_GP3_12/15PIN R3031 10K MICOM_NON_MHL R3021 10K MICOM_NON_GED R3017 10K MODEL1_OPT_6 For CEC POWER_ON/OFF1 EDID_WP +3.5V_ST C MODEL_OPT_4 0 1 E MODEL_OPT_2 N/A R3029 120K R3028 27K MC8101_ABOV (TACT_KEY) G 0 Q3000 MMBT3904(NXP) EDID_WP B D3000 CEC_REMOTE BAT54_SUZHO Q3001 RUE003N02 HDMI_CEC_FET_ROHM Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes S D THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI_CEC S CM3231_CAPELLA (GP4 Soft touch) D CM3231_CAPELLA (GP3 Soft touch) G 1 Q3001-*1 SI1012CR-T1-GE3 HDMI_CEC_FET_VISHAY 2011.11.21 MICOM 30 LGE Internal Use Only R1X2N 7 R1X2P 8 220K R3206 62K R3201 1/10W 3 2 1 ARC TX2P TX2N TX1P TX1N TX0P TX0N TXCP TXCN TCVDD12 TPVDD12 R0XCN R0XCP R0X0N R0X0P R0X1N R0X1P R0X2N R0X2P AVDD12_3 VDD12_3 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 VDD33_2 43 44 CBUS_HPD4 42 DSDA4 DSCL4 41 R3PWR5V 40 39 DSCL3 CBUS_HPD3 38 DSDA3 36 37 R1PWR5V CBUS_HPD1 35 DSCL1 33 32 34 DSDA1 R0PWR5V CBUS_HPD0 30 29 31 DSCL0 DSDA0 R4X0N SPDIF_OUT_ARC R3221 10 OPT IN DDC_SDA_3 3 2 OUT L3203 VDD12_3 10K R3202 WKUP 51 LPSBV R3X2N 17 50 PWRMUX_OUT R3X2P 18 49 SBVCC5 AVDD12_2 19 48 R5PWR5V[VGA] VDD33_1 20 47 DSCL5[VGA] R4XCN 21 46 DSDA5[VGA] R4XCP 22 45 R4PWR5V HDMI_WKUP R3216 10 RGB_5V R3242 10 RGB_DDC_SCL RGB_DDC_SDA C3209 0.1uF 16V 44 43 42 DSCL4 DSDA4 41 R3PWR5V 40 39 DSCL3 10K R3203 52 16 10K R3244 67 TX2P ARC 68 69 TX1P TX1N TX2N 70 71 72 TX0N TX0P 73 74 TXCN TXCP 75 76 77 TCVDD12 TPVDD12 78 R0XCN 79 80 R0XCP R0X0N 81 82 R0X0P R0X1N 83 84 15 Device Address : 0XB0 +3.3V_NORMAL 1/16W R3213 5.1K 5% CBUS_HPD4 R3204 0 R3205 0 L3201 GND MHL_DET +3.5V_ST +5V_NORMAL 14 CBUS_HPD3 5V HDMI_S/W_RESET R3X1P BLM18PG121SN1D IC3200 AZ1117BH-1.2TRE1 I2C_SDA5 R3X1N 5V_HDMI_3 HDMI_HPD_3 R0X1P 53 CD_SENSE0 23 C3210 0.1uF 16V C3211 0.1uF 16V R0X2N CD_SENSE1 13 33 I2C_SCL5 R3X0P 38 D2+_HDMI3 R0X2P 54 12 R3X0N 37 +3.3V_NORMAL AVDD12_3 55 GPIO2 FHD DSDA3 HDMI2 D1+_HDMI3 85 88 CD_SENSE3 R3XCP R1PWR5V D0-_HDMI3 HDMI_INT CD-SENSE4 11 SPDIF_OUT 33 56 R3XCN 36 D2+_HDMI2 R3211 GPIO0 35 CK+_HDMI3 D2+ INT 57 10 IC3201 SII9587CNUC 34 D2_GND 64 58 9 VDD12_1 DSCL1 CK-_HDMI3 OPT R3224 33 59 8 AVDD12_1 CBUS_HPD1 D2-_HDMI2 SPDIF_IN GPIO1 33 HDMI3 D2- RSVDL 65 60 7 R1X2P 32 DDC_SCL_4 66 TPWR DSDA1 D2+_HDMI2 DDC_SDA_4 +3.3V_NORMAL 33 C3221 C3215 0.1uF 16V C3212 1uF 10V C3222 10uF 10V C3218 10uF 10V 1uF 10V 1 DDC_SCL_3 NC GND/ADJ CE_REMOTE CEC_REMOTE CK- C3200 10uF 10V C3203 10uF 10V C3201 10uF 10V OPT R3215 33 C3216 10uF 10V C3206 0.1uF 16V 12V_EXT_PWR_DET HDMI_WKUP CK-_HDMI3 R3212 CK_GND 33 MHL_DET CK+ CK+_HDMI3 D0D0-_HDMI3 D0_GND C3204 0.1uF 16V C3207 0.1uF 16V C3217 0.1uF 16V DDC_SCL_4 DDC_SDA_4 DDC_SCL_3 DDC_SDA_3 HDMI_HPD_4 HDMI4 DDC_SCL_2 Vout=0.8*(1+R1/R2) HDMI_HPD_3 D1+_HDMI3 D2- HDMI_HPD_2 D1-_HDMI3 D1+ DDC_SDA_2 D0+_HDMI3 D1D1_GND DDC_SCL_1 D0+ HDMI_HPD_1 4 R4PWR5V 33 DDC_SDA_1 5 DSDA5[VGA] 45 R3214 D2+_HDMI4 6 46 RESET_N D2-_HDMI4 7 21 22 61 D1+_HDMI4 8 DSCL5[VGA] R4XCN R4XCP 6 D1+_HDMI2 HP_DET 9 47 R1X1P R0PWR5V DDC_SCL_3 20 11 10 20 R3237 31 DDC_SDA_3 C3205 10uF 10V 12 R5PWR5V[VGA] VDD33_1 R3236 CBUS_HPD0 D2-_HDMI2 BLM18PG121SN1D 13 SBVCC5 48 CSDA 30 R3229 D2-_HDMI3 14 49 CSCL R1X2N 47K L3200 15 18 19 62 DSCL0 R3226 47K D1-_HDMI2 D1+ DDC_DATA PWRMUX_OUT R3X2P 63 29 47K D1_GND DDC_CLK 50 5 DSDA0 D1+_HDMI2 R3220 D1- RSD-105156-100 16 17 4 28 D0+_HDMI2 R3218 47K D1-_HDMI3 17 LPSBV R3X2N R1X1N VDD12_2 D0+ D0+_HDMI3 18 WKUP 51 R1X0P R4X2P D0_GND 3 27 D1-_HDMI2 JK3200 19 52 16 16V 0.1uF C3225 C3224 0.1uF 16V THERMAL 89 R4X2N D0+_HDMI2 D3205 2 26 D3203 D0-_HDMI2 1 R1XCP R1X0N D0-_HDMI2 A2 D3201 D0- R1XCN R4X1P CK+_HDMI2 CK-_HDMI2 +3.5V_ST CK+_HDMI2 CK_GND CK+ HDMI2 +5V_NORMAL 5V_HDMI_4 25 +5V_NORMAL 5V_HDMI_3 CK-_HDMI2 A1 CEC_REMOTE 86 [EP]GND C CE_REMOTE CK- BODY_SHIELD CD_SENSE0 15 R3X1P D3204 L3202 A1 C DDC_SCL_2 R4X1N 1 DDC_SDA_2 DDC_SCL_2 NC D1-_HDMI4 2 47K DDC_SCL_1 D0+_HDMI4 3 R3228 47K R4X0N 4 R3225 D0-_HDMI4 6 5 DDC_SDA_1 CK+_HDMI4 7 DDC_CLK 47K DDC_SDA_2 CK-_HDMI4 8 R3209 0 R3210 0 DDC_DATA C 9 R3217 47K GND A2 11 10 53 D3202 R3219 A1 12 HDMI4 With MHL 5V C 13 MHL_DET A2 14 14 +5V_NORMAL 5V_HDMI_2 HDMI_HPD_2 A1 15 B Q3200 HDMI S/W OUTPUT A2 A1 5V_HDMI_2 C 16 C MMBT3904(NXP) E D3200 17 C C3223 0.047uF 25V HDMI_RX2+ D3207 D2+_HDMI4 JK3203 20 18 1/16W 5% HDMI_RX2- D2+ +5V_NORMAL 5V_HDMI_1 HP_DET HDMI1 B A2 HDMI1 With ARC RSD-105156-100 E MMBT3906(NXP) Q3201 R3247 10K R3243 1K HDMI_RX1- D2-_HDMI4 HDMI_RX1+ D1+_HDMI4 D2D2_GND HDMI_RX0- D1+ RSD-105156-100 JK3202 19 CD_SENSE1 R3X0P R3X1N +3.5V_ST HDMI_RX0+ 1 D2+_HDMI1 BODY_SHIELD GPIO2 54 D1_GND VDD33_2 1 CD_SENSE3 55 D1-_HDMI4 HDMI_CLK- D2+ CD-SENSE4 12 D0+_HDMI4 D1- 87 2 2 GPIO0 57 D0+ HDMI_CLK+ D2_GND GPIO1 58 MHL_DET CK-_HDMI1 3 D2-_HDMI1 TPWR 59 A2 D0-_HDMI1 4 D1+_HDMI1 D2- D0_GND RESET_N 60 A1 C CK+_HDMI1 D1+ D0-_HDMI4 10K R3245 D0+_HDMI1 5 D0- 5% 1/16W EN D1-_HDMI1 6 D1_GND 3 5 D1+_HDMI1 D0+_HDMI1 4 6 ILIM_SEL D2-_HDMI1 7 D1-_HDMI1 5 4 D2+_HDMI1 8 D1- 6 7 5% 1/16W 9 CK+_HDMI4 ILIM1 24 7 3 R4X0P D0+ OPT C3226 0.1uF 16V CK+ Limit 0.8A D0-_HDMI1 D0_GND 8 10V 11 10 CK_GND 62K R3200 CK+_HDMI1 D0- 9 SPDIF_OUT_ARC CEC_REMOTE CK-_HDMI4 OPT C3202 1uF CK+ EAG62611201 12 ILIM0 CE_REMOTE CK- 1/10W OPT R3248 1K CK-_HDMI1 CK_GND 13 ARC Limit 0.8A CEC_REMOTE OPT R3249 3.9K EAG62611201 14 CE_REMOTE 11 10 8 CSDA 61 AVDD12_2 C3208 0.1uF IN_2 CSCL 62 13 NC CK- 12 DDC_SCL_4 15 ARC 13 OUT_1 INT 63 R3X0N VDD12_2 DDC_SCL_1 15 14 DDC_CLK SPDIF_IN 64 56 27 16 0 RSVDL 65 11 28 R3208 DDC_CLK 30V 2 R3246 10K 16 DDC_SDA_4 9 IN_1 R3XCN 66 R3XCP R4X2P DDC_SDA_1 DDC_DATA +5V_NORMAL 10 26 0 OUT_2 GND 9 VDD12_1 25 R3207 DDC_DATA R3222 0 R3223 0 1 IC3201-*1 SII9587CNUC-3 23 17 17 D3206 MBR230LSFT1G GND 10 THERMAL 89 24 GND FAULT 5V THERMAL 18 5V_HDMI_4 86 [EP]GND 5 6 R4X1P 19 5V 18 EAG62611201 4 R1X1N R1X1P R4X2N HDMI_HPD_1 HDMI_HPD_4 11 HP_DET 5.6V 19 EAG62611201 2 3 R1X0P AVDD12_1 HP_DET 1 R1XCP R1X0N R4X1N [EP] 20 20 IC3202 TPS2554 R4X0P BODY_SHIELD 87 UD R1XCN 5V_HDMI_4 GND 88 BODY_SHIELD 5V_HDMI_1 D2-_HDMI3 D2_GND D2+ D2+_HDMI3 5V_HDMI_1 R3231 10 5V_HDMI_2 R3232 10 5V_HDMI_4 5V_HDMI_3 R3240 10 R3238 10 JK3201 RSD-105156-100 HDMI3 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes C3213 1uF 1/16W R3233 5.1K 5% C3214 1uF 1/16W R3234 5.1K 5% C3220 1uF 1/16W R3241 5.1K 5% GP4 HDMI C3219 1uF 1/16W R3239 5.1K 5% 2011.10.19 32 LGE Internal Use Only RGB/ PC AUDIO/ SPDIF RGB_5V RGB PC +5V_NORMAL RGB_5V A1 C 8 R3642 2.7K 2.7K VCC R3645 10K RGB_EDID E1 E2 VSS 2 7 3 6 4 5 JK3602 2F11TC1-EM52-4F +3.3V_NORMAL WC EDID_WP R3643 SCL 22 SPDIF OUT RGB_DDC_SCL R3644 SDA 22 RGB_DDC_SDA C3633 18pF 50V C3634 18pF 50V R3615 33 R3620 2.7K OPT SPDIF_OUT D3613-*1 5.5V ADUC 5S 02 0R5L ESD_MTK DSUB_VSYNC D3621 ADUC 5S 02 0R5L 5.5V OPT D3615 30V OPT D3613 5.5V ADUC 5S 02 0R5L OPT C3615 0.1uF 16V VIN A VCC B GND C Fiber Optic 1 4 SHIELD R3641 IC3600 M24C02-RMN6T E0 RGB_EDID A2 MMBD6100 D3620 D3622 ADUC 5S 02 0R5L 5.5V OPT DSUB_HSYNC D3616 30V OPT RGB_DEBUG R3602 100 DSUB_B+ SOC_RX RGB_DEBUG R3647 100 PC AUDIO SOC_TX R3600 0 NON_RGB_DEBUG D3600 20V OPT R3601 0 NON_RGB_DEBUG D3601 20V OPT JK3601 KJA-PH-0-0177 5 GND 4 L 3 DETECT PC_L_IN +3.3V_NORMAL DSUB_G+ R3646 10K 1 R D3611 5.6V OPT D3611-*1 ESD_MTK 5.6V DSUB_DET PC_R_IN D3623 5.6V OPT DSUB_R+ 5 15 10 4 D3612-*1 ESD_MTK 5.6V 16 10 5 4 9 3 8 2 7 1 6 16 15 14 9 14 3 13 2 12 7 1 11 8 13 12 11 Closed to JACK 6 D3612 5.6V OPT JK3603 SLIM-15F-D-2 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes JACK HIGH / MID 2011.11.21 36 LGE Internal Use Only HP_LOUT JK3700 KJA-PH-0-0177 +3.3V_NORMAL GND 5 R3700 10K HP_OUT HP_DET HP_ROUT L 4 DETECT 3 R 1 EAG61030001 HP_OUT VA3700 5.6V OPT ESD for MTK ESD for LG1152 VA3700-*1 VA3700-*2 5.6V 5.6V ESD_MTK_HP_OUT ESD_LG1152_HP_OUT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes JACK_COMMON 2011.11.21 37 LGE Internal Use Only 12V_COMMERCIAL_OUT 12V 1A FOR COMMERCIAL(RS-232C POWER) 12V_COMMERCIAL_OUT CVBS 1 PHONE JACK RS232C 10 5 +3.3V_NORMAL 9 4 IR_OUT IC3800 0.1uF C1+ C3800 1 16 0.1uF +3.5V_ST V+ C3801 2 15 3 14 GND D3805 20V OPT D3804 20V OPT RS232 C1- 3 DOUT1 AV1_CVBS_DET 7 RS232 100 R3821 VCC RS232 R3810 10K 8 RS232 100 R3820 +3.5V_ST MAX3232CDR 2 JK3800 KJA-PH-1-0177 6 OPT_RS232 R3834 1 10K D3800 5.6V OPT AV_JACK_BLACK 5 M5_GND 4 M4 3 M3_DETECT 1 M1 6 M6 RS232 FOR COMMERCIAL AV1_CVBS_IN SPG09-DB-009 0.1uF C2+ C3802 4 C2- 0.1uF 13 RIN1 JK3803 RS232 RS232 V- C3803 5 12 6 11 7 10 8 9 ROUT1 DIN1 RS232 DOUT2 RIN2 DIN2 AV1_L_IN AV_JACK_YELLOW ROUT2 JK3800-*1 KJA-PH-1-0177-1 SOC_RX 5 D3801 5.6V M5_GND OPT EAN41348201 SOC_TX UART_4PIN_STRAIGHT +3.5V_ST R3811 4.7K R3814 OPT OPT UART_4PIN_ANGLE P3800 P3801 12507WS-04L 12507WR-04L +3.5V_ST 4 M4 3 M3_DETECT 1 M1 6 M6 AV1_R_IN 4.7K 1 1 2 2 3 3 D3802 5.6V OPT 4 4 5 5 ESD For MTK COMPONENT 1 PHONE JACK ESD For LG1152 D3803-*1 5.6V ESD_MTK +3.3V_NORMAL D3800-*1 5.6V ESD_MTK R3806 10K D3803-*2 5.6V ESD_LG1152 D3800-*2 5.6V ESD_LG1152 COMP1_DET D3801-*1 5.6V D3803 5.6V COMP_JACK_BLACK ESD_MTK OPT JK3801 KJA-PH-1-0177 5 M5_GND 4 M4 3 M3_DETECT 1 M1 6 M6 D3802-*1 5.6V COMP1_Y ESD_MTK D3801-*2 5.6V ESD_LG1152 D3802-*2 5.6V ESD_LG1152 COMP1_Pb COMP_JACK_GREEN JK3801-*1 KJA-PH-1-0177-2 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 5 M5_GND 4 M4 3 M3_DETECT 1 M1 6 M6 COMP1_Pr JACK_COMMON 2011.11.21 38 LGE Internal Use Only +3.5V_ST IR & KEY RGB Sensor EEPROM_SCL C KEY2 C4100 0.1uF +3.5V_ST R4107 10K B E EEPROM_SDA R4114 100 +3.5V_ST COMMERCIAL_IR R4103 3.3K R4102 10K IR Q4100 MMBT3904(NXP) COMMERCIAL_IR KEY1 COMMERCIAL_IR R4101 1K R4104 47K COMMERCIAL_IR C IR_BYPASS +3.5V_ST E C4102 0.1uF R4124 100 1 2 D4101 5.6V AMOTECH CO., LTD. OPT D4106 ADUC 20S 02 010L 20V OPT D4100 5.6V AMOTECH CO., LTD. OPT 3 4 5 L4100 BLM18PG121SN1D B Q4101 MMBT3904(NXP) COMMERCIAL_IR P4102 12507WR-10L D4105 ADUC 20S 02 010L 20V OPT R4113 100 COMMERCIAL +3.5V_ST GP4_IR_10P R4123 100 R4118 10K 5% R4117 10K 5% 6 COMMERCIAL_IR C4104 1000pF 50V R4125 1.5K LED_B/GP4_LED_R 7 8 R4100 0 9 IR_BYPASS COMMERCIAL C4107 100pF 50V +3.5V_ST D4104 5.6V OPT AMOTECH CO., LTD. COMMERCIAL_IR_EU 10 11 +3.5V_ST R4109 1K COMMERCIAL_IR R4105 22 IR_OUT COMMERCIAL_IR Q4102 MMBT3904(NXP) COMMERCIAL_IR_EU C R4115 COMMERCIAL_IR_EU3.3K R4111 10K B E R4119 47K C B Q4104 MMBT3904(NXP) COMMERCIAL_IR R4108 0 COMMERCIAL_IR_US E COMMERCIAL_IR Soft Touch Micom D/L Zener Diode is close to wafer ESD for MTK ESD for LG1152 D4105-*1 ADUC 20S 02 010L 20V 10pF ESD_MTK D4106-*1 ADUC 20S 02 010L 20V 10pF ESD_MTK D4100-*2 D4100-*1 200pF 5.6V ADMC 5M 02 200L 200pF 5.6V ADMC 5M 02 200L ESD_LG1152 ESD_MTK D4101-*2 D4101-*1 5.6V 200pF ADMC 5M 02 200L ESD_MTK D4104-*1 5.6V 200pF ADMC 5M 02 200L ESD_MTK THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 5.6V 200pF ADMC 5M 02 200L ESD_LG1152 D4104-*2 5.6V 200pF ADMC 5M 02 200L ESD_LG1152 IR / KEY 2011.11.21 41 LGE Internal Use Only USB_DM1 25V 1uF C4209 USB_DP1 USB_HUB_IC_IN_DP 1/16W 1% XTALIN/CLKIN VDD33_3 [EP]VSS 36 RBIAS PLLFILT 3 USBDM_DN[2] 4 USBDP_DN[2] 5 VDDA33_1 6 NC_1 21 7 NC_2 NC_7 20 8 NC_3 NC_6 19 9 NC_4 C4213 0.1uF C4214 1uF 25V 10 C4212 0.1uF OPT VDDA33_2 11 C4211 0.1uF OPT C4206 TEST PRTPWR[1]/BC_EN[1] OCS_N[1] 12 13 C4210 0.1uF OPT +3.3V_NORMAL R4210 USB_CTL1 100K OPT /USB_OCD1 USB_CTL2 /USB_OCD2 OPT R4207 OPT R4208 22 0.1uF CRFILT OCS_N[2] NC_5 100K R4203 C4202 14 USB HUB 15 NC_8 VDD33_1 22 0.1uF C4204 SDA/SMBDATA/NON_REM[1] IC4200 USB2512B-AEZG 25V 1uF 23 16 24 VDD33_2 17 SCL/SMBCLK/CFG_SEL[0] 18 25 100K OPT Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 35 34 2 26 R4209 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 12K R4206 15pF C4205 15pF C4207 USBDP_UP USBDM_UP XTALOUT 33 32 31 VDDA33_3 USBDM_DN[1] USBDP_DN[1] THERMAL 37 22 C4201 4.7uF USB_DP2 1 HS_IND/CFG_SEL[1] 100K R4202 +3.3V_NORMAL 100K R4201 C4200 0.1uF OPT USB_DM2 27 RESET_N /RST_HUB 30 VBUS_DET PRTPWR[2]/BC_EN[2] 0.1uF X4200 24MHz 28 C4203 R4200 100K R4205 1% 1M 29 R4204 +3.3V_NORMAL SUSP_IND/LOCAL_PWR/NON_REM[0] 100K 0.1uF C4208 USB_HUB_IC_IN_DM USB3_HUB 2011.06.13 42 LGE Internal Use Only +3.3V_NORMAL +5V_USB FOR USB1 R4327 10K OPT MAX 2A R4323 10K POWER_ON/OFF2_4 IC4303 TPS2554 11 3AU04S-305-ZC-(LG) JK4303 1 R1 R4336 20K C4328 0.01uF 50V ILIM1 OPT C4338 1000pF 50V USB_DM1 2 C4334 4700pF 50V 6 1% R2 2K R4339 USB_DP1 Vout=0.8*(1+R1/R2) DVR Ready MAX 1.8A 3 C4332 47pF 50V VSENSE 5 10uF 10V ILIM0 USB DOWN STREAM 5 USB_CTL1 7 4 4 EN COMP 4 USB1 C4323 OUT_1 5 6 8 OPT RCLAMP0502BA D4303 3A /USB_OCD1 3 OUT_2 R4300 27K OPT 330K R4329 SS/TR 3 ILIM_SEL GND 9 FAULT 1/10W EN 7 2 10 1/10W C4326 0.1uF 50V 8 2 C4336 0.1uF 16V 1 [EP] OPT R4341 27K C4324 10uF 35V 1 C4333 22uF 10V 1% VIN IN_2 820 R4343 BLM18PG121SN1D PH IN_1 1% BOOT GND L4308 6.8uH 10K R4338 L4305 IC4305 TPS54331D 40V 0 R4330 C4329 D4304 SMAB34 16V 0.1uF +24V 40V C4327 0.1uF 16V THERMAL D4304-*1 SX34 R4328 10K R4332 POWER_ON/OFF2_4 IC4306 10K C4300 0.1uF 16V SN1104041, DC-DC+2CH USB SW +12V LX_2 17 DEV_USB_DCDC_BD86180 IC4306-*1 BD86180MUV SS RT CTL2 CTL1 FLG2 FLG1 USB_OUT2 GND_1 GND_2 USB_OUT1 1 2 3 24 25 COMP THERMAL EN 23 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 [EP]GND VREG GND_3 C4337 22uF 10V C4301 22uF 10V LX_1 16 VIN_2 SW_IN_3 VIN_1 15 PGND_2 PGND_1 SW_IN_2 BST SW_2 14 7 8 9 10 11 USB2 MAX 1.5A OPT 10K R4303 OPT R4304 10K 10K ROSC USB_DCDC_SN1104041 C4340-*1 0.01uF 50V USB_DCDC_BD86180 USB_DCDC_SN1104041 EN_SW2 +5V_USB_2 3AU04S-305-ZC-(LG) JK4302 USB_CTL2 1 EN_SW1 /USB_OCD2 NFAULT2 2 6 C4340 4700pF 50V USB_DM2 NFAULT1 USB_DP2 SW_OUT2 +5V_USB_3 C4322 10uF 10V AGND_1 AGND_2 3 C4331 0.1uF 16V 18 5 C4342 100pF 50V USB DOWN STREAM L4307 3.6uH 19 4 SS 4 BST +5V_USB 20 5% 3 5 PGND_1 21 COMP OPT RCLAMP0502BA D4302 PGND_2 22 2 R4342 10K 10K VIN_1 C4325 10uF 16V 23 +3.3V_NORMAL EN R4301 VIN_2 USB_DCDC_SN1104041 AGND_3 1 THERMAL L4306 BLM18PG121SN1D 24 25 V7V C4341 4.7uF 10V R4302 [EP]GND +5V_USB_2 SW_1 USB_IN_3 SW_IN_1 USB_IN_2 13 12 SW_OUT1 USB_IN_1 USB3 MAX 1.5A +5V_USB_3 2 ESD for LG1152 4 ESD_LG1152 RCLAMP0502BA D4300-*2 10uF 10V 5 C4310 3 OPT RCLAMP0502BA D4300 ESD for MTK USB DOWN STREAM 1 3AU04S-305-ZC-(LG) JK4300 ESD_LG1152 RCLAMP0502BA D4302-*1 USB_WIFI +5V_USB L4302 WIFI 120-ohm BLM18PG121SN1D ESD_LG1152 RCLAMP0502BA D4303-*3 From SoC C4319 0.1uF 16V WIFI For EMI C4320 0.1uF 16V WIFI C4321 C4339 10uF 10V WIFI 10uF 10V OPT MAX 0.4A P4301 12507WR-04L USB_DM3 WIFI VDD USB_DP3 DM USB_CTL3 WIFI_DM /USB_OCD3 DP WIFI_DP GND 1 2 3 4 5 . THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes USB3_HUB_WiFi 2011.10.26 43 LGE Internal Use Only +3.3V_NORMAL +12V EU R4601 10K Full Scart(18 Pin Gender) CLOSE TO JUNCTION SC_DET EU E MMBT3906(NXP) Q4600 EU D4611-*1 5.6V 200pF D4611-*2 5.6V 200pF D4611 5.6V OPT ESD_LG1152_SCART C4604 0.1uF C ESD_MTK_SCART SC_CVBS_IN D4609-*2 5.5V 15pF ESD_LG1152_SCART D4609-*1 5.5V 15pF ESD_MTK_SCART D4609 5.5V OPT SHIELD AV_DET 17 16 15 14 13 12 11 75 COM_GND EU Q4601 EU MMBT3904(NXP) C R4602 390 B Gain=1+Rf/Rg Rf R4600 EU C4605 100uF 16V D4610-*1 5.5V 15pF ESD_MTK_SCART SYNC_OUT EU C4606 0.1uF 50V EU R4606 47K EU C4607 47uF 25V E EU D4610 5.5V OPT SYNC_IN R4605 EU R4603 390 19 18 EU 470 B EU R4604 180 Rg R4608 EU R4607 15K DTV/MNT_V_OUT 0 OPT SYNC_GND RGB_IO SC_FB R_OUT D4601 5.6V OPT R_GND G_OUT D4601-*1 5.6V 200pF ESD_MTK_SCART D4601-*2 5.6V 200pF ESD_LG1152_SCART 10 G_GND 9 SC_R ID 8 D4602 5.5V OPT B_OUT 7 AUDIO_L_IN 6 D4602-*1 5.5V 15pF ESD_MTK_SCART B_GND 5 SC_G AUDIO_GND 4 AUDIO_L_OUT 3 AUDIO_R_IN D4603 5.5V OPT D4603-*1 5.5V 15pF ESD_MTK_SCART D4604 5.5V OPT D4604-*1 5.5V 15pF ESD_MTK_SCART 2 AUDIO_R_OUT 1 SC_B DA1R018H91E JK4600 EU SC_ID SC_L_IN D4605 5.6V OPT D4600 20V OPT D4600-*1 20V 10pF ESD_MTK_SCART D4600-*2 20V 10pF ESD_LG1152_SCART D4605-*1 5.6V 200pF ESD_MTK_SCART D4605-*2 5.6V 200pF ESD_LG1152_SCART SC_R_IN D4606 5.6V OPT D4606-*1 5.6V 200pF ESD_MTK_SCART D4606-*2 5.6V 200pF ESD_LG1152_SCART BLM18PG121SN1D L4600 D4607 5.6V OPT EU EU C4600 1000pF 50V DTV/MNT_L_OUT EU C4602 4700pF BLM18PG121SN1D L4601 D4608 5.6V OPT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes EU EU C4601 1000pF 50V EU C4603 4700pF DTV/MNT_R_OUT SCART GENDER 2011.10.26 46 LGE Internal Use Only ZigBee_Radio Pulse M_REMOTE OPTION +3.3V_NORMAL P4800 12507WR-08L L4800 120-ohm M_REMOTE 1 M_REMOTE 3.3V C4800 2 3 4 5 6 7 8 GND 0.1uF AR4800 100 1/16W RX M_REMOTE_RX TX M_REMOTE_TX RESET M_RFModule_RESET DC M_RFModule_ISP DD 3D_SYNC_RF GND M_REMOTE 9 3D_SYNC_RF Only For PDP ALL M_REMOTE OPTION THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes MOTION REMOTE 2011.11.21 48 LGE Internal Use Only Ethernet Block LAN_JACK_POWER C5000 0.1uF 16V C5001 0.01uF 50V C5002 0.1uF 16V C5003 0.01uF 50V JK5000 XRJH-01A-4-DA7-180-LG(B) 1 2 3 4 5 6 7 8 9 10 11 D1 D2 D3 D4 P1[CT] P2[TD+] EPHY_TDP P3[TD-] EPHY_TDN P4[RD+] EPHY_RDP P5[RD-] EPHY_RDN P6[CT] P7 D5000 D5001 D5002 5.5V OPT 5.5V OPT 5.5V OPT D5003 5.5V OPT P8 P9 P10[GND] P11 YL_C YL_A GN_C GN_A ESD for MTK ESD for LG1152 12 ESD_LG1152 SHIELD D5000-*1 ESD_MTK D5000-*2 ADUC 5S 02 0R5L 5.5V ADUC 5S 02 0R5L ESD_LG1152 D5001-*1 ESD_MTK ADUC 5S 02 0R5L D5001-*2 5.5V ADUC 5S 02 0R5L ESD_LG1152 D5002-*1 ESD_MTK D5002-*2 ADUC 5S 02 0R5L 5.5V ADUC 5S 02 0R5L ESD_LG1152 D5003-*1 ESD_MTK D5003-*2 ADUC 5S 02 0R5L THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 5.5V ADUC 5S 02 0R5L LAN_VERTICAL 2011.11.23 50 LGE Internal Use Only Ethernet Block +3.3V_NORMAL +3.3V_NORMAL C5203 0.1uF 16V 4.7K C5201 0.1uF 16V R5215 Place 0.1uF close to each power pins LAN_JACK_POWER R5216 C5200 4.7uF 10V 4.7K +3.3V_NORMAL EPHY_LINK EPHY_ACTIVITY R5217 4.7K ET_RXER ET_COL/SNI Place this cap. near IC EPHY_CRS_DV R5210 X5200 25MHZ +3.3V_NORMAL 22 25MHz, CL 18pF, ESR , max 30 Ohm, +/-30ppm 5 MDIO 22 MDC 21 PHYRSTB 20 TXEN EPHY_LINK CRS/CRS_DV COL RXER/FXEN DVDD10OUT AVDD33_2 17 TXD[1] C5212 0.1uF OPT EPHY_TXD1 TXC TXD[0] +3.3V_NORMAL 100NH EPHY_REFCLK EPHY_TXD0 C5202 56pF 56pF EPHY_INT R5208 4.7K EPHY_RXD1 /RST_PHY EPHY_EN C5211 0.1uF 16V Place near IC EPHY_RXD0 L5211 DVDD33 RXC C5209 RXD[3]/CLK_CTL RXD[1] 22 R5206 R5207 RXD[0] 22 9 4.7K EPHY_MDIO EPHY_MDC 16 8 15 TXD[2] RXDV 14 TXD[3] 18 13 19 7 12 6 11 MDI-[1] 22 RXD[2]/INTB R5203 LED0/PHYAD[0]/PMEB 23 AVDD33_1 EPHY_RDN R5201 +3.3V_NORMAL IC5200 RTL8201F-VB-CG 24 1/16W 5% 4 MDI+[1] EPHY_TDN EPHY_RDP THERMAL 33 R5212 1.5K MDI-[0] EPHY_TDP +3.3V_NORMAL 25 3 26 MDI+[0] 27 2 28 1 29 RSET AVDD10OUT Route Single 50 Ohm, Differential 100 Ohm 10 R5204 2.49K 1% CKXTAL1 Place this Res. near IC 30 [EP] C5205 0.1uF 16V 32 C5204 10uF 10V OPT 31 CKXTAL2 0 50V LED1/PHYAD[1] R5205 C5207 15pF Place this cap. near IC EPHY_ACTIVITY C5206 15pF 50V C5210 10uF 10V OPT ET_COL/SNI ET_RXER C5208 0.1uF 16V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LG1152 A0 ETHERNET 14 50 LGE Internal Use Only +3.3V_NORMAL DUAL COMPONENT C5415 1000pF 50V 2ND : 0TR387500AA 50V 1ST : 0TRIY80001A C5416 L5401 BLM18PG121SN1D AUD_MASTER_CLK +24V_AMP 22000pF Q1801 AMP_RESET_N OPT R5406 3.3 3 LF 4 DGND_PLL 5 GND_1 6 10K E PVDD1_1 PVDD1_2 PVDD1_3 OUT1A_1 OUT1A_2 BST1A /RESET AD PGND1A 37 38 39 40 41 42 43 PGND1B R5414 12 33 BST1B 32 VDR1 31 VCC_5 28 BST2A WCK 10 27 PGND2A BCK 11 26 OUT2A_2 SDA 12 25 OUT2A_1 R5408 12 5.1K C5434 0.47uF 50V SPEAKER_L C5437 0.1uF 50V NRS6045T100MMGK R5412 12 R5416 5.1K C5425 22000pF 50V WAFER-ANGLE 4 SPK_L- 3 SPK_R+ C5427 1uF 25V C5428 1uF 25V C5433 1uF 25V 2 SPK_R- 1 C5426 22000pF 50V P5400 24 23 22 21 20 19 18 C5430 390pF 50V D5401 1N4148W 100V OPT C5436 0.1uF 50V NRS6045T100MMGK R5415 SPK_L+ 9 0x54 L5404 10.0uH SPK_L- SDATA C5417 22000pF PVDD2_3 PVDD2_2 PVDD2_1 SPK_R+ OUT2B_2 B 34 VDR2 OUT2B_1 R5400 AMP_MUTE 100 C5404 1000pF Q5400 50V MMBT3904(NXP) OUT1B_1 AGND PGND2B C 35 29 BST2B R5405 OUT1B_2 30 SCL R5401 10K 36 8 17 C5408 33pF 50V C5406 33pF 50V +3.3V_NORMAL R5407 12 L5405 10.0uH 7 MONITOR2 100 IC5400 NTP-7500L 16 I2C_SCL1 100 SPK_L+ DVDD AUD_SCK R5403 OPT C5424 0.01uF 50V D5400 1N4148W 100V OPT DGND AUD_LRCK R5402 THERMAL 49 15 C5412 0.1uF 16V DVDD_PLL 44 2 45 AVDD_PLL 3.3K 46 1 47 AGND_PLL AUD_LRCH I2C_SDA1 C5422 10uF 35V C5420 0.1uF 50V C5429 390pF 50V MONITOR1 R5404 OPT C5410 10uF 10V C5418 0.1uF 50V C5411 0.1uF 16V 14 OPT C5409 10uF 10V MONITOR0 100pF 50V C5407 4.7uF 10V /FAULT C5402 C5403 1000pF 50V OPT C5405 10uF 10V 48 C5401 0.1uF 50V 13 C5400 0.1uF 50V GND_IO 16V CLK_I 0.1uF L5400 CIS21J121 C5414 10uF 10V [EP] C5413 VDD_IO +24V_AMP +24V +24V_AMP D5402 1N4148W 100V OPT R5409 12 R5413 12 C5419 C5421 C5423 0.1uF 50V 0.1uF 50V 10uF 35V D5403 1N4148W 100V OPT L5403 10.0uH C5432 390pF 50V R5410 12 L5402 10.0uH NRS6045T100MMGK C5431 390pF 50V NRS6045T100MMGK R5411 12 C5435 0.47uF 50V C5438 R5417 0.1uF 50V 5.1K C5439 R5418 0.1uF 50V 5.1K SPEAKER_R 50V WOOFER_MUTE SPK_R- WOOFER_MUTE TP5403 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes AMP_NEO 2011.11.21 54 LGE Internal Use Only +24V_AMP_WOOFER +24V L5501 CIS21J121 C5529 0.1uF 50V +3.3V_NORMAL FW25001-02(SPK 2P) WOOFER C5513 1000pF 50V WOOFER DVDD_PLL 3 LF 4 DGND_PLL 100 WOOFER C5510 1000pF 50V PVDD1_2 PVDD1_1 37 38 OUT1A_1 OUT1A_2 PVDD1_3 39 40 42 PGND1A BST1A AD GND_IO CLK_I VDD_IO /RESET 44 45 46 OUT1B_2 35 OUT1B_1 34 PGND1B 33 BST1B 32 VDR1 WCK 10 27 PGND2A BCK 11 26 OUT2A_2 SDA 12 25 OUT2A_1 WOOFER C5519 0.1uF 50V 0.1uF 50V L5503 10.0uH NRS6045T100MMGK L5504 10.0uH WOOFER R5512 12 WOOFER C5534 0.1uF 50V WOOFER WOOFER C5532 0.47uF 50V WOOFER WOOFER C5535 0.1uF 50V NRS6045T100MMGK WOOFER R5515 5.1K WOOFER R5516 5.1K SPK_WOOFER_L- P5501 FW25003_03 WOOFER C5525 1uF 25V WOOFER C5526 1uF 25V WOOFER C5531 1uF 25V SPK_WOOFER_R- 1 SPK_WOOFER_R+ 2 3 WOOFER C5524 22000pF 50V DEV_WOOFER_STEREO WOOFER_STEREO D5502 1N4148W 100V OPT WOOFER C5521 R5500 12 WOOFER_STEREO R5511 12 C5530 390pF 50V WOOFER_STEREO +24V_AMP_WOOFER WOOFER C5517 WOOFER R5514 12 WOOFER C5523 22000pF 50V 24 PVDD2_3 PVDD2_2 PVDD2_1 OUT2B_2 OUT2B_1 BST2B MONITOR2 WOOFER C5515 WOOFER R5507 12 WOOFER C5527 390pF 50V WOOFER C5528 390pF 50V WOOFER R5508 12 D5501 1N4148W 100V OPT WOOFER_MONO 5% 1/16W BST2A 23 VDR2 28 22 29 9 21 8 20 DVDD SDATA 19 AGND 17 30 16 31 D5503 1N4148W 100V OPT WOOFER_STEREO C5533 390pF 50V R5509 12 R5510 12 SPK_WOOFER_R+ WOOFER_STEREO L5502 10.0uH NRS6045T100MMGK WOOFER_STEREO L5505 10.0uH NRS6045T100MMGK WOOFER_STEREO C5536 0.47uF 50V WOOFER_STEREO WOOFER_STEREO R5513 C5537 0.1uF 5.1K 50V WOOFER_STEREO WOOFER_STEREO C5538 R5519 0.1uF 50V 5.1K SPK_WOOFER_R- WOOFER_STEREO WOOFER_STEREO 10uF 35V 22000pF 50V 5% 1/16W WOOFER_MUTE 2 4.7K R5518 WOOFER_MONO WOOFER R5504 36 7 13 C5505 33pF 50V SPK_WOOFER_L+ SPK_WOOFER_L+ 6 SCL C5503 33pF 50V WOOFER WOOFER WOOFER R5502 100 1 C5522 0.01uF 50V D5500 1N4148W 100V OPT DGND AUD_SCK I2C_SCL1 WOOFER C5520 10uF 35V VCC_5 AUD_LRCH I2C_SDA1 WOOFER C5518 0.1uF 50V GND_1 AUD_LRCK WOOFER R5501 100 5 15 C5509 0.1uF 16V WOOFER IC5500 NTP-7500L MONITOR1 WOOFER THERMAL 49 MONITOR0 OPT C5507 10uF 10V 1 2 SPK_WOOFER_L- OPT WOOFER C5516 0.1uF 50V 4.7K R5517 AVDD_PLL 47 AGND_PLL 3.3K 14 100pF 50V OPT C5502 10uF 10V WOOFER C5501 1000pF 50V WOOFER R5503 WOOFER C5508 0.1uF 16V OPT C5506 10uF 10V /FAULT WOOFER C5500 WOOFER C5504 4.7uF 10V C5512 10uF 10V [EP] 16V WOOFER 48 0.1uF OPT R5506 3.3 41 C5514 AUD_MASTER_CLK +24V_AMP_WOOFER 22000pF 10K WOOFER C5511 WOOFER 50V WOOFER R5505 PGND2B BLM18PG121SN1D P5500 AMP_RESET_N 43 WOOFER L5500 18 WOOFER AMP. THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only +12V EU AUD_OUT >> EU/CHINA_HOTEL_OPT IC6000 AZ4580MTR-E1 L6000 EU EU R6000 OUT1 C6000 1uF 25V EU OPT C6002 6800pF OPT R6002 33K EU R6004 IN1- 470K C6003 33pF EU IN1+ VEE SCART_AMP_L_FB 1 8 2 7 4 C6004 EU 0.1uF OUT2 50V SIGN600005 R6011 2.2K [SCART AUDIO MUTE] EU C6008 DTV/MNT_R_OUT EU 3 VCC 6 IN2- R6008 EU 33K OPT R6010 470K 5 OPT 1uF C6007 25V DTV/MNT_L_OUT 6800pF +3.5V_ST IN2+ C C6005 EU 33pF Q6000 MMBT3904(NXP) SCART_AMP_R_FB B E EU EU R6013 510 SCART_Lout OPT R6012 4.7K 2.2K DTV/MNT_L_OUT SCART_MUTE SCART_Rout DTV/MNT_R_OUT C Q6001 MMBT3904(NXP) B E THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes EU SCART AUDIO AMP 2011.11.21 60 LGE Internal Use Only CI POWER ENABLE CONTROL +5V_CI_ON +5V_NORMAL G C6202 0.1uF 16V D CI OPT S Q6201 AO3407A CI R6241 22K R6221 10K OPT R6223 4.7K PCM_5V_CTL R6218 10K CI C6207 4.7uF 10V OPT C6210 1uF 25V OPT R6248 10K CI R6242 2.2K CI C Q6200 MMBT3904(NXP) CI B CI E Option FOR MTK Option FOR LG1152 C6210-*1 1uF 25V CI_MTK THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes CI SLOT 2011.10.31 62 LGE Internal Use Only +3.3V_NORMAL EARPHONE AMP L6400 120-ohm BLM18PG121SN1D C6403 10uF 10V Place Near jack Side C6405 0.1uF 16V R6406 10 C6402 1uF 10V C6400 1uF 10V 16 INL- HP_LOUT_MAIN 15 1/16W 5% +3.3V_NORMAL 14 13 1 12 2 11 HPVDD C6406 2.2uF 10V HP_ROUT_MAIN 3 10 4 6 OPT R6401 OPT G0 OUTR R6400 4.7K 5 R6402 4.7K 9 EAN60724701 7 PGND CPN 8 C6407 2.2uF 10V Q6400 MMBT3904(NXP) HP_AMP_MUTE INR- CPP B E R6405 1K SIDE_HP_MUTE From Micom HPVSS C6401 1uF 10V IC6400 TPA6132A2 G1 INR+ C6408 0.47uF 16V R6404 4.7K C INL+ HP_LOUT EN VDD SGND OUTL Close to the IC R6407 10 R6403 4.7K HP_ROUT 1/16W 5% C6404 2.2uF 10V C6409 0.47uF 16V Low Pass Filter THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes HEADPHONE AMP 2011.06.29 61 LGE Internal Use Only T/C/S & H/NIM & T2/C TUNER(EU & CHINA) RF_SWITCH_CTL USE: T2/C,T/C,ATSC,DTMB.ISDB-T TU6501 TDSN-G351D TU6500 TDSS-G151D TU6504 TDSH-T151F TU6502 TDSQ-H051F TU6503 TDSQ-G051D +3.3V_TU CHB +5V_TU L6508 BLM18PG121SN1D RESET T/C_H/NIM_V 1 2 NC T2/C_F/NIM_DEV NC_1 1 RESET CHB_V 2 RESET 3 SCL T/C/S2_V +5V[SPLITTER] 1 1 2 RESET 3 TU_SCL CHB N.C_1 RF_SWITCH OPT R6511 100K C6520 0.1uF 16V BR_TW_CN_TUNER R6500-*1 1K TW_H/NIM CHB_CVBS CHB_ERR L9_T2/C/S ATV_OUT CHB_SYNC IC6500 74LVC1G08GW ERROR & VALID PIN CHB_VAL close to TUNER RF_S/W_CTL LNB_TX LNB_OUT 5% CHB_DATA /TU_RESET TU_TS_VAL B 1 3 SDA 4 +B1[3.3V] SIF 5 6 +B2[1.8V] CVBS 7 8 IF_AGC DIF[P] DIF[N] 9 10 11 12 SCL SDA +B1[3.3V] SIF +B2[1.8V] CVBS IF_AGC DIF[P] DIF[N] 4 SDA 5 +B1[3.3V] 6 SIF L9_T2/C/S C6544 TU_TS_ERR A 2 RESET 2 3 SCL 3 C6503 0.1uF 16V R6500 GND 0 BR_TW_CN_TUNER R6508-*1 R6508 100 1K 3 TU_SDA 5 M_+3.3V 6 M_SIF 4 SDA 5 +3.3V_TUNER 6 SIF 4 5 6 +B2[1.8V] 8 CVBS 8 M_CVBS 8 CVBS 8 9 NC_2 9 M_IF_AGC 9 T/C_IF_AGC 9 M_+1.8V 7 +1.8V_TUNER 7 C6551 100pF 50V C6550 0.1uF 16V C6500 10 M_DIF[P] 10 T/C_DIF[P] 10 11 NC_4 11 M_DIF[N] 11 T/C_DIF[N] 11 +B3[3.3V] 12 S_3.3V 12 N.C_2 12 0.1uF 16V R6506 13 N.C_3 13 NC_5 14 S_CVBS 14 N.C_4 14 close to TUNER C6507 100pF 50V R6518 82 R6520 220 TUNER_SIF E R6521 220 2012 perallel because of derating E C R6515 4.7K Q6500 MMBT3906(NXP) B R6519 1K C T/C_H/NIM Q6501 MMBT3906(NXP) T/C/S2 T/C&AT&CHB OPT 1. should be guarded by ground IF_AGC2. No via on both of them 3. Signal Width >= 12mils Signal to Signal Width = 12mils Ground Width >= 24mils 100 T/C&AT&CHB CHB C6523 100pF 50V C6510 1000pF 50V CN C6513 4700pF 50V CN NOT_DVB_S T2/C_F/NIM DVB_S NOT_T/C&AT +1.8V_TU 15 GND_1 15 16 16 ERROR 16 17 SD_SYNC 17 SYNC 17 VALID 18 SD_VALID 18 VALID 18 MCLK 19 SD_MCLK 19 MCLK 19 D0 20 SD_SERIAL_D0 20 D0 20 D1 21 N.C_1 21 D1 21 NOT_T/C&AT&CHB AR6501 0 FE_TS_DATA[0] D2 22 N.C_2 22 D2 22 FE_TS_DATA[1] D3 23 N.C_3 23 D3 23 FE_TS_DATA[3] D4 24 N.C_4 24 D4 24 FE_TS_DATA[4] D5 25 N.C_5 25 D5 25 D6 26 N.C_6 26 D6 26 27 N.C_7 27 D7 27 GND_2 28 GND_2 28 29 GND_3 CHB T2/C DVB_S&CHB DVB_S&CHB T2/C&CN NOT_T/C&AT T/C&AT&CHB CN BR CN T/C&AT&CHB NOT_DVB_S NOT_T/C&AT NOT_T/C&AT Not_L9_T2/C/S T2/C T2/C&CHB&CN RF_SWITCH Not_L9_T2/C/S NOT_DVB_S NOT_T/C&AT&CHB T/C&AT&CHB T2/C&CN NOT_T/C&AT&CHB NOT_T/C&AT&CHB CHB L6507 AT_H/NIM CHB DVB_S DVB_S&CHB Not_L9_T2/C/S NOT_T/C&AT T2/C&CHB&CN T2/C&CHB&CN NOT_DVB_S Not_L9_T2/C/S H/NIM&CHB Not_L9_T2/C/S NOT_T/C&AT&CHB Not_L9_T2/C/S C6516 BLM18PG121SN1D 0.1uF 16V T2/C&CHB&CN SD_ERROR T2/C/S2 +3.3V_D_Demod OPT C6528 10uF 6.3V +1.23V_TU GND_1 T2/C&CHB&CN OPT C6525 0.1uF 16V T2/C&CN L6502 BLM18PG121SN1D 15 ERROR R6516 470 +1.8V_TU C6509 0.1uF 16V CHB S_1.8V NOT_L9_T2/C/S B 16V IF_N 13 R6525 0 +5V_TU +5V_TU TU_CVBS C6522 0.1uF should be guarded by groumd IF_P +B4[1.23V] GND BR_TW_CN_TUNER C6506-*1 68pF 50V close to TUNER C6514 0.1uF 16V C6505 0.1uF 16V close to Tuner NC_3 BR_TW_CN_TUNER C6508-*1 68pF 50V L6500 BLM18PG121SN1D L9 ATSC 10 SHIELD I2C_SDA6 +3.3V_TU 7 FE_TS_VAL 1/16W 5% L9_T2/C/S 5% I2C_SCL6 C6511 100pF 50V R6526 100 Y 4 ATV_OUT R6509 C6508 33 18pF R6510 OPT 50V 33 C6506 OPT 18pF 50V 0.1uF 16V 2 MTK/L9_DVB/ATSC/NTSC RF_SWITCH RF_SWITCH_CTL C6501 10uF 10V 1 7 12 SHIELD 4 VCC 5 MTK/L9_DVB/ATSC/NTSC SCL +3.3V_TU CHB_CLK CHB_CVBS L9_T2/C/S CHB_ERR SYNC CHB_SYNC CHB_VAL NOT_T/C&AT&CHB AR6500 0 CHB_CLK TU_TS_ERR FE_TS_SYNC TU_TS_VAL FE_TS_CLK CHB_DATA FE_TS_DATA[0-7] T2 : Max 1.7A else : Max 0.7A FE_TS_DATA[2] FE_TS_DATA[5] FE_TS_DATA[6] FE_TS_DATA[7] NOT_T/C&AT D7 +3.3V_TU_IN AR6502 0 NOT_T/C&AT&CHB IC6501 AP2132MP-2.5TRG1 +1.23V_TU [EP] NOT_T/C&AT R6527 R2 20K 1% NOT_T/C&AT R6528 11K 1% R6529 R1 10K 1% Seperate GND for CHB 29 SD_1.23V_DEMOD 30 +1.23V_S2_DEMOD 30 SD_RESET S2_RESET 31 SD_3.3V_DEMOD32 N.C_8 DVB_S&CHB L6501 BLM18PG121SN1D 2 +1.23V_TU C6512 100pF C6515 0.1uF DVB_S&CHB C6519 10uF 10V DVB_S&CHB 10uF 16V C6521 0.1uF OPT S2_F22_OUTPUT 33 10 DVB_S&CHB GND 3 NOT_T/C&AT C6533 +3.3V_D_Demod OPT R6512 2.2K R6513 +3.3V_S2_DEMOD 32 33 EN R6523 10K DVB_S&CHB 31 8 PG 9 GND_3 SHIELD 1 C6540 0.1uF THERMAL 28 7 ADJ 6 VOUT VIN 2A 4 +5V_NORMAL CN R6528-*1 12K 1/16W 1% NOT_T/C&AT 5 NC VCTRL NOT_T/C&AT C6549 EAN61387601 /S2_RESET 10uF +3.3V_D_Demod 16V OPT SD_SCL 34 S2_SCL 34 SD_SDA 35 S2_SDA 35 LNB 36 C6524 100pF LNB_TX R6503 36 GND_4 38 OPT C6517 18pF 50V OPT C6518 18pF 50V 22 C6527 0.1uF OPT C6535 1uF OPT Vout=0.6*(1+R1/R2) I2C_SCL4 DVB_S&CHB CHB : Max 480mA else : Max 240mA 37 R6504 SHIELD LNB_OUT SHIELD 22 I2C_SDA4 DVB_S&CHB +3.3V_TU +3.3V_D_Demod IC6503 NOT_T/C&AT L6506 BLM18PG121SN1D AZ1117BH-1.8TRE1 NOT_T/C&AT C6531 0.1uF BR_F/NIM_V CN_ATBM TU6501-*1 TDSN-B051F 2 3 4 5 6 7 AT_H/NIM_V TU6500-*1 TDSS-H151F 8 9 10 1 2 3 4 5 6 7 8 9 10 11 NC 11 12 RESET 13 SCL 14 SDA 15 +B1[3.3V] 16 SIF 17 18 +B2[1.8V] 19 CVBS 20 IF_AGC 21 DIF[P] 22 23 DIF[N] 24 25 12 26 SHIELD 27 RF_S/W_CTL 1 RESET 2 SCL 3 SDA 4 +B1[3.3V] 5 SIF 6 +B2[1.8V] 7 CVBS 8 NC_1 9 NC_2 10 NC_3 11 +B3[3.3V] 12 +B4[1.23V] 13 NC_4 14 GND 15 ERROR 16 SYNC 17 VALID 18 MCLK 19 D0 20 D1 21 D2 22 D3 23 D4 24 D5 25 D6 26 D7 28 27 RF_S/W_CTL 2 RESET 1 SCL 2 SDA 3 +B1[3.3V] 4 RF_S/W_CTL 3 RESET 4 5 SIF 5 SCL 6 SDA 7 +B1[3.3V] 8 9 +B2[1.8V] 6 CVBS 7 NC_1 8 SIF 10 +B2[1.8V] 11 CVBS 12 13 NC_2 9 NC_3 10 +B3[3.3V] 11 NC_1 14 NC_2 15 NC_3 16 17 +B4[1.23V] 12 NC_4 13 GND 14 +B3[3.3V] 18 +B4[1.23V] 19 20 NC_4 21 ERROR 15 SYNC 16 VALID 17 MCLK 18 D0 19 D1 20 D2 21 GND 22 ERROR 23 SYNC 24 25 VALID 26 MCLK 27 28 D0 29 D3 22 D4 23 D1 30 D2 31 D3 32 33 D5 24 D6 25 D7 26 27 D4 34 D5 35 36 D6 D7 28 38 37 SHIELD SHIELD SHIELD THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes IN 3 2 OUT 1 R6531 1 ADJ/GND TU6503-*1 TDSQ-G351D TU6501-*3 TDSN-C051D 28 SHIELD NOT_T/C&AT C6542 0.1uF C6538 10uF 10V T2/C/S2 CN_LG3921 TU6501-*2 TDSN-C251D 1 1 +1.8V_TU +3.3V_TU N.C_1 RESET C6546 10uF 10V SCL SDA +B1[3.3V] SIF +B2[1.8V] Close to the tuner C6548 0.1uF 16V CVBS N.C_2 N.C_3 N.C_4 +B3[3.3V] +B4[1.23V] N.C_5 GND_1 ERROR BR_TW_CN_TUNER R6532-*1 BLM18PG121SN1D 465mA(MAX) SYNC VALID MCLK 150mA(MAX) D0 D1 D2 120-ohm D3 D4 D5 +3.3V_NORMAL +3.3V_TU D6 +5V_TU +5V_NORMAL D7 GND_2 GND_3 +B5[1.23V] S2_RESET +B6[3.3V] S2_F22_OUTPUT MTK/L9_DVB/ATSC/NTSC R6532 0 L6503 BLM18PG121SN1D S2_SCL S2_SDA LNB GND_4 C6526 0.1uF 16V C6529 22uF 10V C6530 0.1uF 16V Close to the tuner TUNER C6532 0.1uF 16V C6534 22uF C6536 22uF 10V 10V C6539 0.1uF 16V Close to the tuner 2011.11.21 65 LGE Internal Use Only DCDC_GND and A_GND are connected DCDC_GND and A_GND are connected in pin#27 PCB_GND and A_GND are connected DVB-S2 LNB Part Allegro (Option:LNB) Input trace widths should be sized to conduct at least 3A Ouput trace widths should be sized to conduct at least 2A 2A D6901-*1 LNB_SX34 D6903-*1 40V 40V LNB_SX34 D6901 LNB_SMAB34 D6903 C6901 0.01uF 50V LNB 3A 40V LNB_SMAB34 40V C6912 68uF 35V LNB C6902 1uF 50V LNB +12V_LNB C6906 68uF 35V LNB LNB L6900 33UH SP-7850_33 LNB_OUT close to Boost pin(#1) DCDC_GND D6900 MBR230LSFT1G DCDC_GND 22000pF LNB A_GND 3 BFO 22 NC_9 23 BFI LX VIN 24 NC_8 20 NC_7 R6904 0 19 BFC 4 IC6900 A8290SETTR-T 18 NC_6 5 LNB 17 NC_5 16 NC_4 15 NC_3 NC_1 TDO EXTM 6 TDI 7 8 LNB_TX 2 TCAP 21 A_GND A_GND +12V 27pF +12V_LNB C6917 LNB 0.1uF 50V LNB C6918 0.1uF 50V LNB OPT C6909 A_GND L6901 BLM18PG121SN1D 4.7K LNB LNB R6901 33 OPT C6908 27pF LNB R6900 33 LNB 0.22uF R6903 C6907 DCDC_GND Max 1.3A IRQ NC_2 SCL ADD SDA VREG GND +3.3V_NORMAL A_GND R6905 0 14 C6905 THERMAL 29 13 LNB 1 VCP 12 BOOST C6903 0.1uF 25 A_GND A_GND 11 D6902-*1 LNB_SX34 40V A_GND GNDLX C6900 0.22uF 25V A_GND D6902 LNB_SMAB34 40V C6904 0.1uF 50V 26 LNB LNB 10 30V LNB Close to Tuner Surge protectioin close to VIN pin(#25) LNB DCDC_GND LNB D6904 LNB R6906 2.2K 1W LNB 27 C6914 33pF LNB 9 C6913 33pF OPT [EP] C6916 18pF LNB 28 C6915 18pF OPT C6911 0.1uF 50V C6910 10uF 25V LNB 2.4A THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes I2C_SCL4 I2C_SDA4 A_GND LNB 2011.11.21 69 LGE Internal Use Only [51Pin LVDS Connector] (For FHD FRC3 HS_LVDS) P7200 L/DIM0_SCLK FI-RE51S-HF-J-R1500 L/DIM0_MOSI L/DIM0_VS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 NC I2C_BE_SDA1 L/DIM0_SCLK NC I2C_BE_SCL1 L/DIM0_MOSI NC FRC3_RESET L/DIM0_VS NC I2C_BE_SDA1 NC I2C_BE_SCL1 NC FRC3_RESET LVDS_SEL R7201 0 NC FRC3_FLASH_WP NC R7200 10K 1 BPL_IN L/DIM_ENABLE GND TP7204 LOCAL_DIM_EN LOCAL_DIM_EN RA0N TXA0N RA0P TXA0P RA1N TXA1N RA1P TXA1P RA2N TXA2N RA2P TXA2P GND RACLKN TXACLKN RACLKP TXACLKP GND RA3N TXA3N RA3P TXA3P RA4N TXA4N RA4P TXA4P GND BIT_SEL RB0N TXB0N RB0P TXB0P RB1N TXB1N RB1P TXB1P RB2N TXB2N RB2P TXB2P GND RBCLKN TXBCLKN RBCLKP TXBCLKP GND RB3N TXB3N RB3P TXB3P RB4N TXB4N RB4P TXB4P GND PANEL_VCC GND GND L7200 120-ohm GND GND NC VLCD C7200 10uF 16V OPT C7201 1000pF 50V OPT C7202 0.1uF 16V OPT VLCD VLCD VLCD 52 GND THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LG1152 A0 Interface block 72 100 LGE Internal Use Only LOCAL DIMMING [To LED DRIVER] +3.3V_NORMAL P7600 12507WR-08L R7600 10K OPT 1 R7601 10K 2 AR7600 33 1/16W 3 L/DIM0_SCLK 4 5 L/DIM0_MOSI 6 I2C_SCL1 7 8 9 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes I2C_SDA1 R7606 33 L/DIM0_VS R7607 4.7K LOCAL DIMMING 2011.11.21 76 LGE Internal Use Only eMMC I/F EMMC_VCCQ 10K 10K 10K 10K R8104 R8105 R8106 R8107 EMMC_DATA[0] A3 EMMC_DATA[1] A4 EMMC_DATA[2] A5 EMMC_DATA[3] EMMC_DATA[4] B2 EMMC_DATA[5] B4 B3 EMMC_DATA[6] EMMC_DATA[7] B5 AR8101 22 1/16W B6 DAT0 NC_25 DAT1 NC_26 DAT2 NC_27 DAT3 NC_28 DAT4 NC_29 DAT5 NC_30 DAT6 NC_31 DAT7 NC_32 NC_33 NC_34 M6 M5 CLK NC_35 CMD NC_36 NC_37 NC_38 A6 C5 E5 E8 AR8102 E9 22 E10 EMMC_CMD F10 EMMC_RST G3 G10 H5 OPT J5 C8107 10pF 50V K6 K7 K10 P7 P10 NC_3 NC_39 NC_4 NC_40 NC_23 NC_41 NC_42 NC_46 NC_43 NC_47 NC_44 NC_48 NC_45 NC_49 NC_52 NC_50 NC_58 NC_51 NC_59 NC_53 NC_66 NC_54 NC_73 NC_55 NC_80 NC_56 NC_81 NC_57 NC_82 NC_60 NC_116 NC_119 K5 RESET OPT C8100 0.1uF 16V C6 M4 3.3V_EMMC EMMC_VCCQ N4 P3 EMMC_RESET_BALL EMMC_CMD_BALL EMMC_CLK_BALL DAT6 DAT5 DAT4 DAT3 P5 VCCQ_1 VCCQ_2 VCCQ_3 VCCQ_4 VCCQ_5 C8105 0.1uF 16V C8106 2.2uF 10V E6 F5 J10 K9 VCC_1 VCC_2 VCC_3 VCC_4 EMMC_VDDI C2 VDDI C8104 0.1uF 16V E7 G5 H10 K8 C8102 0.1uF 16V C8103 2.2uF 10V C4 N2 N5 P4 P6 VSS_1 VSS_2 VSS_3 VSS_4 GED_SANDISK_EMMC_4GB A7 EMMC_CLK IC8100-*3 H26M31001EFR IC8100-*1 H26M21001ECR NC_61 NC_62 NC_63 NC_64 NC_65 NC_67 NC_68 NC_69 NC_70 NC_71 NC_72 NC_74 NC_75 NC_76 NC_77 NC_78 NC_79 NC_83 NC_84 NC_85 NC_86 NC_87 NC_88 NC_89 NC_90 NC_91 NC_92 VSSQ_1 NC_93 VSSQ_2 NC_94 VSSQ_3 NC_95 VSSQ_4 NC_96 VSSQ_5 NC_97 NC_98 NC_99 DAT3 DAT4 A2 A8 A9 A10 A11 A12 A13 A14 B1 B7 B8 B9 B10 B11 B12 Don’t Connect Power At VDDI B13 EMMC_VDDI B14 C1 (Just Interal LDO Capacitor) DAT5 NC_100 A1 C3 C7 NC_1 NC_101 NC_2 NC_102 NC_5 NC_103 NC_6 NC_104 NC_7 NC_105 NC_8 NC_106 NC_9 NC_107 NC_10 NC_108 NC_11 NC_109 NC_12 NC_110 NC_13 NC_111 NC_14 NC_112 NC_15 NC_113 NC_16 NC_114 NC_17 NC_115 NC_18 NC_117 NC_19 NC_118 NC_20 NC_120 NC_21 NC_121 NC_22 NC_122 NC_24 NC_123 DU1 DU2 DU3 DU4 DU5 DU6 DU7 DU8 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes DUMMY_1 DUMMY_9 DUMMY_2 DUMMY_10 DUMMY_3 DUMMY_11 DUMMY_4 DUMMY_12 DUMMY_5 DUMMY_13 DUMMY_6 DUMMY_14 DUMMY_7 DUMMY_15 DUMMY_8 DUMMY_16 C8 A3 C9 A4 C10 A5 C11 B2 C12 B3 C13 B4 B5 C14 D1 D2 DAT5 B6 C8 DAT0 NC_25 DAT1 NC_26 DAT2 NC_27 DAT3 NC_28 DAT4 NC_29 DAT5 NC_30 DAT6 NC_31 DAT7 NC_32 NC_33 D3 D4 M6 D12 M5 D13 NC_34 CLK NC_35 CMD NC_36 NC_37 D14 E1 E2 A7 E3 C5 E12 E5 E13 E8 E14 E9 F1 F2 NC_38 A6 DAT6 E10 F10 G3 F3 F12 G10 F13 H5 F14 J5 G1 K6 G2 K7 G12 K10 G13 P7 G14 P10 H1 NC_3 NC_39 NC_4 NC_40 NC_23 NC_41 NC_42 NC_46 NC_43 NC_47 NC_44 NC_48 NC_45 NC_49 NC_52 NC_50 NC_58 NC_51 NC_59 NC_53 NC_66 NC_54 NC_73 NC_55 NC_80 NC_56 NC_81 NC_57 NC_82 NC_60 NC_116 NC_61 NC_119 NC_62 H2 K5 H3 RESET H12 H13 H14 C6 J1 M4 J2 N4 J3 P3 J12 P5 VCCQ_1 VCCQ_2 VCCQ_3 VCCQ_4 VCCQ_5 J13 J14 K1 K2 EMMC_RESET_BALL E6 F5 J10 K3 K9 K12 VCC_1 VCC_2 VCC_3 VCC_4 K13 K14 C2 L1 VDDI L2 L3 L12 E7 L13 G5 L14 H10 M1 K8 M2 C4 M3 N2 M7 N5 M8 P4 P6 M9 VSS_1 VSS_2 VSS_3 VSS_4 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 M10 NC_65 NC_67 NC_68 NC_69 NC_70 NC_71 NC_72 NC_74 NC_75 NC_76 NC_77 NC_78 NC_79 NC_83 NC_84 NC_85 NC_86 NC_87 NC_88 NC_89 NC_90 NC_91 NC_92 NC_93 NC_94 NC_95 NC_96 NC_97 NC_99 M12 M13 A1 M14 A2 N1 A8 N3 A9 N6 A10 EMMC_CMD_BALL N7 A11 N8 A12 N9 A13 N10 A14 N11 B1 N12 B7 N13 B8 N14 B9 P1 B10 P2 B11 EMMC_CLK_BALL B12 P9 B13 P11 B14 P12 C1 P13 C3 P14 C7 DU9 DU1 DU10 DU2 DU11 DU3 DU12 DU4 DU13 DU5 DU14 DU6 DU15 DU7 DU16 NC_64 NC_98 M11 P8 NC_63 DU8 NC_100 NC_1 NC_101 NC_2 NC_102 NC_5 NC_103 NC_6 NC_104 NC_7 NC_105 NC_8 NC_106 NC_9 NC_107 NC_10 NC_108 NC_11 NC_109 NC_12 NC_110 NC_13 NC_111 NC_14 NC_112 NC_15 NC_113 NC_16 NC_114 NC_17 NC_115 NC_18 NC_117 NC_19 NC_118 NC_20 NC_120 NC_21 NC_121 NC_22 NC_122 NC_24 NC_123 C9 C10 C11 C12 C13 C14 D1 D2 A3 A4 A5 B2 B3 B4 B5 B6 DAT0 NC_25 DAT1 NC_26 DAT2 NC_27 DAT3 NC_28 DAT4 NC_29 DAT5 NC_30 DAT6 NC_31 DAT7 NC_32 D3 NC_33 D4 NC_34 D12 D13 M6 M5 CLK NC_35 CMD NC_36 D14 E1 E2 E3 E12 E13 E14 F1 F2 F3 F12 F13 F14 G1 G2 G12 G13 G14 H1 NC_37 NC_38 A6 A7 C5 E5 E8 E9 E10 F10 G3 G10 H5 J5 K6 K7 K10 P7 P10 NC_3 NC_39 NC_4 NC_40 NC_23 NC_41 NC_42 NC_46 NC_43 NC_47 NC_44 NC_48 NC_45 NC_49 NC_52 NC_50 NC_58 NC_51 NC_59 NC_53 NC_66 NC_54 NC_73 NC_55 NC_80 NC_56 NC_81 NC_57 NC_82 NC_60 NC_116 NC_61 NC_119 NC_62 H2 H3 H12 K5 RESET H13 H14 J1 J2 J3 J12 J13 C6 M4 N4 P3 P5 VCCQ_1 VCCQ_2 VCCQ_3 VCCQ_4 VCCQ_5 J14 K1 K2 K3 K12 K13 E6 F5 J10 K9 VCC_1 VCC_2 VCC_3 VCC_4 K14 L1 L2 C2 VDDI L3 L12 L13 L14 M1 M2 M3 M7 M8 M9 M10 E7 G5 H10 K8 C4 N2 N5 P4 P6 VSS_1 VSS_2 VSS_3 VSS_4 NC_63 NC_64 NC_65 NC_67 NC_68 NC_69 NC_70 NC_71 NC_72 NC_74 NC_75 NC_76 NC_77 NC_78 NC_79 NC_83 NC_84 NC_85 NC_86 NC_87 NC_88 NC_89 NC_90 NC_91 NC_92 VSSQ_1 NC_93 VSSQ_2 NC_94 VSSQ_3 NC_95 VSSQ_4 NC_96 VSSQ_5 NC_97 M11 NC_98 M12 NC_99 M13 NC_100 M14 N1 N3 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P8 P9 P11 P12 P13 P14 A1 A2 A8 A9 A10 A11 A12 A13 A14 B1 B7 B8 B9 B10 B11 B12 B13 B14 C1 C3 C7 NC_1 NC_101 NC_2 NC_102 NC_5 NC_103 NC_6 NC_104 NC_7 NC_105 NC_8 NC_106 NC_9 NC_107 NC_10 NC_108 NC_11 NC_109 NC_12 NC_110 NC_13 NC_111 NC_14 NC_112 NC_15 NC_113 NC_16 NC_114 NC_17 NC_115 NC_18 NC_117 NC_19 NC_118 NC_20 NC_120 NC_21 NC_121 NC_22 NC_122 NC_24 NC_123 IC8100-*2 KLM2G1HE3F-B001 C8 A3 C9 A4 C10 A5 C11 B2 C12 B3 C13 B4 C14 B5 D1 B6 D2 C8 DAT0 NC_25 DAT1 NC_26 DAT2 NC_27 DAT3 NC_28 DAT4 NC_29 DAT5 NC_30 DAT6 NC_31 DAT7 NC_32 NC_33 D3 NC_34 M6 D4 M5 D12 D13 CLK NC_35 CMD NC_36 NC_37 D14 E1 A6 E2 A7 E3 C5 E12 E5 E8 E13 E9 E14 E10 F1 F2 F10 F3 G3 G10 F12 F13 H5 F14 J5 K6 G1 K7 G2 K10 G12 G13 P7 G14 P10 H1 NC_38 NC_3 NC_39 NC_4 NC_40 NC_23 NC_41 NC_42 NC_46 NC_43 NC_47 NC_44 NC_48 NC_45 NC_49 NC_52 NC_50 NC_58 NC_51 NC_59 NC_53 NC_66 NC_54 NC_73 NC_55 NC_80 NC_56 NC_81 NC_57 NC_82 NC_60 NC_116 NC_61 NC_119 NC_62 NC_63 H2 NC_64 K5 H3 RSTN H12 H13 C6 H14 M4 J1 J2 N4 J3 P3 P5 J12 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 J13 J14 K1 E6 K2 F5 J10 K3 K9 K12 VDDF_1 VDDF_2 VDDF_3 VDDF_4 K13 K14 C2 L1 VDDI L2 L3 C4 L12 E7 L13 G5 L14 H10 M1 K8 M2 M3 N2 M7 N5 M8 P4 M9 P6 M10 VSS_1 VSS_2 VSS_3 SAMSUNG_EMMC_2GB 10K R8103 IC8100 SDIN5D2-4G-974L1 AR8100 22 1/16W HYNIX_EMMC_2GB 10K R8102 R8116 10K 10K R8101 R8117 10K 10K R8100 47K 47K 47K 47K R8107-*1 R8106-*1 R8105-*1 EMMC DATA LINE 10K PULL/UP DEV_GED_HYNIX_EMMC_4GB EMMC_DATA[0-7] R8104-*1 47K 47K 47K R8103-*1 R8102-*1 R8101-*1 R8100-*1 47K EMMC DATA LINE 47K PULL/UP NC_65 NC_67 NC_68 NC_69 NC_70 NC_71 NC_72 NC_74 NC_75 NC_76 NC_77 NC_78 NC_79 NC_83 NC_84 NC_85 NC_86 NC_87 NC_88 NC_89 NC_90 NC_91 VSS_4 NC_92 VSS_5 NC_93 VSS_6 NC_94 VSS_7 NC_95 VSS_8 NC_96 VSS_9 NC_97 NC_98 M11 NC_99 M12 NC_100 A1 M13 M14 A2 N1 A8 N3 A9 N6 A10 N7 A11 N8 A12 N9 A13 A14 N10 N11 B1 N12 B7 N13 B8 N14 B9 B10 P1 P2 B11 P8 B12 P9 B13 P11 B14 P12 C1 C3 P13 C7 P14 NC_1 NC_101 NC_2 NC_102 NC_5 NC_103 NC_6 NC_104 NC_7 NC_105 NC_8 NC_106 NC_9 NC_107 NC_10 NC_108 NC_11 NC_109 NC_12 NC_110 NC_13 NC_111 NC_14 NC_112 NC_15 NC_113 NC_16 NC_114 NC_17 NC_115 NC_18 NC_117 NC_19 NC_118 NC_20 NC_120 NC_21 NC_121 NC_22 NC_122 NC_24 NC_123 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D12 D13 D14 E1 E2 E3 E12 E13 E14 F1 F2 F3 F12 F13 F14 G1 G2 G12 G13 G14 H1 H2 H3 H12 H13 H14 J1 J2 J3 J12 J13 J14 K1 K2 K3 K12 K13 K14 L1 L2 L3 L12 L13 L14 M1 M2 M3 M7 M8 M9 M10 M11 M12 M13 M14 N1 N3 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P8 P9 P11 P12 P13 P14 DU9 DUMMY_1 DUMMY_9 DUMMY_2 DUMMY_10 DUMMY_3 DUMMY_11 DUMMY_4 DUMMY_12 DUMMY_5 DUMMY_13 DUMMY_6 DUMMY_14 DUMMY_7 DUMMY_15 DUMMY_8 DUMMY_16 DU10 DU11 DU12 DU13 DU14 DU15 DU16 eMMC 11.09.29 81 LGE Internal Use Only BLM18PG121SN1D L8900 LOGO_LIGHT +3.5V_ST Place Near Micom +3.5V_ST P8900 12507WR-03L 1 LOGO_LIGHT 2 10K R8902 OPT R8900 100 3 LOGO_LIGHT 4 LOGO_LIGHT B C LOGO_LIGHT LOGO_LIGHT R8901 10K LOGO_LIGHT C8900 0.1uF 16V Q8900 1K R8903 E LOGO_LIGHT MMBT3904(NXP) THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only IC9300 LG1132 XTAL(24.75MHz) R9306 100 R9308 100 R9329 1M R9310 100 AB17 SOC_TXA0P AA17 SOC_TXA0N Y16 SOC_TXA1P Y17 SOC_TXA1N AA16 SOC_TXA2P AB16 SOC_TXA2N AB15 SOC_TXACLKP AA15 SOC_TXACLKN Y14 SOC_TXA3P Y15 SOC_TXA3N AA14 SOC_TXA4P AB14 SOC_TXA4N R9301 100 R9303 100 R9305 100 R9307 100 R9309 100 R9311 100 A10 RXA0P TXA0P RXA0N TXA0N RXA1P TXA1P RXA1N TXA1N RXA2P TXA2P RXA2N TXA2N RXACLKP TXACLKP RXACLKN TXACLKN RXA3P TXA3P RXA3N TXA3N RXA4P TXA4P RXA4N TXA4N B10 C9 C10 B9 A9 A8 B8 C7 C8 B7 A7 TXA0N TXA1P X-TAL_1 XTAL_IN TXA1N X9300 24.75MHz 1 4 2 3 GND_1 TXA2P TXA2N +3.3V_NORMAL +1.0VDC GND_2 H8 X-TAL_2 XTAL_OUT C9339 30pF 50V C9333 30pF 50V TXACLKP TXACLKN R9334 R9335 4.7K 10K OPT TXA3P CS SPI_CS TXA3N TXA4P R9337 TXA4N AB13 AA13 SOC_TXB0N Y12 SOC_TXB1P Y13 SOC_TXB1N AA12 SOC_TXB2P AB12 SOC_TXB2N AB11 SOC_TXBCLKP AA11 SOC_TXBCLKN Y10 SOC_TXB3P Y11 SOC_TXB3N AA10 SOC_TXB4P AB10 SOC_TXB4N A6 RXB0P TXB0P RXB0N TXB0N RXB1P TXB1P RXB1N TXB1N RXB2P TXB2P RXB2N TXB2N RXBCLKP TXBCLKP RXBCLKN TXBCLKN RXB3P TXB3P RXB3N TXB3N RXB4P TXB4P RXB4N TXB4N B6 DO[IO1] SPI_DI C5 C6 B5 A5 A4 B4 C3 C4 B3 A3 TXB0P WP SPI/I2C For Aardvak Interface TXB0N FLASH_WP TXB1P TXB1N +3.3V_NORMAL TXB2P P9300 TXB2N 12507WR-10L H9 IC9301 W25X40BVSSIG 1 2 33 SOC_TXB0P IC9300 LG1132 SPI FLASH(4M Bit) TXA0P LG1132_FLASH R9304 100 1/16W R9302 100 R9336 100K R9300 100 GND 3 4 8 7 H14 C9365 0.1uF H15 J8 VCC J15 K8 K15 R9343 HOLD L8 3.3K 6 5 L15 CLK M8 SPI_SCLK M15 N8 DI[IO0] N15 SPI_DO P8 P15 TXBCLKP R8 TXBCLKN R9 TXB3P R10 1 TXB3N R11 TXB4P R12 2 TXB4N R13 SPI_CS R14 Y7 P9301 12507WS-04L AA6 +3.3V_NORMAL AB6 TXC1N RXC2P TXC2P RXC2N TXC2N RXCCLKP TXCCLKP RXCCLKN TXCCLKN RXC3P TXC3P RXC3N TXC3N RXC4P TXC4P RXC4N TXC4N AB5 1 AA5 Y4 Y5 2 AA4 AB4 DEBUG 3 AB3 AA3 Y2 4 Y3 AA2 5 AB2 C18 B17 A17 A16 B16 C15 C16 B15 A15 A14 RXD0P TXD0P RXD0N TXD0N RXD1P TXD1P RXD1N TXD1N RXD2P TXD2P RXD2N TXD2N RXDCLKP TXDCLKP RXDCLKN TXDCLKN RXD3P TXD3P RXD3N TXD3N RXD4P TXD4P RXD4N TXD4N B14 C13 C14 B13 A13 A12 B12 C11 C12 B11 A11 SPI_DO 4 TXC1N TEST MODE Configuration LG1132 Has Internal Pull-up SPI_SCLK TXC2P TXC2N 5 G4 H4 Default Setting All ’H’ = Normal Operation Mode SPI_DI TXCCLKP J4 K4 L4 TXCCLKN 6 TXC3P 3D_DEPTH_RESET DEBUG TXC3N TXC4P OPT R9330 7 0 TMODE0 TXC4N R9331 8 TXD0P 0 FLASH_WP DEBUG TXD0N TXD1P R9332 9 +3.3V_NORMAL TXD1N 0 I2C_SDA2 OPT TXD2P R9333 10 TXD2N TXDCLKN TMODE[3:0] 0000 => 0001 => 0010 => 0011 => 0100 => 1001 => 1010 => 1011 => 1100 => 1101 => 1110 => 1111 => M4 System PLL Test LVDS Rx Isolation Test LVDS Tx Isolation Test LVDS Bypass Test ALL PLL Test DDR PLL IsolationTest Functional Test MBIST Scan Test(Normal) Scan Test (Adaptive) Display PLL Test Normal Operation N4 P4 R4 100 OPT R9338 TMODE0 R9339 100 OPT TMODE1 R9340 100 OPT TMODE2 R9341 100 OPT T4 U4 TXD4P TXD4N TMODE3 W8 W9 0 W10 I2C_SCL2 OPT W11 11 W12 W13 W14 +1.0VDC 33 E2 R9316 33 E1 I2C_SDA2 R9317 33 D1 I2C_SCL2 R9318 33 E3 OPT 0 R9344 OPT 0 R9345 I2C_SCL2 GPIO[6] GPIO[7] SDA_M GPIO[8] SCL_M GPIO[9] SDA_S GPIO[10] SCL_S GPIO[11] GPIO[12] F2 SMODE F1 TMODE0 G3 TMODE1 G2 TMODE2 G1 TMODE3 SMODE GPIO[13] TMODE0 GPIO[14] TMODE1 GPIO[15] TMODE2 GPIO[16] TMODE3 GPIO[17] I2C_SDA1 I2C_SCL1 TRST_N TRST_N TDO TDO TDI TDI TCK TCK TMS TMS 3D_DEPTH_RESET GPIO[18] H1 R9319 33 H3 H2 J3 J2 TRST_N GPIO[19] TDO GPIO[20] TDI GPIO[21] TCK GPIO[22] TMS GPIO[23] GPIO[24] F3 PORES_N GPIO[25] GPIO[26] AB21 XTAL_OUT AA21 XTAL_IN XTALO GPIO[27] XTALI GPIO[28] GPIO[29] GPIO[30] U3 U2 U1 T3 T2 T1 LG1132 HW RESET D9 SMODE D10 100 R9315 SPI_DO V1 D8 +3.3V_NORMAL D11 D12 D13 R3 R9328 10K SW9300 JTP-1127WEM D14 R9342 33 GPIO[5] V2 OPT D15 D16 3D_DEPTH_RESET R1 P3 P2 Y22 C9336 4.7uF AA22 +2.5V_AVDD P1 N3 Y20 N2 AA20 N1 AB20 M3 +3.3V_XTAL_AVDD AB19 M2 L1 L2 Monitoring Pins for 3D-Depth Interanl status A19 L3 B19 K1 C19 K2 D4 K3 D5 J1 D6 +3.3V_IO Decaps TXA1N TXC1N TXA2P TXC2P TXA2N TXC2N TXACLKP TXCCLKP TXACLKN TXCCLKN E4 TXA3P TXC3P TXA3N TXC3N TXA4P TXC4P TXA4N TXC4N TXB0P TXD0P TXB0N TXD0N TXB1P TXD1P TXB1N TXD1N TXB2P TXD2P TXB2N TXD2N TXBCLKP TXDCLKP TXBCLKN TXDCLKN TXB3P TXD3P TXB3N TXD3N TXB4P TXD4P TXB4N TXD4N +1.0VDC E6 +2.5V LVDS_RX Decaps +3.3V_IO +2.5V_LG1132 E7 E8 +2.5V_LVDS_RX +2.5V_LVDS_RX E9 C9304 0.1uF 16V OPT C9308 0.1uF 16V OPT C9311 10uF 10V C9312 10uF 10V E10 C9361 4.7uF 10V C9353 4.7uF 10V L9303 BLM18SG121TN1D C9300 0.1uF 16V OPT VDD_10 VSS_33 VDD_11 VSS_34 VDD_12 VSS_35 VDD_13 VSS_36 VDD_14 VSS_37 VDD_15 VSS_38 VDD_16 VSS_39 VDD_17 VSS_40 VDD_18 VSS_41 VDD_19 VSS_42 VDD_20 VSS_43 VDD_21 VSS_44 VDD_22 VSS_45 VDD_23 VSS_46 VDD_24 VSS_47 VSS_48 VDD33_1 VSS_49 VDD33_2 VSS_50 VDD33_3 VSS_51 VDD33_4 VSS_52 VDD33_5 VSS_53 VDD33_6 VSS_54 VDD33_7 VSS_55 VDD33_8 VSS_56 VDD33_9 VSS_57 VDD33_10 VSS_58 VDD33_11 VSS_59 VDD33_12 VSS_60 VSS_61 LVRX_VDD25_1 VSS_62 LVRX_VDD25_2 VSS_63 LVRX_VDD25_3 VSS_64 LVRX_VDD25_4 VSS_65 LVRX_VDD25_5 VSS_66 LVRX_VDD25_6 VSS_67 LVRX_VDD25_7 VSS_68 LVRX_VDD25_8 VSS_69 VSS_70 LVTX_VDD10_1 VSS_71 LVTX_VDD10_2 VSS_72 LVTX_VDD10_3 VSS_73 LVTX_VDD10_4 VSS_74 VSS_75 LVTX_VDD25_1 VSS_76 LVTX_VDD25_2 VSS_77 LVTX_VDD25_3 VSS_78 LVTX_VDD25_4 VSS_79 LVTX_VDD25_5 VSS_80 LVTX_VDD25_6 VSS_81 LVTX_VDD25_7 VSS_82 LVTX_VDD25_8 VSS_83 LVTX_VDD25_9 VSS_84 LVTX_VDD25_10 VSS_85 VSS_86 DISP_VDD VSS_87 DR3P_VDD VSS_88 SSP_VDD VSS_89 XTAL_VDD VSS_90 VSS_91 DISP_AVDD VSS_92 DR3P_AVDD VSS_93 SSP_AVDD VSS_94 XTAL_AVDD VSS_95 VSS_97 A2 E5 TXC1P VSS_32 VSS_96 D19 TXA1P VSS_31 VDD_9 M1 +1.0V Power Separation TXC0N VDD_8 AA19 D18 TXA0N VSS_30 Y21 D17 TXC0P VDD_7 +1.0V_PLL_VDD R2 GPIO[31] TXA0P VSS_29 D7 3 I2C_SDA2 R9314 SPI_DI V3 1 DEBUG SPI_DO B2 GPIO[4] VSS_28 VDD_6 4 SPI_DI SPI_CS 2 B1 10K C1 R9327 33 GPIO[3] VDD_5 +2.5V_LVDS_TX Default Setting(’0’) 0 : Boot From Ext. Flash(Normal Booting) 1 : Internal RAM Boot (JTAG Booting) W1 10K R9313 SPI_SCLK H13 W2 10K 33 GPIO[2] W3 R9325 SPI_CS R9312 GPIO[1] R9323 SPI_SCLK C2 UART_TXD H12 System Configuration NON_72INCH_LVDS_AB R9321 10K D2 GPIO[0] VSS_27 H10 Y1 UART_RXD VDD_4 W7 H11 D3 VSS_26 +2.5V_LVDS_RX TXD3P TXD3N VSS_25 VDD_3 F4 TXC1P TXDCLKP VSS_24 VDD_2 +3.3V_IO 10K Y6 RXC1N 3 TXC0N 10K AA7 TXC1P C17 R15 OPT R9326 AB7 RXC1P B18 10K AB8 TXC0N OPT R9324 Y9 AA8 RXC0N TXC0P 10K Y8 TXC0P OPT R9322 AA9 A18 RXC0P OPT R9320 AB9 E17 VDD_1 E11 E12 E13 C9318 4.7uF 10V C9315 4.7uF 10V C9321 0.1uF 16V OPT C9324 0.1uF 16V C9327 0.1uF 16V OPT C9330 0.1uF 16V E14 E15 E16 VSS_1 VSS_98 VSS_2 VSS_99 VSS_3 VSS_100 VSS_4 VSS_101 VSS_5 VSS_102 VSS_6 VSS_103 VSS_7 VSS_104 VSS_8 VSS_105 VSS_9 VSS_106 VSS_10 VSS_107 VSS_11 VSS_108 VSS_12 VSS_109 VSS_13 VSS_110 VSS_14 VSS_111 VSS_15 VSS_112 VSS_16 VSS_113 VSS_17 VSS_114 VSS_18 VSS_115 VSS_19 VSS_116 VSS_20 VSS_117 VSS_21 VSS_118 VSS_22 VSS_119 E18 F5 F18 G5 G18 H5 H18 J5 J9 J10 J11 J12 J13 J14 J18 K5 K9 K10 K11 K12 K13 K14 K18 L5 L9 L10 L11 L12 L13 L14 L18 M5 M9 M10 M11 M12 M13 M14 M18 N5 N9 N10 N11 N12 N13 N14 N18 P5 P9 P10 P11 P12 P13 P14 P18 R5 R18 T5 T18 T19 U5 U18 U19 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W4 W5 W6 W15 W16 W17 W18 W19 W20 W21 W22 Y18 Y19 AA1 AA18 AB18 VSS_23 +1.0VDC Decaps +1.0VDC +3.3V Power Separation +2.5V LVDS_TX Decaps +3.3V_NORMAL +3.3V_IO +2.5V_LG1132 L9300 BLM18SG121TN1D C9303 4.7uF 10V C9301 4.7uF 10V +2.5V_LVDS_TX +2.5V_LVDS_TX C9348 0.1uF 16V OPT L9304 BLM18SG121TN1D C9316 4.7uF 10V C9319 4.7uF 10V C9354 0.1uF 16V OPT C9356 10uF 10V C9360 10uF 10V C9364 0.1uF 16V OPT C9366 0.1uF 16V OPT M9300 C9328 0.1uF 16V C9322 0.1uF 16V OPT ALBLOCK MDS62110213 M9301 ALBLOCK MDS62110213 M9302 +3.3V_IO +3.3V_XTAL_AVDD C9307 4.7uF 10V +2.5V_LG1132 +2.5V_AVDD M9303 +1.0VDC +2.5V_AVDD C9314 0.1uF 16V C9317 4.7uF 10V +1.0V_PLL_VDD +1.0V_PLL_VDD C9320 4.7uF 10V C9323 0.1uF 16V OPT C9326 0.1uF 16V OPT C9352 4.7uF 10V ALBLOCK MDS62110213 L9309 BLM18SG121TN1D L9305 BLM18SG121TN1D C9310 4.7uF 10V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes +1.0V_XTAL/DDR3 PLL/SS PLL/DIS PLL_VDD +2.5V DDR PLL/SS PLL/DIS PLL AVDD Decaps +3.3V_XTAL_AVDD L9302 BLM18SG121TN1D ALBLOCK MDS62110213 +3.3V XTAL AVDD Decaps For Heat Sink C9357 4.7uF 10V C9359 0.1uF 16V C9363 0.1uF 16V LG1152 B0 2011. 11. 28 3D Depth LGE Internal Use Only DDR0 PHY VREF +1.5VQ IC9400 H5TQ1G63DFR-PBC DDR_A[0-13] IC9300 LG1132 +0.75V_VREF_M0 +0.75V_VREF_M0 +1.5VQ +0.75V_VREF_M1 +1.5V_LG1132 +1.5VQ R9406 1K 1% DDR_A[0-13] R9410 1K 1% +0.75V_VREF_M1 DDR_A[0] DDR_A[1] N3 DDR_A[2] P3 DDR_A[3] DDR_A[4] DDR_A[5] N2 DDR_A[6] DDR_A[7] R8 P7 P8 P2 R2 T8 DDR_A[8] DDR_A[9] R3 L7 DDR_A[10] R7 DDR_A[11] DDR_A[12] N7 T3 DDR_A[13] Connect A13 for Using 2Gbit Memory N8 M3 VREFDQ 100 1% DDR_CKE +1.5VQ K7 K9 K1 J3 DDR_RASN K3 DDR_CASN L3 DDR_WEN DDR_DQS[1] DDR_DQS_N[1] A7 DDR_A[7] T22 A8 DDR_A[8] C20 DDR_A[9] U22 DDR_A[10] D22 DDR_A[11] B21 DDR_A[12] DDR_A[13] D20 VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 VDD_6 VDD_7 VDD_8 BA0 DDR_DATA[0-15] DDR_DM[0] DDR_DM[1] R9402 240 1% +1.5VQ B2 A9 D9 G7 K2 K8 Connect A13 for Using 2Gbit Memory N1 N9 R9 A1 VDDQ_1 CK VDDQ_2 CK VDDQ_3 CKE VDDQ_4 VDDQ_5 CS VDDQ_6 ODT VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 C1 C9 D2 E9 F1 H2 H9 J1 NC_1 NC_2 NC_4 DQSL A8 J9 L1 T7 D3 DDR_DATA[0] E3 DDR_DATA[1] F7 DDR_DATA[2] F2 DDR_DATA[3] F8 DDR_DATA[4] H3 DDR_DATA[5] H8 DDR_DATA[6] G2 DDR_DATA[7] H7 DDR_DATA[8] DDR_DATA[9] C3 DDR_DATA[10] C8 DDR_DATA[11] C2 DDR_DATA[12] A7 DDR_DATA[13] A2 DDR_DATA[14] B8 DDR_DATA[15] A3 DDR_DATA[1] G20 DDR_DATA[2] N20 DDR_DATA[3] F22 DDR_DATA[4] N22 DDR_DATA[5] F20 DDR_DATA[6] N21 DDR_DATA[7] F21 DDR_DATA[8] H21 DDR_DATA[9] L22 DDR_DATA[10] G22 DDR_DATA[11] M20 DDR_DATA[12] H22 DDR_DATA[13] L21 DDR_DATA[14] H20 DDR_DATA[15] L20 VSS_1 DQSU VSS_2 VSS_3 DML VSS_4 DMU VSS_5 VSS_6 DQL0 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 K22 DQL5 VSS_12 B3 DDR_DQS[1] E1 DDR_DQS_N[1] G8 DDR_CKE J2 DDR_WEN J8 DDR_RASN M1 DDR_CASN M9 DDR_ODT P1 DDR_DM[0] P9 DDR_DM[1] T9 +0.75V_VREF_D1 VSSQ_2 DQU1 VSSQ_3 DQU2 VSSQ_4 DQU3 VSSQ_5 DQU4 VSSQ_6 DQU5 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 J21 E20 R20 P20 P21 P22 G21 M21 R21 D21 DDR_BA[1] R22 DDR_BA[2] B1 DQU0 J22 DDR_BA[0] +0.75V_VREF_D0 DQL6 VSSQ_1 K21 DDR_DQS_N[0] T1 R9407 1K 1% DDR_A[2] DDR_A[3] C9401 4.7uF DDR_A[4] C9413 0.1uF C9417 1000pF R9411 1K 1% C9420 0.1uF C9422 1000pF C9407 4.7uF DDR_A[5] DDR_A[6] DDR_A[7] DDR_A[8] DDR_A[9] DDR_A[10] +1.5VQ +0.75V_VREF_D0 +1.5VQ +0.75V_VREF_D1 DDR_A[11] DDR_A[12] DDR_A[13] U20 DDR_RESET_N R9403 240 A20 DDR_DQ[2] DDR_DQ[3] DDR_DQ[4] R9408 1K 1% DDR_DQ[1] C9400 0.1uF 1K 1% R9405 1K 1% C9406 0.1uF C9410 1000pF R9409 1K 1% C9415 0.1uF C9419 0.1uF C9421 1000pF DDR_DQ[5] DDR_DQ[6] DDR_DQ[7] DDR_DQ[8] DDR_DQ[9] DDR_DQ[10] DDR_DQ[11] DDR_DQ[12] DDR_DQ[13] DDR_DQ[14] DDR_CK +1.5VQ DDR3 1.5V Decaps - Place these caps near Memory DDR_CK_N DDR_DQS[0] DDR_DQS_N[0] DDR_DQS[1] DDR_DQS_N[1] DDR_CKE C9402 C9404 C9405 C9408 C9411 C9412 C9414 C9416 C9418 DDR_WE_N DDR_RAS_N DDR_CAS_N 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF OPT OPT OPT OPT DDR_ODT DDR_DM[0] DDR_DM[1] DDR_BA[0] DDR_BA[1] DDR_BA[2] DDR_RST_N DDR_ZQ_CAL 1% B9 R9404 DDR_DQ[0] DDR_DQ[15] E21 DDR_DQS[0] DQSU DDR_A[1] E22 DDR_CLK A9 DQL7 D7 M22 DDR_CLKN DQSL C7 E7 DDR_DATA[0] L9 NC_6 L9400 BLM18SG121TN1D DDR_A[0] DDR_A[14] R1 VDD_9 U21 B20 DDR_DATA[0-15] BA1 F3 B7 T20 C21 ZQ NC_3 G3 DDR_A[3] T21 RESET DDR_DQS[0] V20 DDR_A[6] L8 A6 T2 DDR_DQS_N[0] B22 DDR_A[2] DDR_A[4] A5 WE DDR_RESET_N V21 DDR_A[1] DDR_A[5] A4 L2 DDR_ODT DDR_A[0] C22 J7 R9401 H1 BA2 DDR_CLKN 200 A3 M2 DDR_BA[2] R9400 A2 A15 DDR_BA[0] VREFCA A1 M7 DDR_BA[1] DDR_CLK M8 A0 V22 D1 A21 D8 E2 DDR_VREF0 DDR_VREF1 DDR3 1.5V/0.75V Decap - Place these caps near IC101 DDR_VDDQ_1 +0.75V_VREF_D0 E19 E8 F19 F9 G19 G1 H19 G9 J19 +1.5VQ J20 K19 K20 L19 M19 N19 P19 R19 +0.75V_VREF_D1 DDR_VDDQ_2 DDR_VDDQ_3 DDR_VDDQ_4 DDR_VDDQ_5 DDR_VDDQ_6 DDR_VDDQ_7 C9403 0.1uF C9409 0.1uF DDR_VDDQ_8 DDR_VDDQ_9 DDR_VDDQ_10 DDR_VDDQ_11 DDR_VDDQ_12 DDR_VDDQ_13 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LG1132 DDR3 2011. 06 .28 LG1132 DDR3 LGE Internal Use Only 3D-Depth Analog for 2.5V +2.5V_LG1132 +2.5V IC9500 AP7173-SPG-13 HF(DIODES) +1.5V_LG1132 +1.5V_DDR PG +5V_USB ZD9500 5.48VTO5.76V VCC R9500 EN 10K 8 2 9 BLM18PG121SN1D 1 THERMAL IN L9500 C9500 10uF 10V Max 600 mA [EP] +3.3V_NORMAL 7 3 6 OUT FB R9502 4.3K R1 1% SS C9513 10uF 10V 1.5A 4 5 GND C9501 2200pF 50V R9501 2K 1% R2 C9514 0.1uF 16V Place near USB JACK Vout=0.8*(1+R1/R2) L9 CORE for 1.0V (UD Model only / LG1132 DDR=792Mh) READY LG1152 for 1.0V UD +12V +1.0VDC +1.0V_VDD Max 2000 mA L9501 BLM18PG121SN1D +1.0V_VDD Max 2000 mA C9502 10uF 16V IC9501 TPS54327DDAR [EP]GND L9502 POWER_ON/OFF2_3 R1 UD 1% Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes VFB VREG5 11K C9503 100pF 50V UD 2 8 3 7 VIN 16V 0.1uF C9506 VBST L9503 3.6uH UD 6 SW UD SS Switching freq: 700K C9504 1uF 10V UD 33K UD R9505 1% THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 1 R9503 R2 **UD Model LG1132 DDR = 792Mhz LG1152 1.0V ==> IC2501 LG1132 1.1V ==> IC2306 EN UD UD **NON UD Model LG1132 DDR = 668Mhz LG1152 1.0V ==> IC2306 LG1132 1.0V ==> IC2306 R9504 10K 9 UD THERMAL +1.0VDC NON_UD CIC21J501NE 4 3A 5 GND C9507 22uF 10V OPT C9508 22uF 10V UD C9505 3300pF 50V UD Vout=0.765*(1+R1/R2) LG1132 Power 2011. 06. 28 LG1132 POWER LGE Internal Use Only 10K R10007 10K R10006 +3.3V_NORMAL +3.3V_NORMAL +12V_MOTOR C10004 0.1uF 16V 8.2V UDZS8.2B 8.2V ZD10001 ZD10000 UDZS8.2B R10009 100 C10005 0.1uF 16V 4.7K BD6222HFP R10023 4.7K MOTOR_CLOSE_SW MOTOR_OPEN_SW R10022 IC10001 R10008 100 VREF OPT R10020 0 OUT1 L/DIM0_VS MOTOR_CW MOTOR+ R10019 R10029 100 0 FIN GND MOTOR_CCW R10017 R10028 SIGN100013 100 0 RIN OUT2 R10018 MOTOR- 0 1 2 3 4 5 6 A_DIM OPT 1 R10034 P10000 R10033 VCC 7 1 12507WR-06L MOTOR_SENSOR CLOSE 1 JP10000 2 R10027 0 MOTOR_SENSOR OPEN MOTOR_SENSOR JP10001 3 L10000 JP10002 MLB-201209-0120P-N2 4 MOTORJP10003 L10001 5 MOTOR+ JP10004 MLB-201209-0120P-N2 6 OPT 7 C10000 0.1uF 50V C10001 0.1uF OPT 50V MOTOR DRIVER +12V_MOTOR +12V MAX 1500mA Close to IC7406 MLB-201209-0120P-N2 L10003 MLB-201209-0120P-N2 L10002 C10011 10uF 50V C10009 0.1uF 50V 20K R10024 1% 1/16W MOTOR_SENSOR_UP R10030 20K 7 6 4 5 6 R10021 0 MOTOR_SENSOR_O MOTOR_SENSOR_UP C10008 0.1uF 4 5 50V MOTOR_SENSOR C10010 0.1uF 50V MOTOR_SENSOR_UP 50V MOTOR_SENSOR 0 R10036 MOTOR_SENSOR_UP C10013 0.1uF 50V 10K 3 10K 3 JP10007 MO_SENS_TO_MAIN_UP MOTOR_SENSOR R10035 MOTOR_SENSOR_UP 7 MOTOR_SENSOR_UP 2 8 R10026 OPT 10K OPT R10013 8 MOTOR_SENSOR_UP C10003 0.1uF 50V 1 22K R10025 JP10005 MOTOR_SENSOR_O C10007 0.1uF MOTOR_SENSOR 2 MOTOR_SENSOR_UP 1/16W 1% R10014 22K MOTOR_SENSOR 1 0 1% 1/10W R10005 51K MOTOR_SENSOR_O MOTOR_SENSOR 1/16W 1% R10002 1K MOTOR_SENSOR 50V MOTOR_SENSOR +12V_MOTOR IC10000 KA4558D R10016 1/10W 1% Q10001 C MMBT3906(NXP) MOTOR_SENSOR 1/8W 1% R10001 22K 1/16W 1% 1/16W 1% MOTOR_SENSOR Q10000 2SC3052 MOTOR_SENSOR E B C10006 0.1uF B C R10000 18K MOTOR_SENSOR E R10003 10K 1/16W 1% R10012 20K JP10006 MOTOR_SENSOR MOTOR_SENSOR +3.3V_NORMAL 0 10K C MOTOR_SENSOR R10010 +12V_MOTOR MOTOR_SENSOR MO_SENS_TO_MAIN_DOWN R10015 12K AC MOTOR_SENSOR R10011 A MOTOR_SENSOR MOTOR_SENSOR 1/10W 1% MOTOR_SENSOR C10002 0.1uF 25V R10004 1K MOTOR_SENSOR D10000 BAT54SWT1 MOTOR Ground +12V_MOTOR +12V_MOTOR MOTOR_SENSOR C10012 0.1uF 50V C10014 0.1uF 50V MOTOR_SENSOR_UP MOTOR SENSOR OPTION THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes GP4 2011.07.01 MOTOR CONTROL LGE Internal Use Only IR BLASTER Pattern Width : 0.5mm +3.3V_IR_Bla +5V_NORMAL G IR_Bla AO3438 Q11002 IR_Bla Q11001 SBT2222A_AUK E L11001 BLM18PG121SN1D IR_Bla R11019 0 IR_Bla IR_Bla R11021 C11004 C11008 10uF 10uF 10V IR_Bla IR_Bla 10K R 1 DETECT 3 JP11001 D11002 B IR_Bla 100 +3.3V_IR_Bla S D R11015 D11001 C IR_Bla C11009 0.1uF 16V OPT IR_Bla JP11002 Pattern Width : 0.5mm 0 IR_Bla +3.3V_NORMAL IR_Bla R11020 L 4 GND 5 KJA-PH-0-0177 JK11001 C11006 0.1uF 16V OPT Close to JK11001 +3.3V_IR_Bla +3.3V_IR_Bla P11001 12507WS-04L IC11002 MC96FR3128R 1 IR_Bla VSS IR_Bla +3.3V_IR_Bla IR_Bla C11003 8MHz 22pF X11001 50V IR_Bla C11005 22pF 50V XIN XOUT P20/RESETB P10/KS8/MOSI1 P11/KS9/MISO1 R11022 4.7K IR_Bla P12/KS10/INT0 P13/KS11/INT1 P14/KS12/SS1/INT2 C IR_B_RESET R11001 1K B Q11003 MMBT3904(NXP) IR_Bla IR_Bla IR_Bla C11010 0.1uF 16V P15/KS13/XCK1/INT3 P16/KS14/MOSI0 P17/KS15/MISO0 E P30/SS0/EC2/EXTREF P31/XCK0/SENSOR IRB_SPI_MOSI IRB_SPI_MISO IRB_SPI_SS IRB_SPI_CK THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes R11006 22 IR_Bla R11007 22 IR_Bla R11008 22 IR_Bla R11009 22 IR_Bla 1 DEV_IR_Bla 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VDD 2 REMOUT DSCL P22/INT3/DSDA DSDA P21/INT2/DSCL 3 4 5 P07/KS7 P06/KS6 P05/KS5/EC3 P04/KS4/EC0 P03/KS3/T3/PWM3 IR_B Micom Download P02/KS2/T2 P01/KS1/T1/PWM1 P00/KS0/T0 P37/INT1/SS0 P36/INT0/XCK0 LG1152 A1 IR Blaster/Boost 2011. 06. 02 94 LGE Internal Use Only IC100 LG1122 R109 100 R114 100 R117 100 R120 100 R122 100 R154 100 1% 1% 1% 1% 1% 1% AC1 RXB4N AC2 RXB4P AB3 RXB3N AC3 RXB3P AB2 RXBCLKN AB1 RXBCLKP AA1 RXB2N AA2 RXB2P Y3 RXB1N AA3 RXB1P Y2 RXB0N Y1 RXB0P R110 100 R121 100 R118 100 R115 100 R123 100 R155 100 RXA4N 1% 1% 1% 1% 1% 1% W2 RXA4P V3 RXA3N W3 RXA3P V2 RXACLKN V1 RXACLKP U1 RXA2N U2 RXA2P T3 RXA1N U3 RXA1P T2 RXA0N T1 RXA0P L/DIM0_VS R148 33 OPT R149 33 R150 33 OPT 33 OPT R151 C26 E22 D24 G22 L/DIM0_SCLK R152 33 D2 L/DIM0_MOSI R153 33 E1 C103 33pF 50V OPT C105 33pF 50V OPT C107 33pF 50V OPT D1 D3 33 SPI_SCLK R125 33 G1 SPI_CS R126 33 G2 R124 F2 SPI_DI R127 33 F1 R128 33 J1 R129 33 J2 I2C_SDA_S R130 33 H1 I2C_SCL_S R131 33 H2 SPI_DO R105 3.3K R104 3.3K +3.3V R103 3.3K R111 R112 1K 1K R101 RXA2P TX2P RXA2N TX2N RXACLKP TX3P RXACLKN TX3N RXA3P TX4P RXA3N TX4N RXA4P TX5P RXA4N TX5N TX6P L3 M3 +3.3V R132 TDO JTP-1127WEM L1 33 L2 TDI M1 TCK N1 3 TMS R133 LG1122_RST TX6N RXB0N TX7P RXB1P TX7N RXB1N RXB2P TXA0P RXB2N TXA0N RXBCLKP TXA1P RXBCLKN TXA1N RXB3P TXA2P RXB3N TXA2N RXB4P TXACLKP RXB4N TXACLKN TXA3P L_VSOUT_LD TXA3N R_VSOUT_LD TXA4P M0_SCLK TXA4N M0_MOSI M1_SCLK TXB0P M1_MOSI TXB0N M2_SCLK TXB1P M2_MOSI TXB1N M3_SCLK TXB2P TXB2N TXBCLKP UART_RXD TXBCLKN UART_TXD TXB3P TXB3N SPI_SCLK TXB4P SPI_CS TXB4N SPI_DI TXC0P TXC0N SDA_M TXC1P SCL_M TXC1N SDA_S TXC2P SCL_S TXC2N TXCCLKP SMODE TXCCLKN TMODE0 TXC3P TMODE1 TXC3N TMODE2 TXC4P TMODE3 TXC4N M2 TRST_N R186 3.3K OPT SW100 RXB0P K2 10K K3 1 TX1N SPI_DO J3 TRST_N TXD0P TDO TXD0N TDI TXD1P TCLK TXD1N TMS TXD2P 0 4 SPI_DL_MODE 2 TX1P RXA1N M3_MOSI H3 UART_TX +3.3V R102 3.3K TX0N RXA1P G3 UART_RX RESET Input 1) LG1122_RST : From Main SOC 2) HW_RESET : From HW Switch 3) SPI_DL_MODE : Download Mode to Flash Mem TX0P RXA0N B26 E2 R134 0 R135 0 TXD2N K1 PORES_N TXDCLKP TXDCLKN AF6 XTAL_OUT AE6 XTAL_IN R136 +1.8LVDS_RX R137 R138 R113 33 OPT 33 OPT N2 33 OPT P3 0 OPT R139 10K N3 XTALO TXD3P XTALI TXD3N TXD4P MON_SYNC0 TX_LOCK MON_SYNC1 GPIO[16] GPIO[17] C1 VIREF_REXT GPIO[18] GPIO[19] TX_LOCKN GPIO[20] GPIO[21] AB5 AD5 AC5 AE4 AD4 R146 PWM_BPL 33 AC4 AF3 AE3 GPIO[1:0] : Local Dimming Debugging AD3 AF2 GPIO[7:3] = PWM[4:0] 1) GPIO[3] : 120Hz Mode --> 60 or 120Hz (Programmable) 240Hz Mode --> 120 or 240Hz (Programmable) AE2 FRAME_OPT AD2 TCON_OPT AE1 SOC_OPT 2) GPIO[4] : 120Hz Mode --> 60 or 120Hz (Programmable) 240Hz Mode --> 120 or 240Hz (Programmable) B25 REVERSE_OPT B24 DISPLAY_OPT C110 0.1uF B3 C111 0.1uF C4 C112 0.1uF C3 C113 0.1uF B4 C114 0.1uF C115 A4 C116 0.1uF B5 C117 0.1uF C6 C118 0.1uF C119 C5 C120 0.1uF A6 C121 0.1uF A7 C122 0.1uF B7 C123 0.1uF D5 D6 TX2P D7 TX2N D8 TX3P D18 TX3N D19 TX4P D20 TX4N D21 TX5P 0.1uF B6 D4 TX1N 0.1uF A5 C7 TX0N TX1P D25 TX5N D26 TX6P E4 TX6N E5 TX7P E6 TX7N E7 A23 E8 B23 E9 C22 E10 C23 E11 B22 E12 A22 E13 A21 E14 B21 E15 C20 E16 C21 E17 B20 E18 E19 A20 E21 A19 E24 B19 F5 F7 C18 F8 C19 F9 B18 F10 A18 A17 F11 B17 F12 C16 F13 C17 F14 B16 F15 A16 F16 F17 A15 F18 B15 F19 C14 F21 C15 F23 B14 G5 A14 G21 A13 G23 B13 H5 C12 H8 C13 H9 B12 H10 A12 H11 H12 A11 H13 B11 H14 C10 H15 C11 H16 H17 B10 H18 A10 +3.3V A9 GPIO[0] GPIO[22] GPIO[1] GPIO[23] GPIO[2] GPIO[24] GPIO[3] GPIO[25] GPIO[4] GPIO[26] GPIO[5] GPIO[27] GPIO[6] GPIO[28] GPIO[7] GPIO[29] GPIO[8] GPIO[30] GPIO[9] GPIO[31] H19 H21 B9 H22 C8 H23 C9 J5 B8 R166 10K A8 R168 10K J8 J19 R160 C24 33 R161 AD1 R162 R1 R163 J21 RBF 33 J22 AGP_EN 33 33 OPT K4 3D_EN K5 3D_LR K8 R2 R3 L/DIMMING_OPT P1 OPT_READY_1 A25 OPT_READY_2 K10 R169 47K OPT R167 47K +3.3V K11 K12 K13 D23 D22 F22 E23 R164 33 E3 R165 33 F3 R156 33 R172 R173 4.7K 4.7K K14 K15 K16 I2C_SCL_PQ K17 I2C_SDA_PQ OPT K19 FLASH_WP K21 A24 PANEL_CTL P2 K22 L4 GPIO[10] L5 GPIO[11] L8 GPIO[12] L10 GPIO[13] L11 GPIO[14] L12 GPIO[15] L13 3) GPIO[5] : 120Hz Mode --> 120 or 240Hz (Programmable) 240Hz Mode --> 240 or 480Hz (Programmable) L14 L15 4) GPIO[6] : 120Hz Mode --> 120Hz (Fixed) 240Hz Mode --> 240Hz (Fixed) I2C Slave Address 0x1C (Direct access) 0xB2 (In-direct access) 5) GPIO[7] : 120Hz Mode --> 120Hz (Fixed) 240Hz Mode --> 240Hz (Fixed) L16 L17 L19 L21 L22 GPIO[8] : External Vsync input for Local Dimming block M4 M5 M6 GPIO[10] : T-Con L/R Sync Monitor(AR) M8 M10 GPIO[12:11] : S/W I2C_Master CH M11 GPIO[26:16] : BLU Direct Control CH M13 M12 +3.3V +3.3V +3.3V +3.3V +3.3V M14 M15 GPIO[28:27] : I2C for PQ tunning M16 R119 10K R108 10K W/O_TCON 240Hz FRAME_OPT R107 10K 120Hz TCON_OPT M17 M19 OLED IMAGE_NORMAL M21 REVERSE_OPT SOC_OPT DISPLAY_OPT M22 N4 R170 10K L9(LG1152) R116 10K W_TCON R189 10K R187 10K R171 10K MTK R188 10K IMAGE_REVERSE R190 10K LCD N5 N6 N8 N10 N11 READY FOR H/W OPTION N12 N13 N14 N15 GPIO NO OPTION NAME HIGH N16 LOW +3.3V 11 FRAME_OPT 240Hz +3.3V +3.3V N17 N19 120Hz N21 12 JIG_OPT Without_TCON With_TCON (for FRC3 JIG) 13 SOC_OPT L9 (LG1152) R140 10K R142 10K R144 10K N22 N24 L/D_ON_FRC OPT OPT L/DIMMING_OPT MTK P4 OPT_READY_1 OPT_READY_2 P5 P6 14 15 IMAGE_OPT IMAGE_OPT (for 72INCH) (for NON_72INCH) OLED LCD L/DIMMING_OPT L/D_ON_FRC L/D_ON_MAIN 21 OPT_READY_1 OPT Default 22 OPT_READY_2 OPT Default 20 DISPLAY_OPT IMAGE_NORMAL R141 10K L/D_ON_MAIN R143 10K R145 10K P8 VSS_1 VSS_135 VSS_2 VSS_136 VSS_3 VSS_137 VSS_4 VSS_138 VSS_5 VSS_139 VSS_6 VSS_140 VSS_7 VSS_141 VSS_8 VSS_142 VSS_9 VSS_143 VSS_10 VSS_144 VSS_11 VSS_145 VSS_12 VSS_146 VSS_13 VSS_147 VSS_14 VSS_148 VSS_15 VSS_149 VSS_16 VSS_150 VSS_17 VSS_151 VSS_18 VSS_152 VSS_19 VSS_153 VSS_20 VSS_154 VSS_21 VSS_155 VSS_22 VSS_156 VSS_23 VSS_157 VSS_24 VSS_158 VSS_25 VSS_159 VSS_26 VSS_160 VSS_27 VSS_161 VSS_28 VSS_162 VSS_29 VSS_163 VSS_30 VSS_164 VSS_31 VSS_165 VSS_32 VSS_166 VSS_33 VSS_167 VSS_34 VSS_168 VSS_35 VSS_169 VSS_36 VSS_170 VSS_37 VSS_171 VSS_38 VSS_172 VSS_39 VSS_173 VSS_40 VSS_174 VSS_41 VSS_175 VSS_42 VSS_176 VSS_43 VSS_177 VSS_44 VSS_178 VSS_45 VSS_179 VSS_46 VSS_180 VSS_47 VSS_181 VSS_48 VSS_182 VSS_49 VSS_183 VSS_50 VSS_184 VSS_51 VSS_185 VSS_52 VSS_186 VSS_53 VSS_187 VSS_54 VSS_188 VSS_55 VSS_189 VSS_56 VSS_190 VSS_57 VSS_191 VSS_58 VSS_192 VSS_59 VSS_193 VSS_60 VSS_194 VSS_61 VSS_195 VSS_62 VSS_196 VSS_63 VSS_197 VSS_64 VSS_198 VSS_65 VSS_199 VSS_66 VSS_200 VSS_67 VSS_201 VSS_68 VSS_202 VSS_69 VSS_203 VSS_70 VSS_204 VSS_71 VSS_205 VSS_72 VSS_206 VSS_73 VSS_207 VSS_74 VSS_208 VSS_75 VSS_209 VSS_76 VSS_210 VSS_77 VSS_211 VSS_78 VSS_212 VSS_79 VSS_213 VSS_80 VSS_214 VSS_81 VSS_215 VSS_82 VSS_216 VSS_83 VSS_217 VSS_84 VSS_218 VSS_85 VSS_219 VSS_86 VSS_220 VSS_87 VSS_221 VSS_88 VSS_222 VSS_89 VSS_223 VSS_90 VSS_224 VSS_91 VSS_225 VSS_92 VSS_226 VSS_93 VSS_227 VSS_94 VSS_228 VSS_95 VSS_229 VSS_96 VSS_230 VSS_97 VSS_231 VSS_98 VSS_232 VSS_99 VSS_233 VSS_100 VSS_234 VSS_101 VSS_235 VSS_102 VSS_236 VSS_103 VSS_237 VSS_104 VSS_238 VSS_105 VSS_239 VSS_106 VSS_240 VSS_107 VSS_241 VSS_108 VSS_242 VSS_109 VSS_243 VSS_110 VSS_244 VSS_111 VSS_245 VSS_112 VSS_246 VSS_113 VSS_247 VSS_114 VSS_248 VSS_115 VSS_249 VSS_116 VSS_250 VSS_117 VSS_251 VSS_118 VSS_252 VSS_119 VSS_253 VSS_120 VSS_254 VSS_121 VSS_255 VSS_122 VSS_256 VSS_123 VSS_257 VSS_124 VSS_258 VSS_125 VSS_259 VSS_126 VSS_260 VSS_127 VSS_261 VSS_128 VSS_262 VSS_129 VSS_263 VSS_130 VSS_264 VSS_131 VSS_265 VSS_132 VSS_266 VSS_133 VSS_267 VSS_134 VSS_268 P10 J9 P11 J10 P12 J11 P13 J16 J17 P14 All of OPT decaps must be placed on PCB Bottom side IC100 LG1122 +0.9VDC B1 TX0P 0.1uF A3 C25 MON_INTR AB4 0.1uF C109 A2 TXD4N C2 Vx1_HS output swing level control via external resistor C108 B2 RXA0P W1 IC100 LG1122 The Vx1_HS Tx AC-coupling Caps must be placed near by LG1122 P15 J18 P16 K9 P17 K18 P19 L9 P21 L18 P22 M9 P24 M18 R4 N9 R5 N18 R6 P9 R8 P18 R10 R9 R11 R18 R12 T9 R13 T18 R14 U9 R15 U18 R16 V9 R17 V10 R19 V11 R21 V12 R22 V13 T5 V14 T6 V15 T8 V16 T10 V17 T11 V18 +3.3V_IO F6 VDD_1 VDD33_1 VDD_2 VDD33_2 VDD_3 VDD33_3 VDD_4 VDD33_4 VDD_5 VDD33_5 VDD_6 VDD33_6 VDD_7 VDD33_7 VDD_8 VDD33_8 VDD_9 VDD33_9 VDD_10 VDD_11 VDD18_1 VDD_12 VDD18_2 VDD_13 VDD18_3 VDD_14 VDD18_4 VDD_15 VDD18_5 VDD_16 VDD18_6 VDD_17 LVRX_VDD18_1 VDD_19 LVRX_VDD18_2 VDD_20 LVRX_VDD18_3 VDD_21 LVRX_VDD18_4 VDD_22 LVTX_VDD18_1 LVTX_VDD18_2 VDD_25 LVTX_VDD18_3 VDD_26 LVTX_VDD18_4 VDD_27 LVTX_VDD18_5 VDD_28 LVTX_VDD18_6 VDD_29 LVTX_VDD18_7 VDD_30 LVTX_VDD18_8 VDD_31 LVTX_VDD18_9 LVTX_VDD_2 LVTX_VDD_3 L100 MLB-201209-0120P-N2 Y6 AA6 +1.8V C134 4.7uF 10V C126 4.7uF 10V F4 C149 0.1uF 16V C161 0.1uF 16V G4 H4 J4 AA5 +1.8LVDS_RX +1.8VLVDS_TX Decaps U4 V4 +1.8LVDS_TX +1.8LVDS_TX +1.8V W4 +1.8LVDS_TX L101 MLB-201209-0120P-N2 D10 D11 C135 4.7uF 10V C127 4.7uF 10V D12 D13 C162 0.1uF 16V D14 D15 D16 D17 +0.9VDC J13 J14 +0.9AVDD AVDD09_1 AF7 AVDD09_2 T21 +1.8V_AVDD AVDD18_1 U5 C158 0.1uF 16V C152 4.7uF 10V C142 4.7uF 10V AE5 T22 +1.8V_AVDD L104 MLB-201209-0120P-N2 AE7 T17 T19 +1.8V_AVDD +1.8V J15 LVTX_VDD_4 T16 +1.8VLVDS_RX Decaps +1.8LVDS_RX +1.8LVDS_RX +1.8V K6 L6 J12 LVTX_VDD_1 T15 J6 D9 VDD_23 VDD_24 T14 +1.8V Power Separation H6 T4 VDD_18 T13 G6 E20 VDD_32 T12 F20 AF5 AVDD18_2 U6 U8 U10 U11 U12 U13 U14 U15 U16 U17 U19 +3.3V_IO Decaps U21 U22 +3.3V_IO V5 V6 V8 V19 V21 C157 10uF 25V C151 10uF 25V V22 W5 W6 W8 W9 W10 W11 W12 +3.3V Power Separation W13 W14 +3.3V W15 +3.3V_IO W16 L102 MLB-201209-0120P-N2 W17 W18 W19 C137 4.7uF 10V C129 4.7uF 10V W21 W22 Y4 Y5 Y21 Y22 AA4 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 +0.9VDC Decaps AA16 AA17 +0.9VDC AA18 AA19 AA20 AA21 C154 10uF 25V C148 10uF 25V AA22 AA23 AB6 AB7 AB8 AB9 AB10 AB11 AB12 +0.9AVDD Decaps +0.9V Power Separation AB13 AB14 +0.9V +0.9VDC AB16 L103 MLB-201209-0120P-N2 AB17 L105 MLB-201209-0120P-N2 AB18 AB20 C153 4.7uF 10V C144 4.7uF 10V C139 4.7uF 10V C131 4.7uF 10V AB19 C163 0.1uF 16V AB22 AB23 AC6 AC7 AC8 AC9 AC10 AC23 AC24 AC25 AC26 AD6 AD7 AD8 AD17 AD18 AE8 AF4 AF8 I2C For PQ tunning UART For CPU For JTAG Interface P103 P102 +3.3V +3.3V P100 12507WR-04L 12507WR-04L +3.3V P101 12507WR-10L 12507WR-08L R175 1 1 1K 1 R147 C125 0.1uF 16V +3.3V SPI FLASH(4MByte) C159 0.1uF 16V AB21 SPI/I2C For Aardvak Interface XTAL(24.75MHz) +0.9AVDD +0.9AVDD +0.9VDC AB15 1 2 3.3K 2 UART_RX Will be deleted pull-up resistor from B0+3D Depth B’d R106 1M X-TAL_1 XTAL_IN SPI_FLASH X100 24.75MHz 1 GND_1 C100 27pF 50V 2 GND_2 R157 R158 X-TAL_2 4.7K 10K OPT 4 3 C104 27pF 50V XTAL_OUT IC101 MX25L3206EM2I-12G CS# SPI_CS R159 SO/SIO1 SPI_DI 1 8 2 7 3 6 4 5 VCC HOLD# 33 FLASH_WP R191 0 R174 SPI_CS 2 R180 33 TDI 3 3 SPI_DO 3 R181 33 TMS 4 4 SPI_SCLK 4 R182 33 TCK SPI_DI 5 R183 33 5 5 UART_TX 3 I2C_SDA_PQ 4 I2C_SCL_PQ 5 TDO 3.3K WP# R185 10K OPT C124 0.1uF 2 GND SCLK SPI_SCLK 6 SPI_DO 7 SI/SIO0 8 9 Write Protection - HIGH : Normal Operation - LOW : Write Protection 10 6 SPI_DL_MODE R176 OPT 0 R177 OPT 0 R178 TRST_N 7 8 FLASH_WP 9 0 I2C_SDA_S R179 0 I2C_SCL_S 11 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 240Hz Back-End Board FRC-III(LG1122) 2011. 07. 05 1 6 LGE Internal Use Only IC200 H5TQ1G63DFR-PBC DDR0_A[0-12] IC100 LG1122 +0.75V_VREF0_M0 IC201 H5TQ1G63DFR-PBC DDR1_A[0-12] DDR0_A[0-12] DDR1_A[0-12] +0.75V_VREF1_M0 +0.75V_VREF0_M1 N3 DDR0_A[0] DDR0_A[1] P7 DDR0_A[2] P3 DDR0_A[3] DDR0_A[4] DDR0_A[5] N2 DDR0_A[6] DDR0_A[7] R8 DDR0_A[8] DDR0_A[9] T8 P8 P2 R2 R3 DDR0_A[10] L7 DDR0_A[11] DDR0_A[12] R7 N7 T3 VREFCA A1 M3 DDR0_BA[2] AB24 Y24 DDR0_A[4] G26 Y25 A5 DDR0_A[5] DDR0_A[6] G25 DDR0_A[7] Y26 DDR0_A[8] G24 DDR0_A[9] AA26 L8 A6 ZQ 100 1% R201 DDR0_CLKN K7 K9 DDR0_CKE +1.5VQ0 A8 K1 J3 DDR0_RASN R200 DDR0_CASN 150 DDR0_WEN K3 L3 VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 VDD_6 VDD_7 VDD_8 F25 DDR0_A[12] H24 K8 AA25 N1 F24 DDR0_DATA[0-15] N9 R1 K26 BA2 DDR0_DATA[3] A1 DDR0_DATA[4] U26 A8 DDR0_DATA[5] K24 C1 DDR0_DATA[6] U25 C9 DDR0_DATA[7] K25 DDR0_DATA[8] M25 E9 DDR0_DATA[9] R26 F1 DDR0_DATA[10] L26 H2 DDR0_DATA[11] T24 H9 DDR0_DATA[12] M26 DDR0_DATA[13] R25 J1 DDR0_DATA[14] M24 J9 DDR0_DATA[15] R24 VDDQ_1 CK VDDQ_2 CK VDDQ_3 CKE VDDQ_4 VDDQ_5 CS VDDQ_6 ODT VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 NC_1 NC_2 NC_4 DQSL D2 L1 L9 D3 DDR0_DM[1] DDR0_DATA[0] E3 DDR0_DATA[1] F7 DDR0_DATA[2] F2 DDR0_DATA[3] F8 DDR0_DATA[4] H3 DDR0_DATA[5] H8 DDR0_DATA[6] G2 DDR0_DATA[7] H7 DDR0_DATA[8] D7 DDR0_DATA[9] C3 DDR0_DATA[10] C8 DDR0_DATA[11] C2 DDR0_DATA[12] A7 DDR0_DATA[13] A2 DDR0_DATA[14] B8 DDR0_DATA[15] A3 VSS_2 VSS_3 DML VSS_4 DMU VSS_5 VSS_6 DQL0 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 VSS_12 VSSQ_2 DQU1 VSSQ_3 DQU2 VSSQ_4 DQU3 VSSQ_5 DQU4 VSSQ_6 DQU5 VSSQ_7 DQU6 VSSQ_8 N25 J24 DDR0_CKE G8 W24 DDR0_WEN J2 V24 DDR0_RASN J8 V25 DDR0_CASN M1 V26 DDR0_ODT M9 L25 DDR0_DM[0] P1 T25 DDR0_DM[1] P9 W25 DDR0_BA[0] +0.75V_VREF0_D0 T1 H25 DDR0_BA[1] T9 W26 DDR0_BA[2] AA24 DDR0_RESET_N R211 B1 VSSQ_1 DQU0 N26 DDR0_DQS_N[1] E1 +0.75V_VREF0_D1 DQL7 P25 DDR0_DQS[1] B3 DQL6 DQU7 P26 DDR0_DQS_N[0] A9 VSS_1 DQSU E7 DDR0_DM[0] J25 DDR0_CLKN DDR0_DQS[0] DQSU 240 E25 1% AB26 D1 E26 J23 +1.5VQ0 E2 DDR1_A[1] DDR0_A[2] DDR1_A[2] DDR0_A[3] DDR1_A[3] DDR0_A[4] DDR1_A[4] DDR0_A[5] DDR1_A[5] DDR0_A[6] DDR1_A[6] DDR0_A[7] DDR1_A[7] DDR0_A[8] DDR1_A[8] DDR0_A[9] DDR1_A[9] DDR0_A[10] DDR1_A[10] DDR0_A[11] DDR1_A[11] DDR0_A[12] DDR1_A[12] DDR0_A[13] DDR1_A[13] DDR0_A[14] DDR1_A[14] DDR0_DQ[0] DDR1_DQ[0] DDR0_DQ[1] DDR1_DQ[1] DDR0_DQ[2] DDR1_DQ[2] DDR0_DQ[3] DDR1_DQ[3] DDR0_DQ[4] DDR1_DQ[4] DDR0_DQ[5] DDR1_DQ[5] DDR0_DQ[6] DDR1_DQ[6] DDR0_DQ[7] DDR1_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] DDR0_DQ[11] DDR1_DQ[11] DDR0_DQ[12] DDR1_DQ[12] DDR0_DQ[13] DDR1_DQ[13] DDR0_DQ[14] DDR1_DQ[14] DDR0_DQ[15] DDR1_DQ[15] DDR0_CK DDR0_CK_N DDR0_DQS[0] DDR0_DQS_N[0] DDR0_DQS[1] DDR0_DQS_N[1] DDR0_CKE DDR0_WE_N DDR1_CK DDR1_CK_N DDR1_DQS[0] DDR1_DQS_N[0] DDR1_DQS[1] DDR1_DQS_N[1] DDR1_CKE DDR1_WE_N DDR0_RAS_N DDR1_RAS_N DDR0_CAS_N DDR1_CAS_N DDR0_ODT DDR1_ODT DDR0_DM[0] DDR1_DM[0] DDR0_DM[1] DDR1_DM[1] DDR0_BA[0] DDR1_BA[0] DDR0_BA[1] DDR1_BA[1] DDR0_BA[2] DDR1_BA[2] DDR0_RST_N L23 G1 M23 N23 G9 VSSQ_9 P23 R23 T23 U23 V23 W23 Y23 DDR3 1.5V/0.75V Decap - Place these caps near IC100 +0.75V_VREF0_D0 DDR1_A[0] DDR1_A[0] N3 AF25 DDR1_A[1] DDR1_A[2] DDR1_A[1] P7 DDR1_A[2] P3 AD11 DDR1_A[3] DDR1_A[3] N2 AF24 DDR1_A[4] DDR1_A[4] P8 AE11 DDR1_A[5] DDR1_A[5] P2 AD9 DDR1_A[6] R8 AF11 DDR1_A[7] DDR1_A[7] R2 AD24 DDR1_A[8] DDR1_A[8] T8 DDR1_A[9] DDR1_A[9] R3 AF23 DDR1_A[10] DDR1_A[10] AE25 DDR1_A[11] DDR1_A[11] R7 AD23 DDR1_A[12] DDR1_A[12] N7 AE24 AF10 DDR1_A[6] DDR1_RST_N DDR0_VREF0 DDR1_VREF0 DDR0_VREF1 DDR1_VREF1 AD25 AF15 DDR1_DATA[0] AD20 DDR1_DATA[1] AD14 DDR1_DATA[2] AF21 DDR1_DATA[3] AF14 DDR1_DATA[4] AD21 DDR1_DATA[5] AE14 DDR1_DATA[6] AE21 DDR1_DATA[7] AE19 DDR1_DATA[8] AF16 DDR1_DATA[9] AF20 DDR1_DATA[10] DDR1_DATA[0-15] DDR0_VDDQ_3 DDR1_VDDQ_3 DDR0_VDDQ_4 DDR1_VDDQ_4 DDR0_VDDQ_5 DDR1_VDDQ_5 DDR0_VDDQ_6 DDR1_VDDQ_6 DDR0_VDDQ_7 DDR1_VDDQ_7 DDR0_VDDQ_8 DDR0_VDDQ_9 DDR1_VDDQ_8 DDR1_VDDQ_9 DDR0_VDDQ_10 DDR1_VDDQ_10 DDR0_VDDQ_11 DDR1_VDDQ_11 DDR0_VDDQ_12 DDR1_VDDQ_12 C201 C202 C203 +1.5VQ1 DDR1_CASN DDR1_DATA[13] 150 DDR1_WEN AD16 DDR1_DATA[15] K1 DDR1_ODT J3 DDR1_RASN K3 L3 A6 A8 A9 VDD_1 A10/AP VDD_2 A11 VDD_3 A12/BC VDD_4 A13 VDD_5 VDD_6 BA0 DDR1_DQS[0] DDR1_DQS_N[0] DDR1_DQS[0] AE17 DDR1_DQS_N[0] AF18 DDR1_DQS[1] DDR1_DQS[1] AE18 DDR1_DQS_N[1] DDR1_DQS_N[1] AD22 DDR1_CKE AD12 DDR1_WEN AD13 DDR1_DATA[0-15] DDR1_RASN AE13 DDR1_DM[0] DDR1_DM[1] DDR1_CASN AF13 B7 VDDQ_2 CK VDDQ_3 CKE VDDQ_4 VDDQ_5 CS VDDQ_6 ODT VDDQ_7 RAS VDDQ_8 CAS VDDQ_9 D3 DDR1_ODT DDR1_DATA[0] E3 DDR1_DATA[1] DDR1_DATA[2] F2 DDR1_BA[0] DDR1_DATA[3] F8 DDR1_BA[1] DDR1_DATA[4] H3 DDR1_BA[2] DDR1_DATA[5] H8 DDR1_DATA[6] G2 DDR1_DATA[7] H7 AF9 DDR1_DATA[8] D7 AE26 DDR1_DATA[9] C3 DDR1_DATA[10] C8 DDR1_DATA[11] C2 DDR1_DATA[12] A7 AC13 DDR1_DATA[13] A2 AC14 DDR1_DATA[14] B8 DDR1_DATA[15] A3 AE23 AF12 AD10 R216 +0.75V_VREF1_D0 +0.75V_VREF1_D1 DDR1_RESET_N 240 1% AC11 +1.5VQ1 AC15 K2 K8 N1 N9 R1 R9 NC_2 NC_4 DQSL A8 C1 C9 D2 E9 F1 H2 H9 J1 NC_1 J9 L1 L9 T7 NC_6 A9 DQSU VSS_1 DQSU VSS_2 VSS_3 E7 DDR1_DM[0] AE12 G7 A1 VDDQ_1 C7 DDR1_DM[1] AE15 D9 DQSL F7 AE20 +1.5VQ1 VDD_9 CK F3 G3 1% BA1 RESET DDR1_CLK AF17 AD26 VDD_7 VDD_8 T2 DDR1_CLKN 240 B2 NC_3 AE22 R223 L8 ZQ A7 WE DDR1_RESET_N DML VSS_4 DMU VSS_5 VSS_6 DQL0 VSS_7 DQL1 VSS_8 DQL2 VSS_9 DQL3 VSS_10 DQL4 VSS_11 DQL5 VSS_12 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 DQL6 DQL7 AC16 B1 VSSQ_1 DQU0 VSSQ_2 DQU1 VSSQ_3 DQU2 VSSQ_4 DQU3 VSSQ_5 DQU4 VSSQ_6 DQU5 VSSQ_7 DQU6 VSSQ_8 DQU7 VSSQ_9 B9 D1 D8 E2 E8 F9 G1 G9 AC17 AC18 AC19 AC20 AC21 AC22 DDR3 1.5V/0.75V Decap - Place these caps near IC100 +0.75V_VREF0_D1 +0.75V_VREF1_D0 +0.75V_VREF1_D1 +1.5VQ1 DDR3 1.5V beCaps - Place these caps near Memory C209 C210 0.1uF 0.1uF C235 0.1uF C236 0.1uF C237 C238 C241 C242 C244 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF DDR0 PHY VREF +1.5VQ0 +0.75V_VREF0_M0 +1.5VQ0 DDR1 PHY VREF +0.75V_VREF0_M1 +1.5V +1.5VQ0 +0.75V_VREF1_M0 +1.5VQ1 R212 1K 1% R207 1K 1% R203 1K 1% +1.5VQ1 +0.75V_VREF1_M1 R204 1K 1% C212 0.1uF +1.5VQ0 C213 1000pF R208 1K 1% +0.75V_VREF0_D0 C216 0.1uF C218 1000pF +1.5VQ0 C219 4.7uF 10V C222 4.7uF 10V +0.75V_VREF0_D1 R217 1K 1% L201 MLB-201209-0120P-N2 R213 1K 1% C224 0.1uF R209 R214 1K 1% 1K 1% 1K 1% R206 1K 1% C214 0.1uF C215 1000pF C217 0.1uF R210 1K 1% C220 0.1uF C221 1000pF C223 0.1uF C225 1000pF R218 1K 1% +0.75V_VREF1_D0 +1.5VQ1 R205 C211 0.1uF +1.5VQ1 +1.5V L200 MLB-201209-0120P-N2 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes A5 L2 R221 DDR1_DATA[14] K7 K9 DDR1_CKE DDR1_DATA[12] H1 VREFDQ A4 BA2 DDR1_CLKN C204 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. A3 J7 100 1% R222 AF19 AD19 M3 DDR1_BA[2] DDR1_CLK DDR1_DATA[11] AE16 N8 DDR1_BA[1] DDR3 1.5V Decaps - Place these caps near Memory C206 A2 M2 DDR1_BA[0] VREFCA A1 A15 AD15 DDR1_VDDQ_1 DDR1_VDDQ_2 M8 A0 M7 AC12 DDR0_VDDQ_2 L7 T3 AE10 DDR1_ZQ_CAL K23 F9 AE9 AF22 DDR0_VDDQ_1 E8 +1.5VQ0 DDR1_A[0] DDR0_A[1] DDR0_ZQ_CAL B9 D8 DDR0_A[0] J26 DDR0_CLK T7 NC_6 C7 B7 T26 U24 R9 DQSL DDR0_DQS[1] DDR0_DATA[0] DDR0_DATA[1] F3 DDR0_DQS_N[1] DDR0_DATA[0-15] H26 DDR0_A[11] K2 DDR0_DATA[2] NC_3 DDR0_DQS_N[0] DDR0_A[10] G7 VDD_9 RESET G3 D9 BA1 BA0 T2 DDR0_DQS[0] +1.5VQ0 L24 WE DDR0_RESET_N 1% B2 A9 L2 DDR0_ODT R202 240 A7 J7 DDR0_CLK F26 DDR0_A[2] H1 VREFDQ M2 N8 AB25 DDR0_A[1] DDR0_A[3] A3 A15 DDR0_BA[1] DDR0_A[0] A4 A2 M7 DDR0_BA[0] +0.75V_VREF1_M1 M8 A0 C228 0.1uF C230 1000pF +1.5VQ1 C231 4.7uF 10V C234 4.7uF 10V +0.75V_VREF1_D1 R219 1K 1% R215 1K 1% C226 0.1uF C227 1000pF C229 0.1uF R220 1K 1% C232 0.1uF C233 1000pF 240Hz Back-End Board LG1122_DDR3 2011. 07. 05 2 6 LGE Internal Use Only FRC-III AIP for 1.8V FRC-III CORE for 0.9V TYP 0.278A TYP 2.521A MAX 0.345A MAX 3.124A VLCD_POWER (+12V) VLCD_POWER (+12V) L302 L306 MLB-201209-0120P-N2 MLB-201209-0120P-N2 +1.8V C300 0 C309 C311 0.1uF 10uF 10uF 16V 25V OPT 25V [EP]GND 10K 22pF 1% VFB Vout=0.765*(1+R1/R2) VREG5 R2 1 2 8 9 30K THERMAL EN 50V R300 7 6 SS 22K 1% 4 5 25V C334 100pF GND C312 C315 C301 C303 22uF 22uF 1uF 3300pF 10V 10V 25V 50V L304 3.6uH [EP]LX NR8040T3R6N R1 L300 3.6uH SW +0.9V IC302 AOZ1038PI PGND NR8040T3R6N R301 10uF 25V +1.8V C305 0.1uF 16V 3 C326 10uF +0.9V VIN VBST OPT C328 50V OPT VIN R316 0 C322 R306 0.1uF 4.7K 16V AGND FB 1% 1 2 8 9 R304 R313 C307 THERMAL IC300 TPS54327DDAR R1 7 NC_2 +3.3V NC_1 R310 3 6 4 5 EN COMP C332 C336 22uF 22uF 3300pF 10V 10V 50V OPT 10K R312 3.3K R2 C329 C320 4700pF 50V R307 22K 1% tss(ms)=[C303(nF)*Vref]/Iss(uA) Vout=0.8*(1+R1/R2) FRC-III DDR3 for 1.5V FRC-III I/O for 3.3V TYP 1.149A TYP 0.043A MAX 1.184A MAX 0.046A VLCD_POWER (+12V) VLCD_POWER (+12V) L307 MLB-201209-0120P-N2 +1.5V L303 +3.3V +3.3V MLB-201209-0120P-N2 R302 100pF 10K 50V EN 18K 1% VFB Vout=0.765*(1+R1/R2) R2 VREG5 1 2 3 8 7 C310 R308 C313 0.1uF 10uF 10uF 16V 25V OPT 25V VIN 68K 1% R315 VBST +1.5V SS C302 1uF 25V 4 5 22pF 10K C306 SW L301 3.6uH 50V EN VFB R2 VREG5 1 2 8 C316 C304 22uF 22uF 0.01uF 10V 10V 1% 50V tss(ms)=[C304(nF)*Vref]/Iss(uA) C330 10uF 10uF 16V 25V OPT 25V 7 VBST 3 6 4 5 SW +3.3V C323 0.1uF 16V L305 3.6uH NR8040T3R6N SS 22K C314 C327 0.1uF VIN R309 GND C325 [EP]GND 1% NR8040T3R6N 1% R311 Vout=0.765*(1+R1/R2) R303 22K C318 5.1K 0.1uF 16V 6 IC303 TPS54327DDAR R1 C308 [EP]GND 9 1% R305 9 3.6K C335 THERMAL R314 THERMAL IC301 TPS54327DDAR R1 C319 C321 1uF 0.01uF 25V 50V GND C331 C333 22uF 22uF 10V 10V OPT tss(ms)=[C321(nF)*Vref]/Iss(uA) LG1122(FRC-III) Power up Sequence Ton_DIO 20us(min) Analog I/O Power +1.8V Digital I/O Power +3.3V DDR3PHY Power +1.5V Ton_DDR 40us(min) Ton_CORE 40us(min) Core Power THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes +0.9V 120Hz Back-End Board POWER 2011. 07. 05 3 6 LGE Internal Use Only IC401 LGE5812B IC401 LGE5812B [All of OPT decaps must be placed on PCB Bottom side] +3.3VDD TX0P A13 TX0N B13 TX1P A12 TX1N B12 TX2P A11 TX2N B11 TX3P A10 TX3N B10 TX4P A9 TX4N B9 TX5P A8 TX5N B8 TX6P A7 TX6N B7 TX7P A6 TX7N B6 SOE 2. AGP_EN - NO input indicator LOW : Normal HIGH : No input LLV0P RX0N LLV0N RX1P LLV1P RX1N LLV1N RX2P LLV2P RX2N LLV2N RX3P LLVCLKP RX3N LLVCLKN RX4P LLV3P RX4N LLV3N RX5P LLV4P RX5N LLV4N RX6P LLV5P RX6N LLV5N RX7P 33 L1 GSP R403 33 M1 GOE R404 33 N2 GSC R405 33 N1 POL R406 33 E2 FLK R407 33 F1 DPM R408 33 F2 H_CONV R409 33 M2 OPT_P R410 33 D1 OPT_N R411 33 E1 LRV0P LRV0N SOE LRV1P GSP LRV1N GOE LRV2P GSC LRV2N POL LRVCLKP FLK LRVCLKN DPM LRV3P H_CONV LRV3N OPT_P LRV4P OPT_N LRV4N LRV5P B4 R412 A2 33 A4 OPT AGP_EN 3D_EN B3 3D_LR A3 R413 RBF RLV0P 3D_EN RLV0N 3D_LR_IN RLV1P RLV1N P1 15K RMLVDS RLV2P TMODE0 RLVCLKP TMODE1 RLVCLKN TMODE2 RLV3P TMODE3 RLV3N TMODE4 RLV4P TMODE5 RLV4N TMODE6 RLV5P TMODE7 RLV5N 1% 3. 3D_EN - 2D/3D mode selection LOW : 2D mode HIGH : 3D mode M18 L17 L18 4. 3D_LR - Left/Right frame Indicator LOW : Left HIGH : Right K17 K18 J17 J18 H17 H18 R400 10K JTP-1127WEM TMODE8 TCON_SCL R414 33 F18 TCON_SDA R415 33 F17 I2C_SCL_S R416 33 E18 I2C_SDA_S R417 33 E17 RRV0P RRV0N SCL_M RRV1P SDA_M RRV1N SCL_S RRV2P SDA_S RRV2N RRVCLKP C18 TCON_RST RST_N RRVCLKN RRV3P G17 EEP_ADDR = HIGH -> EEPROM Address = 0xA6 WP_EEPROM_TCON R418 R426 G18 33 3.9K 1% No USE(NC at Rx side) TX_LOCK R425 33 EEP_ADDR RRV3N WP RRV4P RRV4N A15 D18 D17 U1 VX1_RBG RRV5P HPD_VX1 RRV5N E16 LLV1N U2 F3 LLV2P V2 F16 LLV2N T2 G3 LLVCLKP T3 G16 LLVCLKN V3 H3 LLV4P U3 H16 LLV4N U4 J3 LLV5P V4 J16 LLV5N T4 K16 LLV6P T5 +3.3AVDD_TX LLV6N R7 R8 LRV0N U6 R9 LRV1P V6 R10 LRV1N T6 R11 LRV2P T7 R12 LRV2N V7 R13 LRVCLKP U7 +1.0VDD LRVCLKN U8 G12 LRV4N T8 H7 LRV5P T9 H12 LRV5N V9 J7 LRV6P U9 J12 LRV6N K7 K12 RLV0P V10 L7 RLV0N T10 L12 RLV1P T11 M7 RLV1N V11 M8 RLV2P U11 M9 RLV2N U12 M10 RLVCLKP V12 M11 RLVCLKN T12 M12 RLV4P T13 +3.3AVDD_PLL RLV4N V13 C12 +1.0VDD RRV0N G9 RRV1N U16 G10 RRV2P V16 G11 RRV2N T16 RRVCLKP T17 L10 RRV4P U17 L11 RRV4N U18 L14 RRV5P T18 L15 RRV5N R17 L16 RRV6P R18 M4 RRV6N M5 LOCKN_VX1 M14 D2 C1 K3 L3 M3 N3 N17 N18 M17 M15 GPIO0 M16 GPIO1 N4 GPIO2 N5 GPIO3 N14 GPIO4 N15 GPIO5 P2 GPIO6 P3 GPIO7 P4 GPIO8 P5 K1 K2 J1 J2 H1 H2 G1 G2 L2 GND_44 VDD33_7 GND_45 VDD33_8 GND_46 VDD33_9 GND_47 VDD33_10 GND_48 VDD33_11 GND_49 VDD33_12 GND_50 VDD33_13 GND_51 GND_52 AVDD33_TX_1 GND_53 AVDD33_TX_2 GND_54 AVDD33_TX_3 GND_55 AVDD33_TX_4 GND_56 AVDD33_TX_5 GND_57 AVDD33_TX_6 GND_58 AVDD33_TX_7 GND_59 AVDD33_TX_8 GND_60 GND_61 VDD10_1 GND_62 VDD10_2 GND_63 VDD10_3 GND_64 VDD10_4 GND_65 VDD10_5 GND_66 VDD10_6 GND_67 VDD10_7 GND_68 VDD10_8 GND_69 VDD10_9 GND_70 VDD10_10 GND_71 VDD10_11 GND_72 VDD10_12 GND_73 VDD10_13 GND_74 VDD10_14 GND_75 VDD10_15 GND_76 VDD10_16 GND_77 GND_78 P6 NC1 P7 NC2 P8 NC3 P9 NC4 P10 NC5 P11 NC6 P12 NC7 P13 NC8 P14 NC9 P15 P16 P17 P18 R3 I2C Slave Address : 0x70 R4 R5 R14 R15 R16 GND_79 GND_80 GND_81 GND_82 AVDD33_VX1_1 GND_83 AVDD33_VX1_2 GND_84 GND_85 AVDD10_VX1_1 GND_86 AVDD10_VX1_2 GND_87 AVDD10_VX1_3 GND_88 AVDD10_VX1_4 GND_89 GND_90 L9 RRVCLKN V17 GND_43 VDD33_6 G8 RRV1P U15 VDD33_5 C11 RRV0P V15 GND_42 VDD10_PLL +3.3AVDD_VX1 RLV6N T15 VDD33_4 A17 RLV6P V14 GND_41 AVDD33_PLL +1.0VDD_PLL RLV5N U14 GND_40 VDD33_3 B18 RLV5P U13 GND_39 VDD33_2 G7 LRV4P V8 A5 VDD33_1 R6 LRV0P U5 T14 TMODE9 SW400 VCC_LCM (+3.3V) RLV2N N16 E3 LLV1P U10 AGP_EN D16 LLV0N T1 LRV5N LR_IND_OUT D3 LLV0P R2 V5 RX7N R402 RBF 1. RBF - Pattern selection of No Video input LOW : Rolling Pattern HIGH : Black Pattern R1 RX0P GND_1 GND_91 GND_2 GND_92 GND_3 GND_93 GND_4 GND_94 GND_5 GND_95 GND_6 GND_96 GND_7 GND_97 GND_8 GND_98 GND_9 GND_99 GND_10 GND_100 GND_11 GND_101 GND_12 GND_102 GND_13 GND_103 GND_14 GND_104 GND_15 GND_105 GND_16 GND_106 GND_17 GND_107 GND_18 GND_108 GND_19 GND_109 GND_20 GND_110 GND_21 GND_111 GND_22 GND_112 GND_23 GND_113 GND_24 GND_114 GND_25 GND_115 GND_26 GND_116 GND_27 GND_117 GND_28 GND_118 GND_29 GND_119 GND_30 GND_120 GND_31 GND_121 GND_32 A14 A16 B1 B2 +3.3AVDD_PLL Decaps B5 B14 B15 VCC_LCM (+3.3V) +3.3AVDD_PLL +3.3AVDD_PLL B16 B17 C2 L400 MLB-201209-0120P-N2 C3 C4 C5 C6 C407 4.7uF 10V C401 4.7uF 10V C413 0.1uF 16V C7 C8 C9 C10 C13 C14 C15 C16 C17 D4 +1.0VDD_PLL Decaps D5 D6 D7 VCORE (+1.0V) +1.0VDD_PLL +1.0VDD_PLL D8 D9 D10 L401 MLB-201209-0120P-N2 D11 D12 D13 D14 C402 4.7uF 10V C408 4.7uF 10V C414 0.1uF 16V D15 E4 E5 E6 E7 E8 E9 E10 E11 E12 +3.3VDD Decaps E13 E14 E15 VCC_LCM (+3.3V) +3.3VDD F4 F5 F14 L402 MLB-201209-0120P-N2 F15 G4 G5 G14 C409 0.1uF 16V C403 0.1uF 16V G15 H4 H5 H8 H9 H10 H11 H14 H15 J4 +3.3AVDD_TX Decaps J5 J8 J9 VCC_LCM (+3.3V) +3.3AVDD_TX J10 J11 J14 L403 MLB-201209-0120P-N2 J15 K4 K5 K8 C410 0.1uF 16V C404 0.1uF 16V K9 K10 K11 K14 K15 L4 L5 L8 +1.0VDD Decaps GND_33 GND_34 VCORE (+1.0V) GND_35 GND_36 GND_37 +1.0VDD L404 MLB-201209-0120P-N2 GND_38 C405 4.7uF 10V C411 4.7uF 10V [T-Con EEPROM(32KBIT)] VCC_LCM (+3.3V) [T-Con EEPROM Debug] P400 12507WR-03L R401 10K R420 10K IC400 AT24C32D-SSHM-T A0 1 8 VCC +3.3AVDD_VX1 Decaps C400 R421 10K OPT R423 2K 1 R424 2K VCC_LCM (+3.3V) 2 0.1uF A1 A2 GND 2 7 3 6 4 5 +3.3AVDD_VX1 TCON_SDA 16V L405 MLB-201209-0120P-N2 WP 3 WP_EEPROM_TCON SCL 4 TCON_SCL TCON_SCL C406 0.1uF 16V C412 0.1uF 16V SDA TCON_SDA R422 10K I2C Slave Address : 0xA6 - Write Protection HIGH : Write Protection LOW or NC : Normal Operation THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 240Hz Back-End Board 240Hz T-Con(LG5812) 2011. 07. 05 4 6 LGE Internal Use Only [PMIC Block] SWB PANEL_VCC (+12V) VCC_LCM (+3.3V) R514 0 VL (+5V) L503 22uH R506 150K 1% R533 0 2.2A C514 10uF 25V C510 10uF 25V D503 SMAB34 40V C532 1uF 25V C536 22uF 10V C540 0.1uF 50V C538 22uF 10V R536 5.1K TCOMP C527 0.1uF 50V PANEL_VCC (+12V) 28 SCL PVINB12_1 BST1 SWB1_2 SWB1_1 NC_4 VLOGIC1 SWB2 PGND2 37 36 35 34 33 32 31 MAX17139 25 NC_3 BST3 7 24 CTRLN SWB3 8 23 NC_2 9 22 VGL 10 21 VGH SWO NC_1 0 VGL (-5V) VCC_LCM (+3.3V) R523 I2C_SDA_S 33 R521 I2C_SCL_S R531 10K 33 TCON_RST Q501 2SC3052 VGH_S (+27V) E 20 VGL_FB R532 VCC_LCM (+3.3V) D504 1N4148W D505 1N4148W 100V 100V C B 680 C546 0.22uF 50V OPT C548 0.22uF 50V C547 0.22uF 50V OPT C549 0.22uF 50V 0 C552 10uF 25V C553 10uF 25V R545 3.6K 1/10W VCC_LCM (+3.3V) R542 2K 1/8W 1% OPT R543 0 OPT R526 10K OPT C551 0.1uF 50V OPT VDD_LCM (+16.8V) CTRLP R518 33K C525 2200pF 50V R544 R541 0 VGL_FB R525 10K C524 0.1uF 50V C522 120pF 50V C537 10uF 25V 33 CTRLP SWI 11 SS SW_2 PGND3 C516 0.01uF 50V 19 6 18 PVINB3 17 RST 16 26 15 A0 IC501 14 27 5 13 4 0 C534 10uF 25V R522 3 SW_1 R515 SDA VL 0 C505 10uF 25V VLOGIC2 29 AVIN OUT3 C504 10uF 25V 30 AGND PGND_2 R508 R527 2.2uH THERMAL 41 PGND_1 L501 10uH 3.1A 2 38 [EP]AGND C517 0.1uF 50V 1 12 C509 1uF 25V HVDD (+8.4V) EN1 TCOMP PVINB12_2 40 TCOMP COMP VL (+5V) NC_5 C515 1uF 25V 39 R516 0 R507 2.7K VCORE (+1.0V) L502 LQM2HPN2R2MG0L 120K SWB R509 TH500 47k-ohm R535 PANEL_VCC (+12V) 0 C531 10uF 25V C533 10uF 25V C535 10uF 25V R538 9.1K 1/8W R503 0 L500 22uH D502 SMAB34 40V C502 10uF 25V C501 10uF 25V R513 2.2 C521 10uF 25V C519 0.1uF 50V C513 C523 10uF 25V 1000pF C507 0.47uF 50V 100V 1/10W Q500 MMBT3906(NXP) R519 C R510 10 VGH_S (+27V) C508 0.47uF 50V D501 1N4148W E D500 1N4148W 0 100V C511 0.1uF 50V to prevent inrush current B VDD_LCM (+16.8V) C528 4.7uF 50V R517 680 C530 4.7uF 50V R520 18K 1/10W R524 18K 1/10W CTRLP C512 0.1uF 50V [P-Gamma Block] GMA14 I2C_SCL_S PANEL_POWER HVDD (+8.4V) R539 R558 1.8K PANEL_CTL_FRC 50V GPM_ON R512 OPT R537 GMA1 VDD_LCM (+16.8V) HVDD GM7 GM8 NC_1 16 17 18 IC503 BUF08630 15 GM6 14 GM5 13 GM4 12 GM3 11 GM2 GMA16 GMA15 GMA9 GMA7 GMA6 10 0xE8 5 9 4 8 3 VCOM_GND VCOM_OUT GMA2 SCL HVDD GM7 GM8 EP[GND] C554 1uF 10V R548 10K GMA3 19 16 17 18 19 SCL NC_1 GMA4 DVDD THERMAL 21 GMA5 0 PANEL_CTL PANEL_CTL_FRC Q502 MMBT3904(NXP) PANEL_CTL_FRC B E R529 0 R530 10 R540 10K C543 4.7uF 50V Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 11 GM2 2 R552 0 VCOMOUT R553 0 VCOMFB C R556 10K THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 20 C564 0.1uF 50V VDD_LCM (+16.8V) C500 56pF G PANEL_CTL_FRC GM3 1 A0 GM1 DPM 12 SDA BKSEL 5 0xEA 5 13 GMA10 AVDD_1 4 IC502 BUF08630 R549 33 7 33 VDD C562 0.1uF 50V OPT 4 VCOM_OUT GM4 I2C_SDA_S GMA12 6 R505 C561 10uF 16V R557 10K PANEL_CTL_FRC 3 VCOM_GND 14 GM5 10 VDPM R511 0 1/10W GPM_ON C542 1uF 10V GM6 AVDD_AVDD 6 GPM_ON CE Q503 AO3407A PANEL_CTL_FRC 15 C558 1uF 25V VCOM_FB 3 R504 OPT DVDD VCC_LCM (+3.3V) GM1 RE GND 2 9 15K 1% GPM_ON 7 THERMAL 21 BKSEL R500 2 10K S VGH_M R555 0 GPM_ON 1 A0 8 GPM_OFF SDA 7 C559 0.01uF 50V C560 0.1uF 50V 33 AVDD_1 VDD_LCM (+16.8V) I2C_SDA_S R528 AVDD_AVDD VCC_LCM (+3.3V) CIS21J121 PANEL_CTL_MAIN 6 8 VFLK L505 VCOM_FB 1 GPM_ON R534 C563 OPT 1uF 25V VGH 0 FLK D R554 C550 1uF 25V EP[GND] VCC_LCM (+3.3V) R502 33 GPM_ON IC500 KIA3820FK VGH_S (+27V) 33 PANEL_VCC GSC VGH (+27V) R550 33 VLCD_POWER (+12V) OPT R501 33 GMA17 HVDD (+8.4V) 20 [GPM Block] GMA18 I2C_SCL_S GMA13 C544 4.7uF 50V R546 0 R547 10 R551 10K C555 4.7uF 50V C545 0.1uF 50V 240Hz Back-End Board PMIC/GAMMA/GPM C556 4.7uF 50V C557 0.1uF 50V 2011. 07. 05 5 6 LGE Internal Use Only [80P mini-LVDS output wafer] VDD_LCM (+16V) [51P HS-LVDS input wafer] P600 +3.3V FI-RE51S-HF-J-R1500 1 L/DIM0_SCLK C620 L/DIM0_MOSI 0.1uF 50V G 2 3 C602 0.1uF 50V 6 P602 104060-8017 Q600 2N7002K R600 33 OPT LG1122_RST 7 8 FLASH_WP 9 PWM_BPL 10 +3.3V 11 12 RXA0N VDD 1 GND 2 VDD 2 LLV0+ 3 GND 3 LLV0- 4 VCC 4 LLV1+ 5 LLV1- 6 LLV2+ 7 LLV2- 8 GND 9 LLVCLK+ 10 LLVCLK- 11 GND 12 LLV3+ 13 LLV3- 14 LLV4+ 15 LLV4- 5 VCC 6 GND 7 HVDD 8 HVDD 9 GND VGL GND 13 GOE 14 GSC 15 GND 16 VGH 16 LLV5+ 17 GND 17 LLV5- 18 RVCOM_FB VCOMFB 18 GND VCOMOUT 19 LRV0+ 20 LRV0- 21 LRV1+ VCOM_R 20 GND 21 ZOUT 22 GND 23 GMA1 24 GMA2 25 GMA3 26 GMA4 27 GMA5 28 GMA6 29 GMA7 30 GMA9 31 GMA10 32 GMA12 S D G 19 0.1uF 50V 17 Q601 2N7002K RXA2P 18 R601 19 20 33 OPT RXACLKN RXACLKP 21 22 RXA3N 33 GMA13 23 RXA3P 34 GMA14 35 GMA15 36 GMA16 37 GMA17 38 GMA18 39 GND 40 GSP 24 RXA4N 25 RXA4P 26 27 41 POL 28 RXB0N 42 GND 29 RXB0P 43 SOE 44 H_CONV RXB1N 45 OPT_N RXB1P 46 GND 47 RLV0+ 30 31 32 RXB2N 48 RLV0- 33 RXB2P 49 RLV1+ 50 RLV1- 51 RLV2+ 52 RLV2- 53 GND 54 RLVCLK+ 55 RLVCLK- 56 GND 34 35 RXBCLKN 36 RXBCLKP 37 38 RXB3N 57 RLV3+ 39 RXB3P 58 RLV3- 59 RLV4+ 60 RLV4- 61 RLV5+ 62 RLV5- 63 GND 64 RRV0+ 65 RRV0- 66 RRV1+ 67 RRV1- 68 RRV2+ 69 RRV2- 70 GND 71 RRVCLK+ 72 RRVCLK- 73 GND 74 RRV3+ 75 RRV3- 76 RRV4+ 77 RRV4- 78 RRV5+ 79 RRV5- 80 GND 40 RXB4N 41 RXB4P 42 43 44 VLCD_POWER 45 (+12V) 46 47 L600 MLB-201209-0120P-N2 48 49 50 C600 10uF 25V C601 10uF 25V 51 52 VGL (-5V) 12 C621 I2C_SCL_S C610 0.01uF 50V 11 RXA1N RXA2N C607 0.1uF 50V 10 RXA0P RXA1P HVDD (+8V) OPT_P 14 16 VCC_LCM (+3.3V) 1 13 15 C605 10uF 25V P601 I2C_SDA_S S D 5 C604 10uF 25V 104060-8017 L/DIM0_VS 4 C603 10uF 25V OPT_P GOE GSC VGH (+27V) Z_OUT 22 LRV1- GMA1 23 LRV2+ GMA2 24 LRV2- GMA3 25 GND GMA4 26 LRVCLK+ GMA5 27 LRVCLK- GMA6 28 GND GMA7 29 LRV3+ GMA9 30 LRV3- GMA10 31 LRV4+ GMA12 32 LRV4- GMA13 33 LRV5+ GMA14 34 LRV5- GMA15 35 GND GMA16 36 OPT_N GMA17 37 H_CONV GMA18 38 GSP 39 POL GSP 40 GND POL 41 SOE 42 GND SOE 43 GMA1 H_CONV 44 GMA2 OPT_N 45 GMA3 46 GMA4 RLV0P 47 GMA5 RLV0N 48 GMA6 RLV1P 49 GMA7 RLV1N 50 GMA9 RLV2P 51 GMA10 RLV2N 52 GMA12 53 GMA13 RLVCLKP 54 GMA14 RLVCLKN 55 GMA15 56 GMA16 RLV4P 57 GMA17 RLV4N 58 GMA18 RLV5P 59 GND RLV5N 60 GND RLV6P 61 ZOUT RLV6N 62 GND 63 VCOM_L RRV0P 64 LVCOM_FB RRV0N 65 GND RRV1P 66 VGH RRV1N 67 GND RRV2P 68 GSC RRV2N 69 GOE 70 GND RRVCLKP 71 VGL RRVCLKN 72 GND 73 HVDD RRV4P 74 HVDD RRV4N 75 GND RRV5P 76 VCC RRV5N 77 VCC RRV6P 78 GND RRV6N 79 VDD 80 VDD 81 LLV0P LLV0N LLV1P LLV1N LLV2P LLV2N LLVCLKP LLVCLKN LLV4P LLV4N LLV5P LLV5N LLV6P LLV6N LRV0P LRV0N LRV1P LRV1N LRV2P LRV2N LRVCLKP LRVCLKN LRV4P LRV4N LRV5P LRV5N LRV6P LRV6N OPT_N H_CONV GSP POL SOE GMA1 GMA2 GMA3 GMA4 GMA5 GMA6 GMA7 GMA9 GMA10 GMA12 GMA13 GMA14 GMA15 GMA16 GMA17 GMA18 Z_OUT VGH (+27V) VCOMOUT VCOMFB VGL (-5V) GSC GOE HVDD (+8V) VCC_LCM (+3.3V) C616 0.1uF 50V 81 C618 0.01uF 50V VDD_LCM (+16V) C614 10uF 25V [RIGHT FFC CONNECTOR] THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes C615 10uF 25V C617 10uF 25V C619 0.1uF 50V [LEFT FFC CONNECTOR] 240Hz Back-End Board Wafer 2011. 07. 05 6 6 LGE Internal Use Only Revision History ------------------------------------------------------------------------------------------------(0) Proto Design 1.73V 0.53V 1.13V R100 10K R104 1.8K R102 4.7K TP104 TP102 0.09V R106 270 TP106 TP108 SW100 SW102 SW104 SW106 JTP-1127WEM JTP-1127WEM JTP-1127WEM JTP-1127WEM 1 GND 2 KEY2 3 GND 4 TP101 KEY1 TP100 P100 12507WR-04L OPT ZD100 5.6B 1 2 1 2 1 2 1 2 3 4 3 4 3 4 3 4 KEY1 VOL- VOL+ ENTER MENU KEY2 OPT ZD101 5.6B 5 1.54V R101 10K R103 4.7K TP103 0.09V 0.51V 1.03V R105 1.8K R107 270 TP109 TP107 TP105 SW101 SW103 SW105 SW107 JTP-1127WEM JTP-1127WEM JTP-1127WEM JTP-1127WEM 1 2 1 2 1 2 1 2 3 4 3 4 3 4 3 4 CH+ CH- POWER INPUT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only LCD TV Repair Guide `12 years New Models < Applicable Model > XXLM960V-ZB XXLM860V-ZB V : T2/C/S2 T : T2/C S : T/C/S2 0 : T/C Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only 2 types of LED - Edge Benefit: More Clear More Real Feature Edge Type w/ Local Dimming Edge LED Best picture quality + thin TV Local Local dimming depicts more Dimming deep black. LED Array BLU structure Upper Metal Cover Model LED Array is on the side of Module Local Dimming Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes XXLW750T/W/S/G 42inch : H(2) * V(8) = 16Block 42inch : H(2) * V(8) = 16Block 42inch : H(2) * V(8) = 16Block LGE Internal Use Only 2 types of LED - ALEF Benefit: More Clear More Real Feature ALEF Type Local Dimming ALEF LED` Best picture quality + thin TV Slimmer depth better picture quality Local Local dimming depicts more Dimming deep black. DBEF Prism sheets Diffuser plate BLU structure Light Blocking Pattern Guiding Layer Reflecting coating w/patterns PCB LED Array is on the back of Module Model XXLM960V 47inch : H(6) * V(4) = 24Block 55inch : H(6) * V(4) = 24Block Local Dimming Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Main PCB for Broadband XXLM960V-ZB XXLM860V-ZB Main + TCON all in one Local Dim. Woofer Spk 3 4 To PSU 1 1 To FRC BOARD 6 2 wifi Motion assy Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 2 Main processor_analog(LG1152A) 3 Micom for Key/IR sensing 4 Audio AMP (10W+10W) 5 HDMI switch (4:1) 6 3D Depth Control IC, DDR Memory 5 Local Key +IR Front Spk Main processor_Digital(LG1152D), DDR Memory Flash Memory 4 LGE Internal Use Only FRC Board for Broadband Main + TCON all in one XXLM960V-ZB From Main Board 1 FRC Processor(LG1122) 2 T-Con IC(LG5812) 1 2 To Pannel ( Left ) Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes To Pannel ( Right ) LGE Internal Use Only Block Diagram TS In(CHB) CVBS(CHB) SIF(1 Ch) DTV TS L9A AUD L9D SPIDF_OUT Built-in WiFi BB_TP_DATA Audio L/R (5 Ch) EB_DATA CI Slot Line-Out SCART I2S 16 CHB_DATA 16 CVBS (8 Ch) DDR3 X 3 16 CVBS-Out SCART 8 DAC_DATA eMMC Component (2 Ch) USB2.0x3 HDMI1 HDMI2 HDMI SW HDMI3 HDMI (1 Ch) AAD_DATA RMII PHY Ethernet HDMI4 TXA/B 51Pin LVDS HSR_P/M PC-RGB (WUXGA) Keypad MICOM IR M-Remote_R/TX Motion-R Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Jack Interface COMP_Y+/Pb+/Pr+ AV_CVBS_IN COMP_DET AV_L/R_IN AV_CVBS_DET SPDIF_OUT SPDIF PC_L/R_IN SC_DET PC_Audio HP_L/ROUT Earphone Block SC_CVBS_IN SC_FB/ID_IN 2bit SC_R/G/B 3bit SC_L/R_IN Main Chip EEPROM IC802/ R1EX24002ASAS0A EDID_WP MICOM RGB_DDC_SCL/SDA 2bit DSUB_R/G/B 3bit DSUB_DET DTV/ATV_SELECT RGB DTV/MNT_V_OUT SCART MUX IC2502 ATV_OUT Tuner Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only L9 Block diagram Analog Chip DIF ATSC Half NIM GBB AFE 1ch@30MHz w/ PLL SIF Digital Chip 4(val, err, clk, sop) +8 (data) Parallel TS Global Baseband V/Q, DVB-T/C System Demux Video Decoder (Dual HD) AAD (THAT) H.264 Encoder SD upto 480p 10(data)+1(en)+5(gc) BTSC AFE [email protected] w/ PLL 3(lrck, lrch, sck) SW 1ch L/R Audio-ADC 24b@48KHz Audio Codec1 (Digital Part) Audio I2S (mono) Mux Audio L/R (5-ch) 1ch mono Audio-ADC 24b@48KHz Audio Codec0 (Digital Part) Audio DSP Sound Multi-STD DSP Audio Decoder I2S(stero) (Headphone) I2S Digital Audio Output CPU Dual C-A9 (1GHz) I2S SPDIF 3(lrck, lrch, sck) Graphic Engine 2D-VG / 3D Open-ES2.0 Tuner_CVBS Component(2ch) PC-RGB HDMI(1ch) ARC (1ch) SW CVBS AFE(2-ch) 12b@54MHz 3ch Video AFE 10b@165MHz w/ LLPLL HDMI-Rx 1.4 HDMI (1-port PHY) (1-Link) 3D, ARC, 4kx2k 12 : CVBS Video Capture Block (3CH) 3D or UD Data bridge LVDS 12 LVDS LVDS 12 8 9 I2C I2C LVDS OSD I2S or SPDIF Audio Audio Clocks 6(gbb, l9da) I2C interrupt Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes MC NR, Vertical MC IPC Scaler, PE OSD, VCR LVDS 1 (ARC data) Audio PLL w/ DCO LVDS Mux SW Mux CVBS(6ch) Video Diplay Engine I2C Ethernet MAC USB2.0 Host (x3) DDR3(x16) * 3 eMMC Controller PHY (3-port) DDR3-PHY 3(hdmi, 3ch, gbb) LGE Internal Use Only L9 Block diagram 30/48 Mhz 2 port USB PHY Clock Divide & Reset generation w/ test logic 30/48Mhz 1 port USB PHY USB controller u_crg CPU 1 Ghz DDR3PLL SSC setting - 0xFD3001D4 - 0xFD3001D8 Clock Divide & Reset generation w/ test logic Memory Controller Clock Divide & Reset generation w/ test logic Memory Controller Clock Divide & Reset generation w/ test logic Memory Controller xi_main xo_main 0 1 SSC setting - 0xFD3001CC - 0xFD3001D0 CT R 0 1 1.6Ghz DDR3PLL1 24Mhz 1.6Gh z i_m01_ddrclk 1.6Ghz i_m2_ddrclk 800Mhzi_core800_clk 0 1 DDR3PLL2 1.6Ghz SSC setting - 0xFD3001C4 - 0xFD3001D8 1/2 Video/Audio Block CPU peripherial 800Mhzi_core320_clk 1/5 Clock Divide & Reset generation w/ test logic dcoin_clk DCO 200Mhz 200Mhz 27Mhz sdec_dco_o ut Glitch-free logic between de_dco_out and sdec_dco_out CT R 0 1 DCO de_dco_ou t SSC setting -0xFD300108 27Mhz -0xFD30010C DISPLL udnt_buf_dpll_fin 27Mhz 27Mhz About 220 internally generated clocks Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes disp_fout Clock Divide & Reset generation w/ test logic u_DPLL DE sclk TE LGE Internal Use Only Appendix. Block Diagram for Edge/ALEF Backlight Main SoC 3D Chip FRC FHD@60Hz Dual-Link LVDS For Video FHD@60Hz Dual-Link LVDS For OSD FRC-III V by One TCON (240Hz) FHD@240Hz Quad-Link HF mini-LVDS 8 SPI/Vsync LED LED BLU BLU control control [ XXLM960V ALEF LED Backlight] LLV0~6P/N LRV0~6P/N IC401 LG5812B TXP 0~7 TXN 0~7 IC100 LG1122A RXAP 0~4 RXAN 0~4 RXBP 0~4 RXBN 0~4 51Pin LVDS RRV0~6P/N DDR1_A[0~12] RRV0~6P/N DDR1_DATA[0~15] IC201 DDR1 80Pin mini LVDS DDR0_A[0~12] DDR0_DATA[0~15] IC200 DDR0 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Interconnection - 1 XXLM960V-ZB [PCBs] 1 Main PCB 2 LED driver 3 WIFI ASSY 4 RF MOTION ASSY 5 IR Key PCB 6 FRC ASSY 7 PSU 2 7 1 6 5 4 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes 3 LGE Internal Use Only Interconnection – sub PCB( XXLM960V Series ) Speaker cover Assy 5 IR Key PCB RF MOTION ASSY 4 3 SPK unit WIFI ASSY Local Key PCB IR PCB RF MOTION ASSY WIFI ASSY 1 To Main Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Contents of LCD TV Standard Repair Process No. Error symptom (High category) Error symptom (Mid category) Page 1 No video/Normal audio 1 2 No video/No audio 2 Picture broken/ Freezing 3 4 Color error 4 5 Vertical/Horizontal bar, residual image, light spot, external device color error 5 6 No power 6 Off when on, off while viewing, power auto on/off 7 No audio/Normal video 8 9 Wrecked audio/discontinuation/noise 9 10 Remote control & Local switch checking 10 M4 operating checking 11 12 Wifi operating checking 12 13 External device recognition error 13 3 A. Video error B. Power error 7 8 Remarks C. Audio error 11 D. Function error 14 E. Noise Circuit noise, mechanical noise 14 15 F. Exterior error Exterior defect 15 First of all, Check whether there is SVC Bulletin in GCSC System for these model. Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Error symptom LCD TV A. Video error Established date No video/ Normal audio Revised date 2012.01.16 1/15 First of all, Check whether all of cables between board is inserted properly or not. (Main B/D↔ Power B/D, LVDS Cable,Speaker Cable,IR B/D Cable,,,) ☞A1 No video Normal audio Normal audio Y ☞A4 Check Back Light On with naked eye N Move to No video/No audio Y On Check Power Board 24V, 12V,3.5V etc. N ☞A2 Y Replace T-con Board or module And Adjust VCOM N Repair Power Board or parts Check Power Board 24V output Normal voltage Normal voltage Y Replace Inverter or module End N Repair Power Board or parts ※Precaution ☞A7 & A3 Always check & record S/W Version and White Balance value before replacing the Main Board Replace Main Board Re-enter White Balance value 1 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Error symptom A. Video error Established date No video/ No audio Revised date 2012.01.16 2/15 ☞A4 No Video/ No audio Check various voltages of Power Board ( 3.5V,12V,20V or 24V…) Normal voltage? Y N Check and replace MAIN B/D End Replace Power Board and repair parts 2 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Error symptom LCD TV ☞ A6 Check RF Signal level Normal Signal? Y A. Video error Established date Picture broken/ Freezing Revised date 2012.01.16 3/15 . By using Digital signal level meter . By using Diagnostics menu on OSD ( Setting→ Set up→ Manual Tuning → Check the Signal ) - Signal strength (Normal : over 50%) - Signal Quality (Normal: over 50%) Check whether other equipments have problem or not. (By connecting RF Cable at other equipment) → DVD Player ,Set-Top-Box, Different maker TV etc` N ☞ A7 Check RF Cable Connection 1. Reconnection 2. Install Booster Normal Picture? Y Check S/W Version N N Y Check Tuner soldering Close N Y N Normal Picture? SVC Bulletin? S/W Upgrade Contact with signal distributor or broadcaster (Cable or Air) Normal Picture? Y N Replace Main B/D Y Close Close 3 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Error symptom Established date Color error Revised date 2012.01.16 4/15 ☞ A10 ☞A9 Check color by input -External Input -COMPONENT -RGB -HDMI/DVI A. Video error Color error? N Y ※ Check and replace Link Cable (LVDS) and contact condition Y Color error? Y Color error? Replace Main B/D N N End Check error color input mode ☞A12 Check Test pattern Replace module External Input/ Component error Check external device and cable External device Y /Cable normal Replace Main B/D N Request repair for external device/cable N RGB/ HDMI/DVI error Check external device and cable External device Y /Cable normal Replace Main B/D 4 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Error symptom A. Video error Established date Vertical / Horizontal bar, residual image, light spot, external device color error Revised date 2012.01.16 5/15 Vertical/Horizontal bar, residual image, light spot Replace Module ☞A9 ☞ A10 Check color condition by input -External Input -Component -RGB -HDMI/DVI Screen Y normal? Check external device connection condition N N N Screen N normal? Y Request repair for external device Replace module ☞A12 Y Normal? Check and replace Link Cable End Screen normal? Replace Main B/D (adjust VCOM) For LGD panel Y Replace Main B/D End For other panel Check Test pattern External device screen error-Color error Check S/W Version Check N version Y External Input error Component error S/W Upgrade Normal screen? Check screen condition by input -External Input -Component -RGB -HDMI/DVI RGB error N HDMI/ DVI Y End Connect other external device and cable (Check normal operation of External Input, Component, RGB and HDMI/DVI by connecting Jig, pattern Generator ,Set-top Box etc. Connect other external device and cable (Check normal operation of External Input, Component, RGB and HDMI/DVI by connecting Jig, pattern Generator ,Set-top Box etc. N Screen normal? Replace Main B/D Y Request repair for external device Y Screen normal? N Replace Main B/D 5 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Error symptom B. Power error Established date No power Revised date ☞A17 Check Power LED 2012.01.16 6/15 ☞A19 DC Power on by pressing Power Key On Remote control Y Power LED On? . Stand-By: Red or Turn Off N . Operating: Turn Off Normal N operation? Check Power On ‘”High” Y OK? Replace Power B/D N Y Check Power cord was inserted properly Replace Main B/D ☞A4 Measure voltage of each output of Power B/D N Normal? Y Close Y ※ Check ST-BY 3.5V Normal Y voltage? ☞A18 Normal voltage? Y Replace Main B/D N Replace Power B/D N Replace Power B/D 6 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Error symptom B. Power error Established date Off when on, off while viewing, power auto on/off Revised date 2012.01.16 7/15 Check outlet ☞A22 Check A/C cord Error? N Check Power Off Mode CPU Abnormal Normal? Replace Main B/D Y End N Check for all 3- phase power out Y Abnormal 1 ☞A19 Fix A/C cord & Outlet and check each 3 phase out (If Power Off mode is not displayed) Check Power B/D voltage ※ Caution Check and fix exterior of Power B/D Part * Please refer to the all cases which can be displayed on power off mode. Replace Power B/D Normal voltage? Y Replace Main B/D N Replace Power B/D Status Power off List "POWEROFF_REMOTEKEY" "POWEROFF_OFFTIMER" "POWEROFF_SLEEPTIMER" "POWEROFF_INSTOP" "POWEROFF_AUTOOFF" Normal "POWEROFF_ONTIMER" "POWEROFF_RS232C" "POWEROFF_RESREC" "POWEROFF_RECEND" "POWEROFF_SWDOWN" "POWEROFF_UNKNOWN" "POWEROFF_ABNORMAL1" Abnormal "POWEROFF_CPUABNORMAL" Power Power Power Power Power Power Power Power Power Power Power Power Power off off off off off off off off off off off off off Explanation by REMOTE CONTROL by OFF TIMER by SLEEP TIMER by INSTOP KEY by AUTO OFF by ON TIMER by RS232C by Reservated Record by End of Recording by S/W Download by unknown status except listed case by abnormal status except CPU trouble by CPU Abnormal 7 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Error symptom C. Audio error Established date No audio/ Normal video Revised date ☞A24 No audio Screen normal Check user menu > Speaker off 2012.01.16 8/15 ☞A25 N Off Check audio B+ 24V of Power Board Normal voltage Y N Cancel OFF Check Speaker disconnection Y Replace Power Board and repair parts N Disconnection Replace MAIN Board End Y Replace Speaker 8 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Error symptom C. Audio error Established date Wrecked audio/ discontinuation/noise Revised date 2012.01.16 9/15 → abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio ☞A25 Check input signal -RF -External Input signal Wrecked audio/ Discontinuation/ Noise for all audio Signal normal? Check and replace speaker and connector Check audio B+ Voltage (24V) Y Y Wrecked audio/ Discontinuation/ Noise only for D-TV N Normal voltage? Replace Main B/D N Wrecked audio/ Discontinuation/ Noise only for Analog (When RF signal is not received) Request repair to external cable/ANT provider (In case of External Input signal error) Check and fix external device Replace Power B/D Replace Main B/D Wrecked audio/ Discontinuation/ Noise only for External Input Connect and check other external device Normal audio? End N Y Check and fix external device 9 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Established date D. Function error Error symptom Remote control & Local switch checking 2012.01.16 Revised date 10/15 1. Remote control(R/C) operating error ☞A27 Check R/C itself Operation Normal Y operating? ☞A27 Check & Repair Cable connection Connector solder N Normal operating? N Y Check R/C Operating When turn off light in room Check & Replace Baterry of R/C If R/C operate, Explain the customer cause is interference from light in room. Y Normal operating? Replace Main B/D ☞A27 Check B+ 3.5V On Main B/D ☞A4 Close Normal Voltage? Y Check IR Output signal N Check 3.5v on Power B/D Replace Power B/D or Replace Main B/D (Power B/D don’t have problem) Normal Signal? Y N Repair/Replace IR B/D Close N Replace R/C 10 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Established date D. Function error Error symptom M4 operating checking 2012.01.16 Revised date 11/15 2. M4(Magic Remocon) operating error ☞A7 Check the INSTART menu RF Receiver ver is “00.00”? N Check M4 itself Operation Normal Y operating? Press the wheel N ☞A28 Y Y Check & Replace Batterry of M4 Check & Repair RF assy connection Y Normal operating? ☞A7 RF Receiver ver is “00.00”? N Close Turn off/on the set and press the wheel Is show ok N message? Close Close Is show ok message? N N Press the back key about 5sec Y Replace M4 Close Y Down load the Firmware * If you conduct the loop at 3times, change the M4. * INSTART MENUÆ15.RF Remocon TestÆ3. Firmware download 11 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Established date D. Function error Error symptom Wifi operating checking 2012.01.16 Revised date 12/15 3.Wifi operating error ☞A7 Check the INSTART menu ☞A29 Wi-Fi Mac value is “NG”? N Check the Wifi wafer (P4301)_1pin Normal Voltage? N Replace Main B/D Y ☞A29 Y Close Check & Repair Wifi cable connection ☞A7 Wi-Fi Mac value is “NG”? N Close Y Change the Wifi assy 12 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Check input signal Error symptom Y Signal input? N D. Function error Established date External device recognition error Revised date Check technical information - Fix information - S/W Version Check and fix external device/cable Technical information? N External Input and Component Recognition error 2012.01.16 13/15 Replace Main B/D Y Fix in accordance with technical information RGB,HDMI/ DVI, Optical Recognition error Replace Main B/D 13 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV Identify nose type Error symptom E. Noise Established date Circuit noise, mechanical noise Revised date Circuit noise Check location of noise Mechanical noise Check location of noise 2012.01.16 14/15 Replace PSU(with LED driver) OR Replace LED driver ※ When the nose is severe, replace the module (For models with fix information, upgrade the S/W or provide the description) ※ Mechanical noise is a natural phenomenon, and apply the 1st level description. When the customer does not agree, apply the process by stage. ※ Describe the basis of the description in “Part related to nose” in the Owner’s Manual. OR OR ※ If there is a “Tak Tak” noise from the cabinet, refer to the KMS fix information and then proceed as shown in the solution manual (For models without any fix information, provide the description) 14 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process LCD TV F. Exterior defect Error symptom Zoom part with exterior damage Exterior defect Module damage Replace module Cabinet damage Replace cabinet Remote controller damage Stand dent Established date Revised date 2012.01.16 15/15 Replace remote controller Replace stand 15 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Contents of LCD TV Standard Repair Process Detail Technical Manual No. Error symptom 1 Content Page Check LCD back light with naked eye A1 LED driver B+ 24V measuring method A2 Check White Balance value A3 Power Board voltage measuring method A4 TUNER input signal strength checking method A6 LCD-TV Version checking method A7 Tuner Checking Part A8 LCD TV connection diagram A9 Check Link Cable (LVDS) reconnection condition A10 10 Adjustment Test pattern - ADJ Key A12 11 Exchange T-Con Board (1) A-1/5 Exchange T-Con Board (2) A-2/5 Exchange LED driver Board (PSU) A-3/5 Exchange Module (1) A-4/5 Exchange Module (2) A-5/5 2 A. Video error_ No video/Normal audio 3 4 A. Video error_ No video/Audio 5 6 A. Video error_ video error /Video lag/stop 7 8 9 12 13 14 A. Video error _Vertical/Horizontal bar, residual image, light spot A. Video error_ Color error <Appendix> Defected Type caused by T-Con/ Inverter/ Module 15 Remarks Continue to the next page Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Contents of LCD TV Standard Repair Process Detail Technical Manual Continued from previous page No. Error symptom 16 17 B. Power error_ No power 18 19 20 22 B. Power error_Off when on, off while viewing C. Audio error_ No audio/Normal video 22 23 D. Function error 24 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes Content Page Check front display LED A17 Check power input Voltage & ST-BY 3.5V A18 Checking method when power is ON A19 POWER OFF MODE checking method A22 Checking method in menu when there is no audio A24 Voltage and speaker checking method when there is no audio A25 Remote controller operation checking method A27 Motion Remote operation checking method A28 Wifi operation checking method A29 Remarks LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_No video/Normal audio Content Check LCD back light with naked eye Established date Revised date 2011. 12 .14 A1 <XXLM9600> After turning on the power and disassembling the case, check with the naked eye, whether you can see light from 2 locations. A1 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_No video/Normal audio Content LED driver B+ 24V measuring method Established date Revised date 2011. 12 .14 A2 Check the DC 24V and Inverter on ALEF LED 14 Pin (Power Board ↔ Driver) PSU 1~5 24V 6 ~ 10 GND 11 Detect 12 Inverter On/Off 13 Int. PWM 14 Ext. PWM (PDIM) A2 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_No video/Normal audio Content Check White Balance value Established 2011. 12 .14 date Revised date A3 <ALL MODELS> Entry method method Entry 1. 1. Press Press the the ADJ ADJ button button on on the the remote remote controller controller for for adjustment. adjustment. 2. Enter into into White White Balance Balance of of item item 10. 6. 2. Enter 3. 3. After After recording recording the the R, R, G, G, B B (GAIN, (GAIN, Cut) Cut) value value of of Color Color Temp Temp (Cool/Medium/Warm), re-enter the value after replacing (Cool/Medium/Warm), re-enter the value after replacing the the MAIN MAIN BOARD. BOARD. A3 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_No video/ Audio Content Power Board voltage measuring method ALEF LED Established 2011. 12 .14 date Revised date A4 Check the DC 24V, 12V, 3.5V. 24 Pin (Power Board ↔ Main Board) - 공통 SMAW200-H24S (YEONHO) 1 Power on 2 20V (24V) 3 20V (24V) 4 20V (24V) 5 GND 6 GND 7 GND 8 GND 9 3.5V 10 3.5V 11 3.5V 12 3.5V 13 GND 14 GND 15 GND 16 N.C (Only LPB : V-sync) 17 12V 18 Inverter On/off 19 12V 20 N.C (LPB, Lamp : A-dim) 21 12V 22 PWM Dim #1 23 N.C (only Lamp SCANNING Model : PWM Dim #2) 24 Error-out A4 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_Video error, video lag/stop Content TUNER input signal strength checking method Established 2011. 12 .14 date Revised date A6 <ALL MODELS> Settings Æ Set up Æ Manual Tuning Æ select channel When the signal is strong, use the attenuator (-10dB, -15dB, -20dB etc.) A6 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_Video error, video lag/stop Content LCD-TV Version checking method <ALL MODELS> Established 2011. 12 .14 date Revised date A7 1. Checking method for remote controller for adjustment Version Press the IN-START with the remote controller for adjustment A7 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_Video error, video lag/stop Content TUNER checking part Established 2011. 12 .14 date Revised date A8 <ALL MODELS> Checking method: 1. Check the signal strength or check whether the screen is normal when the external device is connected. 2. After measuring each voltage from power supply, finally replace the MAIN BOARD. A8 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error _Vertical/Horizontal bar, residual image, light spot Content LCD TV connection diagram (1) Established 2011. 12 .14 date Revised date A9 <ALL MODELS> As the part connecting to the external input, check the screen condition by signal A9 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_Color error Content Check Link Cable (LVDS) reconnection condition Established 2011. 12 .14 date Revised date A10 <ALL MODELS> Check the contact condition of the Link Cable, especially dust or mis insertion. A10 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom A. Video error_Color error Content Adjustment Test pattern - ADJ Key Established 2011. 12 .14 date Revised date A12 You can view 6 types of patterns using the ADJ Key Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..) 4.Video error (Classification of MODULE or Main-B/D!) A12 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Appendix : Exchange T-Con Board (1) Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken Solder defect, CNT Broken T-Con T-Con Defect, Defect, CNT CNT Broken Broken Solder defect,CNT CNTBroken Broken T-Con Defect, Abnormal Power Section Solder defect, Short/Crack Abnormal Power Section Solder defect, Short/Crack A - 1/5 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Appendix : Exchange T-Con Board (2) Abnormal Power Section Solder defect, Short/Crack GRADATION Abnormal Power Section Solder defect, Short/Crack Fuse Open, Abnormal power section Abnormal Display Noise GRADATION A - 2/5 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Appendix : Exchange LED driver Board (PSU) No Light Dim Light Dim Light Dim Light No picture/Sound Ok A - 3/5 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Appendix : Exchange the Module (1) Panel Mura, Light leakage Crosstalk Panel Mura, Light leakage Press damage Press damage Crosstalk Un-repairable Cases In this case please exchange the module. Press damage A - 4/5 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Appendix : Exchange the Module (2) Vertical Block Source TAB IC Defect Horizontal Block Gate TAB IC Defect Vertical Line Source TAB IC Defect Horizontal Gate TAB ICBlock Defect Gate TAB IC Defect Vertical Block Source TAB IC Defect Horizontal line Gate TAB IC Defect Gate TAB IC Defect Un-repairable Cases In this case please exchange the module. Horizontal Block Gate TAB IC Defect Gate TAB IC Defect A - 5/5 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom B. Power error _No power Content Check front display LED Established 2011. 12 .14 date Revised date A17 <XXLM9600> Front LED control : Menu Æ Option Æ Standby Light Æ ON/ Off ST-BY condition: Red or Turn Off Power ON condition: Turn Off A17 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom B. Power error _No power Content Check power input voltage and ST-BY 3.5V Established 2011. 12 .14 date Revised date A18 <XXLM9600> Check the DC 24V, 12V, 3.5V. ALEF LED 24 Pin (Power Board ↔ Main Board) - 공통 SMAW200-H24S (YEONHO) 1 Power on 2 20V (24V) 3 20V (24V) 4 20V (24V) 5 GND 6 GND 7 GND 8 GND 9 3.5V 10 3.5V 11 3.5V 12 3.5V 13 GND 14 GND 15 GND 16 N.C (Only LPB : V-sync) 17 12V 18 Inverter On/off 19 12V 20 N.C (LPB, Lamp : A-dim) 21 12V 22 PWM Dim #1 23 N.C (only Lamp SCANNING Model : PWM Dim #2) 24 Error-out A18 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom Content Established 2011. 12 .14 date Revised date B. Power error _No power Checking method when power is ON A19 <XXLM9600> Check “power on” pin is high ALEF LED 24 Pin (Power Board ↔ Main Board) - 공통 SMAW200-H24S (YEONHO) 1 Power on 2 20V (24V) 3 20V (24V) 4 20V (24V) 5 GND 6 GND 7 GND 8 GND 9 3.5V 10 3.5V 11 3.5V 12 3.5V 13 GND 14 GND 15 GND 16 N.C (Only LPB : V-sync) 17 12V 18 Inverter On/off 19 12V 20 N.C (LPB, Lamp : A-dim) 21 12V 22 PWM Dim #1 23 N.C (only Lamp SCANNING Model : PWM Dim #2) 24 Error-out A19 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom B. Power error _Off when on, off whiling viewing Established 2011. 12 .14 date Content POWER OFF MODE checking method Revised date A22 <ALL MODELS> Entry method 1. Press the IN-START button of the remote controller for adjustment 2. Check the entry into adjustment item 3 A22 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom C. Audio error_No audio/Normal video Content Checking method in menu when there is no audio Established 2011. 12 .14 date Revised date A24 <ALL MODELS> Checking method 1. Press the Setting button on the remote controller 2. Select the Sound function of the Menu 3. Select the Sound Setting 4. Select TV Speaker from Off to On A24 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom C. Audio error_No audio/Normal video Content Voltage and speaker checking method when there is no audio Established date Revised date 2011. 12 .14 A25 <XXLM9600> ALEF LED 24 Pin (Power Board ↔ Main Board) Power on 24V 1 2 ② 24V 24V 3 4 GND GND 5 6 GND GND 7 8 ② 3.5V 3.5V 9 10 3.5V 3.5V 11 12 GND 13 GND 14 V-sync 15 GND 16 17 12V 18 Inverter On/off N.C 19 12V 20 21 12V 22 PWM Dim #1 23 PWM Dim #2 24 Error-out ① ③ Checking order when there is no audio ① Check the contact condition of or 24V connector of Main Board ② Measure the 24V input voltage supplied from Power Board (If there is no input voltage, remove and check the connector) ③ Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the GND and output terminal, the speaker is normal. A25 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom D. Function error Content Remote controller operation checking method Established 2011. 12 .14 date Revised date A27 <XXLM9600> ③ ④ 1 2 3 4 5 6 7 8 9 10 P4102 SCL SDA GND KEY1 KEY2 St 3.5V GND GP4_LED_R IR GND ② ① Checking order 1, 2. Check IR cable condition between IR & Main board. 3. Check the st-by 3.3V on the terminal 6. 4. When checking the Pre-Amp when the power is in ON condition, it is normal when the Analog Tester needle moves slowly, and defective when it does not move at all. A27 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual LCD TV Error symptom Content D. Function error Motion Remote operation checking method Established 2011. 12 .14 date Revised date A28 <XXLM9600> ③ 1 2 3 4 5 6 7 8 P4800 3.3V GND RX TX RESET DC DD GND ① ② Checking order 1, 2. Check Motion cable condition between Motion assy & Main board. 3. Check the 3.3V on the terminal 1. A28 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only Standard Repair Process Detail Technical Manual Error symptom LCD TV Content D. Function error Wifi operation checking method Established 2011. 12 .14 date Revised date A29 <XXLM9600> ③ ① 1 2 3 P4301 VDD DM DP 4 GND ② Checking order 1, 2. Check Wifi cable condition between Wifi assy & Main board. 3. Check the 5V on the terminal 1. A29 Copyright © 2012 LG Electronics. Inc. All rights reserved. Only for training and service purposes LGE Internal Use Only