Download Samsung DVD-S229 Service manual
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FILE NO. SERVICE MANUAL LCD-22VT10DVD(B) PRODUCT CODE NO.: DVD built-in LCD TV 1 682 348 96 REFERENCE No. SM0948001 CONTENTS Safety precautions………………………………………………………………………..… Alignment instructions …………………………….…….………………………………… Method of software upgrading…………………………………………………………….. Working principle analysis of the unit……………………………….………….…………. Block diagram…………………………………..………………………………….………… IC block diagram………………………………………………………………………..…… Wiring diagram ……………………………………………………………………………. Troubleshooting guide ………………………………………………………………..…… Schematic diagram………………………………………………………………………… APPENDIX-A: Assembly list APPENDIX-B: Exploded View Removing or Installing the Stand Wall mounting instructions Safety precautions 1. Instructions Be sure to switch off the power supply before replacing or welding any components or inserting/plugging in connection wire Anti static measures to be taken (throughout the entire production process!): a) Do not touch here and there by hand at will; b) Be sure to use anti static electric iron; c) It’s a must for the welder to wear anti static gloves. Please refer to the detailed list before replacing components that have special safety requirements. Do not change the specs and type at will. 2. Points for attention in servicing of LCD 2.1 Screens are different from one model to another and therefore not interchangeable. Be sure to use the screen of the original model for replacement. 2.2 The operation voltage of LCD screen is 700-825V. Be sure to take proper measures in protecting yourself and the machine when testing the system in the course of normal operation or right after the power is switched off. Please do not touch the circuit or the metal part of the module that is in operation mode. Relevant operation is possible only one minute after the power is switched off. 2.3 Do not use any adapter that is not identical with the TV set. Otherwise it will cause fire or damage to the set. 2.4 Never operate the set or do any installation work in bad environment such as wet bathroom, laundry, kitchen, or nearby fire source, heating equipment and devices or exposure to sunlight etc. Otherwise bad effect will result. 2.5 If any foreign substance such as water, liquid, metal slices or other matters happens to fall into the module, be sure to cut the power off immediately and do not move anything on the module lest it should cause fire or electric shock due to contact with the high voltage or short circuit. 2.6 Should there be smoke, abnormal smell or sound from the module, please shut the power off at once. Likewise, if the screen is not working after the power is on or in the course of operation, the power must be cut off immediately and no more operation is allowed under the same condition. 2.7 Do not pull out or plug in the connection wire when the module is in operation or just after the power is off because in this case relatively high voltage still remains in the capacitor of the driving circuit. Please wait at least one minute before the pulling out or plugging in the connection wire. 2.8 When operating or installing LCD please don’t subject the LCD components to bending, twisting or extrusion, collision lest mishap should result. 2.9 As most of the circuitry in LCD TV set is composed of CMOS integrated circuits, it’s necessary to pay attention to anti statics. Before servicing LCD TV make sure to take anti static measure and ensure full grounding for all the parts that have to be grounded. 2.10 There are lots of connection wires between parts behind the LCD screen. When servicing or moving the set please take care not to touch or scratch them. Once they are damaged the screen Attention: This service manual is only for service personnel to take reference with. Before servicing please read the following points carefully. 2 would be unable to work and no way to get it repaired. If the connection wires, connections or components fixed by the thermotropic glue need to disengage when service, please soak the thermotropic glue into the alcohol and then pull them out in case of dagmage. 2.11 Special care must be taken in transporting or handling it. Exquisite shock vibration may lead to breakage of screen glass or damage to driving circuit. Therefore it must be packed in a strong case before the transportation or handling. 2.12 For the storage make sure to put it in a place where the environment can be controlled so as to prevent the temperature and humidity from exceeding the limits as specified in the manual. For prolonged storage, it is necessary to house it in an anti-moisture bag and put them altogether in one place. The ambient conditions are tabulated as follows: 2.13 Display of a fixed picture for a long time may result in appearance of picture residue on the screen, as commonly called “ghost shadow”. The extent of the residual picture varies with the maker of LCD screen. This phenomenon doesn’t represent failure. This “ghost shadow” may remain in the picture for a period of time (several minutes). But when operating it please avoid displaying still picture in high brightness for a long time. 3. Points for attention during installation 3.1 The front panel of LCD screen is of glass. When installing it please make sure to put it in place. 3.2 For service or installation it’s necessary to use specified screw lest it should damage the screen. 3.3 Be sure to take anti dust measures. Any foreign substance that happens to fall down between the screen and the glass will affect the receiving and viewing effect 3.4 When dismantling or mounting the protective partition plate that is used for anti vibration and insulation please take care to keep it in intactness so as to avoid hidden trouble. 3.5 Be sure to protect the cabinet from damage or scratch during service, dismantling or mounting. Alignment instructions 1. Test equipment VG-848 (YPbPr,VGA signal generator) VG-849 (HDMI signal generator) CA210 (white balancer) 2. Power test Connect power board, digital processing board, IR board and backlight board according the wiring diagram, connect the power and press to turn on the TV. Test the pin voltage of X401, the data is shown in table1: Table1 voltage data of X401 X401 Pin1 2 3 4 5, 6 7, 8 9 10 11 12 13 Voltage 5V±5% 0 5V±5% 0 12V±5% 0 ≤3.3V ≤5V ≤3.3V 32V±5% 0 3. Alignment flow-chart Fig-1 adjustment flow-chart 4. Adjustment instruction 4.1 Unit adjustments 4.1.1Connect all the boards according to wiring diagram, then power on and observe the display. 4.1.2 Method for entering factory menu: a) Press “SOURCE”, “2”, “5”, ”8” and “0” in turn to enter factory menu; b) Press “” and “” to move the cursor to the adjustment page of the level one factory menu, then press ”OK” to enter; c) Press “” and “” to move the cursor up and down; d) Press “” and “” to adjust the item when the cursor move to a certain adjust item; e) Press “MENU” to exit to the previous factory menu; f) Press “EXIT” to exit the factory menu at any situation; g) Press “OK” to enter the sub factory menu; h) ADC ADJUST, ADC correction of VGA, Component channel; i) W/B ADJUST, white balance adjustment; j) POWER MODE, set the turn-on modes. Standby---standby when power on; Mem---memory; ForceOn---power on; ForceOn can be used for aging; set the “power mode” to “Standby” when preset ex-factory unless the client appointed it; k) ISP MODE, ON---soft upgrading through VGA port with ISP instrument, OFF---DDC function of VGA; the setting will not be memory and will be “OFF” when power on again; l) RESTALL, initialization of the factory and user data; after this item is confirm, the unit will restart and display the guiding image. m) FACTORYDATAREST, factory data initialization (including white balance adjustment, ADC correction and other adjusted data); n) FACEORY Channel PRESET, preset the factory channel; please connect to the center signal source when operating; the present digital frequency is CH28(529.5MHz), CH33(564.5MHz) for Australia, if the signal changes, perform “DTV manual search” in “Channel” menu and the operation needs 15s or so. o) CUSTOM Channel PRESET, preset the custom ATV channel, they are CH2(66.5MHz), CH7(184.5MHz), CH9(198.5MHz), CH10(212.5MHz), CH28(529.5MHz); p) MST DEBUG, the default is OFF. OFF---RS-232 should match the design criterion; ON--- it should be convenient for using exploitation tool to adjust. The setting will not be memory and will be “OFF” when power on again; q) BACKLIGHT: adjust the backlight brightness, adjust the data and test the voltage of X804 pin2 (PWM), let the voltage to be the corresponding PWM voltage which the brightness is maximum. It will be preset and doesn’t need adjust. r) SSC ADJUST, adjust the frequency spectrum expand, it will be preset and doesn’t need adjust. s) AUDIO CURVE, adjust the sound curve, it will be preset and doesn’t need adjust. t) RF AGC delay Adj, adjust ATV RF AGC-take; u) There is data in EEPROM after software upgrade, please perform REST ALL before the first adjustment. Preset ex-factory 5 4.1.3 ADC correction in D-SUB channel a) Switch to D-SUB channel b) Press” SOURCE”, then press “2, 5, 8, 0” in turn to enter the level one factory menu. c) Move the cursor to “ADC ADJUST” and press OK to enter the sub-menu. d) Input D-SUB signal (VG-848 Timing:856(1024x768/60Hz), Pattern:920 8step Gray). Move the cursor to “MODE”, press and to select “RGB”, move the cursor to “AUTO ADC” and press OK to adjust automatically till display “success”. 4.1.4 ADC correction of Component channel a) Switch to Component channel. b) Press” SOURCE”, then press “2, 5, 8, 0” in turn to enter the level one factory menu. c) Move the cursor to “ADC ADJUST” and press OK to enter the sub-menu. d) Input Component signal (VG-848 Timing:969(PAL), Pattern:918 100% color bar). Move the cursor to “MODE”, press and to select “YPbPr(SD)”, move the cursor to “AUTO ADC” and press OK to adjust automatically till display “success”. e) Input Component signal (VG-848 Timing:972(1080i), Pattern:918 100% color bar). Move the cursor to “MODE”, press and to select “YPbPr(HD)”, move the cursor to “AUTO ADC” and press OK to adjust automatically till display “success”. 4.2 White balance adjustment The default of color temperature of COOL is 12000K and the coordinate is (272, 278); color temperature of NORMAL is 9300K and the coordinate is (285,293), color temperature of WARM is 6500K and the coordinate is (313,329). 4.3 Adjustment steps Before the white balance adjustment, please let the unit working at least 30 minutes and at a stable situation, use BBY channel of the white balancer CA-210 (19” for example). a) Switch to HDMI channel; b) Press” SOURCE”, then press “2, 5, 8, 0” in turn to enter the level one factory menu. c) Move the cursor to “W/B ADJUST” and press OK to enter the sub-menu. d) Input HDMI signal (VG-848 Timing:856(1024X768/60Hz), Pattern:921 16 step Gray). Move the cursor to “MODE”, press and to select “HDMI”, move the cursor to “TEMPERTURE” and press and to select “COOL”. e) Fix G GAIN, adjust R GAIN, B GAIN and let the color coordinate of the thirteenth scale be (272,278). f) Fix G OFFSET, adjust R OFFSET, B OFFSET and let the color coordinate of the forth scale be (272,278). g) When adjusting, please keep the color temperature of high light to be X=272±5, Y=278±15 and the low light to be X=272±8, Y=278±30; h) Move the cursor to “COPY ALL” and copy the data to the other channels (except DTV); i) Check if the color temperatures of NORMAL and WARM are up to the mustard (NORMAL high light acceptable error: x±10, y±15, NORMAL low light acceptable error: x±10, y±25; WARM high light and low light acceptable error: x±10, y±10), if not, adjust R-GAIN/B-GAIN/R-OFF/B-OFF. j) Check the white balance of other channels, if they are not up to the mustard then adjust and store the data separately. k) Select DTV channel and 16-level gray scale signal. l) Press “SOURCE” and “2, 5, 8, 0” one by one to enter the level one factory menu. m) Move the cursor to “W/B ADJUST” and press OK to enter the sub-menu. 6 n) Move the cursor to “MODE”, pressand to select “DTV”, move the cursor to “TEMPERTURE” and press and to select “COOL”. o) Repeat the steps e)-I); p) After adjustment, check if the pictures are normal. q) The reference of adjustment rule is below: B gun: lower B gun to increase X, Y coordinate data, while raise B gun to decrease the data; R gun: raise R gun to increase X coordinate data, while lower R gun to decrease the data; (R gun adjustment will affect X and Lv slightly) G gun: raise G gun to increase Y coordinate data, while lower G gun to decrease the data; (G gun adjustment will affect Y and Lv greatly) 5. Performance check 5.1 TV function Connect RF to the center signal source, enter Channel menu → auto search, check if there are channels be skipped, check if the picture and speaker are normal. 5.2 AV terminals Input AV signal, check if the picture and sound are normal. 5.3 Component terminal Input Component signal (VG-848 signal generator), separately input the Component signals listed in table2 and check if the display and sound are normal at any situation (power on, channel switch and format switch, etc.) Table2 Component signal format 5.4 D-SUB terminal Input D-SUB signal (VG-848 signal generator), separately input the signals listed in table3 and check the display and sound. If the image is deflection of the Horizontal and vertical, select Picture->Screen->Auto Adjusting to perform auto-correct. Table3 D-SUB signal format 5.5 HDMI terminal Input HDMI signal (VG-849 signal generator), separately input the signals listed in table2 and table3 and check the display and sound (32KHz, 44.1KHz, 48KHz) at any situation (power on, channel switch and format switch, etc.) 5.6 other functions check a) Check the turn on/turn off timer, asleep timer, picture/sound mode, OSD, stereo and digital sound port, etc. b) Check the digital program, if Audio Only is normal. c) Check logical channel number (LCN) for Australia. d) Check OTA function for Australia special custom. 6. Presetting before ex-factory Enter user menu LOCK page, select “Restore Factory Default” to preset the ex-factory. a) Clear the program information b) Clear VCHIP, parental control, etc. c) Set the default data of user menu 8 d) Set Menu Language to English e) Set Power on Mode to Off Software instruction 17MB37 Analog Part Software Update With Bootloader Procedure 1.1 The File Types Used By The Bootloader All file types that used by the bootloader software are listed below: 1. The Binary File : It has “.bin” extension and it is the tv application. Its size is 1920 Kb. 2. The Config Binary File : It has “.cin extension and it is the config of the tv application. Its size may be 64 Kb or a few times 64 Kb. 3. The Test Script File : It has “.txt” extension and it is the test script that is parsed and executed by the bootloader. It don’t have to be any times of 64 Kb. 4. The Test Binary File : It has “.tin” extension and it is used and written by the test groups. It is run to understand the problem part of the hardware. Alltough a file that is used by the bootloader can be had any one of these extensions, its name has to be “VESTEL_S” and it has to be located in the root directory of the usb device. 1.2 Usage of The Bootloader 1. The starting to pass through : The chassis is only powered up. 2. The starting to download something : When chassis is powered up the menu key has to be pushed.Before the chassis is powered up and if any usb device is plugged to the usb port, the programme is downloaded from usb firstly. Any usb device is plugged to usb port , user must open hyperterminal in the pc and connect pc to chassis via Mstar debug tool and any one of scart,dsub9 or I2c connectors. Serial connection settings are listed below: - Bit per second: 115200 Data bits: 8 Parity: None Stop bits: 1 Flow control: None In this case the bootloader sofware puts “C” character to uart. After repeating “C” characters are seen in the hyperterminal user can send any file to chassis by selecting Transfer -> Send File menu item and choosing “1K Xmodem” from protocol section. Figure 1. The Sample Output Before Sending The File EEProm update To Update eeprom content via uart scart,dsub9 or i2c with Mstar tool can used. Serial connection settings are listed below: - Bit per second: 9600 Data bits: 8 Parity: None Stop bits: 1 Flow control: None Programming menu item is choosed in the service menu and switch “HDCP Key Update Mode” from off to on. Figure 2. The Programming Service Menu After then you must see Xmodem menu in the hyperterminal.To download hdcp key press k or to download eeprom content press w. Figure 3. Xmodem Menu If the repeated “C” characters are seen you can transfer file content via select Transfer>Send File and choose “Xmodem” protocol and click the “Send” button. Figure 4. The Starting To Send 17MB37 HDCP key upload procedure. 1) Turn on TV set. 2) Open a COM connection using fallowing parameters and select ISP COM Port No Baud Rate: 9600 bps Data Bits: 8 Stop Bits: 1 Parity: None Flow Control: None 3) Enter service menu by pressing “4” “7” “2” 5” consecutively while main menu is open 4) Select “9. Programming” 5) Select “HDMI HDCP Update Mode” yes. 6) On Hyper Terminal Window press “k” 7) Click on send file under Transfer Tab. 8) Select Xmodem and choose the HDCP key to be uploaded. 9) Press send button 10)Restart TV set 17MB37 Digital Software Update From SCART Adjusting DTV Download Mode: 1. Power on the TV. 2. Exit the Stby Mode. 3. Enter the “Tv Menu”. 4. Enter “4725” for jumping to “Service Settings”. 5. Select “8. Programming” step. 6. Change “6. DTV Download” to “On”. 7. Switch to the Stby mode. Adjusting HyperTerminal: 1. Connect the “MB37 SCART Interface” to SCART1 (bottom SCART plug). 2. Also connect the “MB37 SCART Interface” to PC. 3. Open “HyperTerminal”. 4. Determine the “COM” settings listed and showed below. Bit per second: 115200 Data bits: 8 Parity: None Stop bits: 1 Flow control: None COM Properties Window 6. Click “OK”. Software Updating Procedure 1. In the HyperTerminal Menu, click the “Connect” button. 2. Exit the Stby Mode. 3. The “Space” button on the keyboard must be pressed, when the following window can be seen. Selection Window 4. Press the “2” button on the keyboard for choosing “2. Upgrade Application with Xmodem”. 5. Repeating “C” characters are seen in the “HyperTerminal” menu. The Sample Output Before Sending The File 6. Click the “Send” button on the HyperTerminal 7. Select the “Filename xxxx_slot1.img” using “Browse”. 8. Choose the “1K Xmodem” from “Protocol” option. Selection of File File and Protocol Selection Window Note: In the Software updating Procedure section, when the first “C” character is seen, the filename selection process must be finished before 10 seconds. If the process can not be finished, the file sending operation will be cancelled. The following figure shows this situation. Capture of Receving Data Failing 9. When sending the file the following window must be seen. Capture of Sending Process 10. After the sending process the following HyperTerminal window must be seen. Capture of End of The Sending Process 11. For sending second program file, the Software Updating Procedure must be repeated from the step X. Select the “Filename xxxx_slot2.img” using “Browse”. 12. After sending the second program file, the Software Updating Procedure will be succesful. Note: After the File Sending Process, 1. Upgrade Application with FUM 2. Upgrade Application with Xmodem, options must be seen. End of The Sending Process Checking Of The New Software 1. Turn off and on the TV. 2. Enter the “Setup” submenu in the “DTV Menu”. 3. Choose the “Configuration” option. 4. For controlling new software, check the “Receiver Upgrade” option. 17MB37 Digital Software Update From USB Software upgrade is possible via USB disk by folowing the steps below. 1. Copy the bin file, including higher version than the software loaded in flash, into the USB flash memory root directory. This file should be named up.bin. 2. Insert the USB disk. 3. Digital module performs version and CRC check. If version and CRC check is successful, then a message prompt appears to notify user about new version. If the user confirms loading of new version, upgrade.bin file is written into flash unused slot. 4. Digital module disables the previous software in the flash and then a system reset is performed. 5. After the reset, digital module starts with new software. Revert operation: With revert operation, it is possible to downgrade the software. Revert operation is very similar to upgrade process. In the revert operation, file name should be f_up.bin. Also user confirmation is not asked. 1. Copy the bin file into the USB flash memory root directory. This file should be named force_upgrade.bin. 2. Insert the USB disk. 3. A lower version than the software in flash can be loaded with revert operation. Digital module performs only CRC check. If CRC check is successful, then force_upgrade.bin file is written into flash unused slot. 4. Digital module disables the previous software in the flash. 5. A message prompt is displayed to notify user about end of revert process. 6. Power off/on is required to start digital module with the new software. For controlling new software, check the “Receiver Upgrade” option. ***** ****Block Diagram IC Block Diagram STI7101YWC The MST6WB7GQ-3 is a high performance and fully integrated IC for multi-function LCD monitor/TV with resolutions up to full HD (1920x1080). It is configured with an integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI receiver, a multi-standard TV video and audio decoder, two video de-interlacers, two scaling engines, the MStarACE-3 color engine, an on-screen display controller, an 8-bit MCU and a built-in output panel interface. By use of external frame buffer, PIP/POP is provided for multimedia applications. Furthermore, 3-D video decoding and processing are fulfilled for high-quality TV applications. To further reduce system costs, the MST6WB7GQ-3 also integrates intelligent power management control capability for greenmode requirements and spread-spectrum support for EMI management. Pin Description Signal names are prefixed by NOT if they are active low; otherwise they are active high. On the pin-out diagram, black indicates that the pin is reserved and must not be used. The following pages give the allocation of pins to the package, shown from the top looking down using the PCB footprint. Table : Key to pin-out diagram STx7101 18 A B C Pin list and alternative functions 19 LMIVID LMIVID DATASTRO DATA BE[0] MASK[2] 20 21 22 23 24 25 26 27 28 29 30 31 AUDANA MRIGHT OUT 33 34 NC AUD_ GNDA VIDANA REXT[0] VIDANA VIDANAID VIDANAC1 REXT[1] UMPC1 OUT A LMIVID DATA[16] LMIVID DATA[18] LMIVID DATA[20] LMIVID DATA[22] GNDE AUDPCM OUT0 VDDE 3V3 LMIVID LMIVID LMIVID DATA DATASTRO DATA[17] MASK[0] BE[2] LMIVID DATA[19] LMIVID DATA[21] LMIVID DATA[23] GNDE AUDPCM OUT1 VDDE 3V3 AUDANA PLEFT OUT AUDANA PRIGHT OUT AUD_ VCCA AUD_ GNDAS VIDANA GNDA REXT[0] VIDANA VIDANAID VIDANAY1 GNDA UMPY1 OUT REXT[1] B GNDE GNDE GNDE GNDE GNDE AUDPCM OUT2 VDDE 3V3 AUDANA IREF AUDANA VBGFIL FS0_ VCCA NC FS0_ GNDA DA_HD_0_ VIDANAID VIDANACV GNDA UMPCV1 1OUT C NOT TRST TCK TDI GNDE AUDDIG DA_HD_0_ VDDE2V5_ AGNDPLL VIDANAID VIDANAR0 DATAIN VCCA AUD_ANA 80V0 UMPR0 OUT D NOT ASEBRK TMS TDO GNDE VDDE2V5_ AUDLR SYSBCLK AUDDIGLR DA_SD_0_ VDDE2V5_ GNDE_ VIDANAID VIDANAB0 PLL80_ CLKOUT INALT CLKIN VCCA FS0_ANA AUD_ANA UMPB0 OUT ANA E GNDE GNDE D TRIGGER NOT OUT RESETIN E TMUCLK WDOG RSTOUT AUDSPDIF AUDPCM AUDPCM AUDDIG GND_ANA OUT OUT3 CLKOUT STRBIN AUDS CLKOUT AUDPCM OUT4 DA_SD_0 _GNDA GNDE_ 4FS_ ANA GNDE_ FS0_ ANA FS0_ VDDD FS0_ GNDD VDDE2V5 _4FS_ANA H CKGB_ 4FS1_ VDDD CKGB_ 4FS1_ GNDD J CKGB_ 4FS0_ VDDD CKGB_ 4FS0_ GNDD F Pin-out (R) G VIDANAID VIDANAG0 UMPG0 OUT VDDE 3V3 F VDDE 3V3 G VID VDDE2V5 DIGOUT _VID_ANA YC[7] VID DIGOUT YC[6] H GNDE_ VID_ANA VID DIGOUT YC[5] VID DIGOUT YC[4] J DGND PLL80V0 GNDE_ PLL80_ ANA VID DIGOUT YC[3] VID DIGOUT YC[2] K CKGB_ 4FS1_ GNDA VID DIGOUT YC[1] VID DIGOUT YC[0] L VID DIGOUT VSYNC M K DVDD PLL80V0 L CKGB_ 4FS1_ VCCA NC M CKGB_ 4FS0_ VCCA CKGB_ 4FS0_ GNDA GND_ ANA VID DIGOUT HSYNC GND AVDD PLL80V0 VID DIGOUT YC[15] TMDS VSSD TMDS VSSC1 TMDS VSSC0 N GND VID DIGOUT YC[14] VID DIGOUT YC[13] TMDS VSSP TMDS TX2P TMDS TX2N P VDD VID DIGOUT YC[12] VID DIGOUT YC[11] TMDS GNDE TMDS TX1P TMDS TX1N R VDD VID DIGOUT YC[10] VID DIGOUT YC[9] TMDS REF TMDS TX0P TMDS TX0N T GNDE 3V3 TMDS VSSSL TMDS TXCP TMDS TXCN U N P Confidential 32 AUDANA MLEFT OUT R T VDD VDD VDD GND VDD GND GND GND GND GND GND GND GND GND GND VDD U GND GND GND VDD VDD VID DIGOUT YC[8] V GND GND GND VDD VDD GNDE 3V3 TMDS VDD TMDS VSSCK TMDS VSSX TMDS VSSC2 V W GND GND GND VDD VDD TMDS VDDE3V3 TMDS VDDC0 TMDS VDDCK TMDS VDDX TMDS VDDC2 W Y VDD GND GND GND VDD PIO5[6] PIO5[7] TMDS VDDC1 PIO5[4] PIO5[3] Y AA VDD GND GND GND GND PIO4[7] PIO5[5] TMDS VDDSL PIO5[2] PIO5[1] AA AB VDD VDD GND GND GND PIO4[5] PIO4[6] TMDS VDDD PIO5[0] PIO3[7] AB AC PIO4[3] PIO4[4] TMDS VDDP PIO3[6] PIO3[5] AC AD PIO4[1] PIO4[2] PIO4[0] PIO3[4] PIO3[3] AD AE PIO2[7] PIO2[6] PIO3[0] PIO3[2] PIO3[1] AE AF VDD VDDE 3V3 VDDE 3V3 VDDE 3V3 VDDE 3V3 AF AG PIO2[4] PIO2[5] GNDE 3V3 GNDE 3V3 GNDE 3V3 AG AH PIO2[2] PIO2[3] GNDE 3V3 PIO1[7] PIO1[6] AH AJ PIO2[0] PIO2[1] GNDE 3V3 PIO1[5] PIO1[4] AJ GND GND GNDE 3V3 PIO1[3] PIO1[2] AK GND PIO0[7] PIO1[1] PIO1[0] AL AK AL EMIA DDR[16] EMIT EMI EMI EMI READYOR VDDE3V3 VDDE3V3 ADDR[18] ADDR[20] ADDR[22] WAIT SYS ITRQ[0] SYS ITRQ[1] SYS ITRQ[2] SYS ITRQ[3] GND EMI EMI EMI EMI EMIDMA ADDR[17] ADDR[19] ADDR[21] ADDR[23] REQ[1] USB VSSBS USB VDDB3V3 USB VDDBS SATA SATA VDDOSC VSSOSC SATA VDDR[1] SATA SATAVDDR VDDDLL EF EMI BUSREQ USB VSSP 2V5 USB VDDBC 2V5 USBREF SATAVDD SATA OSC2V5 VSSREF SATA VSSDLL SATA VDDR[0] ATAREF NC PIO0[0] PIO0[5] PIO0[6] AM EMI BUSGNT AM VDD VDD AN EMI DATA[10] EMI DATA[9] EMI EMI EMIDMA DATA[8] FLASHCLK REQ[0] USB VSSC 2V5 USB VDDP 2V5 USBDP GND SYSB CLKOSC SATA VSSR SATA VDDT[0] ATATXP ATARXP GND PIO0[2] PIO0[4] AN AP EMI DATA[2] EMI DATA[1] EMI DATA[0] NOT EMIBAA NOT EMILBA USB VSSP USB VDDP USBDM GND SYSB CLKIN SATA VSST SATA VDDT[1] ATATXN ATARXN GND PIO0[1] PIO0[3] AP 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND 7983497A STMicroelectronics Confidential 57/1172 Pin list and alternative functions 7.2 STx7101 Alternative functions To improve flexibility and to allow the STx7101 to fit into different set-top box application architectures, the input and output signals from some of the peripherals and functions are not directly connected to the pins of the device. Instead they are assigned to the alternative function inputs and outputs of a PIO port bit, or an I/O pin. This scheme allows the pins to be configured with their default function if the associated input or output is not required in that particular application. Some pins have several alternative functions, for inputs and/or outputs. In Table 6 to Table 11, the different alternative functions are listed under the table headings Alt 1, Alt 2, to Alt n. Inputs connected to the alternative function input are permanently connected to the input pin. The output signal from a peripheral is only connected when the PIO bit is configured into either push-pull or open drain driver alternative function mode. Some alternative function signals are available on more than one PIO port. Figure 20: I/O port pins Confidential Pin 58/1172 Push-pull tri-state open drain weak pull-up Alternative function input Alternative function 1 0 Alternative function output Output latch STMicroelectronics Confidential 7983497A Input latch TUNER A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3 Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH). The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info about the tuner. 1.1. General description of TDTC-G101D: The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C bus. 1.2. Features of TDTC-G101D: Digital Half-NIM tuner for COFDM Covers 3 Bands(From 48MHz to 862MHz for COFDM, From 45.25MHz to 863.25MHz for CCIR CH) Including IF AGC with SAW Filter Bandwidth Switching (7/8 MHz) possible DC/DC Converter built in for Tuning Voltage Internal(or External) RF AGC, Antenna Power Optional 1.3. Pinning: Audio Amplifier MAX9736(8-10WATT) General Description The MAX9736A/B Class D amplifiers provide high-performance,thermally efficient amplifier solutions. The MAX9736A delivers 2 x 15W into 8Ω loads, or 1 x 30W into a 4Ω load. The MAX9736B delivers 2 x 6W into 8Ω loads or 1 x 12W into a 4Ω load. These devices are pinfor pin compatible, allowing a single audio design to work across a broad range of platforms, simplifying design efforts, and reducing PCB inventory. Both devices operate from 8V to 28V and provide a high PSRR, eliminating the need for a regulated power supply. The MAX9736 offers up to 88% efficiency at 12V supply. Pin-selectable modulation schemes select between filterless modulation and classic PWM modulation. Filterless modulation allows the MAX9736 to pass CE EMI limits with 1m cables using only a low-cost ferrite bead and capacitor on each output. Classic PWM modulation is optimized for best audio performance when using a full LC filter. A pin-selectable stereo/mono mode allows stereo operation into 8Ω loads or mono operation into 4Ω loads. In mono mode, the right input op amp becomes available as a spare device, allowing flexibility in system design. Comprehensive click-and-pop reduction circuitry minimizes noise coming into and out of shutdown or mute. Input op amps allow the user to create summing amplifiers, lowpass or highpass filters, and select an optimal gain. The MAX9736A/B are available in 32-pin TQFN packages and specified over the -40°C to +85°C temperature range. Features Wide 8V to 28V Supply Voltage Range ♦ Spread-Spectrum Modulation Enables Low EMI Solution ♦ Passes CE EMI Limits with Low-Cost Ferrite Bead/Capacitor Filter ♦ Low BOM Cost, Pin-for-Pin Compatible Family ♦ High 67dB PSRR at 1kHz Reduces Supply Cost ♦ 88% Efficiency Eliminates Heatsink ♦ Thermal and Output Current Protection ♦ < 1μA Shutdown Mode ♦ Mute Function ♦ Space-Saving, 7mm x 7mm x 0.8mm, 32-Pin TQFN Package Applications LCD/PDP/CRT Monitors LCD/PDP/CRT TVs MP3 Docking Stations Notebook PCs PC Speakers All-in-One PCs Absolute Ratings Electrical Characteristics Operating Specifications Pinning PT2333(2.5 WATT) Description The PT2333 is a Class-D power amplifier designed for audio equipments, maximum output power can reach up to 2.5W (VDD=5V, RL=4Ω, THD=10%). The PT2333 composed of exclusively designed Class-D circuitry (patented) by PTC, along with the most advanced semi-conductor technology. When compared to the traditional Class-AB amplifiers, the PT2333’s has a much higher efficiency (>80%), low heat dissipation, and produces superior audio quality. PT2333’s external circuitry is simple and easily accessible, and consists of flawless self-protection capabilities. The chip’s packaging is small, thus it occupies an insignificant amount of space on the circuit board; therefore, making it the predominant choice when it comes to audio amplifiers. Features CMOS technology Operating voltage range from 2.7V up to 5.5V Differential analog input Maximum output power 2.5W(4Ω) @ THD=10% Output low-pass LC filter is not required. Voltage gain determinate by the external resister Contains shutdown function POP noises free in shutdown and power ON/OFF period Built-in short circuit protection Built-in overheat protection High efficiency (8Ω load >85%), low heat dissipation Available in MSOP 10-pin and WLCSP 9-pin miniature packages Aplications Cellular phone Portable media player GPS LCD monitor Small multimedia speakers Hand-free phone Laptop Other audio applications Block Diagram POWER STAGE The DC voltages required at various parts of the chassis and inverters are provided by a main power supply unit. The power supply generates 33V, 24V, 12V, 5V, 3,3V and 5V, 3,3V stand by mode DC voltages. Power stage which is on-chasis generates 1,26V stand by voltage and 8V, 2.5V, 2,6V, 1,8V and 1V supplies for other different parts of the chassis. ADAPTOR USE (Optional) The DC voltages required at various parts of the chassis and inverters are provided by an external power supply unit or produced on the chassis if an adapter is used for the supply. The 12V dc voltage is switched by IRF 7314 power mosfet in TV sets with mechanical switch to produce the required standby voltage. Also regulators and mosfets generate 1.8V, 3.3V and 5V and 1.26V voltages for other different parts of the chassis. MPEG-2/MPEG-4 DVB Decoder (STi7101) 1.4. General Description The STi7101 is a new generation, high-definition IDTV / set-top box / DVD decoder chip, and provides very high performance for low-cost HD systems. STx7101 includes an H.264 video decoder for new, low bit rate applications. Based on the Omega2 (STBus) architecture, this system-on-chip is a full back-end processor for digital terrestrial, satellite, cable, DSL and IP client high-definition set-top boxes, compliant with ATSC, DVB, DIRECTV, DCII, OpenCable and ARIB BS4 specifications. It includes all processing for DVD applications. The STx7101 demultiplexes, decrypts and decodes HD or SD video streams with associated multi-channel audio. Video is output to two independently formatted displays: a full resolution display intended for a TV monitor, and a downsampled display intended for a VCR or DVD-R. Connection to a TV or display panel can be analog through the DACs, or digital through a copy protected DVI/HDMI. Composite outputs are provided for connection to the VCR with Macrovision protection. Audio is output with optional PCM mixing to an S/PDIF interface, PCM interface, or through integrated stereo audio DACs. Digitized analog programs can also be input to the STx7101 for reformatting and display. The STx7101 includes a graphics rendering and display capability with a 2D graphics accelerator, three graphics planes and a cursor plane. A dual display compositor provides mixing of graphics and video with independent composition for each of the TV and VCR/DVD-R outputs. The STx7101 includes a stream merger to allow seven different transport streams from different sources to be merged and processed concurrently. Applications include DVR time-shifted viewing of a terrestrial program, while acquiring an EPG/data stream from a satellite or cable front end. The flexible descrambling engine is compatible with required standards including DVB, DES, AES and Multi2. The STx7101 embeds a 266 MHz ST40-202 CPU for applications and device control. A dual DDR1 SDRAM memory interface is used for higher performance, to allow the video decoder the required memory bandwidth for HD H.264 and sufficient bandwidth for the CPU and the rest of the system. A second memory bus is also provided for flash memory, storing resident software, and for connection of peripherals. This bus also has a high speed synchronous mode that can be used to exchange data between two STx7101 devices. This can be used to connect a second STx7101 as a co-decoder for a dual TV STB application. A harddisk drive (HDD) can be connected either to the serial ATA interface, or as an expansion drive through the USB 2.0 port. The figure below shows the architecture of the Sti7101. 6.2 Features The STx7101 is a single-chip, high definition video decoder including: _ H.264 support _ Linux® and OS21 compatible ST40 CPU core: 266 MHz _ transport filtering and descrambling _ video decoder: H.264 (MPEG-4 part 10) and MPEG-2 _ SVP compliant _ graphics engine and dual display: standard and highdefinition _ audio decoder _ DVD data retrieval and decryption The STx7101 also features the following embedded interfaces: _ USB 2.0 host controller/PHY interface _ DVI/HDMI™ output _ digital audio and video auxiliary inputs _ low-cost modem _ 100BT ethernet controller with integrated MAC and MII/ RMII interface for external PHY _ serial ATA (SATA) Processor subsystem _ ST40 32-bit superscaler RISC CPU _ 266 MHz, 2-way set associative 16-Kbyte ICache, 32-Kbyte DCache, MMU _ 5-stage pipeline, delayed branch support _ floating point unit, matrix operation support _ debug port, interrupt controller Transport subsystem _ TS merger/router _ 2 serial/parallel inputs _ 1 bidirectional interface _ merging of 3 external transport streams _ transport streams from memory support _ NRSS-A module interface _ TS routing for DVB-CI and CableCARDmodules _ Programmable transport interfaces (PTIs) _ two programmable transport interfaces _ two transport stream demultiplexers: DVB, DIRECTV®, ATSC, ARIB, OpenCable, DCII _ integrated DES, AES, DVB and Multi2 descramblers _ NDS random access scrambled stream protocol (RASP) compliant _ NDS ICAM CA _ support for VGS, Passage and DVS042 residue handling Video/graphics subsystem _ H.264(MPEG-4 part 10) main and high profile level 4.1/MPEG-2 MP@HL video decoder _ advanced error concealment and trick mode support _ dual MPEG-2 MP@HL decode _ SD digital video input _ Displays _ one HD display multi format capable (1080I, 720P, 480P/576P, 480I/576I) analog HD output RGB or YPbPr HDMI encoded output _ one standard-definition display analog SD output: YPbPr or YC and CVBS _ Gamma 2D/3D graphics processor _ triple source 2D gamma blitter engine _ alpha blending and logical operations _ color space and format conversion _ fast color fill _ arbitrary resizing with high quality filters _ acceleration of direct drawing by CPU _ Gamma compositor and video processor _ 7-channel mixer for high definition output _ independent 2-channel mixer for SD output _ 3 graphic display planes _ high-quality video scaler _ motion and detail adaptive deinterlacer _ linear resizing and format conversions _ horizontal and vertical filtering _ Copy protection _ HDMI /HDCP copy protection hardware _ SVP compliant _ Macrovision® copy protection for 480I, 480P, 576I, 576P outputs _ DTCP-IP _ AWG-based DCS analog copy protection Audio subsystem _ Digital audio decoder _ support for all the most popular audio standards including MPEG-1 layer I/II, MPEG-2 layer II, MPEG-2 AAC, MPEG- 4 AAC LC 2-channel/5.1 channel MPEG-4 AAC+SBR 2channel/5.1 channel, Dolby® Digital EX, Pro Logic® II, MLP™ and DTS® _ PCM mixing with internal or external source and sample rate conversion _ 6- to 2-channel downmixing _ PCM audio input _ independent multichannel PCM output, S/PDIF output and analog output _ Stereo 24-bit audio DAC for analog output _ IEC958/IEC1937 digital audio output interface (S/PDIF) _ CSS/CPxM copy protection hardware Interfaces _ External memory interface (EMI) _ 16-bit interface supporting ROM, flash, SFlash, SRAM, peripherals _ access in 5 banks _ high speed synchronous mode for interconnecting two STx7101 devices _ External microprocessor interface (EMPI) _ 32-bit MPX satellite, target-only interface, _ synchronous operation at MPX clock speed, capable of 100 MHz, _ Dual local memory interface (LMI) _ dual interface (2 x 32-bit) for DDR1 200-MHz (DDR400) memories, supports 128-, 256- and 512-Mbit devices _ USB 2.0 host controller/PHY interface _ Serial ATA hard-disk drive support _ record and playback with trick modes _ pause and time shifting, watch and record _ 100BT Ethernet controller, MAC and MII/RMII _ On-chip peripherals _ 4 ASCs (UARTs) with Tx and Rx FIFOS, two of which can be used in smartcard interfaces _ 2 smartcard interfaces and clock generators (improved to reduce external circuitry) _ 3 SSCs for I²C/SPI master slaves interfaces _ serial communications interface (SCIF) _ 2 PWM outputs _ teletext serializer and DMA module _ 6 banks of general purpose I/O, 3.3 V tolerant _ SiLabs line-side (DAA) interface _ modem analog front end (MAFE) interface _ infrared transmitter/receiver supporting RC5, RC6 and RECS80 codes _ UHF remote receiver input interface _ interrupt level controller and external interrupts, 3.3 V tolerant _ low power/RTC/watchdog controller _ integrated VCXO _ DiSEqC 2.0 interface _ PWM capture/compare functions _ Flexible multi-channel DMA Services and package _ JTAG/TAP interface, ST40 toolset support, ST231 toolset support _ Package _ 35 x 35 PBGA, 580 + 100 balls (standard version) 6.3 Absolute Maximum Ratings I/O specifications 3.3 volt pads I/O specifications 2.5 volt pads DVB-T DEMODULATOR – STV0362 8.1 General Description The STv0362 is a single-chip demodulator using coded orthogonal frequency division multiplexing (COFDM) and is intended for digital terrestrial receivers using compressed video, sound and data services. It converts IF or baseband differential signals to MPEG-2 format by processing OFDM carriers. The STv0362 is fully compliant with the DVB-T specification (ETS 300 744) and NorDig Unified specification. The chip implements all the functions to convert the signals from the IF or direct conversion tuner, to produce the MPEG-2 transport stream output; in terms of IF tuner configuration, the chip is compatible with the popular STV0360/STV0361. The STv0362 offers improved performance over the STV0360 with respect to: channel estimation and correction, an extended CRL frequency and TRL timing offset, additional features such as: o synchronization for echo outside GI, o impulse noise rejection, o PLL allowing 4 MHz quartz usage. The STv0362 processes 2, 4 and 8 K modes and integrates two A/D converters capable of handling up to 64 QAM carriers in a direct IF or zero IF sampling architecture. This eliminates the need for an external downconverter. A 12-bit ADC, intended for RF signal strength indication, eliminates the need for external components when using wide-band AGC tuners. In addition to the demodulation and forward error correction (FEC) functions required for recovery of the QAM modulated bit streams with very low BER, the chip also includes several features that give easy and immediate access to various quality monitoring parameters or lock status. The STv0362 also provides delayed AGC and a noise-free I2C bus dedicated to tuner control, which facilitate the design of high quality integrated receiver decoders. The STv0362 outputs an error-corrected MPEG-2 transport stream that complies with the DVB common interface format with programmable data clock frequency. The STv0362 features the full DVB-T and DVB-H standards framing structure, channel coding and modulation. The symbol, timing and carrier recovery loops are fully digital and sized with regard to the state-of-the-art RF down-converting devices. The STv0362 is compatible with direct conversion tuners featuring two differential ADC for I and Q channels. The tuner baseband power is controlled by a classic AGC loop, and the radio frequency level is monitored by a dedicated single-ended 8-bit ADC. It is recommended the RF power is left under the tuner’s control, but it can be derived from baseband power by a dedicated power split algorithm. If required, the tuner serial I2C bus can be isolated by the STv0362 I2C bus repeater. The terrestrial DVB-T network can be subjected to several interference sources which are the neighboring digital and analog channels, as well as the in-band analog channels. The STv0362 cancels these interference sources as well removing the effects of impulse noise. The channel equalization is capable of static and dynamic echo cancelling even in severe urban environments. The embedded algorithms are enhanced to cope with out-ofguard interval echoes; specific channel quality monitoring is available for acquisition and survey. The specific power handling constraints are primarily addressed by both technology and clock rate management. The efficiency of channel acquisition and reacquisition, minimizes power consumption. 8.2 Features Compatible with direct conversion (ZIF) and IF tuners o Wide range carrier tracking loop for offset recovery o Dual analog to digital conversion for IQ baseband interface o Signal strength indicator dedicated ADC o Dual ΣΔ digital split AGC for RF and BB o Flexible clock generation to operate with 4 MHz to 27 MHz external reference Channel management o NorDig Unified Specification (v1.0.2) capable o Dynamic fading compatible o Urban environment compatible o Channel reception quality indicator o Out of guard interval echoes compatible o Impulsive noise rejection capable o Outstanding adjacent and co-channel rejection capability with integrated channel filters Digital carrier, timing and symbol recovery loops Decoding o 2K, 4K, 8K FFT length o 6, 7 and 8 MHz channels bandwidth o 1/4, 1/8, 1/16, 1/32 guard interval length o QPSK - 16 QAM - 64 QAM modulations o Hierarchical capability o TPS decoding o Viterbi soft decoder rate 1/2 o Puncture rates are 1/2, 2/3, 3/4, 5/6, 7/8 o Outer Reed-Solomon decoder as per DVB-T system o Energy dispersal descrambler Technology o Low power CMOS process (90nm) o Multi supply: 1.0 V core, 2.5 V analog, 3.3 V digital interface o TQFP64 7x7x1.0 mm o Power consumption: 350 mW (typ), o Standby < 80 mW Data to transport decoder o DVB common interface compliant o 12-bit parallel and 5-bit serial data interface with data on D7 (packet error private line) o Automatic regulation of the transport bit o rate with regard to transport clock o Up to 33 Mbit/s payload data rate I2C serial bus interface o Fast I2C up to 400 kHz slave interface o Four possible slave addresses o Up to 400 kbit/s private repeater for tuner isolation GPIOs and interruption line o Lock indicators: AGC, symbol, TPS, VITERBI-decoder and transport synchronization o ΣΔ analog and logical levels generation Monitoring through I2C serial interface o C/N estimator o Constellation and frequency response display o BER and PER estimator 8.3 Absolute Maximum Rating 8.4 Pinning DVB-C DEMODULATOR – STV0297E 7.1 General Desription The STV0297E is a complete single-chip QAM (quadrature amplitude modulation) demodulation and FEC (forward error correction) solution that performs sampled IF to transport stream (MPEG-2 or MPEG-4) block processing of QAM signals. It is intended for the digital transmission of compressed television, sound, and data services over cable. It is fully compliant with ITU-T J83 Annexes A/C or DVB-C specification bitstreams (ETS 300 429, “Digital broadcasting systems for television, sound and data services – Framing structure, channel coding and modulation - Cable Systems”). It can handle square (16, 64, 256-QAM) and non-square (32, 128-QAM) constellations. Japanese DBS systems require a transport stream multiplex frame (TSMF) layer to carry digital signals over cable systems. When the recovered transport stream is a multiplex frame, the STV0297E postprocesses it to extract a single transport stream. Automatic detection of the TSMF layer is provided. The chip integrates an analog-to-digital converter that delivers the required performance to handle up to 256-QAM signals in a direct IF sampling architecture, thus eliminating the need for external downconversion. 7.2 Features Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams Processes Japanese transport stream multiplex frame (TSMF) High-performance integrated A/D converter suitable for direct IF architecture in all QAM (quadrature amplitude modulation) modes Supports 16, 32, 64, 128 and 256 point constellations Small footprint package: (10 x 10 mm²) Very low power consumption Full digital demodulation Variable symbol rates Front derotator for better low symbol rate performance and relaxed tuner constraints Integrated matched filtering Robust integrated adaptive pre and post equalizer On-chip FEC A/C with ability to bypass individual blocks 10 programmable GPIO Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs) Integrated signal quality monitors, plus lock indicator and interrupt function mapped to GPIO pin Improved signal acquisition System clock generated on-chip from quartz crystal Low frequency crystal operations 4, 16, 25 - 30 MHz 4 I2C addresses Easy control and monitoring via 2-wire fast I2C bus 7.3 Absolute Maximum Ratings 7.4 Pinning STE100P Ethernet PHY 7.5 General Description The STE100P, also referred to as STEPHY1, is a high performance Fast Ethernet physical layer interface for 10Base-T and 100Base-TX applications. It was designed with advanced CMOS technology to provide a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MAC) and a physical media interface for 100Base-TX of IEEE802.3u and 10Base-T of IEEE802.3. The STEPHY1 supports both half-duplex and fullduplex operation, at 10 and 100 Mbps operation. Its operating mode can be set using auto-negotiation, parallel detection or manual control. It also allows for the support of auto-negotiation functions for speed and duplex detection. 7.6 Features - IEEE802.3u 100Base-TX and IEEE802.3 10Base-T compliant - Support for IEEE802.3x flow control - IEEE802.3u Auto-Negotiation support for 10Base-T and 100Base-TX - MII interface - Standard CSMA/CD or full duplex operation supported - Integrates the whole Physical layer functions of 100Base-TX and 10Base-T - Provides Full-duplex operation on both 100Mbps and 10Mbps modes - Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps - Provides MLT-3 transceiver with DC restoration for Base-line wander compensation - Provides transmit wave-shaper, receive filters, and adaptive equalizer - Provides loop-back modes for diagnostic - Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder - Supports external transmit transformer with turn ratio 1:1 - Supports external receive transformer with turn ratio 1:1 - Standard 64-pin QFP package pinout 7.7 Absolute Maximum Ratings 12.4 Pinning 8 SAW FILTER 8.1 IF Filter for Audio Applications – Epcos K9656M 8.1.1 Standart: B/G D/K I L/L’ 8.1.2 Features: TV IF audio filter with two channels Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75 MHz (L’- NICAM) Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz and 33,40 MHz 8.1.3 Pin configuration: 1 Input 2 Switching input 3 Chip carrier - ground 4 Output 5 Output 8.1.4 Frequency response: 8.2 IF Filter for Video Applications – Epcos K3958M 8.2.1 Standart: B/G D/K I L/L’ 8.2.2 Features: TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz Constant group delay Pin configuration: 1 Input 2 Input - ground 3 Chip - carrier ground 4 Output 5 Output 8.2.3 Frequency response: IC DESCRIPTIONS 8.3 LM1117 8.3.1 General Description The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to improve the transient response and stability. 8.3.2 Features Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions Space Saving SOT-223 Package Current Limiting and Thermal Protection Output Current 800mA Line Regulation 0.2% (Max) Load Regulation 0.4% (Max) Temperature Range LM1117 0°C to 125°C LM1117I -40°C to 125°C 8.3.3 Applications 2.85V Model for SCSI-2 Active Termination Post Regulator for Switching DC/DC Converter High Efficiency Linear Regulators 15 32” TFT TV Service Manual 10/01/2005 Battery Charger Battery Powered Instrumentation 8.3.4 Absolute Maximum Ratings 8.3.5 Pinning 8.4 74HCT4053 8.4.1 General Description The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for 74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). 8.4.2 Features Low ON resistance: 80 W (typical) at VCC - VEE = 4.5 V 70 W (typical) at VCC - VEE = 6.0 V 60 W (typical) at VCC - VEE = 9.0 V Logic level translation: To enable 5 V logic to communicate with ±5 V analog signals Typical ‘break before make’ built in Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM EIA/JESD22A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 8.4.3 Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 8.4.4 Absolute Maximum Ratings 8.4.5 Pinning 8.5 NUP4004M5 8.5.1 General Description This 5-Pin bi-directional transient suppressor array is designed for applications requiring transient overvoltage protection capability. It is intended for use in transient voltage and ESD sensitive equipment such as computers, printers, cell phones, medical equipment, and other applications. Its integrated design provides bi-directional protection for four separate lines using a single TSOP-5 package. This device is ideal for situations where board space is a premium. 8.5.2 Features Bi-directional Protection for Four Lines in a Single TSOP-5 Package Low Leakage Current Low Capacitance Provides ESD Protection for JEDEC Standards JESD22 Machine Model = Class C Human Body Model = Class 3B Provides ESD Protection for IEC 61000-4-2, 15 kV (Air), 8 kV (Contact) This is a Pb-Free Device 8.5.3 Absolute Maximum Ratings 8.5.4 Pinning 8.6 FDN336P 8.6.1 General Description The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits.This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The ST24LC21 cannot switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. 8.6.2 Features 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION 2.5V to 5.5V SINGLE SUPPLY VOLTAGE 400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE PAGE WRITE (up to 8 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES 8.6.3 Absolute Maximum Ratings 8.6.4 Pinning 8.7 TL062 - 8.7.1 General Description Low-power JFET-input operational amplifier 8.7.2 Features Very Low Power Consumption Typical Supply Current . . . 200 µA (Per Amplifier) Wide Common-Mode and Differential Voltage Ranges Low Input Bias and Offset Currents Common-Mode Input Voltage Range Includes VCC+ Output Short-Circuit Protection High Input Impedance . . . JFET-Input Stage Internal Frequency Compensation Latch-Up-Free Operation High Slew Rate . . . 3.5 V/µs Typ 8.7.3 Absolute Maximum Ratings 8.7.4 Pinning 8.8 PI5V330 8.8.1 General Description Pericom Semiconductor.s PI5V series of mixed signal video circuits are produced in the Company.s advanced CMOS low-power technology, achieving industry leading performance. The PI5V330 is a true bidirectional Quad 2-channel multiplexer/demultiplexer that is recommended for both RGB and composite video switching applications. The VideoSwitch. can be driven from a current output RAMDAC or voltage output composite video source. Low ON-resistance and wide bandwidth make it ideal for video and other applications. Also this device has exceptionally high current capability which is far greater than most analog switches offered today. A single 5V supply is all that is required for operation. The PI5V330 offers a high-performance, lowcost solution to switch between video sources. The application section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier. 8.8.2 Features High-performance, low-cost solution to switch between video sources Wide bandwidth: 200 MHz Low ON-resistance: 3Ω Low crosstalk at 10 MHz: .58 dB Ultra-low quiescent power (0.1 µA typical) Single supply operation: +5.0V Fast switching: 10 ns High-current output: 100 mA Packages available: 16-pin 300-mil wide plastic SOIC (S) 16-pin 150-mil wide plastic SOIC (W) 16-pin 150-mil wide plastic QSOP (Q) 8.8.3 Absolute Maximum Ratings 8.8.4 Pinning 8.9 AZC099-04S 8.9.1 General Description AZC099-04S is a high performance and low cost design which includes surge rated diode arrays to protect high speed data interfaces. The AZC099-04S family has been specifically designed to protect sensitive components, which are connected to data and transmission lines, from over-voltage caused by Electrostatic Discharging (ESD), Electrical Fast Transients (EFT), and Lightning. AZC099-04S is a unique design which includes surge rated, low capacitance steering diodes and a unique design of clamping cell which is an equivalent TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the power supply line or to the ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. AZC099-04S may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (± 15kV air, ±8kV contact discharge). 8.9.2 Features ESD Protect for 4 high-speed I/O channels Provide ESD protection for each channel to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) (5/50ns) Level-3, 20A for I/O, 40A for Power IEC 61000-4-5 (Lightning) 4A (8/20μs) 5V operating voltage Low capacitance : 1.0pF typical Fast turn-on and Low clamping voltage Array of surge rated diodes with internal equivalent TVS diode Small package saves board space Solid-state silicon-avalanche and active circuit triggering technology 8.9.3 Absolute Maximum Ratings 8.9.4 Pinning 8.10 TDA1308 8.10.1 General Description The TDA1308; TDA1308A is an integrated class-AB stereo headphone driver contained in an SO8, DIP8 or a TSSOP8 plastic package. The TDA1308AUK is available in an 8 bump wafer level chip-size package (WLCSP8). The device is fabricated in a 1 mm Complementary Metal Oxide Semiconductor (CMOS) process and has been primarily developed for portable digital audio applications. The difference between the TDA1308 and the TDA1308A is that the TDA1308A can be used at low supply voltages. 8.10.2 Features Wide temperature range No switch ON/OFF clicks Excellent power supply ripple rejection Low power consumption Short-circuit resistant High performance High signal-to-noise ratio High slew rate Low distortion Large output voltage swing 8.10.3 Absolute Maximum Ratings 8.10.4 Pinning 8.11 LM358D 8.11.1 General Description The LM158 series consists of two independent, high gain, internally frequency compensated operational amplifiers which were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. Application areas include transducer amplifiers, dc gain blocks and all the conventional op amp circuits which now can be more easily implemented in single power supply systems. For example, the LM158 series can be directly operated off of the standard +5V power supply voltage which is used in digital systems and will easily provide the required interface electronics without requiring the additional ±15V power supplies. The LM358 and LM2904 are available in a chip sized package (8-Bump micro SMD) using National’s micro SMD package technology. 8.11.2 Features Available in 8-Bump micro SMD chip sized package, Internally frequency compensated for unity gain Large dc voltage gain: 100 dB Wide bandwidth (unity gain): 1 MHz (temperature compensated) Wide power supply: Single supply: 3V to 32V or dual supplies: ±1.5V to ±16V Low supply current drain (500 µA)—essentially independent of supply voltage Low input offset voltage: 2 mV Input common-mode voltage range includes ground Differential input voltage range equal to the power supply voltage Large output voltage swing 8.11.3 Absolute Maximum Ratings 8.11.4 Pinning 8.12 74LCX244 8.12.1 General Description The LCX244 contains eight non-inverting buffers with 3-STATE outputs. The device may be employed as a memory address driver, clock driver and bus-oriented transmitter/receiver. The LCX244 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. 8.12.2 Features 5V tolerant inputs and outputs 2.3V to 3.6V VCC specifications provided 6.5ns Tpd max. (VCC=3.3V), 10µA ICCmax. Power down high impedance inputs and outputs Supports live insertion/withdrawal ±24mA output drive (VCC=3.0V) Implements patented noise/EMI reduction circuitry Latch-up performance exceeds 500mA ESD performance:Human body model>2000V, Machine model>200V Leadless DQFN package 8.12.3 Absolute Maximum Ratings 8.12.4 Pinning 8.13 74LCX245 8.13.1 General Description The LCX245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V and 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The T/R input determines the direction of data flow through the device. The OE input disables both the A and B ports by placing them in a high impedance state. The LCX245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. 8.13.2 Features 5V tolerant inputs and outputs 2.3V to 3.6V VCC specifications provided 7.0ns tPDmax. (VCC=3.3V), 10µA ICCmax. Power down high impedance inputs and outputs Supports live insertion/withdrawal ±24mA output drive (VCC=3.0V) Implements patented noise/EMI reduction circuitry Latch-up performance exceeds 500mA ESD performance: Human body model>2000V, Machine model>200V Leadless DQFN package 8.13.3 Absolute Maximum Ratings 8.13.4 Pinning 8.14 FSA3157 8.14.1 General Description The NC7SB3157 / FSA3157 is a high-performance, single- pole / double-throw (SPDT) analog switch or 2:1 multiplexer/ de-multiplexer bus switch. The device is fabricated with advanced sub-micron CMOS technology to achieve high-speed enable and disable times and low on resistance. The break-beforemake select circuitry prevents disruption of signals on the B Port due to both switches temporarily being enabled during select pin switching. The device is specified to operate over the 1.65 to 5.5V VCC operating range. The control input tolerates voltages up to 5.5V, independent of the VCC operating range. 8.14.2 Features Useful in both analog and digital applications Space-saving, SC70 6-lead surface mount package Ultra-small, MicroPak™ Pb-free leadless package Low On Resistance: <10Ω on typical at 3.3V VCC Broad VCC operating range: 1.65V to 5.5V Rail-to-rail signal handling Power-down, high-impedance control input Over-voltage tolerance of control input to 7.0V Break-before-make enable circuitry 250 MHz, 3dB bandwidth 8.14.3 Absolute Maximum Ratings 8.14.4 Pinning 8.15 TSH343 8.15.1 General Description The TSH343 is a triple single-supply video buffer featuring an internal gain of 6dB and a large bandwidth of 280MHz. The main advantage of this circuit is that its input DC level shifter allows for video signals on 75Ω video lines without damage to the synchronization tip of the video signal, while using a single 5V power supply with no input capacitor. The DC level shifter is internally fixed and optimized to keep the output video signals between low and high output rails in the best position for the greatest linearity. Chapter 4 of this datasheet gives technical support when using the TSH343 as Y-Pb-Pr driver for video DAC output on a video line (see TSH344 for RGB signals). The TSH343 is available in the compact SO8 plastic package for optimum space-saving. 8.15.2 Features Bandwidth: 280MHz 5V single-supply operation Internal input DC level shifter No input capacitor required Internal gain of 6dB for a matching between 3 channels AC or DC output-coupled Very low harmonic distortion Slew rate: 780V/μs Specified for 150Ω and 100Ω loads Tested on 5V power supply Data min. and max. are tested during production 8.15.3 Absolute Maximum Ratings 8.15.4 Pinning 8.16 MT48LC4M16A2TG8E 8.16.1 General Description The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then ollowed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). 8.16.2 Features PC66-, PC100- and PC133-compliant 143 MHz, graphical 4 Meg x 16 option Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8 or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and AutO Refresh Modes Self Refresh Modes: standard and low power 64ms, 4,096-cycle refresh LVTTL-compatible inputs and outputs Single +3.3V ±0.3V power supply 8.16.3 Absolute Maximum Ratings 8.16.4 Pinning 8.17 MP1583 8.17.1 General Description The MP1583 is a step-down regulator with a built in internal Power MOSFET. It achieves 3A continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. Adjustable soft-start reduces the stress on the input source at turn-on. In shutdown mode the regulator draws 20µA of supply current. The MP1583 requires a minimum number of readily available external components to complete a 3A step down DC to DC converter solution. 8.17.2 Features 3A Output Current Programmable Soft-Start 100mΩ Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors Up to 95% Efficiency 20µA Shutdown Mode Fixed 385KHz frequency Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide 4.75 to 23V operating Input Range Output Adjustable From 1.22 to 21V Under Voltage Lockout Available in 8 pin SOIC Package 3A Evaluation Board Available 8.17.3 Absolute Maximum Ratings 8.17.4 Pinning 8.18 MP2112 8.18.1 General Description The MP2112 is a 1MHz constant frequency, current mode, PWM step-down converter. The device integrates a main switch and a synchronous rectifier for high efficiency without an external Schottky diode. It is ideal for powering portable equipment that powered by a single cell Lithium-Ion (Li+) battery. The MP2112 can supply 1A of load current from a 2.5V to 6V input voltage. The output voltage can be regulated as low as 0.6V. The MP2112 can also run at 100% duty cycle for low dropout applications. The MP2112 is available in a space-saving 6-pin QFN package. 8.18.2 Features High Efficiency: Up to 95% 1MHz Constant Switching Frequency 1A Available Load Current 2.5V to 6V Input Voltage Range Output Voltage as Low as 0.6V 100% Duty Cycle in Dropout Current Mode Control Short Circuit Protection Thermal Fault Protection <0.1µA Shutdown Current Space Saving 3mm x 3mm QFN6 Package 8.18.3 Absolute Maximum Ratings 8.18.4 Pinning 8.19 MAX809LTR 8.19.1 General Description The MAX809 and MAX810 are cost-effective system supervisor circuits designed to monitor VCC in digital systems and provide a reset signal to the host processor when necessary. No external components are required. The reset output is driven active within ~200msec of VCC falling through the reset voltage threshold. Reset is maintained active for a timeout period which is trimmed by the factory after VCC rises above the reset threshold. The MAX810 has an active-high RESET output while the MAX809 has an active-low RESET output. Both devices are available in SOT-23 and SC-70 packages. The MAX809/810 are optimized to reject fast transient glitches on the VCC line. Low supply current of 0.5 A (VCC = 3.2 V) makes these devices suitable for battery powered applications. 8.19.2 Features Precision VCC Monitor for 1.5 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps Four Guaranteed Minimum Power-On Reset Pulse Width Available (1 ms, 20 ms, 100 ms, and 140 ms) RESET Output Guaranteed to VCC = 1.0 V. Low Supply Current Compatible with Hot Plug Applications VCC Transient Immunity No External Components Wide Operating Temperature: -40°C to 105°C Pb-Free Packages are Available 8.19.3 Absolute Maximum Ratings 8.19.4 Pinning 19 BLOCK DIAGRAMS RJ45 I2C_TUN_DVB I2C_5V TS_CI RF_AGC_DVB THOMSON DTT75430 LG TDTC-GXX1D ETHERNET PHY STE101P FSA3157 IF AGC SWITCH IF AGC MPEG4 DECODER STi7101 TS_C DVB-C QAM DEMOD. STV0297 2xFLASH NOR 64Mbit (common) NAND 2Gbit (w/ethernet) TS_CI 4xDDR1 16Mx16 IF AGC_C IF AGC_T USB HUB USB2503 ANALOG IF UART LVDS CONNECTOR 2MB SD RAM YPbPr 14.3181MHz XTAL SPDIF RESET IC MAX809LTR EEPROM 24C32 PANEL SUPPLY 1MB Serial Flash PANEL_VCC PANEL VCC SW SAW K3958M I2C_5V SCL/SDA I2C LEVEL SHIFTER CIRCUIT VIF_TUNER StBy M I2C SIF_TUNER MST6Wx7 SC1 CVBS SC1 RGB/FB SCART I/O PORTS +12V +1V2_STBY +2V6 SC1_CVBS_OUT +3V3 SC1_AUD_OUT AUDIO AMP. PT2333 or MP1720 2 x 2.5W ON/OFF MAIN SPEAKER OUT L/R “” HDMI_2 YPbPr BACKLIGHT_ON/OFF BACKLIGHT_DIMMING POWER_ON/OFF DVD AUDIO_IN DVD Y/C_IN HP AMPLIFIER TDA1308T DVD Connector VGA HDMI_1 -P POP NOISE CIRCUIT +24V +12V +5V_STBY IR DVD_SENSE DRAWN BY: SADIK ŞEHİT LINE OUT L/R PI5V330 RGB Switch IDTV/YPbPr_SW IDTV_YPbPr/SOY DATE:03.03.2009 +5V LINE OUT HDMI1 TMDS DATA/CLOCK 2 VESTEL ELECTRONICS R&D GROUP 17MB37 BLOCK DIAGRAM VGA/YPbPr AUDIO L/R YPbPr AUDIO L/R CVBS Y/C DDC TMDS DATA/CLK I2C2/UART DDC SVHS FAV_Video/Audio HP OUT L/R DDC 4 Layer PCB EDID E2PROM 24C02 TMDS DATA/CLK HDMI2 DETACHED HP MUTE HDMI1 EDID E2PROM 24C02 +P +V I/O PORTS LED1 LED2 DDC_WP PANEL_VCC_ON/OFF POWER ON/OFF SCART1 PIN8 MPEG DECODER IRQ PROTECTION NVM_WP KEYBOARD +3V3_STBY SC1 AUD_IN TRANSISTOR SWITCH TV/AV PANEL_ VCC_ ON/OFF I/O PORTS SAW K9656M SCL/SDA2 This Block does not exist, unless PCB has enough space Main Speaker 4R RF AGC I2C BUFFERS 74LCX244 TS_T DVB-T COFDM DEMOD. STV0362 RF_AGC_A DIGITAL IF 74HCT4053 I2C & AGC SWITCH 19.1 General Block Diagram CI_BUFFERS IR ON/OFF +5V +3V3_STBY +3V3 DVD Power Connector +12V POWER MODULE -V 1 2 3 4 5 AIF 12 ANALOG_IF DIF1 11 TUNER_PIN11 DIF2 10 TUNER_PIN10 IF_AGC 9 7 B2 6 F116 1 OVER_CUR_DETECT 5V_TUN R502 10k 1 330R 2 2 1 1 4 1 330R RF_AGC R622 1k 3 1 1 Q102 FDN336P BC848B Q115 2 2 1 R503 10k 2 1 C359 10u 10V AGC B 33V_TUNER C532 1u 50V 2 2 1 47p 50V D121 1 1 33V_TUNER 2 1N4148 R111 12k C448 47u 16V 1 RF_AGC_A +5V AIF_OUT IF_AGC_DVB_IN 8 N.C. 2 6 SDA 5 SCL 4 1 S308 BA 2 1 F159 2 1 2 5V_TUN 330R 2 1 SCL_TUNER 2 1 2 3 4 5 6 7 8 SCL_TUN_DVB SCL RF_AGC_DVB RF_AGC RF_AGC_A 10V 100n C137 NEAR THE TUNER 2 2 1 2 SCL_TUN 2Y1 2Y0 3Y1 3Z 3Y0 E VEE GND RF_AGC 2 ACT_ANT 2 1 1 SCL_TUN SDA_TUN SDA_TUN_DVB SDA R254 4k7 1 C 2 5V_VCC 2 IDTV_SW 3 R127 47R C587 47p 50V 1 SDA_TUNER 16 15 14 13 12 11 10 9 VCC 2Z 1Z 1Y1 1Y0 S1 S2 S3 3 S104 2 74HCT4053 1 1 R126 47R C586 47p 50V 1 SCL_TUNER 2 R624 1k 100n U115 10V IF_AGC_DVB ANALOG_IF 2 SDA_TUNER 1 RF_AGC 10V 100n C136 T_AGC R505 10k This part must be placed near the tuner ADDRESS_SEL_TUNER SAS 1 IF_AGC_DVB_IN 2 5V_TUN 7 1 S105 AND I2C SWITCH PART 5V_VCC TUNER_PIN10 10 9 2 C128 1u C626 L116 11 Near Tuner supply pin 2 2 ACT_ANT 2 1 IF_AGC C1158 220u 6V3 ANT_CTRL 1 TU101 DTOS403LH172A VT 1 C134 100n 10V !!!En az 1.8 cm2 altta ve üstte soðutma alaný býrakýlmalý. 1K 2 1 1 Samsung/Thomson IFOUT+ 2 3 ACT_ANT 33V_TUNER 2 R460 330R 1 SCL_TUNER TUNER_PIN11 IFOUT- C360 10u 10V 2 1 ANT_PWR 5V_TUN VOUT R504 10k 3 TP151 RF_AGC OUT 2 GND 1 1 4 B1 SDA_TUNER 5 SCL C600 47u 16V 1 2 F234 SDA 3 IN 2 330R 5V_TUN TH101 ADDRESS_SEL_TUNER 1 8V_VCC 2 2 5V_TUN U123 LM1117 1 NC A 2 2R1 IF_AGC_DVB_IN 8 R482 4R7 R408 1k 1 2 AS B C 8 ACTIVE ANTENNA R501 10k TU102 TDTC-G101D 7 TUNER SUPPLY OPSION LG A 6 2 Q116 BC848B SDA_TUN 2 R595 22k 1 1 C913 TUNER_PIN11 2p2 50V C1029 DIGITAL_IF1n 50V C914 TUNER_PIN10 1 Q140 2 1 BSN20 2 3 Q144 BF799 2 2 10n 16V N.C. 2 R384 10R VIFM Z102 C547 1 IN1 OUT1 4 K3958M IN2 OUT2 5 2 GND 1 1 R623 1k 2 1 1 2 2 R209 100k 1 2 1 F187 1 2 62 AVDD_MPLL 63 VR27 64 VR12 65 AVDD_RXS 66 GND_RXS 67 SIFP 68 SIFM 69 VIFM 70 VIFP 71 GND_RXV 72 AVDD_RXV 73 TAGC 2 1 330R 2 100n 10V F184 2 330R 2 1 3V3_VCC SIFP SIFM VIFM C361 1 1 2 330R 5V_TUN C129 2 1 10u 10V F185 3V3_VCC VIFP 2 100n 10V F186 1 U138 MST6WB7GQ-3 2 3V3_STBY 100p 50V C597 220p 50V C620 1 1 2 2 100n 10V 1 C636 220n 10V 2 1 330R 2 1 C510 100n 10V 4k7 R253 2 4 E T_AGC 3 10n 16V 2u2 N.C. 1 R680 56R 1 L104 1u 1 22k R594 SIF_CTL 1 ANALOG_IF 2 2 R210 100k C545 L111 R125 47R 2 2 2 2 3 1 1 680R R735 1 1 1u 2 R483 1k2 L114 1 L101 1u 1 2 C135 100n 10V 1 2 1 R252 4k7 E 2 2 C520 47u 16V 1 1 C611 220u 6V3 C130 SIFM 10u 10V 100n WARNING!!! This part must be close to chip 10V C363 C131 10u 10V 1 2 2 1 D145 2 C132 1 1 2 2 5V_TUN SIFP 1 5V_TUN 10n 16V OPTIONAL COIL R38 220R R474 6k8 R1300 220R 1 IN1 OUT1 4 K9656M IN2 OUT2 5 2 GND BA782 2 3 1 C467 10u 10V Z101 C546 D C364 R231 3k3 1 1 R473 6k8 2 5V_TUN 2 5V_TUN WARNING!!! Saw filter outputs must be close the chip DIGITAL_IF+ 1n 50V D VIFP WARNING!!! This part must be close to chip F F V-1 e gecerken yapilan updateler VESTEL PROJECT NAME : 17mb37 Video SAW filitre cikislari caprazlandý SHEET:1 OF:18 SCH NAME :ANALOG IF DRAWN BY :SADIK 1 2 3 4 5 6 7 A3 SEHIT 14-10-2009_09:09 8 AX M 1 2 3 4 5 6 7 8 50V 220p TP360 C107 2 R219 100R 1 600R SPDIF_OUT_COAXIAL 1 SC1_AUD_L_OUT 2 1 F194 D184 2 C5V6 2 AUDIO LINE OUT 100n 10V 1 R1250 47R TP289 RED 4 3 TP300 TP299 2 WHT 2 1 TP302 F209 2 2 600R F215 1 IPOD_Y_IN 2 1n 50V 30 1 R1251 47R 75R R1327 YPBPR_AUD_L_IN S292 1n 50V 1 75R R1328 2 IPOD_C_IN 1 10k R1234 C1143 1 1 75R R1325 1 1 1 1 2 2 2 R506 10k R507 10k R511 10k 1 1 1 1 1 TP103 TP104 TP102 TP105 1 2 50V 27p 2 1 50V 2 1 27p 50V C437 2 1 C438 2 YPBPR INPUT 2 1 1 1 2 3 4 5 6 7 8 1 IN S1A S2A DA S1B S2B DB GND VCC EN S1D S2D DD S1C S2C DC 16 15 14 13 12 11 10 9 10k R1235 10k R1238 1u S276 6V3 2 5V_VCC 2 1 10k R1237 C1144 1 DVD_AUD_L_IN 1 2 5V_VCC 50V 1n 1 600R 27p 50V 2 DVD_SPDIF F211 1 1 C473 2 600R TP297 TP298 JK106 6 5 RED 2 10k R1239 S294 2 1u 6V3 SAV_AUD_L_IN TP296 1 10k R1229 5V_VCC 2 10k R1232 C1141 1 2 1 10k R1228 2 1 10k R1231 2 5V_VCC 1 1 4 10k R1230 2 S282 IPOD_L 2 SIDE AV INPUT 2 2 1u 6V3 S281 SAV_CVBS TP283 50V 1n SW_L_IN 1 2 E 1 600R 2 1 YLW SAV_AUD_R_IN C474 2 4 3 DVD_AUD_L_IN 50V 1n F212 1 2 1 1 R683 33k 50V F216 2 TP295 2 50V 1n C1119 R1288 22k D 1 2 100n 10V RCA_Y 2 10u 10V 27p 2 WHT 2 2 C440 1 2 1 10u 25V 1 C1138 27p 50V 2 C1113 R1286 22k 2 2 1 R639 75R 1 2 1 SW_C_IN 3 R1254 47R C365 2 2 TP4 50V 1n C1118 R1287 22k F DVD_AUD_R_IN 2 50V 1n 10k R1233 C1142 1 2 VESTEL PROJECT NAME : 2 1 2 1 1 3 CN143 C1044 SW_R_IN 1 2k2 R712 2k2 R711 2 1 1 2 DVD_AUD_R_IN 600R 1 S278 COAXIAL SPDIF OUTPUT YPBPR/PC LINE INPUT 1 1 C1140 27p 50V TP293 RCA_PB 75R R638 1 1 100n 10V 2 C1137 TP10 F292 2 TX/SDA 5V_VCC U194 PI5V330 DVD_C_IN 2 3 2 27p 50V TP284 C1050 2 600R 2 SW_Y_IN C480 1 75R R1326 1 4 2 5V_VCC S277 1 F 1 YPBPR_AUD_R_IN C479 1 IR_IN GRN 2 1 75R R637 1 DVD_Y_IN DVD_IR 1 C1139 2 1 27p 50V BLU 4 3 2 2 2 TP12 F291 TP2 S293 2 600R R1261 1k 2 600R 2 28 DVD_Y_IN 600R 1 1 6 F293 1 C1049 100n 10V 1 1 5 TP20 TP13 SPDIF_OUT_COAXIAL F208 1 10V IPOD_GPIO1 100n R1267 4k7 2 1 TP1F288 1 1 RED 3V3_VCC DVD_SENSE DVD_C_IN 27p C1136 50V 2 600R C1061 TP14 DVD_IPOD_SW 6 5 26 1 1 7 1 1 BLK 25 29 2 2 C115 S217 8 MAIN_L 600R 50V 220p JK104 24 TP6 F290 TP21 2 C1135 2 2 2 600R IPOD_L 1 RX/SCL TP301 23 27 2 E 22 R1285 22k F289 1 9 20 21 1 TP7 TP5 1 IPOD_GPIO2 TP19 IPOD_GPIO3 TP17 C1060 1 D183 1 C5V6 2 C1059 100n 10V TP3 10 18 19 TP24 D194 IPOD_C_IN 16 17 TP22 MAIN_R LINE_L_OUT 2 TP294 RCA_PR 220p 50V 2 1 6 5 1 600R 1n R216 50V 100R 15 4A/24VDC 1 11 14 12V_VCC R1240 10k 2 1 2 C15V TP9 2 C113 2 WHT 1 2 TP11 IPOD_R 1 12 C5V6 F205 1 12 13 C489 1 11 AMP_MUTE 1 2 TP8 LINE_R_OUT 10 2 C442 JK101 D185 IPOD_Y_IN 9 FS1 1 POP_MUTE TP16 50V 27p R682 33k 8 ! 1 7 C1090 220n 25V TP292 6 DVD CONNECTION C441 5 12V_IPOD NUP4004M5 2 4 D104 5 4 2 3 1 12V_IPOD 2 2 2 C 12V_IPOD 1 3 2 D187 1 C18V 12V_IPOD 2 4 RED 3 1 600R TP347 JK111 2 INPUT TP18 CN141 SC1_AUD_R_OUT 1 2 VGA 2 F204 100n 10V 75R R1329 R213 100R C475 TP15 1 S192 2 C1075 1 50V 1n TP334 VGA_R CN118 C1121 2 C488 R217 100R 1 SPDIF_OUT 2 TP382 600R IPOD INTERFACE TP348 VGA_G 2 1n 50V 600R VGA_B 2 1n 50V SC1_AUD_R_IN 1 1 1 R464 100R 1 2 600R F207 1 2 2 1 1 1 1 2 1 TP335 F195 SCART1 TP288 3 2 1n 50V 1 2 100n 10V C484 1 2 4 27p C478 C602 50V 220p TP362 Q117 BC848B 2 C229 F197 1 3 R400 1k SC1_AUD_L_IN 600R TP363 TP336 5 50V TP357 1 2 B 6 TP303 TP305 TP306 1 VGA_HSNC 3 F198 C477 R752 4k7 2 100n 10V 2 1 C108 SPDIF OUTPUT INTERFACE 1 2 1 2 600R 4 D 2 5V_SPDIF 2 R242 4k7 1 2 2 100R 7 1 F196 1 5 1 2 1 C5V6 10k R1236 2 50V 1n SC1_B VGA_VSNC R349 1 27p 2 C140 50V 220p 5 R4 4 VGA_DDC_5V TP304 2 NUP4004M5 4 D101 5 1 GND 4 1 3 1 R255 4k7 C15V 6 2 2 D116 SC1_PIN8 TP359 7 C 10u 10V RX/SCL_SC 1 2 2 TP358 8 2 75R R643 C116 1 9 R596 22k D140 12 1 50V 220p 10 A2 3 8 TP352 2 A1 2 ST24LC21 5 SDA 9 SC1_G 11 7 WP 6 SCL 10 A A0 1 U112 6 R3 3 C439 2 12 S-VIDEO IN D146 BAV70 2 TP354 8 VCC 7 R2 2 11 VGA CONNECTOR C104 13 5 VGA_DDC_5V 13 S_VIDEO_Y_IN C112 TP355 TP351 14 1 TX/SDA_SC 1 TP291 3 2 D114 50V 220p 1 75k R641 4 1 1 2 TP290 S_VIDEO_C_IN C5V6 2 JK102 TP282 TP356 SC1_R 50V 220p SC1_FB 1 1 D113 2 15 D117 2 C5V6 47R R128 C103 14 C5V6 1 2 1 C138 100n 10V R584 100R 8 1 R1 PROG_EN 1 2 2 75R R644 1 D111 1 15 C5V6 2 1 2 75R R640 5V_SPDIF C1007 100n 10V 3 2 1 2 1 1 16 SCART LT1 D115 2 SC1_CVBS_OUT TP346 17 2 330R 2 C366 220p 50V 50V 220p 18 SC101 2 C5V1 1 5V_VCC R120 10k C111 C5V6 2 C105 220p 50V 1 SC1_CVBS_IN TP361 20 F118 1 19 B D172 1 C5V6 C106 TP101 NUP4004M5 2 4 D102 5 D112 2 50V 220p A 1 3 21 NUP4004M5 2 4 D106 5 TP287 5V_VCC 1 C1120 R1284 22k 2 DRAWN BY :SADIK 6 7 A3 SHEET:2 OF:18 SCH NAME :A/V INTERFACE IPOD_R 1u 6V3 5 17mb37 SEHIT 14-10-2009_09:10 8 AX M 3 4 2 1 C656 100n 10V 10V 10u 2 2 SW_Y_IN 1 R142 47R C151 100n 10V 1 2 1 2 Y0 REFP AUVRP 77 1 21 REFM AUVAG 78 AVDD_AU_2 79 LINE_IN_0L 80 2 100n 10V BIN1P 22 BIN1P 1 C422 2 1 2 Y1 R654 75R 1 1 47R R146 R773 470R 2 1 2 1 2 1 1 1 DVB_CVBS 1 GND3 LINE_OUT_3L 90 100n 10V 34 HSYNC0 LINE_OUT_3R 91 SC1_FB 35 VSYNC0 LINE_OUT_2L 92 VSYNC2 LINE_OUT_2R 93 2 2 IN1- 2 R687 33k 1 CVBS3 36 2 37 BIN2P BIN2P DSP_CH4_R 94 LINE_OUT_1L 10V 10u DSP_CH1_L 2 LINE_R_OUT 38 SOGIN2 SOGIN2 95 LINE_OUT_1R DSP_CH1_R 2 1 1 C372 LINE_OUT_0L 96 RIN2P 40 RIN2P LINE_OUT_0R 97 C1 41 C1 Y1 42 Y1 43 C0 Y0 44 CVBS3 45 CVBS3 CVBS2 46 CVBS2 Y0 1 2 RIN0P 47 CVBS1 CVBS1 C425 48 SW_PB 1 R149 47R C428 2 1 2 R859 10k BIN2P 1 R148 47R 1 C426 2 1 2 1 R403 470R 1 2 CVBS0 50 VCOM0 51 AVDD_33_4 2 47n AVDD_33 52 C144 2 1 100n 10V C490 2 49 GIN2P 47n 16V 1 47n C416 47n 16V SW_Y VCOM1 2 SOGIN2 CVBSOUT1 53 CVBSOUT0 54 GND4 R155 47R R690 33k 8V_VCC 50V 220p R522 10k R751 3k3 1 2 BC848B Q121 2 SW_PR 1 R147 47R 1 E 2 CVBS0_OUT 1 R351 100R 1 1 2 1 OUT1 2 VDD 8 1 Pin79 R737 20k OUT2 7 3 IN1+ V+ 2 1 5V_VCC V+ Pin74 1 C646 100n 16V 33k R685 4 VSS IN2+ 5 2 8V_VCC 2 2 1 2 SC1_CVBS_OUT 1 2 DVB_Y C444 2 1 RCA_Y 27p AUDIO PREAMPLIFIERS Place close to Paulo 1 R662 75R 2 50V R830 47R 1 2 RIN1P 47n 16V 1 1 1 R224 100R R228 100R 2 R229 100R GAIN_SW1 2 1 2 1 100n 16V R520 10k C499 2 1 IN S1A S2A DA S1B S2B DB GND VCC EN S1D S2D DD S1C S2C DC 2 16 15 14 13 12 11 10 9 1 C147 10u C1006 2 DVB/YPBPR SWITCH 1 2 5V_VCC 27p 330R 1 10V 2 1 SW_PB DSP_CH1_L 1 R227 100R 1 22k R420 2 LINE_OUT_L 1 1 MAIN_L 1 1 E R418 22k 2 2 DSP_CH1_R 1 R226 100R 22k R415 2 2 DSP_CH3_L 1 R225 100R 1 2 LINE_OUT_R DSP_CH3_R 1 C551 AUDIO OUTPUT FILTERS MAIN_R R223 100R 22k R417 2 2 SC1_L 1 2 1 1 22k R416 R222 100R 1 2 2 22k R414 2 SC_1_R VESTEL PROJECT NAME : 17mb37 Q154 2N7002 1 2 C445 DVB_PB R663 75R RCA_PB 2 2 CVBS0_OUT DSP_CH4_R D F151 HP_R 10n 16V R753 4k7 2 1n 50V R598 22k HP_L 22k R419 10n 16V 2 1 1 Place close to Paulo C430 SAV_AUD_R_IN C498 2 C550 1 2 C SW_Y DSP_CH2_R DSP_CH4_L 2 SAV_AUD_L_IN 2 1n 50V R599 22k 2 2 1 1 2 3 4 5 6 7 8 SW_PR 1 F R660 75R 2 R620 300R 1 100n 16V R519 10k 10V 100n 2 10u 10V 1 R777 75R 2 VGA_R R661 75R 2 1 1n 50V 1 R646 75R R627 1k 50V C666 1u 16V 2 2 C496 2 LINE_IN_3R U129 PI5V330 1 1 SOGIN1 1 YPBPR_AUD_R_IN 2 1 100n 16V R518 10k 1n 50V 27p C378 Q119 BC848B 3k3 R750 2 2 1n 50V R600 22k C661 LINE_OUT_L 1 DVB/YPBPR_SW 1 3 C491 2 1 1 R404 470R 1 POP_MUTE 100n 16V 2 3 1 C663 R736 20k V+ 1 100R R221 R467 15k 2 Q146 BC858B GIN1P 47n 16V 2 1 2 2 1 2 2 IN2- 6 DVB_PR 1 VGA_G R521 10k 2 RCA_PR 330R BIN1P C431 R831 47R C118 R675 82k C443 2 1 47n 16V R658 75R 1 C554 C429 R829 47R 2 1 100n 16V 1 1 3 YPBPR_AUD_L_IN C497 LINE_IN_3L 2 SCART VIDEO OUTPUT AMPLIFIERS 2 1 LINE_L_OUT BC848B Q120 TL062 C662 1 2 2 C660 1 F119 VGA_B 2 2 2 RIN2P R402 470R 2 R659 75R 1 U117 LINE_OUT_R 100n 16V R517 10k 1 10V 10u 50V 220p 100n 16V 2 47n 16V 1 C371 DSP_CH2_L C427 2 1 C555 1 2 2 1n 50V R601 22k LINE_IN_2R 2 C119 R676 82k 1 LINE_IN_2L 2 R153 47R B C494 2 C643 C630600R 2 IN1- R674 39k 2 SC1_L 1 1 100n 16V R516 10k C642 2 100n 16V F219 1n 50V R655 75R C650 R738 20k 1 2 SW_R_IN 2 1n 50V R603 22k 2 V+ R689 33k 1 1 1 1 IN2+ 5 1 C0 1 POP_MUTE 1 C417 2 220p 50V R677 82k IN2- 6 3 DSP_CH3_R C367 GIN0P 1 1 DSP_CH3_L 2 GIN2P 33k R684 GIN2P 39 BIN0P 47n 16V R139 47R 3 IN1+ 2 C495 LINE_IN_1R C374 2 TL062 V+ SW_L_IN 1 2 1 2 2 C644 SC1_AUD_L_OUT DSP_CH4_L 1 1 OUT2 7 1 1 C418 2 VDD 8 DSP_CH2_R AVDD_AU R138 47R C120 1 OUT1 2 100n 16V R515 10k 2 2 U118 R739 20k 1 DSP_CH2_L 1 2 1 1 4 VSS 2 1 R692 33k 1 2 10u 10V 2 D R657 75R 1 220p 50V R678 82k 100n 16V LINE_IN_3R R686 33k C142 100n 10V R137 47R 2 1 CVBS2 47n 16V 2 88 LINE_IN_3R 33 1 1 SC1_R 2 RIN0P 1 SC_1_R 8V_VCC 10V R691 10u 33k C143 C421 1 1 R656 75R 1 LINE_IN_3L 2 1 SC1_G 2 LINE_IN_2L LINE_IN_2R 87 LINE_IN_3L 89 47n 16V R666 75R SOGIN0 AVDD_33_3 LINE_IN_MONO SOGIN0 47n 16V 1 2 86 100n 10V 1 SC1_B R667 75R LINE_IN_2R 1 C145 100n 10V R665 75R 2 GIN0P C121 C375 2 2 2 2 1 85 32 AVDD_33 47n 16V C435 2 LINE_IN_2L 1 600R 100n 16V 2 C R140 47R 2 GIN0M S106 1 1 2 330R R664 75R 1 30 31 50V C433 2 84 F217 1 1 2 R141 47R AUCOM 3V3_VCC R649 75R BIN0P 2 SC1_AUD_R_OUT LINE_IN_1R F120 2 83 C649 RIN0P 1n SAV_CVBS 29 SOGIN0 C612 2 2 47n 16V CVBS1 47n 16V LINE_IN_1R C631 2 28 1 GIN0P SC1_CVBS_IN BIN0M LINE_IN_1L C149 27 2 C424 2 2 47n 16V C419 R134 47R 47n 16V 1 1 BIN0P 1 B 2 1 LINE_IN_1L 10V 10u C549 S_VIDEO_Y_IN R144 47R LINE_IN_1L LINE_IN_0R C548 2 RIN1P 82 2 1n 50V R605 22k C553 R652 75R 26 81 C420 R133 47R C423 1 1 1 C552 RIN1P LINE_IN_0R GIN1P SC1_AUD_R_IN C492 D167 C1 25 1 2 24 2 47R R145 2 10n 16V 1 GIN1P 1 10n 16V S_VIDEO_C_IN 16V 47n 2 2 C645 1 2 100n 16V R514 10k LINE_IN_0L 2 R653 75R SOGIN1 A 2 1n 50V R606 22k 1 100n 16V AVDD_AU AVDD_AU DECOUPLING CAPACITORS 1 SOGIN1 23 1 LINE_IN_0R 1 47n 16V C493 2 C655 C368 C659 C150 100n 10V C434 20 2 1 1 1 C0 C432 2 SC1_AUD_L_IN 2 2 2 10V 10u C369 2 10n 16V 1 75R R651 R650 75R 76 2 100n 16V R513 10k 1 1 2 AUVRM C152 1 1 VCLAMP 1 2 1 SW_C_IN R143 47R GND5 19 2 C5V1 A VSYNC1 75 10n 16V VGA_VSNC 16V 47n 18 R607 22k 1 LINE_IN_0L 1 74 AUDIO INPUT VOLTAGE DIVISION AND DC BLOCK Place close to Paulo C148 2 AVDD_AU_1 8 10n 16V HSYNC1 7 10n 16V 17 VGA_HSNC 6 1 U138 MST6WB7GQ-3 VIDEO TERMINATIONS AND DIFFERENTIAL TRACING Place 75R termination resistors close to Paulo reference GNDs 5 2 2 AVDD_AU 1 22k R413 F 2 A3 SHEET:3 OF:18 SCH NAME :<DRAWING NAME HERE> 3 DRAWN BY :<YOUR NAME HERE> 1 2 3 4 5 6 7 14-10-2009_09:10 8 AX M 1 2 3 4 5 6 7 8 A A CN121 HDMI Receiver In_B 2 BAV70 D147 5V_VCC U138 MST6WB7GQ-3 HDMIB_5V 1 3 HDMIB_2+ 2 2 1 2 2 R392 10R HDMIB_C- 2 10R R393 1 1 2 2 WP 7 HDMI_WP1 2 3 A2 SCL 6 4 VSS SDA 5 HDMIB_SCL HDMIB_SDA HDMIB_SCL HDMIB_SDA HDMIB_5V HDMIB_HPD 1 R119 910R 2 2 RXACKP AVDD_USB 192 AVDD_USB 3 GND1 USB20_DM 193 USB_DM_A USB_DP_A HDMIA_0- 4 RXA0N USB20_DP 194 HDMIA_0+ 5 RXA0P GND11 195 6 AVDD_33_1 VDDP2 196 HDMIA_1- 7 RXA1N GND12 197 HDMIA_1+ 8 RXA1P VDDP3 216 AVDD_33 1 VDDP B VDDP 9 USB_VBUS 217 GND2 HDMIA_2- 10 RXA2N USB_DM 218 HDMIA_2+ 11 RXA2P USB_DP 219 12 HPLUGA 13 AVDD_33_2 14 REXT DI[0] 232 I2S_WS_DVB HDMIA_SDA 15 DDCDA_SDA DI[1] 233 I2S_CLK_DVB C154 HDMIA_SCL 16 DDCDA_SCL DI[2] 234 I2S_DATA_DVB HDMIA_HPD 1 1 R491 47k R492 47k 10R R396 U110 HDMIA_C+ 24LC02 CEC 1 2 A1 VCC 8 HDMIA_5V 1 R391 10R HDMIB_0HDMIB_C+ 1 A0 2 10R R390 HDMIB_1HDMIB_0+ USB20_REXT 191 RXACKN 1 R1263 1k 1 R389 10R 1 1 HDMIA_C- 4k7 R257 10R R394 1 C153 100n 10V 1 2 2 2 TP106 1 R388 10R 2 1 1 10R R387 1 TP134 HDMIB_2HDMIB_1+ 1 2 1 R386 10R TP132 TP133 1 2 B R385 10R 1 2 HDMI1 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 3 Q179 BC848B 2 2 1 1 R1264 1k R1281 4k7 1 AVDD_33 2 ICLK 231 2 1 R412 390R USB_CID 220 Pin196 Pin216 Pin236 3V3_HDMI VDDP C C155 100n 10V 2 1 2 1 C156 100n 10V 2 1 C157 100n 10V 1 282 VDDC5 DI[3] 235 283 RXBCKN VDDP5 236 284 RXBCKP DI[4] 237 285 AVDD_33_5 DI[5] 238 HDMIB_0- 286 RXB0N DI[6] 239 HDMIB_0+ 287 RXB0P DI[7] 240 288 GND DI[8] 241 HDMIB_1- 289 RXB1N DI[9] 242 HDMIB_1+ 290 RXB1P 100n 10V HDMIB_CPin6 Pin13 C158 100n 10V 2 1 2 1 Pin285 C159 100n 10V 2 1 AVDD_33 C160 100n 10V F124 3V3_VCC 1 2 AVDD_USB 330R 2 1 1 HDMIB_2- 292 RXB2N HDMIB_2+ 293 RXB2P 1 294 HPLUGB 2 HDMIA_2- HDMIB_HPD 3 Q123 BC848B 1 R630 1k 2 HDMIB_SDA 295 DDCDB_SDA HDMIB_SCL 296 DDCDB_SCL 1 BAV70 D193 2 2 HDMIA_1+ 2 HDMIA_1- 5V_VCC 2 1 HDMIA_5V 1 TP411 1 CEC R11 10R 2 A1 2 HDMIA_C- 2 HDMIA_SCL 2 HDMIA_SDA 2 HDMIA_HPD 4k7 R1282 1 WP 7 HDMI_WP2 E 24LC02 HDMIA_C+ 2 VCC 8 U193 1 1 A0 3 A2 SCL 6 HDMIA_SCL 4 VSS SDA 5 HDMIA_SDA TP410 TP409 1 HDMIA_0- C1069 100n 10V 3V3_HDMI 1 1 HDMIA_0+ 2 1 1 1 R9 10R R8 10R R17 10R R16 10R 1 2 1 1 R12 10R R14 10R TP412 2 1 2 2 1 R13 10R R18 10R HDMIA_2+ D HDMIA_5V 47k R494 2 F 1 2 1 1 F R493 47k R632 1k 2 HDMI2 E 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 VDDP R258 4k7 CN122 R10 10R R15 10R 3 1 C 291 GND18 R629 1k HDMI Receiver In_A C173 100n 10V 2 D VDDC HDMIB_C+ HDMIB_5V AVDD_33 2 VESTEL PROJECT NAME : 17mb37 SHEET:4 OF:18 SCH NAME :HDMI&USB DRAWN BY :SADIK 1 2 3 4 5 6 7 A3 SEHIT 14-10-2009_09:10 8 AX M 3 4 5 9 10 8 7 6 5 4 6 5V_STBY R277 4k7 2 3V3_STBY LED1 U138 MST6WB7GQ-3 1 R276 4k7 2 3V3_STBY 3V3_STBY 2 LED&VFD 1 3V3_STBY 2 600R F230 1 VFD_CLK_STBY VFD_DATA_STBY 2 S118 2 2 220R R43 R526 10k D148 2 2 C608 IR_IN 600R 1 R274 4k7 2 DVB_RESET C5V6 Q131 BC848B 2 1 STBY_ON/OFF_NOT 2 2 R608 22k GAIN_SW1 3V3_VCC R288 3V3_VCC 4k7 DVB/YPBPR_SW R268 3V3_VCC 4k7 DVB_IRQ Q125 BC848B 2 1 1 1 Q148 Q149 1 GPIOL[4] PWM0 208 60 XOUT PWM1 209 220R R381 VDDP OVER_CUR_DETECT For Internal CPU Selection BACKLIGHT_DIM For Internal CPU Selection 4k7 3V3_STBY R524 3V3_STBY R279 10k 4k7 3V3_STBY R287 SDA 4k7 3V3_STBY R286 SCL 4k7 3V3_STBY R289 TX/SDA 2 61 XIN DDCR_SDA 210 98 GPIOD[0] DDCR_SCL 211 GPIOD[1] DDCA_SDA 212 100 GPIOD[2] DDCA_SCL 213 101 GPIOD[3] INT 214 102 GPIOD[4] IRIN 215 103 GPIOD[5] GPIOB[0] 221 104 GPIOD[6] GPIOB[1] 222 105 GPIOD[7] PWM2 223 106 GPIOD[8] PWM3 224 107 GPIOD[9] GND14 225 108 VDDP1 VDDP4 226 2 1 2 1 2 1 RX/SCL 2 R1280 4k7 1 PIN272 2 1 1 MECH_SWITCH 1 2 1 C178 100n 10V PIN226 3V3_VCC R269 4k7 R270 4k7 2 2 3V3_STBY PIN110 AMP_MUTE 2 2 4k7 R1279 IPOD_GPIO1 1 3V3_STBY 1 VDDP 109 GND6 GPIOT[0] 227 110 VDDC1 GPIOT[1] 228 111 GPIOD[10] GPIOT[2] 229 1 112 GPIOD[11] GPIOT[3] 230 1 OPTION2 VDDC 1 1 PROTECT R161 47R R162 47R 2 HWRESET 243 2 5V_TOLERANT 114 GPIOD[13] VDDP7 272 115 GPIOD[14] GND17 273 HDMI_WP2 116 GPIOD[15] GPIOE[3] 274 HDMI_WP1 117 GPIOD[16] GPIOE[2] 275 118 GPIOD[17] GPIOE[1] 276 3V3_STBY C174 100n 10V VFD_CLK_STBY DVB_RXD 2 2 DVD_IR_ON/OFF KEYBOARD_STBY 600R F280 2 4 3 2 C1037 1 CN114 3V3_VCC 1 2 10V 100n C182 1 VDDP 1 R1248 47R HP_DETECT 2 2 5V_TOLERANT VFD_DATA_STBY R840 4k7 R858 4k7 TK_SUPPLY 1 4u7 TP383 HDMIB_5V R283 4k7 R264 4k7 2 3V3_STBY PROTECT_PANEL 100n C 3V3_VCC 2 5V_TOLERANT 2 R857 1k 149 GPIOR[0] GPIOE[0] 277 150 GPIOR[1] GPIOM[0] 278 151 GPIOR[2] GPIOM[1] 279 152 GPIOR[3] GPIOM[2] 280 153 GPIOR[4] GPIOM[3] 281 1 R261 4k7 R262 4k7 1 3V3_STBY 1 3V3_STBY 1 2 MAX810 GND RST MAX809LTR VCC U130 C1129 3 22u 25V SDA_NVM SCL_NVM 1 R964 47R 2 USB_ENA_A 3V3_STBY 2 R1036 4k7 1 2 C183 1 5V_VCC D Reset IC supplyi 3V3 stbyden 1 ANT_CTRL 10V 100n R1265 1k 1 2 VFD_CLK_STBY VFD_DATA_STBY R395 1k 1 HDMIA_5V 1 R1268 4k7 2 DVB_TXD R356 100R 2 3V3_STBY C1036 1 1 1 1 2 2 N.C. R292 4k7 1 F188 R167 47R 1 3V3_VCC 1 3V3_VCC 2 220p 50V 1 1 TP159 113 GPIOD[12] 4k7 R271 2 R291 4k7 2 2 S299 4k7 R278 2 2 600R DVD_IR 2 R1283 22k 1 C176 100n 10V 2 D152 2 C5V6 F231 R1330 47k B SW_UPDATE_SELECT D174 3V3_STBY R724 100k 1 C177 100n 10V 1 D150 1 C5V6 1 D C5V6 3V3_STBY 1 2 2 MECH_ONBOARD C598 3 4k7 R294 1 NVM_WP 1 3V3_STBY 1 IR_IN KEYBOARD_ONBOARD IR_IN 4k7 R290 2 C175 100n 10V IDTV_SW C R1269 4k7 1 1 1 VDDC PIN108 2 A 1 1N4148 KEYBOARD & TOUCHPAD 2 BC848B Q178 R742 20k 2 VDDP 1 S125 59 2 DVD_SENSE D155 1 SAR3 207 1 1 220R R382 2 LED1 BC858B 1 2 LED2 1 R757 4k7 1 2 2 2 S117 GPIOL[3] 1 2 3 R422 10k 2 1 58 2 STBY_ON/OFF 2 BC858B 5V_STBY GPIOL[2] SAR2 206 2 1 3 2 3V3_STBY SC1_PIN8 57 99 2 1 3 1 KEYBOARD_STBY 2 PROG_EN 1 3V3_STBY 1 SAR1 205 1 2 3V3_VCC 3 10k R531 2 10k R528 Q130 BC848B 2 2 4k7 R293 GPIOL[1] 2 3V3_STBY 1 B 1 R267 4k7 27p 50V 27p 50V 3 1 2 2 2 5V_STBY 1 R421 10k 1 3V3_STBY F225 1 STBY_ON/OFF_NOT S193 R748 3V3_STBY 47R 3V3_STBY 2 1 2 1 SIF_CTL 4k7 R265 5 4 3 2 1 CN119 600R S119 2 3 2 C446 1 1 27p 50V VFD_CSB F229 C5V6 56 8 SAR0 204 1 1 2 2 X104 1 600R R527 10k D149 2 1 F228 C5V6 GPIOL[0] C447 1 2 R552 10k 2 14.31818MHZ R110 1M 1 1 D130 2 55 1 LED2 A 7 N.C. 1 3 1 2 2 CN106 1 VFD_CSB 5V_TOLERANT 154 GPIOR[5] DVD_IPOD_SW 155 GPIOR[6] 6 5 4 3 2 1 CN130 DVD_IR_ON/OFF 3V3_VCC 2 IPOD_GPIO3 CN142 1 3 2 4 TK_SUPPLY PUSH V+ AND VVOL+ TV/AV VOL- R1292 5k1 R1305 3k9 2 1 R233 4k7 2 2 1 1 2 S123 1 2 1 R352 100R R353 100R 5V_STBY TP110 TP109 TP108 TP112 2 2 S194 2 1 R232 4k7 HC4052 DISABLE HC4052 ENABLE SW_UPDATE_SELECT 0 DVB_SW_UPDATE 1 ANALOG_SW_UPDATE 2 Q126 BC848B 2 1 1 1 C529 1 2 220p 50V MEGA_DCR 3 1 R234 4k7 C531 1 2 R354 100R R355 100R Q127 BC848B 2 1 2 TP350 TP353 TP307 DIMMING 2 PROG_EN SW_UPDATE_SELECT RESET_7101 F 2 2 1 1 SW_UPDATE_SELECT 1 3 3 BACKLIGHT_DIM 4k7 R284 VESTEL PROJECT NAME : 17mb37-1 DRAWN BY :SADIK SEHIT 2 3 4 5 6 7 A3 SHEET:5 OF:18 SCH NAME :CONTROLLER 220p 50V 1 E Q147 BC858B 2 C530 1 5V_STBY 1 TP111 1 220p 50V PROG_EN 0 1 NVM_WP SCL_NVM SDA_NVM 1 2 TX/SDA TX/SDA_SC UART_TXD 8 7 6 5 1 100n 10V 16 15 14 13 12 11 10 9 VCC WC SCL SDA 10u 10V 3 1 RX/SCL VCC 1Y2 1Y1 1Z 1Y0 1Y3 S0 S1 1 2 2 2 2 F 2Y0 2Y2 2Z 2Y3 2Y1 E VEE GND E0 E1 E2 VSS 5V_VCC R745 1k S195 1 S196 RX/SCL_SC 1 1 2 3 4 5 6 7 8 2 1 1 1 2 R281 4k7 2 4k7 R280 1 R282 4k7 BC848B Q128 2 UART_RXD S121 1 2 3 4 3V3_VCC 3V3_STBY 1 2 PDP_IRQ 1 1 2 1 C180 U127 M74HC4052 S18 R1345 4k7 C1163 100n 10V 1 2 R1333 2k7 1 2 1 R1289 1k2 2 R1331 470R R1332 270R 1 DEBUG SOCKET 1 2 2 4 1 2 100n 10V 1 3 2 U103 24C32 2 1 1 SW2 4 3 SW3 3 4 2 1 SW6 3 4 2 1 SW1 4 3 2 1 SW4 4 SW5 2 1 2 C181 159 GPIOR[10] STBY 3 P- 158 GPIOR[9] USB_OCD 4 P+ 1 3 PROG_EN 1 R164 47R R163 47R 5V_STBY TX/SDA 1 1 KEYBOARD_ONBOARD 2 RX/SCL 4k7 R1277 AT THE SAME TIME FOR MENU CN145 2 157 GPIOR[8] 2 5V_STBY E S120 AMP_SHDN 156 GPIOR[7] C383 N.C. 1 2 2 1 KEYBOARD_ONBOARD IPOD_GPIO2 3V3_STBY R31 47R 1 2 3V3_STBY MECH_ONBOARD R1266 4k7 R1278 4k7 1 14-10-2009_16:25 8 AX M 1 2 3 4 5 6 7 8 121 AD[2] AVDD_MI_3 162 122 AD[3] MDATA[0] 163 MDATA[0] 1 2 1 C201 100n 10V 2 1 C202 100n 10V C200 100n 10V 2 1 2 1 C199 100n 10V 2 1 C198 100n 10V 2 1 C197 100n 10V 2 1 C196 100n 10V 123 WRZ MDATA[1] 164 MDATA[1] 124 RDZ GND9 165 125 ALE MDATA[2] 166 MDATA[2] BADR1 126 BADR[1] MDATA[3] 167 MDATA[3] BADR0 127 BADR[0] AVDD_MI_4 168 DVD_SPDIF 2 3V3_VCC 8 7 6 5 1 R296 4k7 2 S220 BKL_ON/OFF PIN131 PIN147 PIN162 PIN168 PIN173 PIN179 PIN184 PANEL_VCC_ON/OFF SCK 1 SDI VDDC 1 3V3_VCC 1 TP160 2 SERIAL FLASH 1 C194 100n 10V PIN129 2 1 C195 100n 10V 1 R295 4k7 2 S216 PIN203 R795 10k BACKLIGHT_ON/OFF R357 100R 2 BKL_ON/OFF 128 RASZ MDATA[4] 169 MDATA[4] 3V3_VCC VDDC 129 VDDC2 MDATA[5] 170 MDATA[5] 130 GND7 MDATA[6] 171 MDATA[6] 131 AVDD_MI_1 MDATA[7] 172 MDATA[7] C1145 BKL_ON/OFF VDDM 132 CASZ CASZ 2 VDD_DMQ MDATA[0] MDATA[1] MDATA[2] MDATA[3] C R4 5 R3 6 R2 7 R1 8 100R R1310 3 4 4 3 2 1 5 6 7 VDD_DMQ MDATA[4] MDATA[5] MDATA[6] MDATA[7] 4 R4 5 3 R3 6 2 R2 7 1 R1 8 100R R1312 VDD1 DQ0 VDDQ1 DQ1 DQ2 VSSQ1 DQ3 8 DQ4 9 VDDQ2 10 11 12 DQ5 DQ6 MDATA[8] 134 WADR[11] MDATA[9] 175 MDATA[9] MADR[10] 135 WADR[10] GND10 176 MADR[9] 136 WADR[9] MDATA[10] 177 MDATA[10] 54 MADR[8] 137 WADR[8] MDATA[11] 178 MDATA[11] DQ15 53 MADR[7] 138 WADR[7] AVDD_MI_6 179 VDDM VSSQ4 52 MADR[6] 139 WADR[6] MDATA[12] 180 MDATA[12] MADR[5] 140 WADR[5] MDATA[13] 181 MDATA[13] MADR[4] 141 WADR[4] MDATA[14] 182 MDATA[14] MADR[3] 142 WADR[3] MDATA[15] 183 MDATA[15] MADR[2] 143 WADR[2] AVDD_MI_7 184 VDDM VSSQ2 VSS3 DQ14 51 DQ13 50 VDDQ4 49 4 R4 5 3 R3 6 2 R2 7 1 R1 8 100R R1309 VDD_DMQ MDATA[15] MDATA[14] MDATA[13] MDATA[12] DQ12 48 DQ11 47 MADR[1] 144 WADR[1] DQS1 185 VSSQ3 46 MADR[0] 145 WADR[0] DQM1 186 DQ10 45 DQ9 44 4 R4 5 3 R3 6 2 R2 7 1 R1 8 100R R1311 146 GND8 MDATA[11] MDATA[10] MDATA[9] MDATA[8] 147 AVDD_MI_2 VDDM F157 3V3_VCC 1 2 D DQ8 SPI_SCK 198 330R VDD2 VSS2 41 WEZ 1 CASZ 1 RASZ 1 BADR[0] 1 BADR[1] 1 E MADR[0] MADR[1] MADR[2] MADR[3] R1324 100R R1338 22R R1337 22R R1336 22R 2 15 DQML NC2 40 2 16 WE# DQMH 39 R1335 22R R1334 22R 2 17 2 18 CAS# RAS# CLK 38 CKE 37 19 CS# NC1 36 2 20 BA0 A11 35 2 21 BA1 A9 34 22 A10 A8 33 23 A0 A7 32 R1315 100R R1 8 R2 7 R3 6 R4 5 1 2 3 4 1 24 A1 A6 31 25 A2 A5 30 26 A3 A4 29 27 VDD3 VSS1 28 1 R1323 100R 2 UDM Place MCLKE Clock resistor close to MSTAR Pin MCLK 1 R1322 100R 2 MVREF 190 2 MCLK MCLKE R1316 100R 1 R1 SCK SPI_SDI 199 7 R2 2 SDI SPI_SCZ 200 6 R3 3 SCZ SPI_SDO 201 5 R4 4 SDO 8 GND13 202 MCLKE 2 VDDC3 203 R1314 100R R1 8 R2 7 R3 6 R4 5 1 2 3 4 R1313 100R 1 R1 8 2 R2 7 3 R3 6 4 R4 5 PIN1 F287 1 VDDM F 2 1 C193 100n 10V WARNING!!!DON'T USE VIA FOR MCLK AND 1 VDDC C1112 1n 50V PIN27 VDD_DMC 60R 1 C1077 220u 6V3 2 1 C1066 100n 10V PIN3 2 1 C1067 100n 10V PIN9 C1068 100n 10V 2 1 PIN43 PIN49 2 VDD_DMQ 60R 1 2 1 PIN14 2 F286 VDDM C1045 100n 10V 2 C1076 220u 6V3 2 1 C1065 100n 10V 2 1 C1063 100n 10V 2 1 C1062 100n 10V 2 1 C1064 100n 10V F DATA SIGNALS VESTEL PROJECT NAME : 17mb37 DRAWN BY :ÖNDER GENÇ 3 4 5 6 7 A3 SHEET:6 OF:18 SCH NAME :MEMORY INTERFACE 2 1 C501 1n 50V E MADR[7] MADR[6] MADR[5] MADR[4] 2 1 D 2 MADR[11] MADR[10] MADR[9] MADR[8] 1 VDD_DMC R499 100R 1 MCLKE 189 42 VDD_DMQ VDDM UDM 1 1 MCLK 188 43 14 VDD_DMC LDM DQ7 148 AVDD_MIPLL C213 100n 10V C MCLKZ 187 VDDQ3 2 13 VDDM MADR[11] U195 MT48LC4M16A2TG8E VDD_DMC AVDD_MI_5 173 MDATA[8] 174 8MB SDRAM 1 B 133 WEZ WEZ MEMORY VDDM RASZ R794 10k Q157 BC848B B A VDDM 2 1 C469 10u 10V R535 10k 2 2 1 1 VDDM 330R 3V3_STBY 2 R761 4k7 1 VCC HOLD# SCLK SI R365 100R 2 3V3_STBY 3V3_VCC 2 330R C605 10u 10V 2 1u 6V3 SDO CS# SO WP# GND 2 C184 100n 10V 1 R536 10k C5V1 1 1 1 F150 1 TP115 TP114 TP113 1 1 1 1 2 3 4 LDM DQS0 161 SPDIF_OUT D169 1 U132 MX25L512 DQM0 160 5 120 AD[1] F125 A SCZ 119 AD[0] DVB_SPDIF TP116 TP119 TP118 TP117 U138 MST6WB7GQ-3 14-10-2009_09:10 8 AX M 220n 10V 2 2 1 C538 2n2 50V 2 D124 10k R1241 1 1 A 1 2 D127 1N4148 2 HP_DETECT 1 S296 2 1 C625 2n2 50V 1 2 C453 1 1 Q150 BC858B 2 2 BC848B Q133 2 1 R541 10k 2 3 BC848B C668 Q132 100n 50V 2 2 R542 10k 1 1 R722 10k 2 1 3k9 R236 AMP_MUTE 2 3 2 HP_L 2 S126 1 R729 100k 4k7 R424 C633 1 3 8V_VCC 2 100u 16V 3V3_VCC AMP_EN 600R 1 220p 50V 2 2 1 R801 22R 2 1 R212 100k INBP 5 2 F191 4 VSS 1 1 5V_VCC B 1 1 INBN 6 50V 1n C502 2 S127 1 1u 16V R211 100k B 1 2 1 220p 50V C122 2 TDA1308T JK110 D125 C540 OUTB 7 3 INAP C665 D126 C386 10u 10V 1 1 U128 2 INAN 2 220n 10V 2 VDD 8 1 R238 20k R423 4k7 1 HP_R C537 2n2 50V 1 OUTA 1 C632 R237 20k 100u 16V 8V_VCC 1 2 2 1n 50V 2 MUTE_HP_L 2 2 1 1 C123 2 1 S128 1 16V 100u 1 2 3 2 1 1N4148 C541 6 5 4 2 1N4148 C503 9 8 7 R123 15k R1223 15k 1 C624 2n2 50V 5k1 R1291 3k3 R1290 2 1 1N4148 MUTE_HP_R R800 22R 12V_VCC VDD_AUDIO A 8 POP NOISE CIRCUIT 5V_VDD_AUDIO HEADPHONE AMPLIFIER 7 2 6 2 5 R546 10k 4 2 3 1 2 HP_DETECT 1 MUTE_HP_R 3 OUTP SDB 2 2 R544 10k C385 1 1 5V_VCC 2 10u 10V 1 C3 C2 INN GNDB C1 VDD1 B3 VDDA B2 OUTN BC848B Q134 PT2333 B1 A3 GNDA SDB INP A2 A1 60R F4 C3 C2 C1 OUTP U191 INN GNDB VDD1 VDDA B2 OUTN PT2333 B1 A3 A2 A1 INP GNDA U192 B3 2.5 WATT OPTION MUTE_HP_L C1133 1u 16V POP_MUTE C D1 S22 VDD_AUDIO SK24 S20 12V_VCC C12 330u 35V 1N4148 1 1 2 C1043 10u 10V 2 R545 10k D2 C1042 10u 10V 2 1 24V_VCC 5V_VDD_AUDIO 2 R44 47k 60R F6 R_OUT_N C1116 1n 50V C3 2u2 10V 150k R40 1 60R 15K 5V_VDD_AUDIO 2 1 2u2 10V C6 47u F5 BC848B Q135 150k R42 R_AUDIO_N R_AUDIO_P 47u R_OUT_P C5 10V 2u2 2 C1057 100n 10V 150k R1317 AMP_EN 3 L1 150k R41 C1132 1u 16V L_OUT_N 150k R39 50V C1117 1n C4 2u2 10V F7 60R C1115 50V 1n 1 L_OUT_P 47u R1319 150k C1056 100n 10V 2 L_AUDIO_N AMP_EN L2 C 47u 15K L4 MAIN_R_AUDIO L_AUDIO_P C1114 50V 1n L3 MAIN_L_AUDIO S23 1 18V_VCC 5V_VDD_AUDIO 5V_VCC F3 1 S17 VDD_AUDIO C13 S279 2 1 2 3 4 5 CN115 L_OUT_P C19 100n C10 1u 16V 5V_VDD_AUDIO C11 1u 16V OUTL-2 OUTL-1 BOOT MUTE 10 SHDN 11 REGEN PVDD2 30 12 COM PGND2 29 13 AGND1 PGND1 28 14 AGND2 PVDD1 27 15 REG OUTR+2 26 MAX9736B U1 10V OUTL+2 32 OUTL+1 31 2 R_AUDIO_N C18 100n 10V L_AUDIO_P VDD_AUDIO 3 2 1 L_AUDIO_N C16 100n 50V S14 9 100n 50V E 1 2 1 C15 AMP_EN 10k R25 10k MONO R27 5V_VCC FBL 5V_VDD_AUDIO 15K R24 10k INL MAIN_L_AUDIO NC1 R_AUDIO_P NC2 16V 1u C1131 6 8 R1320 150k 7 L_OUT_N AMP_SHDN E 4 OPTIONAL CN3 OUTR-2 R_OUT_P OUTR+1 R_AUDIO_P 2 R_AUDIO_N 3 L_AUDIO_P 4 L_AUDIO_N 5 25 24 OUTR-1 23 22 C1P C1N 21 20 MOD FBR VS 19 16 18 C9 1u 16V 17 5V_VDD_AUDIO INR 1 S15 NC3 R20 100R 1 D S16 BC848B Q2 S12 5V_Audio 5V_VDD_AUDIO 10V 220u C1134 1u 25V R28 10k 3 1 2 60R MAIN_L_AUDIO 2 MAIN_L 2 AUDIO INPUTS R30 20k D 1 S298 3 BC848B Q1 6 R1318 150k 15K R_OUT_N 100n 50V F MAIN_R_AUDIO MAIN_R_AUDIO S13 16V 1u C1130 S11 R19 100R F R29 20k 1 C14 R26 10k 2 MAIN_R VESTEL PROJECT NAME : 17mb37 5V_VDD_AUDIO SHEET:7 OF:18 SCH NAME :AUDIO DRAWN BY :SADIK SEHIT 1 2 3 4 5 6 7 A3 15-10-2009_16:06 8 AX M 2 4 5 6 R1209 1k DIGITAL_IF1V0_FE C1157 220u 6V3 C356 C849 100n DIGITAL_IF+ C225 100n 10V 2 IF_M IF_P 1 R331 10k 1V_QAM 2 3V3_QAM 33 GPIO2 GPIO3/SCLT 34 35 GPIO1/AGC1 36 GPIO0/AGC2 37 VDD3 38 GND3 39 VDD_IO_3V3_3 40 GNDAS_AD 41 INM INP 42 43 VCCAISO_D 44 INCM 45 REFM 47 46 REFP C_D6 TS_DATA[5] 29 3 R3 6 C_D5 TS_DATA[4] 28 4 R4 5 C_D4 VDD_IO_3V3_2 27 GND2 26 VDD2 25 TS_DATA[3] 24 1 TS_DATA[2] 23 2 R2 7 C_D2 3 R3 6 C_D1 4 R4 5 R1342 1 8 R1 3V3_QAM 3 R3 6 C_STRT M_CKOUT 17 4 R4 5 SDA C_D0 C_ERR 2 16 15 14 13 GND1 12 1 11 CLK_TST 10 64 SCL 18 VDD_IO_3V3_4 GPIO5/CS1 C_VAL M_SYNC GND4 63 GPIO6/CS0 2 R2 7 VDD_IO_3V3_1 M_VALID 19 62 VDD1 20 N_RESET M_ERR GPIO7/AUX_CLK VDD4 1 C_CLK C188 15p 50V 2 1 100R R312 1 2 R311 100R S234 S235 2 IDTV_SW 2 4k7 R469 1 FE1_SDA FE1_SCL 2 R463 4k7 1 3V3_QAM 1 3V3_QAM 1 3V3_QAM R803 4k7 1 1 RESET_DVB 33p 50V 2 2 2 3V3_QAM C1041 100n 10V IDTV_SW C_RESET 1 2 R1018 4k7 R1098 33R R239 4k7 R171 33R 2 SCL_TUN_DVB Q171 BC847B 100n 16V C906 C907 IF_AGC_T 1 R1167 180R 1V_QAM 2 R909 10k IF_AGC_T Q170 BC847B 3V3D_FE 1 C700 100n 10V 2 1 IF_AGC_C F255 C699 100n 10V 1V0_FE 3 B0 A 4 F128 6V3 100u IP_1 2 330R C1161 22u 6V3 F256 3V3_QAM 2 1 C223 100n 10V 2 1 C207 100n 10V 2 1 1V0_FE C206 100n 10V 1V0D_FE1 220R 2 1 D165 C750 100n 10V 2 1 C749 100n 10V 2 1 C748 100n 10V IF_AGC_DVB 2V5A_FE TP161 BA159 F 1 C1159 6V3 220u 3V3_VCC 2 330R C1160 22u 6V3 F127 1 2 1 2 IF_AGC_DVB F S239 1V_QAM 2V5_QAM 330R C721 100n 10V S240 1 F237 IF_AGC_C IF_AGC_T BA159 D164 2 1 C283 10u 10V 2 1 C221 100n 10V 2 1 C725 100n 10V 2 1 C217 100n 10V 2 1 C216 100n 10V 2 1 C215 100n 10V 2 1 C214 100n 10V 2 1 C220 100n 10V VESTEL PROJECT NAME :17mb37 DRAWN BY :ERTUG BAL 2 3 4 5 6 7 A3 SHEET:8 OF:18 SCH NAME :DVB COFDM & QAM place this cap close to pin#56 1 5V_VCC R1037 4k7 1 3V3_VCC C1151 1 2 S256 VCC 5 FSA3157 10n 16V C758 100n 16V S 6 2 GND IF_AGC_T C927 1 B1 U182 1V0A_FE1 220R 100n 10V 2 100n 10V 1 C723 100n 10V C1033 2 E R1038 4k7 2 330R C1162 22u 6V3 INCM_1 2 10n 16V F238 1 3V3_VCC C743 R1063 1k R1062 1k C756 1 2V5A_FE IM_1 1 C912 2 C757 DIGITAL_IF+ C C_D3 AGC_S1 16V 10n DIGITAL_IF- 1V_QAM R426 8 R1 61 9 3V3_QAM 100n 16V 2 R2 7 1u 6V3 10u 16V E 30 21 IF_AGC_C C1027 REFM_1 C_D7 TS_DATA[6] TS_DATA[0] 2 1V_QAM 1V_QAM 27MHz 33p 50V 10u 10V C695 100n 16V C1022 C1031 R427 33R 8 R1 TS_DATA[1] X108 1V0A_FE1 C1028 100n 16V REFP_1 1 VDD10REG R314 100R R313 100R 3V3D_FE C1023 1u 6V3 31 VBASE 1 R908 10k 100n 16V 2V5A_FE 100p 50V C1032 TS_DATA[7] D 2V5A_FE 2V5A_FE IP_1 INCM_1 IM_1 REFM_1 REFP_1 1n 50V C946 100n 16V R1153 30k C911 C799 32 60 8 2 100n 16V 4p7 50V B 22 C936 D GNDA_AD12 48 2 VCCA_AD12 10u 16V C930 100n C830 1 2 RF_AGC_DVB C908 100n 16V C910 R117 150R C227 100n 10V R1168 180R C909 VDDA_2V5_4 3V3D_FE R910 10k 16 XTAL_I 15 14 XTAL_O VDDA_2V5_3 13 VDDA_1V 12 IP 11 10 IM INCM 9 REFM 8 7 REFP VDDA_2V5_2 6 VDDA_ISO QM 5 4 QP VDDA_2V5_1 3 1 TEST 2 RF_LEVEL 100n 16V 64 1V0D_FE1 R911 10k 1 GNDA_OSC 3V3_QAM 1 59 TMS AGC_IF 17 SCL_TUN_DVB 1 58 7 18 4k7 R298 1 TCK AGC_RF 2 TRST VDD_3V3_7 2 6 63 19 C228 100n 10V 33p 50V 3 5 3V3D_FE SCLT VDD_1V_1 BC817-25 Q103 SDA_TUN_DVB A 2 TDO VDD_1V_8 1 57 2 GPIO4/SDAT U109 STV0297E 2 62 VCCA_OSC 1 GPIO9 1V0D_FE1 20 56 2V5_QAM C305 2V5_QAM SDA_TUN_DVB 61 ZO 27MHZ TDI 21 VCCD_PLL 55 2 4 SDAT R332 10k 2 DVB-C DEMODULATOR 3 GPIO2 R1043 4k7 54 GPIO8 VDD_3V3_1 C304 2 GPIO3 22 GNDA_PLL GNDD_PLL 33p 50V 3V3D_FE R1042 4k7 R1083 100R R1084 100R 51 VCCA_PLL 1 1V0D_FE1 VCCD_AD12 53 2V5_QAM 1 23 50 1k X101 AUX_CLK GNDD_AD12 52 F264 2V5_QAM 49 GPIO9 60 24 1V_QAM 100n 59 CS0 VDD_1V_2 FE1_SDA 3V3D_FE C905 GPIO4 U152 STV0362 25 FE1_SCL 1 26 1V0D_FE1 R1077 100R R1078 100R R407 1k CS1 58 IF_AGC_C 4p7 50V 2V5_QAM 33p 50V GPIO0 27 C935 100n 33p 50V 28 BA159 C937 VDD_3V3_2 DVB-T DEMODULATOR RESET_DVB C941 GPIO7 2 C224 100n 3V3_VCC 100n 16V 53 10V 1 2V5_QAM C657 10u 16V 100n 100n 16V 29 GPIO5 IF_P RESET_T C1019 D0 SDA VDD_3V3_6 2 IF_CM 33 34 VDD_3V3_3 D1 35 36 D2 D3 GPIO8 C929 3V3D_FE 1V0D_FE1 37 38 VDD_1V_4 39 D4 40 VDD_3V3_4 D5 41 42 D6 43 44 52 57 100n 16V 45 30 3V3D_FE C1026 46 SCL 56 A IF_CM 1 S266 C1025 100n 16V C1024 VDD_1V_6 VDD_1V_7 1 10n 16V BCP56-16 Q175 S267 31 GPIO6 R1061 1k R1060 1k C658 R1141 47k VDD_1V_3 55 IF_M 1 C384 Q176 BC846B NOT_RESET 1V0D_FE1 2 1 4 R4 5 3 R3 6 2 R2 7 R1117 33R 8 R1 1 4 R4 5 3 R3 6 2 R2 7 3V3D_FE 16V 10n 100n 16V C945 3V3_VCC C904 R928 10k R 4 10u 16V 3V3_VCC 32 54 C1021 D7 51 CLK_OUT 1V0D_FE1 VDD_1V_5 VDD_3V3_5 STR_OUT 50 D/NOT_P 3V3D_FE C 47 48 ERROR 100n 16V C1020 GPIO1 B 8 A 5 D166 49 7 C928 TS_DATA0_1 TS_DATA1_1 TS_DATA2_1 TS_DATA3_1 TS_DATA4_1 TS_DATA5_1 TS_DATA6_1 R1116 3p9 33R 8 R1 TS_DATA7_1 1 2 3 C R1059 220R 1n 50V 1 4 R4 5 3 R3 6 2 R2 7 1 R1341 33R 8 R1 C916 A 1V0D_FE1 3 U174 TS431AIL TSBYTECLK_1 TSPKTCLK_1 TSVALID_1 TSPKTERR_1 1 14-10-2009_09:10 8 AX M 3 LMI SYSTEM DDR A VDD_S_LMI_2V6 1 VDD1 VSS3 66 S_LMIDATA[0] 2 DQ0 DQ15 65 VDD_S_LMI_2V6 3 VDDQ1 VSSQ5 64 S_LMIDATA[1] 4 DQ1 DQ14 63 S_LMIDATA[2] 5 DQ2 DQ13 62 6 VSSQ1 VDDQ5 61 S_LMIDATA[3] 7 DQ3 DQ12 60 S_LMIDATA[4] 8 DQ4 VDD_S_LMI_2V6 9 VDDQ2 S_LMIDATA[5] 10 S_LMIDATA[6] 11 DQ6 12 VSSQ2 S_LMIDATA[7] B VDD_S_LMI_2V6 DQ10 57 DQ9 56 VDDQ4 55 DQ7 DQ8 54 14 NC1 NC7 53 15 VDDQ3 VSSQ3 52 U156 LDQS UDQS HY5DU561622D 51 NC2 NC6 50 18 VDD2 VREF 49 19 NC3 VSS2 48 S_LDQM[0] 20 LDM UDM 47 S_LWE 21 WE# CLK# 46 S_LCAS 22 CAS# CLK 45 S_LRAS 23 RAS# CKE 44 S_LCS 24 CS# NC5 43 25 NC4 A12 42 C S_LBANK[0] 26 BA0 A11 41 S_LBANK[1] 27 BA1 A9 40 S_LMI_AD[10] 28 A10/AP A8 39 S_LMI_AD[0] 29 A0 A7 38 S_LMI_AD[1] 30 A1 A6 37 S_LMI_AD[2] 31 A2 A5 36 S_LMI_AD[3] 32 A3 A4 35 VDD_S_LMI_2V6 33 VSS1 34 VDD3 33R R4 5 R3 6 R2 7 R1 8 R442 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R441 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R439 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R438 R315 100R R193 33R R186 33R R188 33R S_LMI_DATA0 S_LMI_DATA1 S_LMI_DATA2 S_LMI_DATA3 4 3 2 1 S_LMI_DATA4 S_LMI_DATA5 S_LMI_DATA6 S_LMI_DATA7 E 58 17 VDD_S_LMI_2V6 D VSSQ4 13 16 S_LDQS[0] DQ5 DQ11 59 S_LMI_DATA8 S_LMI_DATA9 S_LMI_DATA10 S_LMI_DATA11 S_LMI_DATA12 S_LMI_DATA13 S_LMI_DATA14 S_LMI_DATA15 1 S_NOTLCLK 2 VDD1 VSS3 66 S_LMIDATA[8] 2 DQ0 DQ15 65 VDD_S_LMI_2V6 3 VDDQ1 VSSQ5 64 S_LMIDATA[9] 4 DQ1 DQ14 63 S_LMIDATA[10] 5 DQ2 DQ13 62 6 VSSQ1 VDDQ5 61 S_LMIDATA[11] 7 DQ3 DQ12 60 S_LMIDATA[12] 8 DQ4 VDD_S_LMI_2V6 9 VDDQ2 S_LMIDATA[18] S_LMIDATA[13] 10 S_LMIDATA[17] S_LMIDATA[14] 11 DQ6 12 VSSQ2 S_LMIDATA[23] S_LMIDATA[22] S_LMIDATA[21] VDD_S_LMI_2V6 S_LMIDATA[20] S_LMIDATA[19] VDD_S_LMI_2V6 VDD_S_LMI_2V6 S_LMI_NOTCLK 1 2 S_NOTLCLK 1 2 R1003 1k R1001 1k 2 1 C250 100n 10V 1 C249 100n 10V 2 2 1 C248 100n 10V 1 1 DQ10 57 DQ9 56 VDDQ4 55 DQ7 DQ8 54 14 NC1 NC7 53 15 VDDQ3 VSSQ3 52 16 U154 LDQS UDQS HY5DU561622D 17 NC2 18 51 NC6 50 VDD2 VREF 49 19 NC3 VSS2 48 LDM UDM 47 CLK# 46 CLK 45 20 S_NOTLCLK S_LWE 21 WE# S_LCAS 22 CAS# S_LRAS 23 RAS# CKE 44 S_LCS 24 CS# NC5 43 25 NC4 A12 42 S_LCLK S_LCKEN S_LMI_AD[12] S_LMI_AD[11] S_LBANK[0] 26 BA0 A11 41 S_LMI_AD[9] S_LBANK[1] 27 BA1 A9 40 S_LMI_AD[8] S_LMI_AD[10] 28 A10/AP A8 39 S_LMI_AD[7] S_LMI_AD[0] 29 A0 A7 38 S_LMI_AD[6] S_LMI_AD[1] 30 A1 A6 37 S_LMI_AD[5] S_LMI_AD[2] 31 A2 A5 36 32 A3 A4 35 VSS1 34 S_LMI_AD[3] S_LMI_AD[4] VDD_S_LMI_2V6 33R R4 5 R3 6 R2 7 R1 8 R452 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R451 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R443 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R445 4 3 2 1 S_LMIDATA[16] S_LMIDATA[17] S_LMIDATA[18] S_LMIDATA[19] 33 VDD3 S_LMI_ADDR0 S_LMI_NOTCS0 S_LMI_NOTBANK1 S_LMIDATA[20] S_LMIDATA[21] S_LMIDATA[22] S_LMIDATA[23] S_LMI_ADDR10 S_LMI_ADDR3 S_LMI_ADDR2 S_LMI_ADDR1 S_LMIDATA[24] S_LMIDATA[25] S_LMIDATA[26] S_LMIDATA[27] S_LMI_ADDR4 S_LMI_ADDR9 S_LMI_ADDR12 S_LMI_ADDR11 S_LMIDATA[28] S_LMIDATA[29] S_LMIDATA[30] S_LMIDATA[31] S_LMI_ADDR7 S_LMI_ADDR8 S_LMI_ADDR5 S_LMI_ADDR6 DDR IC'LERE YAKIN OLMALI & C289 DDR PIN33'LERE YAKIN OLMALI DDR IC'LERE YAKIN OLMALI STi7101'E YAKIN OLMALI VE R? BIRBIRINE YAKIN OLMALI S_LMI_NOTBANK0 S_LMI_NOTRAS S_LMI_NOTCAS S_LMI_RDNOTWR S_LMI_DQS0 S_LMI_DQM0 S_LMI_DQM2 S_LMI_DQS2 S_LCKEN C676 10u 10V S_LMI_DQS1 S_LMI_DQM1 S_LMI_DQM3 S_LMI_DQS3 VDD_S_LMI_2V6 2 58 13 S_LMI_VREF F VSSQ4 S_LDQM[1] S_LMI_DATA28 S_LMI_DATA29 S_LMI_DATA30 S_LMI_DATA31 S_LCLK DQ5 DQ11 59 S_LDQM[2] S_LMIDATA[12] S_LMIDATA[13] S_LMIDATA[14] S_LMIDATA[15] 2 VDD_S_LMI_2V6 S_LMI_VREF S_LMI_DATA24 S_LMI_DATA25 S_LMI_DATA26 S_LMI_DATA27 1 S_LDQS[1] S_LDQS[2] S_LMIDATA[8] S_LMIDATA[9] S_LMIDATA[10] S_LMIDATA[11] R315 C288 C??? C254 C277 S_LMIDATA[15] S_LMIDATA[16] S_LMI_DATA20 S_LMI_DATA21 S_LMI_DATA22 S_LMI_DATA23 S_LMI_CLK S_LMI_CKEN 1 S_LMIDATA[4] S_LMIDATA[5] S_LMIDATA[6] S_LMIDATA[7] S_LCLK 5 6 LMI SYSTEM DDR VDD_S_LMI_2V6 S_LMI_DATA16 S_LMI_DATA17 S_LMI_DATA18 S_LMI_DATA19 S_LMIDATA[0] S_LMIDATA[1] S_LMIDATA[2] S_LMIDATA[3] 4 C289 10u 10V 33R R4 5 R3 6 R2 7 R1 8 R450 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R444 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R446 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R437 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R183 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R434 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R435 4 3 2 1 7 LMI VIDEO DDR VDD_V_LMI_2V6 1 VDD1 VSS3 66 V_LMIDATA[23] 2 DQ0 DQ15 65 VDD_V_LMI_2V6 3 VDDQ1 VSSQ5 64 V_LMIDATA[22] 4 DQ1 DQ14 63 V_LMIDATA[21] 5 DQ2 DQ13 62 6 VSSQ1 VDDQ5 61 V_LMIDATA[20] 7 DQ3 DQ12 60 V_LMIDATA[19] 8 DQ4 VDD_V_LMI_2V6 9 VDDQ2 S_LMIDATA[26] V_LMIDATA[18] 10 DQ5 S_LMIDATA[25] V_LMIDATA[17] 11 DQ6 12 VSSQ2 S_LMIDATA[31] S_LMIDATA[30] S_LMIDATA[29] VDD_S_LMI_2V6 S_LMIDATA[28] S_LMIDATA[27] VDD_S_LMI_2V6 V_LMIDATA[16] S_LMIDATA[24] VDD_V_LMI_2V6 V_LDQS[2] S_LDQS[3] VDD_V_LMI_2V6 S_LMI_VREF DQ11 59 VSSQ4 58 DQ10 57 DQ9 56 VDDQ4 55 13 DQ7 DQ8 54 14 NC1 NC7 53 15 VDDQ3 VSSQ3 52 16 U153 LDQS UDQS HY5DU561622D 17 NC2 18 50 VDD2 VREF 49 19 NC3 VSS2 48 LDM UDM 47 CLK# 46 CLK 45 S_LDQM[3] V_LDQM[2] 20 S_NOTLCLK V_LWE 21 WE# V_LCAS 22 CAS# V_LRAS 23 RAS# CKE 44 V_LCS 24 CS# NC5 43 25 NC4 A12 42 S_LCLK S_LCKEN S_LMI_AD[12] S_LMI_AD[11] V_LBANK[0] 26 BA0 A11 41 S_LMI_AD[9] V_LBANK[1] 27 BA1 A9 40 S_LMI_AD[8] V_LMI_AD[10] 28 A10/AP A8 39 S_LMI_AD[7] V_LMI_AD[0] 29 A0 A7 38 S_LMI_AD[6] V_LMI_AD[1] 30 A1 A6 37 S_LMI_AD[5] V_LMI_AD[2] 31 A2 A5 36 S_LMI_AD[4] V_LMI_AD[3] 32 A3 A4 35 VDD_V_LMI_2V6 33 VSS1 34 VDD3 LMI VIDEO DDR 1 VDD1 VSS3 66 V_LMIDATA[31] 2 DQ0 DQ15 65 VDD_V_LMI_2V6 3 VDDQ1 VSSQ5 64 V_LMIDATA[30] 4 DQ1 DQ14 63 V_LMIDATA[29] 5 DQ2 DQ13 62 6 VSSQ1 VDDQ5 61 V_LMIDATA[28] 7 DQ3 DQ12 60 V_LMIDATA[27] 8 DQ4 VDD_V_LMI_2V6 9 VDDQ2 V_LMIDATA[5] V_LMIDATA[26] 10 V_LMIDATA[6] V_LMIDATA[25] 11 DQ6 12 VSSQ2 V_LMIDATA[0] V_LMIDATA[1] V_LMIDATA[2] VDD_V_LMI_2V6 V_LMIDATA[3] V_LMIDATA[4] VDD_V_LMI_2V6 V_LMIDATA[24] V_LMIDATA[7] VDD_V_LMI_2V6 51 NC6 8 VDD_V_LMI_2V6 V_LDQS[3] V_LDQS[0] VDD_V_LMI_2V6 V_LMI_VREF DQ5 DQ11 59 VSSQ4 58 DQ10 57 DQ9 56 VDDQ4 55 13 DQ7 DQ8 54 14 NC1 NC7 53 15 VDDQ3 VSSQ3 52 UDQS 51 16 U155 LDQS HY5DU561622D 17 NC2 NC6 50 18 VDD2 VREF 49 19 NC3 VSS2 48 LDM UDM 47 V_LDQM[0] V_LDQM[3] 20 V_NOTLCLK V_LWE 21 WE# CLK# 46 V_LCAS 22 CAS# CLK 45 V_LRAS 23 RAS# CKE 44 V_LCS 24 CS# NC5 43 25 NC4 A12 42 V_LCLK V_LCKEN V_LMI_AD[12] V_LMI_AD[11] V_LBANK[0] 26 BA0 A11 41 V_LMI_AD[9] V_LBANK[1] 27 BA1 A9 40 V_LMI_AD[8] V_LMI_AD[10] 28 A10/AP A8 39 V_LMI_AD[7] V_LMI_AD[0] 29 A0 A7 38 V_LMI_AD[6] V_LMI_AD[1] 30 A1 A6 37 V_LMI_AD[5] V_LMI_AD[2] 31 A2 A5 36 V_LMI_AD[4] V_LMI_AD[3] 32 A3 A4 35 VDD_V_LMI_2V6 33 VSS1 34 VDD3 V_LMIDATA[8] V_LMIDATA[10] VDD_V_LMI_2V6 V_LMIDATA[11] V_LMIDATA[12] V_LMIDATA[13] V_LMIDATA[14] VDD_V_LMI_2V6 V_LMIDATA[15] B V_LDQS[1] V_LMI_VREF V_LDQM[1] V_NOTLCLK V_LCLK V_LMI_AD[12] V_LMI_AD[11] V_LMI_AD[9] V_LMI_AD[8] V_LMI_AD[7] V_LMI_AD[6] V_LMI_AD[5] V_LMI_AD[4] D V_LMI_CKEN S_LBANK[1] S_LMI_AD[10] S_LMI_AD[3] S_LMI_AD[2] S_LMI_AD[1] V_LMI_ADDR11 V_LMI_ADDR3 V_LMI_ADDR2 V_LMI_ADDR1 S_LMI_AD[4] S_LMI_AD[9] S_LMI_AD[12] S_LMI_AD[11] V_LMI_ADDR4 V_LMI_ADDR12 V_LMI_ADDR9 V_LMI_ADDR10 V_LMI_ADDR8 V_LMI_ADDR7 V_LMI_ADDR6 V_LMI_ADDR5 S_LMI_AD[7] S_LMI_AD[8] S_LMI_AD[5] S_LMI_AD[6] S_LBANK[0] S_LRAS S_LCAS S_LWE V_LMI_NOTBANK1 V_LMI_NOTBANK0 V_LMI_NOTRAS V_LMI_NOTCAS S_LDQS[0] S_LDQM[0] S_LDQM[2] S_LDQS[2] V_LMI_DQS2 V_LMI_DQM2 V_LMI_DQM0 V_LMI_DQS0 S_LDQS[1] S_LDQM[1] S_LDQM[3] S_LDQS[3] V_LMI_DQS3 V_LMI_DQM3 V_LMI_DQM1 V_LMI_DQS1 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R1105 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R1115 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R1107 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R1104 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R1106 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R1112 33R 4 R4 5 3 R3 6 2 R2 7 1 R1 8 R1114 V_LMI_AD[0] V_LCS V_NOTLCLK 1 V_LCKEN V_LMI_CLK V_LMI_AD[11] V_LMI_AD[3] V_LMI_AD[2] V_LMI_AD[1] V_LMI_AD[4] V_LMI_AD[12] V_LMI_AD[9] V_LMI_AD[10] V_LMI_AD[8] V_LMI_AD[7] V_LMI_AD[6] V_LMI_AD[5] 1 V_LMI_NOTCLK 1 V_LMI_RDNOTWR 1 R318 C289 C??? C260 C278 R318 100R R182 33R R189 33R R190 33R 2 2 2 2 V_LCLK V_LCLK V_LMI_DATA0 V_LMI_DATA1 V_LMI_DATA2 V_LMI_DATA3 1 2 3 4 R453 33R R1 8 R2 7 R3 6 R4 5 V_LMI_DATA4 V_LMI_DATA5 V_LMI_DATA6 V_LMI_DATA7 1 2 3 4 R432 33R R1 8 R2 7 R3 6 R4 5 V_LMI_DATA8 V_LMI_DATA9 V_LMI_DATA10 V_LMI_DATA11 1 2 3 4 V_LMI_DATA12 V_LMI_DATA13 V_LMI_DATA14 V_LMI_DATA15 1 2 3 4 V_NOTLCLK V_LWE DDR IC'LERE YAKIN OLMALI DDR PIN33'E YAKIN OLMALI DDR IC'LERE YAKIN OLMALI STi7101'E YAKIN OLMALI VE R? BIRBIRINE YAKIN OLMALI V_LMIDATA[0] V_LMIDATA[1] V_LMIDATA[2] V_LMIDATA[3] V_LMI_DATA16 V_LMI_DATA17 V_LMI_DATA18 V_LMI_DATA19 1 2 3 4 R436 33R R1 8 R2 7 R3 6 R4 5 V_LMIDATA[16] V_LMIDATA[17] V_LMIDATA[18] V_LMIDATA[19] V_LMIDATA[4] V_LMIDATA[5] V_LMIDATA[6] V_LMIDATA[7] V_LMI_DATA20 V_LMI_DATA21 V_LMI_DATA22 V_LMI_DATA23 1 2 3 4 R433 33R R1 8 R2 7 R3 6 R4 5 V_LMIDATA[20] V_LMIDATA[21] V_LMIDATA[22] V_LMIDATA[23] R448 33R R1 8 R2 7 R3 6 R4 5 V_LMIDATA[8] V_LMIDATA[9] V_LMIDATA[10] V_LMIDATA[11] V_LMI_DATA24 V_LMI_DATA25 V_LMI_DATA26 V_LMI_DATA27 1 2 3 4 R440 33R R1 8 R2 7 R3 6 R4 5 V_LMIDATA[24] V_LMIDATA[25] V_LMIDATA[26] V_LMIDATA[27] R449 33R R1 8 R2 7 R3 6 R4 5 V_LMIDATA[12] V_LMIDATA[13] V_LMIDATA[14] V_LMIDATA[15] V_LMI_DATA28 V_LMI_DATA29 V_LMI_DATA30 V_LMI_DATA31 1 2 3 4 R447 33R R1 8 R2 7 R3 6 R4 5 V_LMIDATA[28] V_LMIDATA[29] V_LMIDATA[30] V_LMIDATA[31] V_LBANK[1] V_LBANK[0] V_LRAS V_LCAS 4 V_LDQS[2] V_LDQM[2] V_LDQM[0] V_LDQS[0] 2 1 C266 100n 10V C675 10u 10V VDD_V_LMI_2V6 2 1 V_LDQS[3] V_LDQM[3] V_LDQM[1] V_LDQS[1] 5 E V_LMI_VREF C273 100n 10V 2 1 C247 100n 10V C677 10u 10V F VESTEL PROJECT NAME : 17mb37 6 7 A3 SHEET:9 OF:18 DRAWN BY :HUSEYIN E. CETIN 3 C V_LCKEN SCH NAME :DDR RAM FOR STi7101 2 A V_LMIDATA[9] 33R V_LMI_ADDR0 V_LMI_NOTCS0 S_LMI_AD[0] S_LCS R1002 1k 2 R1004 1k 1 14-10-2009_09:10 8 AX M 2 15 S19 2 3V3_STBY PIN 13-14 OF CN4 ARE 3V3 5V_STBY 16 F279 1 12V_VCC C470 47u 16V 1 18V_VCC 17 12V_VCC 18 2 1 19 20 21 22 23 24 25 26 2 1 2 R249 200k 1 2 D161 C876 100n F244 8V_VCC VOUT 1 L120 8 VCC 4 1 2V6_ST S269 F8 2 2V5_ST OUT 1 7 GND C20 100n 6 FSW INH 3 5 FB C761 R1142 2k7 C920 10n COMP 4 1 S289 C18V D186 1 12V_INV 1 C1051 100n 10V 1 11 1 2 C5V6 2 60R 1 1 12V_STBY 1 12V_VCC S306 S307 2 5V_VCC 1 2 1 2 PANEL_VCC 60R F172 12V_IPOD 12V_VCC 1 2 60R 5V_STBY 12V_STBY 1 S300 C1089 220n 25V C1072 10n 16V 2 1 2 3 4 1 2 C1105 22u 16V 2 2 1 1 C1104 22u 16V BS IN SW GND SS EN COMP FB 1 2 JK109 Q181 BC848B 2 1 1 7A/32VDC 2 1 FS4 1 2 1 1 100n 16V NC R1246 10k 1 3 3 PANEL_VCC_ON/OFF TP378 2 R575 10k C309 100n 10V 2 3 2 1 C17 22u 16V Q139 BC848B 2 1 C2 22u 16V 1 1 PANEL SUPPLY SWITCH 1 R1293 15k 1 2 F ! 3V3_STBY 2 1 C1099 22u 16V 2 1 NC VESTEL PROJECT NAME : 17mb37 12V_INV 4 5 6 7 A3 SHEET:10 OF:18 SCH NAME :POWER DRAWN BY :SADIK 2 E 2 2 2 7A/32VDC 1 R205 47R 1 5n6 C1081 50V 2 10u C1100 22u 16V 12V_PSU 3 1 2 SS33 2 1 2 C5V6 2 MOSFET_CONTROL 1 FS5 1 L125 60R 2 D178 4 D191 2 1 R1297 33k ! 5 3 R1276 4k7 C1055 100n 10V 1 1 8 7 6 5 2 2 2 F 100n 10V C1125 R1304 3k9 U189 MP1583 2 1 1 2 3 S301 1 2 R1253 47R 1 1 2 1 2 2 1 1 F285 3V3_VCC 2 R566 10k Q177 BC848B 2 1 TP387 FDC642P Q183 6 5 4 1 R1296 33k 2 1 220n 25V C1085 5V_VCC 7A/32VDC 2 1 R1321 2k MOSFET_CONTROL R1274 4k7 C1054 100n 10V 2 F171 4 R1252 47R 25V 220n C1 F170 1 C1047 2 D 1 3 FS3 1 C1078 4u7 16V 1 2 E 5V_STBY C1091 220n 25V 2 FDC642P Q104 2 ! TP385 1 2 TP384 INVERTER SOCKET 3 TP377 6 1 TP149 1 6 FDC642P Q182 5 4 2 1 C1098 C1097 22u 22u 16V 16V 2 TP386 Q180 BC848B 2 1 2 1 R1273 4k7 C1053 100n 10V R1298 33k 1 5 1 2 3V3_VCC 1 2 C 3 2 1 1 2 R1249 47R BACKLIGHT_ON/OFF DIMMING 2 1 MOSFET_CONTROL S21 R1306 30k FDC642P Q184 1 2 5V_STBY 10u SS33 R1245 10k 3V3_STBY 2 10p 1 1 2 1 2 1 L122 D188 1 C759 R929 10k C918 10n COMP 4 2 1 100n 16V 2 C1103 22u 16V 2 5n6 C1080NC 50V 1 1 C1108 C1109 22u 22u 16V 16V ADAPTER OPTIONS 2 R1299 33k 2 1 2 TP380 2 1 8 7 6 5 R1257 1k C1086 C1102 220n22u 25V 16V 1 SS EN COMP FB R1301 3k9 2 2 BS IN SW GND 2 C1122 1 1 1 2 3 4 1 10V 100n C1046 C1092 2 2 1 2 C5V6 C1071 10n 16V U187 MP1583 5V_Audio 2 10u SS33 2 12V_STBY S303 R1308 30k 2 1 2 1 1 D 1 1 CN137 L124 D190 MECH_SWITCH 4 1 5 FB C753 47u 16V 12V_VCC 12V_STBY 2 2 STBY_ON/OFF_NOT 3 3 STBY_ON/OFF 2 INH 3 2V5_ST 1 4 1 BACKLIGHT_ON/OFF 2 6 FSW 2 2 1 1 C1083 16V 100n 2 5 2 R1242 10k 2 1 7 6 DIMMING 2 NC 1 C1093 220n 25V 220n 25V R1294 33k 8 1 R1270 4k7 R1271 4k7 R1275 4k7 R1272 4k7 1 5n6 50V C1079 4u7 16V 33k R1295 1 2 1 8 7 6 5 1 9 1 D180 TP23 2 SS EN COMP FB 2 2 1 10 12V_VCC C1088 220n 25V C1111 22u 16V BS IN SW GND R1262 1k 11 2 12 C1110 22u 16V 1 2 3 4 1 D179 C5V6 C 2 1 R1303 3k9 C1084 12V_STBY S305 TP381 TP27 5V_STBY 12V_VCC 1 D181 13 1 14 D182 C5V6 18V_VCC 1 3 15 1 16 220n 25V 12V_STBY 1 2 1 C1124 U190 MP1583 2 TP388 C1074 10n 16V 2V5_ST 10u SYNCH 2 L5985 R930 10k R1075 10k 1 C779 10n 16V R1176 2k 7 GND 12V_STBY 4 17 12V_PSU 2 OUT 1 U184 33k R700 18 1 8 VCC 220n 25V 5V_PW 3V3_VCC TP25 3V3_VCC TP28 12V_STBY 2 2 19 L121 12V_VCC S302 1 C814 22u 16V SK24 1 20 100n 10V C1058 C815 22u C618 5V_PW B D162 C875 100n F243 5 17IPS17 CONNECTOR 1 1 S280 STBY_ON/OFF_NOT C754 47u 16V MOSFET_CONTROL 1 MOSFET_CONTROL TP26 2 6 28 3k9 R1340 3k9 R1339 27 2 STBY_ON/OFF 10p 1V0_ST 2 2 R476 1k C1052 100n 10V 1 7 2 8 R378 10k 9 1 12V_VCC 10 B 1V0_ST SYNCH 2 L5985 R931 10k R1074 10k 330R C764 10n 16V 10u U183 C972 220u 25V C812 22u 16V SK24 12V_VCC OUT 2 GND C816 22u 1 TP33 6V3 220u 3 IN 2 330R A 1 S134 1n U122 LM1117 12V_STBY 2 R1139 390R 1 12V_STBY 1 NC R818 180k AVDD_33 C306 100n 10V 2 2V5_ST R1064 6k8 14 FB 1 C535 2 1 1V0_ST D176 R1152 30k 12 13 R702 33k 1 2 6 12V_STBY 11 U144 6 EN NC C575 22u 16V 2 1 ! 1 GND 2 1 330R 3V3_VCC 7A/32VDC TP31 1 2 5 VINA 1V26_STBY C579 22u 16V 5 10 C576 22u 16V D177 10u 2 9 1 3V3_STBY 10V 10u 2 1 SW 3 MP2112 F145 FS6 1 1 2 4 VINB 1 2 8 1 C578 22u 16V 2 1 1 7 NC VDDC C308 100n 10V 2 2 10u 25V 47u 16V 5V_VCC 8 CN144 TP30 6V3 220u C8 1 C452 6 7 L110 S210 1 3V3_STBY 2 5 5V_PW 2 2 330R 10V 10u C7 6 F147 1 24V_VCC 1 2 3V3_VCC C408 10V 10u 2 VDDP C307 100n 10V R411 2k 4 5V_VCC C410 2 3 2 C409 1 330R 1V26_STBY 24V_VCC 2 1 KEYBOARD_ONBOARD 1 1 3V3_STBY 2 1 CN4 2 1 1 5 F146 R22 4k7 R21 4k7 R23 4k7 2 TP29 1 4 PAULO DECOUPLING A/D DIMMING SELECTION 17PW26 CONNECTOR A 3 C464 1 SEHIT 15-10-2009_15:59 8 AX M 1 2 3 4 5 6 7 8 U138 MST6WB7GQ-3 GND15 244 VDDC4 245 19" TO 22" FFC OPTIONS RX_B_0_N 1 LVA4P 246 RX_B_0_P 2 LVA4M 247 RX_B_1_N 3 LVDS CABLE CN139 1 VDDC TP402 CN138 6 TP396 RX_B_1_P 4 RX_B_0_P LVA3M 249 RX_A_3_N RX_B_2_N 5 RX_B_1_N RX_A_CLK_P RX_B_2_P 6 RX_B_1_P RX_B_2_N RX_A_2_P RX_B_CLK_N 8 RX_B_2_P LVA2M 253 RX_A_2_N RX_B_CLK_P 9 LVA1P 254 RX_A_1_P RX_B_3_N 10 LVA1M 255 RX_A_1_N RX_B_3_P 11 RX_A_0_P RX_A_0_N 12 LVA0M 257 RX_A_0_N RX_A_0_P 13 VDDP6 258 2 LVB4M 261 RX_A_1_N RX_A_0_N 3 4 15 RX_A_1_P 16 LVB3M 263 RX_A_2_N RX_B_3_N RX_A_2_P 5 RX_A_CLK_N 20 LVBCKM 265 RX_B_CLK_N RX_A_CLK_P 21 RX_A_3_N 22 LVB2P 266 C RX_B_2_P LVB2M 267 RX_B_2_N LVB1P 268 RX_B_1_P LVB1M 269 RX_B_1_N LVB0P 270 RX_B_0_P LVB0M 271 RX_B_0_N RX_A_3_P 9 10 RX_A_1_P 11 12 S295 13 14 15 BACKLIGHT_ON/OFF TP405 TP406 2 2 S290 1 26 S291 1 27 RX_A_2_P 17 18 RX_A_CLK_N 19 20 1 TP403 1 TP391 1 TP401 1 TP394 1 21 22 13 14 15 16 17 18 19 20 21 22 PANEL_VCC B S285 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 OPTION1 43 44 OPTION2 45 46 OPTION3 47 48 49 50 2 24 OPTION2 RX_A_3_P 25 26 OPTION3 27 28 29 30 2 10k R1244 10k R1243 3V3_VCC 1 PDP_IRQ TP400 TP398 RX_A_2_N 1 1 1 3V3_VCC 1 1 RX_A_CLK_P TP397 RX_A_3_N TP399 RX_A_3_P TP393 OPTION1 23 1 S288 2 BACKLIGHT_ON/OFF 1 S286 2 1 C 1 1 MEGA_DCR 1 12 1 RX_A_3_N S283 10 1 RX_A_CLK_N 2 PANEL_VCC TP389 RX_A_2_P 25 PANEL_VCC 1 9 11 16 23 1 TP407 TP395 RX_A_1_N 24 2 1 RX_A_1_P RX_A_CLK_P 8 2 8 RX_A_1_N RX_A_2_N 6 7 6 19 RX_B_CLK_P TP408 RX_B_3_P 18 LVBCKP 264 1 RX_A_0_P 7 RX_B_3_P TP390 RX_B_3_N 17 LVB3P 262 1 RX_A_0_N RX_A_0_P C311 100n 10V LVB4P 260 2 TP404 RX_B_CLK_P 14 VDDP GND16 259 1 1 RX_B_CLK_N CN140 RX_B_3_P TP392 2 LVA0P 256 PANEL_VCC RX_A_CLK_N 5 A 2 B 7 LVA2P 252 4 S284 LVACKM 251 3 1 LVACKP 250 2 S287 RX_A_3_P 1 1 1 LVA3P 248 1 A RX_B_0_N 28 29 PANEL_VCC = 5V 30 D D SHORT CCT PROTECTION R706 33k 8V_VCC 1 2 1 PANEL_VCC PANEL_VCC 1 2 2V6_ST 1k R1260 2 R705 33k 1 12V_VCC 3 1 Q163 BC848B 2 2 3 1 10k R32 1 2 24V_VCC 2 3 2 1V0_ST S228 LOWER_SUP 2 R563 10k R37 33k 1V0_FE R913 10k D158 BAW56 R564 10k R1255 Q162 BC848B 1 1 2 BC848B D3 BAW56 1 LOWER SUPPLY SHORT CCT PROTECTION 1 R562 10k 2 3 2V5_ST 1k 2 R914 10k Q151 BC858B 1 10k R568 1 1 1 Q136 2 D137 BAW56 TP150 PROTECT 3 3 E 1k R1256 1 R912 10k R565 10k 2 2 2 1 1k R1000 1k R1259 3V3_VCC D159 BAW56 LOWER_SUP 5V_VCC 1 PANEL_VCC F 1 1 2 CN1 1 2 3 4 5 6 F PANEL_VCC = 5V/12V 3V3_STBY F2 330R 1 1 2 2 10k R7 10k R6 F1 2 7 1 2 3 CN2 8 9 2 10 3 10k R571 D136 BAW56 PANEL_VCC 3V3_VCC OPTION3 PANEL_VCC 1 1 3V3_VCC 1 R4 10k R5 10k 330R 2 1 1 2 1 2 4 11 12 5 6 13 14 7 8 15 16 17 9 10 11 18 12 19 13 20 14 21 5V_TUN R708 33k 3V3_VCC S2 RX_A_0_N R3 10k RX_A_0_P RX_A_1_N RX_A_1_P RX_A_2_N RX_A_2_P RX_A_CLK_N RX_A_CLK_P 15 22 23 2 1 2 S9 16 24 17 18 25 26 19 27 20 28 21 29 2 BC848B 1 RX_A_3_N RX_A_3_P S4 2 2 S3 1 10k R569 3 Q137 1 1 22 23 30 D135 BAW56 PDP_IRQ 3 PROTECT_PANEL 2 OPTION1 3V3_VCC 1 2 S8 10k R2 2 1 1 2 S5 2 3V3_VCC OPTION2 10k R1 1 MEGA_DCR 2 S6 1 2 S1 24 25 26 27 28 29 30 1 E PANEL_VCC PANEL VCC = 5V/12V 2 2 VESTEL PROJECT NAME : 17mb37 SHEET:11 OF:18 SCH NAME :LVDS INTERFACE DRAWN BY :SADIK SEHIT 1 2 3 4 5 6 7 A3 14-10-2009_09:09 8 AX M 1 2 3 4 5 6 7 8 S250 3V3D_USB S259 42 XTAL2 43 XTAL1/CLKIN 44 3V3D_USB 45 3V3D_USB R1212 12k 46 ATEST/REG_EN 47 RBIAS GR3/PRTDIS0 17 VDDA33PLL PRTPWR2 16 OCS3_N 15 PRTPWER3 14 VDDA33_3 13 USBDP3 100n 16V C900 100n 16V C836 3V3A_USB 100n 16V USB_PWR_EN_2 1 OUT 5 U166 IN 2 GND USB_PWR_A 3V3A_USB C933 3V3_VCC 5V_USB 1p 5V_USB R1222 4k7 R1221 4k7 R1220 4k7 5V_USB STMP2161 3 FAULT EN 4 R1140 47k USB_OCD USB_DN_2 USB_DN_1 22u 16V C811 Should be close to Pin#40 R1069 100k USB_DP_2 USB_DN USB_DP_1 3V3A_USB USB_DP_1 S233 USB_DN_1 USB_DP 1p USB_DN S236 1p USB_DP w/o USB Hub Opsiyonu 1 C934 B 3V3D_USB R891 10k 12 USBDN3 VSS_2 10 11 USBDN2 9 USBDP2 VDDA33_2 8 7 USBDP1 USBDN1 6 5 VSS_1 USBDN0 4 3 USBDP0 2 R892 10k C C931 100n 16V C894 26 VDDA18PLL 1V8_D 100n 16V 20 C895 GANG_EN R890 10k C897 21 100n 16V GR1/NON_REM0 C1034 10u 10V 100n 16V 22 3V3A_USB 330R 1V8_D C893 VSS_3 F248 3V3_VCC C899 VDD18_1 23 100n 16V 24 18 1 3V3D_USB Should be close to Pin#45 TEST0 PRTPWR_POL VSS_7 330R FE1_SDA 19 VDDA33_1 100n 16V C896 22u 16V C818 48 3V3_VCC 25 SDA/SMBDATA CFG_SEL1 SCL/SMBCLK/CFG_SEL0 27 28 29 30 31 32 33 34 35 F236 FE1_SCL GR2/NON_REM1 U177 USB2503 A 5V_USB C1035 10u 10V C926 22p 5V_VCC C898 3V3D_USB 1V8_D USB_OC_2 R1016 4k7 R950 47R R939 47R SELF_PWR VSS_6 VSS_4 41 VBUS_DET VDD18_3 OCS2_N 1V8_D S257 3V3D_USB 22u 16V USB_PWR_EN_1 1u 6V3 VDD18_2 VDD33CR 40 PRTPWR1 39 OCS1_N 3V3D_USB CLKIN_EN 36 VSS_5 R1144 1M 24MHz RESET_N 38 C925 X109 37 TEST1 USB_RESET 22p C1030 R889 10k 3V3D_USB B USB_OC_1 R893 10k A R1031 4k7 R1032 4k7 C819 R1160 470k USB_ENA_A C R1035 4k7 5V_USB USB_OC_1 USB_OC_1 U165 ST2052 USB_OC_2 1 2 3 4 5V_USB USB_PWR_EN_1 USB_PWR_EN_2 GND IN EN1 EN2 OC1 OUT1 OUT2 OC2 8 7 6 5 USB_OC_1 USB_PWR_1 USB_PWR_2 USB_OC_2 w/o USB Hub Opsiyonu 2 USB_DP_2 D OPTIONAL USB S7 USB_DN USB_DN_2 F250 C1126 S10 USB_DP 10V 10u D CN131 1 USB_PWR_1 330R USB_DN_1 2 USB_DP_1 3 10V 10u DEFAULT USB E C1127 4 F249 E CN132 1 USB_PWR_2 330R 2 USB_DN_2 R1058 10R F251 1 IO1 2 GND IO4 6 U167 USB_PWR_A USB_DP_A 4 5 330R 6 VDD 5 SERVICE USB AZ099-04S 3 IO2 3 C1128 USB_DM_A 10V 10u USB_DP_2 IO3 4 7 8 R1057 10R F F VESTEL PROJECT NAME : 17mb37 SHEET:12 OF:18 SCH NAME :USB DRAWN BY :SADIK SEHIT 1 2 3 4 5 6 7 A3 14-10-2009_09:09 8 AX M 4 5 BUFADDR_6 FLASH_ADDR3 TS_DATA3_1 BUFADDR_7 U163 1Y2 74LCX244 6 1A3 2A3 15 7 2Y2 1Y3 14 8 1A4 2A2 13 9 2Y1 1Y4 12 10 GND 2A1 11 S258 5V_VCC 16 5V_CI BUFADDR_1 FLASH_ADDR5 FLASH_ADDR7 1 B CD1 B 3V3_CI 2 A 74LVC1G32 3 GND Y 4 100n 16V EMI_BE0 3V3_CI 4k7 R1025 2 1A1 VCC 20 2OE- 19 FLASH_NOTCSD CI_IOWR EMI_NBAA CD1 1 3V3_CI CI_IRQ 1 CI_WAIT 1 CI_RESET 1 R1053 4k7 R1052 4k7 R1023 4k7 R1049 4k7 R1044 4k7 2 3V3_CI 2 3V3_CI 3 2Y4 1Y1 18 4 1A2 2A4 17 5 6 CI_OE 3V3_CI 2 3V3_CI 2 3V3_CI CI_CLK 3 68 2 3V3_CI CI_WE 2p2 50V 2p2 50V 7 U161 2Y3 1Y2 74LCX244 1A3 2Y2 C957 15 1Y3 14 8 1A4 2A2 13 9 2Y1 1Y4 12 10 GND 2A1 11 2p2 50V 2p2 50V 16 2A3 TSBYTECLK_3 FLASH_NOTWE R1050 3V3_CI 4k7 FLASH_NOTOE CI_OE 1 CI_WE 1 CI_IOWR 1 CI_IORD 1 R34 4k7 R36 4k7 R33 4k7 R35 4k7 2 3V3_CI 2 3V3_CI 2 3V3_CI 2 3V3_CI F VESTEL PROJECT NAME :17mb37 4 5 6 7 A3 SHEET:13 OF:18 DRAWN BY :ERTUG BAL 2 34 TS_DATA2_3 CD2 67 BUFDATA_2 R333 10k 1 32 E C968 SCH NAME :STi7101 NOR FLASH & CI 1 65 31 BUFDATA_1 64 30 BUFDATA_0 5V_CI line should be thick ! C967 2 33 TS_DATA1_3 4 R4 5 66 TS_DATA0_3 TSPKTCLK_3 R1 R324 2 R2 7 47R 3 R3 6 63 29 BUFADDR_0 62 8 TSVALID_3 26 BUFADDR_3 28 25 BUFADDR_4 BUFADDR_1 24 BUFADDR_5 1 2 1 TS_DATA7_1 R1093 33R TSBYTECLK_3 1 BUFADDR_10 2 8 FLASH_NOTCSD 42 7 BUFDATA_7 1 6 BUFDATA_6 41 5 BUFDATA_5 40 4 BUFDATA_4 1 C903 100n 16V D C958 CI_IORD CI_WE F 100n 16V C834 FLASH_NOTCSD 1OE- 39 3 BUFDATA_3 35 36 2 1 CN116 100n 16V CD2 E 1 57 FLASH_DATA7 23 B8 GND BUFADDR_6 FLASH_DATA6 11 BUFADDR_7 12 TS_DATA6_1 B7 56 A8 10 55 9 BUFDATA_7 22 FLASH_DATA5 21 13 BUFADDR_12 B6 TS_DATA5_1 A7 54 8 53 BUFDATA_6 20 FLASH_DATA4 19 14 2 B5 5V_CI A6 4k7 3V3_CI R471 TS_DATA4_1 7 1 BUFDATA_5 52 FLASH_DATA3 18 B4 74LCX245 R472 4k7 A5 15 A4 2 FLASH_DATA2 6 3V3_CI B3 BUFDATA_4 5V_CI BUFDATA_3 TS_DATA3_1 FLASH_DATA1 16 51 17 50 B2 U164 17 A3 5 16 4 CI_IRQ BUFDATA_2 TS_DATA2_1 FLASH_DATA0 TS_DATA1_1 B1 49 A2 48 BUFDATA_1 15 FLASH_NOTCSD 18 14 19 CI_WE OE- BUFADDR_14 A1 3 TS_DATA0_1 2 TSPKTCLK_1 BUFDATA_0 C831 D 3V3_CI 47 20 13 VCC BUFADDR_8 DIR BUFADDR_13 1 CI_DATA_DIR CI_IOWR 2A1 CD1 GND 11 46 BUFADDR_11 10 45 2Y1 FLASH_ADDR14 12 1Y4 12 11 13 BUFADDR_9 2A2 C CI_IORD 1A4 BUFADDR_10 44 1Y3 FLASH_ADDR13 43 2Y2 14 9 9 15 10 8 2A3 CI_OE 7 74LCX244 TSPKTERR_1 1 BUFADDR_9 BUFADDR_11 1A3 R963 47R 2 TS_DATA7_3 6 1Y2 16 3V3_CI 2Y3 FLASH_ADDR12 TSPKTERR_3 U162 5 BUFADDR_8 CI_CLK 17 TSVALID_1 2A4 1 FLASH_ADDR11 1A2 CI_DETECT FLASH_NOTCSD 47R R200 4k7 R241 BUFADDR_14 18 2 C 1Y1 TS_DATA6_3 FLASH_ADDR10 2OE- 2Y4 S249 3V3_CI TS_DATA5_3 BUFADDR_13 4 1A1 19 TS_DATA4_3 FLASH_ADDR9 3 20 3 R3 6 47R 2 R2 7 R323 R1 1 8 BUFADDR_12 VCC 1OE- 38 FLASH_ADDR8 2 TS_DATA3_3 TSBYTECLK_1 TSPKTCLK_1 1 4 R4 5 C_CLK 4 R4 5 FLASH_NOTCSD 37 C_STRT VCC 5 U157 TSPKTERR_1 TSVALID_1 3V3_CI BUFADDR_3 TS_DATA1_1 2 R2 7 10R 3 R3 6 C_VAL CI_DATA_DIR FLASH_ADDR6 C832 R1172 1 8 R1 3V3_CI R956 47R R1022 4k7 BUFADDR_2 CD2 C_ERR 100n 16V 2Y3 C841 5 FLASH_ADDR4 10u 16V 17 C1095 2A4 CI_REG R199 47R TS_DATA0_1 1A2 1 A 5 VCC 2 B 3 GND Y 4 FLASH_NOTOE EMI_NBAA R1045 3V3_CI 4k7 61 C_D0 4 R4 5 4 BUFADDR_0 BUFADDR_2 B 18 U171 74V1G08 60 TS_DATA2_1 C_D1 2 R2 7 10R 3 R3 6 C_D2 1Y1 R1021 4k7 3V3_CI 27 R1174 1 8 R1 2Y4 3V3_CI 22u CI_WAIT C_D3 3 A L118 3V3_VCC FLASH_NOTCSD 100n 16V FLASH_ADDR2 TS_DATA4_1 19 C844 TS_DATA5_1 2OE- CI_RESET 4 R4 5 BUFADDR_5 1A1 3V3_CI 59 C_D4 FLASH_ADDR1 TS_DATA6_1 2 8 58 C_D5 2 R2 7 10R 3 R3 6 BUFADDR_4 TS_DATA7_1 20 7 10u 16V C_D6 R1173 1 8 R1 VCC C1094 C_D7 1OE- 100n 16V FLASH_ADDR0 1 100n 16V FLASH_NOTCSD C846 A 6 C845 3 100n 16V 2 C829 1 14-10-2009_09:10 8 AX M 4 NOR FLASH FLASH_ADDR17 2 A14 BYTE 47 VCC_F 3 A13 VSS2 46 4 A12 DQ15A-1 45 5 A11 DQ7 44 FLASH_DATA7 6 A10 DQ14 43 FLASH_DATA14 A9 DQ6 42 1 R894 10k R941 47R R948 47R R943 47R A19 DQ5 40 A20 DQ12 39 R1055 4k7 FLASH_DATA13 FLASH_DATA5 FF_OE_NOT 1 OE VCC 20 Q0 Q7 19 NAND_WP_NOT 100n 16V 41 NAND_R_NOT VCC_F NAND_E_NOT NC 14 VPP/WP FLASH_ADDR18 FLASH_ADDR8 FLASH_ADDR7 FLASH_ADDR6 FLASH_ADDR5 FLASH_ADDR4 FLASH_ADDR3 FLASH_ADDR2 Boot Straps For NOR Flash E VCC_F DQ11 36 FLASH_DATA11 NAND_AL DQ3 35 FLASH_DATA3 NAND_CL M29W640 FLASH_DATA4 FLASH_ADDR1 3 D0 D7 18 FLASH_ADDR2 4 D1 D6 17 5 Q1 Q6 16 6 Q2 Q5 15 7 D2 D5 14 8 D3 D4 13 U168 74LCX374 RB DQ10 34 FLASH_DATA10 16 A18 DQ2 33 FLASH_DATA2 17 A17 DQ9 32 FLASH_DATA9 9 Q3 Q4 12 18 A7 DQ1 31 FLASH_DATA1 10 GND CK 11 19 A6 DQ8 30 FLASH_DATA8 20 A5 DQ0 29 FLASH_DATA0 21 A4 G 28 FLASH_NOTOE A3 VSS1 27 23 A2 E 26 FLASH_NOTCSA FLASH_RDNOTWR 24 A1 A0 25 FLASH_ADDR1 NAND_OR_OUT_2 22 FLASH_ADDR15 D VCC 37 15 S241 FLASH_ADDR19 38 2 FLASH_ADDR14 FLASH_ADDR13 FLASH_ADDR12 FLASH_ADDR10 FLASH_ADDR9 FLASH_ADDR8 FLASH_ADDR7 FLASH_ADDR6 FLASH_ADDR5 FLASH_ADDR4 FLASH_ADDR3 FLASH_ADDR2 FLASH_ADDR1 FLASH_NOTCSA R916 10k R918 10k R917 10k R915 10k R899 10k R897 10k R898 10k R921 10k R920 10k R919 10k R922 10k R924 10k R925 10k R903 10k R902 10k R907 10k R906 10k R905 10k R904 10k R923 10k FLASH_ADDR3 VCC_F NC2 NC28 47 3 NC3 NC27 46 4 NC4 NC26 45 5 NC5 I/O7 44 FLASH_DATA7 I/O6 43 FLASH_DATA6 FLASH_DATA5 FLASH_DATA4 E0 E1 E2 VSS VCC WC SCL SDA 8 7 6 5 F254 5V_VCC 60R FE1_SCL FE1_SDA VCC 5 I/O5 8 R I/O4 41 9 E NC25 40 10 NC7 NC24 39 11 NC8 NC23 38 VDD2 37 U169 TP376 TP375 B VCC_F 13 VSS1 VSS2 36 14 NC9 NC22 35 15 NC10 NC21 34 NAND_CL 16 CL NC20 33 NAND_AL 17 AL I/O3 32 FLASH_DATA3 NAND_W_NOT R896 10k R895 10k 18 W I/O2 31 FLASH_DATA2 FLASH_DATA1 FLASH_DATA0 NAND512-A FE1_SCL FE1_SDA 19 WP I/O1 30 20 NC11 I/O0 29 21 NC12 NC19 28 22 NC13 NC18 27 23 NC14 NC17 26 24 NC15 NC16 25 C VCC_F U158 2 A 74LVC1G32 3 GND Y 4 1 NC RB 42 VDD1 NC 3V3_CI NC6 7 FF_CLK VCC_F 1 B 6 12 C843 13 1 2 3 4 2 FF_CLK D VCC 5 VCC_F U178 FLASH_ADDR4 2 A 74LVC1G04 3 GND Y 4 F_ADDR4_INV 3V3_CI FAST FLASHPROGRAMMING VCC_F R1013 4k7 FLASH_NOTCSB 3V3_CI FLASH_ADDR4 NAND_OR_OUT_1 3V3_CI FLASH_NOTCSB F_ADDR4_INV 3V3_CI NAND_OR_OUT_2 100n 16V S243 S242 DQ4 U172 RP NAND_E_NOT 100n 16V FLASH_ADDR22 VCC_F FLASH_WP VCC_F W 12 48 100n 16V RESET_7101 11 FLASH_DATA12 C853 FLASH_WE 10 C828 FLASH_ADDR21 C851 B C DQ13 NC29 A 1 1A VCC 14 2 1B 4B 13 FLASH_NOTOE 3 1Y 4A 12 NAND_OR_OUT_1 4 2A 4Y 11 U175 74LVC32 5 2B 3B 10 6 2Y 3A 9 3Y 8 7 GND VCC_F VCC_F FLASH_RDNOTWR R1051 4k7 U170 74V1G08 1 A 5 VCC 2 B 3 GND Y 4 100n 16V 9 FLASH_ADDR20 A8 FLASH_DATA6 C840 8 FLASH_ADDR9 NC1 U151 24C32 FLASH_DATA15 VCC_F 7 FLASH_ADDR10 EEPROM NAND FLASH VCC_F 60R 8 100n 16V FLASH_ADDR11 48 C852 FLASH_ADDR12 7 C850 FLASH_ADDR13 A16 100n 16V FLASH_ADDR14 A15 100n 16V FLASH_ADDR15 6 F253 3V3_VCC 1 C842 FLASH_ADDR16 100u 16V A 5 100n 16V 3 C892 2 C826 1 E VCC_F FLASH_WE NAND_R_NOT FLASH_RDNOTWR NAND_OR_OUT_1 NAND_W_NOT 3V3_CI 3V3_CI F F VESTEL PROJECT NAME :17mb37 SHEET:14 OF:18 SCH NAME :STi7101 FLASH & EEPROM DRAWN BY :ERTUG BAL 1 2 3 4 5 6 7 A3 14-10-2009_09:10 8 AX M 1 2 3 4 LMI SYSTEM A B C S_LMI_ADDR0 M4 S_LMI_ADDR1 N5 V1 LMISYSDATA[1] V2 S_LMI_ADDR2 N4 LMISYSADD[2] LMISYSDATA[2] W1 S_LMI_ADDR3 P5 LMISYSADD[3] LMISYSDATA[3] W2 S_LMI_ADDR4 U4 LMISYSADD[4] LMISYSDATA[4] Y1 S_LMI_ADDR5 V5 LMISYSADD[5] LMISYSDATA[5] Y2 S_LMI_ADDR6 V4 LMISYSADD[6] LMISYSDATA[6] AA1 S_LMI_ADDR7 W5 LMISYSADD[7] LMISYSDATA[7] AA2 S_LMI_ADDR8 W4 LMISYSADD[8] LMISYSDATA[8] E2 S_LMI_ADDR9 U5 LMISYSADD[9] LMISYSDATA[9] E1 S_LMI_ADDR10 P4 LMISYSADD[10] LMISYSDATA[10] F2 S_LMI_ADDR11 T5 LMISYSADD[11] LMISYSDATA[11] F1 S_LMI_ADDR12 T4 LMISYSDATA[12] G2 LMISYSADD[1] LMISYSADD[12] S_LMI_DQM0 AB2 LMIS_DMASK0 S_LMI_DQM1 J1 LMIS_DMASK1 S_LMI_DQM2 AC1 LMIS_DMASK2 S_LMI_DQM3 K2 S_LMI_DQS0 AB1 LMIS_DSTROBE0 LMISYSDATA[13] G1 LMISYSDATA[14] H2 3 LMISYSDATA[15] U160 LMIS_DMASK3 LMISYSDATA[16] STI7101YWC 6 LMI VIDEO LMISYSDATA[0] LMISYSADD[0] 5 V_LMI_ADDR0 E10 LMIVIDADD[0] LMIVIDDATA[0] A14 S_LMI_DATA1 V_LMI_ADDR1 D10 LMIVIDADD[1] LMIVIDDATA[1] B14 S_LMI_DATA2 V_LMI_ADDR2 E9 S_LMI_DATA3 V_LMI_ADDR3 D9 S_LMI_DATA4 V_LMI_ADDR4 S_LMI_DATA5 S_LMI_DATA0 LMIVIDADD[2] V_LMI_DATA2 LMIVIDADD[3] LMIVIDDATA[3] B15 V_LMI_DATA3 D6 LMIVIDADD[4] LMIVIDDATA[4] A16 V_LMI_DATA4 V_LMI_ADDR5 E6 LMIVIDADD[5] LMIVIDDATA[5] B16 V_LMI_DATA5 S_LMI_DATA6 V_LMI_ADDR6 D5 LMIVIDADD[6] LMIVIDDATA[6] A17 V_LMI_DATA6 S_LMI_DATA7 V_LMI_ADDR7 E5 LMIVIDADD[7] LMIVIDDATA[7] B17 V_LMI_DATA7 S_LMI_DATA8 V_LMI_ADDR8 D4 LMIVIDADD[8] LMIVIDDATA[8] A1 V_LMI_DATA8 V_LMI_ADDR9 E7 LMIVIDADD[9] LMIVIDDATA[9] B2 S_LMI_DATA10 V_LMI_ADDR10 D8 LMIVIDADD[10] LMIVIDDATA[10] A2 S_LMI_DATA11 V_LMI_ADDR11 E8 LMIVIDADD[11] LMIVIDDATA[11] B3 S_LMI_DATA12 V_LMI_ADDR12 D7 LMIVIDDATA[12] A3 H1 S_LMI_DATA16 V_LMI_DQM3 S_LMI_DATA17 V_LMI_DQS0 S_LMI_DQS1 J2 LMIS_DSTROBE1 LMISYSDATA[18] AE1 S_LMI_DQS2 AC2 LMIS_DSTROBE2 LMISYSDATA[19] AE2 S_LMI_DQS3 K1 LMIS_DSTROBE3 LMISYSDATA[20] AF1 S_LMI_NOTBANK0 K4 LMISYSBKSEL[0] LMISYSDATA[21] AF2 S_LMI_DATA21 S_LMI_NOTBANK1 L5 LMISYSBKSEL[1] LMISYSDATA[22] AG1 S_LMI_CLK U1 LMISYSCLK LMISYSDATA[23] AG2 S_LMI_CKEN R1150 120k Y5 LMISYSCLKEN LMISYSDATA[24] L2 R1 LMISYSREF LMISYSDATA[25] L1 S_LMI_VREF H5 LMISYSVREF LMISYSDATA[26] M2 S_LMI_NOTCAS J4 NOTLMISYSCAS LMISYSDATA[27] M1 A6 A5 S_LMI_DATA19 V_LMI_DQS2 S_LMI_DATA20 V_LMI_DQS3 LMIVIDDATA[13] B4 LMIVIDDATA[14] A4 4 B19 LMIV_DSTROBE2 LMIVIDDATA[19] B21 B7 LMIV_DSTROBE3 LMIVIDDATA[20] A22 LMIVIDDATA[23] B23 V_LMI_DATA23 C11 LMIVIDVREF LMIVIDDATA[26] A8 S_LMI_DATA27 V_LMI_NOTCAS D15 NOTLMIVIDCAS LMIVIDDATA[27] B9 AK26 TP262 AN22 EMIDMAREQ[0] SYSITRQ[2] AK27 TP261 AL22 EMIDMAREQ[1] SYSITRQ[3] AK28 D21 AL6 NC2 TDI D22 AM5 NC3 TDO E22 NC4 TMDSREF T32 NC5 U160 TMDSTX0N STI7101YWC AP9 NC6 TMDSTX0P T33 C30 NC7 TMDSTX1N R34 L31 NC8 TMDSTX1P R33 AM31 NC9 TMDSTX2N P34 E16 NMI TMDSTX2P P33 V_LMI_DATA24 V_LMI_DATA25 NOT_TRST TMDSTXCN U34 NOTASEBRK TMDSTXCP U33 TMS E21 NOTRESETIN SYSB_CLKOSC R887 10k R1076 100R DVB_IRQ R957 47R CI_IRQ R879 10k R882 10k TCK TDI TDO R1124 75R T34 A29 R883 10k V_LMI_DATA21 E17 TCK A SYSB_CLKIN_ALT AN27 NC1 5 SYSB_CLKIN E27 G5 RESET_7101 R881 10k A13 LMIVIDCLK V_LMI_VREF SYSITRQ[1] D19 V_LMI_CLK S_LMI_DATA26 DAA_C2A V_LMI_DATA20 S_LMI_DATA23 S_LMI_DATA25 AK25 E20 V_LMI_DATA22 B8 SYSITRQ[0] NOTRST S_LMI_DATA22 LMIVIDDATA[25] DAA_C1A AP5 NOTASEBRK LMIVIDDATA[22] A23 LMIVIDDATA[24] AN5 V_LMI_DATA19 E13 LMIVIDBKSEL[1] B12 LMIVIDREF SYSCLKOUT D20 V_LMI_NOTBANK1 V_LMI_CKEN R1151 120k ATATXP AN9 V_LMI_DATA18 V_LMI_NOTBANK0 S_LMI_DATA24 AN30 V_LMI_DATA17 LMIVIDDATA[21] B22 A7 SYSBCLKOSC V_LMI_DATA16 D14 LMIVIDBKSEL[0] D13 LMIVIDCLKEN SYSBCLKINALT V_LMI_DATA15 LMIVIDDATA[18] A21 SYSA_CLKIN ATATXN V_LMI_DATA14 LMIV_DSTROBE1 SYSBCLKIN ATARXP V_LMI_DATA13 LMIVIDDATA[17] B20 C1 AP27 AP30 V_LMI_DATA12 B5 ATARXN SYSACLKIN AN31 V_LMI_DATA11 A20 ATAREF AP31 V_LMI_DATA10 LMIVIDDATA[15] 8 MISCELLANEOUS AM30 V_LMI_DATA9 U160 LMIV_DMASK3 LMIVIDDATA[16] STI7101YWC A18 LMIV_DSTROBE0 V_LMI_DQS1 S_LMI_DATA18 LMIV_DMASK1 A19 LMIV_DMASK2 V_LMI_DQM2 S_LMI_DATA15 LMISYSDATA[17] AD2 B6 V_LMI_DQM1 S_LMI_DATA14 LMIVIDADD[12] B18 LMIV_DMASK0 V_LMI_DQM0 S_LMI_DATA13 AD1 V_LMI_DATA1 LMIVIDDATA[2] A15 S_LMI_DATA9 R1130 470R R886 10k R880 10k R888 10k R885 10k V_LMI_DATA0 7 B TMDSTX0N TMDSTX2N TMDSTX0P TMDSTX2P TMDSTX1N TMDSTX1N TMDSTX1P TMDSTX1P TMDSTX2N TMDSTX0N TMDSTX2P TMDSTX0P TMDSTXCN TMDSTXCN 2 R2 7 10k 3 R3 6 TMDSTXCP TMDSTXCP 4 R4 5 RTCCLKIN TMUCLK E18 D NOTLMISYSCLK LMISYSDATA[28] N2 DCUTRIGGERIN D17 TRIGGERIN USBDM AP25 DCUTRIGGEROUT R878 10k D18 TRIGGEROUT USBDP AN25 E19 WDOGRSTOUT USBREF AM25 USB_DN USB_DP R1005 12k R1020 4k7 R1054 4k7 R1048 4k7 R871 10k R901 10k R900 10k R875 10k R877 10k R873 10k R872 10k R876 10k R874 10k V_LMI_DATA26 S_LMI_NOTCS0 L4 NOTLMISYSCS[0] LMISYSDATA[29] N1 TP251 M5 NOTLMISYSCS[1] LMISYSDATA[30] P2 S_LMI_NOTRAS K5 NOTLMISYSRAS LMISYSDATA[31] P1 V_LMI_DATA27 S_LMI_DATA28 V_LMI_NOTCLK B13 NOTLMIVIDCLK LMIVIDDATA[28] S_LMI_DATA29 V_LMI_NOTCS0 D11 NOTLMIVIDCS[0] LMIVIDDATA[29] B10 S_LMI_DATA30 TP250 S_LMI_DATA31 V_LMI_NOTRAS A9 LMIVIDDATA[30] A10 V_LMI_DATA30 E14 NOTLMIVIDRAS LMIVIDDATA[31] A11 V_LMI_DATA31 S231 JTAG_PIN1 V_LMI_DATA29 E11 NOTLMIVIDCS[1] 3V3_VCC C742 100n V_LMI_DATA28 1 1A 1k 2 1Y 6A 13 3 2A 6Y 12 3V3_VCC F258 14 VCC 3V3_VCC 3V3_VCC CI_WAIT 3V3_VCC S_LMI_RDNOTWR J5 NOTLMISYSWE LMIS_GNDCOMP R2 E15 NOTLMIVIDWE V_LMI_RDNOTWR S232 LMIV_GNDCOMP B11 4 NOTASEBRK TSBYTECLK_1 CI_CLK Q168 BC847B R1033 4k7 UART_TXD Q167 BC847B 11 5A 74HCU04 5 3A 5Y 10 6 3Y 4A 9 7 GND 4Y 8 FLASH_ADDR18 CI_REG PONRST TXD_CON 1 1A VCC 14 2 1Y 6A 13 XTAL1 3 2A 6Y 12 XTAL2 4 2Y 5A 11 XTAL2 R965 47R 5 3A C739 100n 10V C992 10u F274 R1072 27k Q165 BC847B 3V3_VCC R970 1k C940 33p 50V RXD_CON SYSA_CLKIN 6 7 S245 UART_RXD F X107 TP366 SYSB_CLKOSC CN135 RXD_CON 30MHz C921 22p 50V 1 2 UART DEBUG TXD_CON S238 UART_TXD R1169 120R C922 22p 50V 3 CLOCKS TP365 U180 74HCU04 3Y GND 5Y 10 4A 9 4Y 8 SYSB_CLKIN C737 100n 10V RESET_7101 R870 10k 3V3_VCC NOTJTAGRST XTAL1 JTAG Q166 BC847B 2V5_ST 1k R1066 3k3 R1068 3k3 R1065 3k3 RESET_DVB R1129 2k2 E UART_RXD 2Y FLASH_WAIT R1067 3k3 12V_VCC C854 100n 16V R1119 75R U181 R998 1k Q169 BC847B XTAL2 XTAL2 R966 47R XTAL1 SYSB_CLKIN_ALT R1143 1M 3 VCC U159 GND RST LM809 1 2 R1071 3k9 CI_REG NOTJTAGRST NOTASEBRK JTAG_PIN1 TDI TCK TMS DCUTRIGGERIN DCUTRIGGEROUT CN136 2 DCUTRIGGERIN 3 4 DCUTRIGGEROUT 5 6 NOTASEBRK 7 8 TMS 9 10 TCK 11 12 TDI 13 14 TDO 15 16 NOTJTAGRST 17 18 NOTRST 19 20 PONRST 3V3_VCC DVB_RESET 1 2 R375 10k R185 33R F 2 RESET_DVB 1 2 RESET 1 C251 100n 10V VESTEL PROJECT NAME : 17mb37 3 4 5 6 7 A3 SHEET:15 OF:18 MISC DRAWN BY :HUSEYIN E. CETIN 2 E 3V3_VCC SCH NAME :STi7101 LMI, 1 D NOTRST 3V3_VCC X106 C924 22p 50V FLASH_ADDR18 1 C821 100u 16V C738 100n 10V XTAL2 30MHz C923 22p 50V 2 FLASH_WAIT JTAG_PIN1 F247 1 4 R4 5 R1154 1 8 R1 C 3V3_VCC U2 2 R2 7 10k 3 R3 6 TMS R884 10k D16 3V3_VCC S_LMI_NOTCLK R1155 1 8 R1 14-10-2009_09:10 8 AX M 1 2 A C693 10u R1343 10k 1 8 R1 2 R2 7 3 R3 6 4 R4 5 R1089 33R VIDDIGOUT0 L34 A27 AUDANAMLOUT VIDDIGOUT1 L33 MII_TXD1 FLASH_ADDR2 A28 AUDANAMROUT VIDDIGOUT2 K34 MII_TXD2 FLASH_ADDR3 B27 AUDANAPLOUT VIDDIGOUT3 K33 MII_TXD3 FLASH_ADDR4 B28 AUDANAPROUT VIDDIGOUT4 J34 MII_TX_EN FLASH_ADDR5 C28 AUDANAVBGFIL VIDDIGOUT5 J33 MII_MDIO FLASH_ADDR6 D29 AUDDIGDATAIN VIDDIGOUT6 H34 MII_MDC FLASH_ADDR7 E28 AUDDIGLRCLKIN VIDDIGOUT7 H33 MII_RX_CLK FLASH_ADDR8 D28 AUDDIGSTRBIN VIDDIGOUT8 U30 MII_RXD0 FLASH_ADDR9 E26 AUDLRCLKOUT VIDDIGOUT9 T31 MII_RXD1 FLASH_ADDR10 VIDDIGOUT10 T30 MII_RXD2 FLASH_ADDR11 A25 AUDPCMOUT0 B 4 R4 5 10k 3 R3 6 R1344 2 R2 7 B25 AUDPCMOUT1 R1 1 8 R1090 33R R1079 100R DVB_SPDIF VID_OUT_BLUE VID_OUT_CVBS VID_OUT_GREEN C VIDDIGOUT11 R31 1 VIDDIGOUT12 R30 U160 VIDDIGOUT13 STI7101YWC I2S_CLK_DVB FLASH_ADDR1 MII_TXD0 MII_RXD3 FLASH_ADDR12 MII_TX_CLK FLASH_ADDR13 MII_COL FLASH_ADDR14 C25 AUDPCMOUT2 P31 D25 AUDPCMOUT3 VIDDIGOUT14 P30 MII_CRS FLASH_ADDR15 E25 AUDPCMOUT4 VIDDIGOUT15 N31 MII_MDINT FLASH_ADDR16 E24 AUDSCLKOUT VIDDIGOUTHS M33 MII_RX_DV FLASH_ADDR17 D24 AUDSPDIFOUT VIDDIGOUTVS M34 MII_RX_ER FLASH_ADDR18 E34 VIDANAB0OUT VIDANAIDUMPCV1 C33 A34 VIDANAC1OUT VIDANAIDUMPG0 F33 FLASH_ADDR20 C34 VIDANACV1OUT VIDANAIDUMPR0 D33 FLASH_ADDR21 F34 VIDANAG0OUT VIDANAIDUMPY1 B33 B31 VIDANAGREXT0 VIDANAR0OUT D34 B32 VIDANAGREXT1 VIDANAREXT0 A31 E33 VIDANAIDUMPB0 VIDANAREXT1 A32 A33 VIDANAIDUMPC1 VIDANAY1OUT B34 FLASH_ADDR19 FLASH_ADDR22 4 R4 5 AL9 should be close to ST7101 AP20 3 R3 6 33R 2 R2 7 AK10 EMIADDR[2] EMIDATA[1] AP19 AL10 EMIADDR[3] EMIDATA[2] AP18 R1 1 8 R1113 4 R4 5 AK11 EMIADDR[4] EMIDATA[3] AP17 AL11 EMIADDR[5] EMIDATA[4] AP15 3 R3 6 33R 2 R2 7 AK12 EMIADDR[6] EMIDATA[5] AP14 AL12 EMIADDR[7] EMIDATA[6] AP13 R1 1 8 R1109 R4 4 5 AK13 EMIADDR[8] EMIDATA[7] AP12 AL13 EMIADDR[9] EMIDATA[8] AN20 3 R3 6 33R 2 R2 7 AK14 EMIADDR[10] EMIDATA[9] AN19 AL14 EMIADDR[11] EMIDATA[10] AN18 D VID_OUT_CVBS VID_OUT_RED VID_OUT_GREEN VID_OUT_BLUE EMIDATA[11] AN17 R1 1 8 R1118 4 R4 5 AL15 EMIDATA[12] AN15 EMIADDR[13] 3 R3 6 33R 2 R2 7 AK17 EMIADDR[14] AN14 AL17 U160 EMIDATA[13] STI7101YWC EMIADDR[15] EMIDATA[14] AN13 R1 1 8 R1108 R4 4 5 AK18 EMIADDR[16] EMIDATA[15] AN12 3 R3 6 33R 2 R2 7 AK19 AL19 R1 1 8 R1110 R944 47R R945 47R AK20 AL20 EMIBUSGNT R1008 VDD_3V3 4k7 R968 FLASH_RDNOTWR 47R F257 5V_VCC VID_OUT_RED F259 PR_OUT S275 VID_OUT_BLUE S270 VID_OUT_GREEN 1 2 3 4 220n 10V C810 C1149 16V 10u IN1 IN2 IN3 +VCC PB_OUT OUT1 OUT2 OUT3 GND R1157 75R R1158 75R R1156 75R 8 7 6 5 PR_OUT PB_OUT Y_OUT Y_OUT should be close to U129 1k C988 68p 50V F260 1k C990 68p 50V F261 1k C991 68p 50V DVB_PR C987 68p 50V 22u F DVB_Y C986 68p 50V C736 100n 10V S265 10p L119 VID_OUT_CVBS 1u2 C994 150p 50V EMIFLASHCLK AN21 EMIADDR[18] NOTEMIBAA AP21 EMIADDR[19] NOTEMIBE[0] AP11 EMIADDR[20] NOTEMIBE[1] AN11 EMIADDR[21] NOTEMICSA AK9 NOTEMICSB AL8 EMIADDR[17] EMIADDR[22] AL21 EMIADDR[23] NOTEMICSC AM8 AM21 EMIBUSGNT NOTEMICSD AP8 AM20 EMIBUSREQ NOTEMICSE AK8 AN10 EMIRDNOTWR NOTEMILBA AP22 AK22 EMITRDY/WAIT NOTEMIOE AP10 FL_DATA1 C_RESET FL_DATA2 DVB_TXD R1099 33R FL_DATA3 FL_DATA4 FL_DATA5 FL_DATA6 FL_DATA7 FL_DATA8 AGC_S1 FL_DATA9 FF_OE_NOT FL_DATA10 FL_DATA11 NAND_WP_NOT FL_DATA12 FLASH_WP FL_DATA13 USB_RESET R1082 100R R1100 33R R1092 33R R1095 33R R1085 33R FL_DATA14 FL_DATA15 FE1_SCL TP280 R967 47R R959 47R R969 47R R934 47R R936 47R R958 47R R1007 4k7 R1009 4k7 R946 47R R955 47R FE1_SDA EMI_NBAA R952 47R R953 47R EMI_BE0 FLASH_ADDR0 FLASH_NOTCSA AM32 PIO0[0] PIO3[0] AE32 AP33 PIO0[1] PIO3[1] AE34 AN33 PIO0[2] PIO3[2] AE33 AP34 PIO0[3] PIO3[3] AD34 AN34 PIO0[4] PIO3[4] AD33 AM33 PIO0[5] PIO3[5] AC34 AM34 PIO0[6] PIO3[6] AC33 AL32 PIO0[7] PIO3[7] AB34 AL34 PIO1[0] PIO4[0] AD32 AL33 PIO1[1] PIO4[1] AD30 AK34 PIO1[2] PIO4[2] AD31 FLASH_NOTCSB FLASH_NOTCSD VDD_3V3 6 AK33 PIO1[3] PIO4[3] AC30 AJ34 U160 PIO1[4] PIO4[4] STI7101YWC AC31 AJ33 PIO1[5] PIO4[5] AB30 AH34 PIO1[6] PIO4[6] AB31 AH33 PIO1[7] PIO4[7] AA30 AJ30 PIO2[0] PIO5[0] AB33 AJ31 PIO2[1] PIO5[1] AA34 AH30 PIO2[2] PIO5[2] AA33 Y34 AH31 PIO2[3] PIO5[3] AG30 PIO2[4] PIO5[4] Y33 PIO5[5] AA31 AG31 PIO2[5] AE31 PIO2[6] PIO5[6] Y30 AE30 PIO2[7] PIO5[7] Y31 A R942 47R R937 47R R940 47R R938 47R IR_7101 CI_RESET UART_RXD UART_TXD B R949 47R ETH_RESET R951 47R DVB_IRQ R954 47R RESET_T CI_DETECT R1210 USB_OC_1 47R R1211 47R USB_PWR_EN_1 FLASH_NOTWE FLASH_NOTOE D TRANSPORT STREAM TS_DATA0_1 AH5 TSIN0DATA[0] TSIN2DATA[0] AP1 TS_DATA0_3 TS_DATA1_1 AG4 TSIN0DATA[1] S244 DVB_CVBS C752 47p 50V Q172 BC857B VDD_3V3 R927 10k R926 10k R1019 4k7 R1039 4k7 R1012 4k7 R1024 4k7 EMIBUSGNT C995 150p 50V R1015 4k7 R1047 4k7 R1056 4k7 R1046 4k7 R1034 4k7 R1014 4k7 R1217 4k7 TSIN2DATA[1] AN2 3V3_VCC TS_DATA1_3 TS_DATA2_1 AK1 TSIN0DATA[2] TSIN2DATA[2] AN1 3V3_VCC TS_DATA2_3 TS_DATA3_1 AK2 TSIN0DATA[3] TSIN2DATA[3] AM2 FLASH_WAIT 3V3_VCC TS_DATA3_3 TS_DATA4_1 AJ1 TSIN0DATA[4] TSIN2DATA[4] AM1 FLASH_NOTCSA 3V3_VCC TS_DATA4_3 TS_DATA5_1 AJ2 TSIN0DATA[5] TSIN2DATA[5] AL2 FLASH_NOTCSB FLASH_NOTCSD 3V3_VCC TS_DATA5_3 TS_DATA6_1 AH1 TSIN0DATA[6] TSIN2DATA[6] AL1 3V3_VCC TS_DATA6_3 TS_DATA7_1 AH2 TSIN0DATA[7] TSIN2DATA[7] AL3 3V3_VCC TS_DATA7_3 C_D0 AE5 TSIN1DATA[0] TSIN0ERROR AH4 TSPKTERR_1 FL_DATA0 FL_DATA8 FL_DATA1 FL_DATA9 R1102 1 R1 8 2 R2 7 3 R3 6 4 R4 5 FL_DATA2 FL_DATA10 FL_DATA3 FL_DATA11 33R R1111 1 R1 8 2 R2 7 3 R3 6 4 R4 5 FL_DATA4 FL_DATA12 FL_DATA5 FL_DATA13 33R R1101 1 R1 8 2 R2 7 3 R3 6 4 R4 5 FLASH_DATA4 FLASH_DATA12 FLASH_DATA5 FLASH_DATA13 FL_DATA6 FL_DATA14 FL_DATA7 FL_DATA15 33R R1103 1 R1 8 2 R2 7 3 R3 6 4 R4 5 FLASH_DATA6 FLASH_DATA14 FLASH_DATA7 FLASH_DATA15 FLASH_DATA0 FLASH_DATA8 FLASH_DATA1 FLASH_DATA9 FE1_SCL FE1_SDA RESET_T UART_RXD UART_TXD ETH_RESET USB_PWR_EN_1 R792 10k 3V3_STBY FLASH_DATA2 FLASH_DATA10 FLASH_DATA3 FLASH_DATA11 R793 10k IR_7101 Q158 BC848B IR_IN TSBYTECLK_3 C751 47p 50V 7 U160 TSIN1DATA[1] STI7101YWC TSIN1ERROR AD4 C_D2 AD5 TSIN1DATA[2] TSIN2ERROR AP2 TSPKTERR_3 C_D3 AC4 TSIN1DATA[3] TSIN0PACKETCLK AJ4 TSPKTCLK_1 C_D4 AC5 TSIN1DATA[4] TSIN1PACKETCLK AF4 C_STRT C_D5 AB4 TSIN1DATA[5] TSIN2PACKETCLK AP3 TSPKTCLK_3 C_D6 AB5 TSIN1DATA[6] TSIN1BYTECLK AG5 C_CLK C_D7 AA4 TSIN1DATA[7] TSIN2BYTECLK AM3 TSBYTECLK_3 TSBYTECLK_1 AK6 TSIN0BYTECLK TSIN1BYTECLKVALID AF5 C_VAL AJ5 TSIN0BYTECLKVALID TSIN2BYTECLKVALID AN3 TSVALID_3 TSVALID_1 AE4 3 SCH NAME :STi7101 A/V, PIO, EMI, TS 4 C_ERR VESTEL PROJECT NAME : 17mb37 33R 2 E C_D1 DRAWN BY :HUSEYIN E. CETIN 1 C VDD_3V3 5V_AV C789 100p 50V DVB_PB C989 68p 50V R1164 220R R1165 220R R1166 220R C917 VDD_3V3 VDD_3V3 L117 5V_VCC AK21 2 DVB_RXD FL_DATA0 VID_OUT_BLUE VID_OUT_RED VID_OUT_RED VID_OUT_BLUE VID_OUT_GREEN 5V_AV AL18 EMIADDR[12] 8 C5V1 1k VID_OUT_GREEN S271 U173 TSH343 7 D170 VID_OUT_CVBS VDD_3V3 E EMIADDR[1] AK15 TP281 VID_OUT_RED R1163 7k5 R1162 7k5 should be close to U129 R1224 150R R1226 150R R1227 150R R1225 150R 6 PIO EMIDATA[0] FLASH_WAIT R1146 150R R1147 150R R1149 150R R1148 150R 5 EMI C27 AUDANAIREF D26 AUDPCMCLKOUT R1091 33R I2S_DATA_DVB 4 AUDIO & VIDEO R1159 560R I2S_WS_DVB 3 5 6 7 F A3 SHEET:16 OF:18 14-10-2009_09:10 8 AX M VDD_CKGA V_LMI_DLL_VDD S_LMI_DLL_VDD VDD_CKGB VDD_CKGA 8 VDD_SATA_OSC_1V0 7 USB_VDD_1V0 VDD_S_LMI_2V6 VDD_V_LMI_2V6 VDD_ANA_2V5 VDD_CKG_2V5 VDD_CKG_2V5 VDD_CKG_2V5 6 A F266 VDD_1V0 1k C728 100n 10V S_LMI_DLL_VDD C791 100p 50V VDD_3V3 VDD_1V0 B F265 VDD_1V0 1k C729 100n 10V V_LMI_DLL_VDD C790 100p 50V C981 1u 6V3 C735 100n 10V F246 1V0_ST 330R USB_VDD_1V0 C801 100p 50V F270 C VDD_AF_2V5 C797 100p 50V 10u 10V 1k C1156 2V5_ST C730 100n 10V C978 1u 6V3 C732 100n 10V VDD_SATA_OSC_1V0 C794 100p 50V C977 1u 6V3 C733 100n 10V USB_VDD_2V5 C793 100p 50V C976 1u 6V3 C731 100n 10V VDD_SATA_OSC_2V5 C792 100p 50V C993 10u 10V C734 100n 10V VDD_CKGA C798 100p 50V C1154 10u 10V C726 100n 10V VDD_ANA_2V5 C795 100p 50V C974 470u 6V3 C702 100n 10V VDD_S_LMI_2V6 C767 10n 16V C973 470u 6V3 C704 100n 10V VDD_V_LMI_2V6 C765 10n 16V C1153 10u 10V C719 100n 10V C717 100n 10V F269 1V0_ST 1k F268 2V5_ST 1k F267 2V5_ST 1k F273 D 1V0_ST 1k F262 2V5_ST 1k F239 2V6_ST 330R 330R E VDDE3V3_11 VDDE3V3_12 VDDE3V3_13 VDDE3V3_14 VDDE3V3_15 VDDE3V3_16 VDDE3V3_17 VDDE3V3_18 VDDE3V3_19 VDDE3V3_20 TMDSVDDE3V3 USBVDDB3V3 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 AUD_GNDA AUD_GNDAS DGNDPLL80V0 FS0_GNDA FS0_GNDD GND_ANA_1 GND_ANA_2 8 U160 STI7101YWC F276 2V5_ST 1k 2V6 8V TP227 TP228 TP273 TP249 TP238 TP226 F277 1k C1152 10u 10V C713 100n 10V C804 100p 50V VDD_CKGB C803 100p 50V C720 100n 10V 1 1 1 1 1 1 2V6_ST VDDM VDD_DMC VDD_DMQ VDD_S_LMI_2V6 VDD_V_LMI_2V6 F252 1V0_ST 60R F C782 220u 6V3 F242 C709 100n 10V C716 100n 10V C777 10n 16V C715 100n 10V VDD_1V0 C780 10n 16V 2V5 TP248 TP247 TP255 TP252 TP256 TP258 TP277 TP246 F241 3V3_VCC 330R C788 220u 6V3 C1155 100n 10V B C D C772 10n 16V E C706 100n 10V C771 10n 16V C705 100n 10V VDD_3V3 C774 10n 16V 1 1 1 1 1 1 1 1 2V5_ST VDD_CKG_2V5 VDD_AF_2V5 VDD_ANA_2V5 VDD_SATA_OSC_2V5 USB_VDD_2V5 2V5A_FE 2V5_QAM 3V3 TP198 TP276 TP275 TP225 TP232 TP231 TP266 TP230 TP229 TP235 TP234 TP236 1 1 1 1 1 1 1 1 1 1 1 1 3V3_VCC AVDD_AU AVDD_USB 3V3_HDMI VDD_3V3 3V3_ETH 3V3A_USB 3V3D_FE 3V3_QAM VCC_F 3V3_CI 3V3D_USB TP143 8V_VCC 1 TP242 TP142 5V_STBY TP202 1 1 VDDC 1V26_STBY 5V_STBY 3V3_STBY TP239 TP240 TP144 12V TP201 12V_VCC 1 1 VDDP AVDD_33 3V3_STBY 1V0 TP260 TP259 TP243 TP257 TP244 TP279 TP278 TP237 TP253 TP254 USB_VDD_1V0 VDD_CKGA VDD_CKGB VDD_SATA_OSC_1V0 VDD_1V0 1V0D_FE1 1V0A_FE1 1V_QAM S_LMI_DLL_VDD V_LMI_DLL_VDD F 5V TP197 TP241 TP274 TP233 TP158 1 1 1 1 1 5V_VCC 5V_CI 5V_SPDIF 5V_AV 5V_TUN VESTEL PROJECT NAME : 17mb37 2 3 4 5 6 7 A3 SHEET:17 OF:18 SCH NAME :STi7101 POWER DRAWN BY :HUSEYIN E. CETIN 1 P13 P14 P15 P16 P19 P20 P21 P22 R14 R15 R16 R19 R20 R21 T15 T16 T17 T18 T19 T20 U15 U16 U17 U18 U19 U20 V15 V16 V17 V18 V19 V20 W15 W16 W17 W18 W19 W20 Y14 Y15 Y16 Y19 Y20 Y21 AA13 AA14 AA15 AA16 AA19 AA20 AA21 AA22 AB13 AB14 AB15 AB20 AB21 AB22 AK29 AK30 AK31 AL31 AM22 AN26 AN32 AP26 AP32 1V26_STBY VDD_CKG_2V5 C808 100p 50V 1V0_ST GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 N22 N21 N20 N15 N14 N13 H3 AP6 AP4 AN6 AN4 AL5 AL4 AK5 AK4 AM6 AM4 AJ3 AH3 AG3 AF3 AE3 AD3 T3 R5 R4 R3 P3 N3 M3 L3 K3 J3 E23 D23 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 B24 A24 U31 V30 AK32 AJ32 AH32 AG34 AG33 AG32 D32 AP23 AL23 V33 U32 P32 N32 V32 V34 N33 N34 R32 AP28 AM27 AN28 AL27 AM28 C12 G3 J32 K32 F32 E32 F31 F30 C32 H31 L32 J31 M31 F240 2V6_ST AK24 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AP7 AN8 W30 AL24 F4 F5 G4 N16 N17 N18 N19 P17 P18 R13 R17 R18 R22 T13 T14 T21 T22 U13 U14 U21 U22 V13 V14 V21 V22 W13 W14 W21 W22 Y13 Y17 Y18 Y22 AA17 AA18 AB16 AB17 AB18 AB19 AF30 AK16 AL16 AM16 AM17 AM18 AM19 AN16 AP16 A30 B30 K31 C31 G31 D27 M32 GND_7 GND_6 GND_5 GND_4 GND_3 GND_2 GND_1 GNDE_49 GNDE_48 GNDE_47 GNDE_46 GNDE_45 GNDE_44 GNDE_43 GNDE_42 GNDE_41 GNDE_40 GNDE_39 GNDE_38 GNDE_37 GNDE_36 GNDE_35 GNDE_34 GNDE_33 GNDE_32 GNDE_31 GNDE_30 GNDE_29 GNDE_28 GNDE_27 GNDE_26 GNDE_25 GNDE_24 GNDE_23 GNDE_22 GNDE_21 GNDE_20 GNDE_19 GNDE_18 GNDE_17 GNDE_16 GNDE_15 GNDE_14 GNDE_13 GNDE_12 GNDE_11 GNDE_10 GNDE_9 GNDE_8 GNDE_7 GNDE_6 GNDE_5 GNDE_4 GNDE_3 GNDE_2 GNDE_1 AGNDPLL80V0 USBVSSP USBVSSBS TMDSVSSX TMDSVSSSL TMDSVSSP TMDSVSSD TMDSVSSCK TMDSVSSC2 TMDSVSSC1 TMDSVSSC0 TMDSGNDE SATAVSST SATAVSSREF SATAVSSR SATAVSSOSC SATAVSSDLL LMIVIDDLL_VSS LMISYSDLL_VSS GNDE_VID_ANA GNDE_PLL80_ANA GNDE_FS0_ANA GNDE_AUD_ANA GNDE_4FS_ANA DA_SD_0_GNDA DA_HD_0_GNDA CKGB_4FS1_GNDD CKGB_4FS1_GNDA CKGB_4FS0_GNDD CKGB_4FS0_GNDA VDD_3V3 VDDE3V3_10 VDDE3V3_9 VDDE3V3_8 VDDE3V3_7 VDDE3V3_6 VDDE3V3_5 VDDE3V3_4 VDDE3V3_3 VDDE3V3_2 VDDE3V3_1 VDDE2V5_VID_ANA VDDE2V5_PLL80_ANA VDDE2V5_FS0_ANA VDDE2V5_AUD_ANA VDDE2V5_4FS_ANA VDDE2V5_5 VDDE2V5_4 VDDE2V5_3 VDDE2V5_2 VDDE2V5_1 USBVSSP2V5 USBVSSC2V5 USBVDDP2V5 USBVDDBC2V5 SATAVDDOSC2V5 CKGB_4FS1_VCCA CKGB_4FS0_VCCA CKGA_PLL2_AVDDPLL2V5 CKGA_PLL2_AGNDPLL2V5 CKGA_PLL1_AVDDPLL2V5 CKGA_PLL1_AGNDPLL2V5 CKGA_PLL_VDDE2V5 AVDDPLL80V0 AUD_VCCA FS0_VCCA DA_SD_0_VCCA DA_HD_0_VCCA LMIVIDVDDE2V5_10 LMIVIDVDDE2V5_9 LMIVIDVDDE2V5_8 LMIVIDVDDE2V5_7 LMIVIDVDDE2V5_6 LMIVIDVDDE2V5_5 LMIVIDVDDE2V5_4 LMIVIDVDDE2V5_3 LMIVIDVDDE2V5_2 LMIVIDVDDE2V5_1 LMISYSVDDE2V5_11 LMISYSVDDE2V5_10 LMISYSVDDE2V5_9 LMISYSVDDE2V5_8 LMISYSVDDE2V5_7 LMISYSVDDE2V5_6 LMISYSVDDE2V5_5 LMISYSVDDE2V5_4 LMISYSVDDE2V5_3 LMISYSVDDE2V5_2 LMISYSVDDE2V5_1 USBVDDP USBVDDBS TMDSVDDX TMDSVDDSL TMDSVDDP TMDSVDDD TMDSVDDCK TMDSVDDC2 TMDSVDDC1 TMDSVDDC0 TMDSVDD SATAVDDT[1] SATAVDDT[0] SATAVDDREF SATAVDDR[1] SATAVDDR[0] SATAVDDOSC SATAVDDDLL LMIVIDDLL_VDD LMISYSDLL_VDD FS0_VDDD DVDDPLL80V0 CKGB_4FS1_VDDD CKGB_4FS0_VDDD CKGA_PLL2_DVDDPLL1V0 CKGA_PLL2_DGNDPLL1V0 CKGA_PLL1_DVDDPLL1V0 CKGA_PLL1_DGNDPLL1V0 AK23 AF34 AF33 AF32 AF31 G34 G33 C26 B26 A26 H32 E29 E31 D31 G32 AN7 AM7 AL7 AK7 AK3 AM23 AN23 AN24 AM24 AM26 L30 M30 C2 D2 B1 D1 C3 N30 B29 C29 E30 D30 E12 D12 C13 C10 C9 C8 C7 C6 C5 C4 AC3 AB3 AA5 AA3 Y4 Y3 W3 V3 U3 T2 T1 AP24 AL25 W33 AA32 AC32 AB32 W32 W34 Y32 W31 V31 AP29 AN29 AL30 AL28 AM29 AL26 AL29 A12 H4 G30 K30 H30 J30 E4 E3 F3 D3 A 5 USB_VDD_2V5 VDD_SATA_OSC_2V5 VDD_CKG_2V5 4 VDD_ANA_2V5 VDD_CKG_2V5 VDD_AF_2V5 3 VDD_ANA_2V5 VDD_CKG_2V5 2 VDD_3V3 1 14-10-2009_09:10 8 AX M 1 2 3 4 5 6 7 8 A 3V3_ETH_A 3V3_ETH_A 3V3_ETH R1190 1k R1186 1k R1189 1k R1181 1k R1178 1k 33 RXD4_RX_ER MDIX_DIS 30 TXD4_TX_ER RIP 29 RESET 28 PWR_DWN 27 TX_EN R1170 10R 31 R1132 47R R1133 47R TEST_SE 34 LED_S 35 LED_C 36 LED_L 37 LED_TR 38 LED_R10 39 VDD 40 41 MDIO GNDE2 MDC 42 43 44 45 46 CF2 TX_CLK 54 MII_TX_EN 32 TR1 S230 S229 ETH_TXP ETH_TXN VCCA3 IREF GNDA3 VCCA2 X1 X2 CFG0 GNDA2 64 VCCA1 CFG1 R1188 NC1 R1187 63 GNDA1 GNDA5 24 TXN 23 3 14 6 11 7 10 8 9 1 R1125 75R 22 3V3_ETH_A TXP 21 ETH_TXP GNDA4 20 RXP 19 RXN 18 ETH_RXN VCCA4 17 3V3_ETH_A TX- 3 RX+ 4 GND1 5 GND2 6 RX- 7 GND3 8 GND4 13 12 R1121 75R R1126 75R ETH_TXN NC2 TX+ 2 Place these capacitors close to transformer R1120 75R C S255 VDD2 FDE MDINT 62 MF0 R999 3V3_ETH CRS 61 MF1 MII_MDINT COL MF2 MII_CRS 60 MF3 59 25 ETH_RXN TXD3 MF4 MII_COL GNDE1 S247 C890 58 MII_TXD3 3V3_ETH TXD2 26 15n 50V 57 MII_TXD2 U186 STE100P TXD1 TEST C1005 56 MII_TXD1 C TXD0 15 5 R1134 47R R1131 47R 55 16 2 4 ETH_RESET ETH_RXP MII_TXD0 1 RESET_DVB JK108 53 MII_TX_CLK RXD3 52 RXD2 51 VDD1 GNDE3 RXD1 50 B SCLK 1n 1kV S262 RX_CLK C996 MII_RX_ER 49 RXD0 MII_RX_CLK RX_DV B 47 48 Place these resistors close to STE100P 100n 16V MII_MDIO MII_MDC MII_RXD3 MII_RXD2 MII_RXD1 3V3_ETH MII_RXD0 MII_RX_DV 3V3_ETH A ETH_RXP Ethernet lines must be 100ohm differential pairs 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R1191 R1192 3V3_ETH_A D R1207 220k R1208 5k1 3V3_ETH_A S263 D 3V3_ETH_A 3V3_ETH 4 3 100n 16V C866 10u 6V3 100n 16V C1017 22p 50V C859 3V3_ETH_A 1k 1 2 C1016 22p 50V F278 3V3_VCC 25MHz C1004 X1 R1193 R1194 3V3_ETH R1197 R1198 3V3_ETH R1185 R1195 R1184 3V3_ETH R1179 R1180 R1182 R1196 3V3_ETH E 3V3_ETH 3V3_ETH R1183 R1145 1M E F271 100n 16V C1014 100n 16V C891 10u 6V3 3V3_ETH 1k C998 3V3_VCC F F VESTEL PROJECT NAME : 17mb37 SHEET:18 OF:18 SCH NAME :ETHERNET DRAWN BY :ERTUG BAL 1 2 3 4 5 6 7 A3 14-10-2009_09:10 8 AX M PARTS LIST N o. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C om ponent VE20432333 VE20444080 VE20500505 VE20439864 VE20449329 VE20454403 VE30064829 VE20447336 VE20484013 VE20492338 VE30066607 VE30064217 VE30064503 VE20463632 VE30064154 VE20444098 D escription BACK CVR.AS.22880 SP-BO&DVD&FBT(WO/IP BUTTON FUNCTION MB25 W/ST.BY(HOTST.-BLK FRONT 22890 (B.C.BL/P-V(S)L-SANYO LENS LED 19890 (PEARL SILVER/P) LENS LED 19890 MILKY%30(I) CN.A.FFC 30P/300 P=1MM LVDS(22"MB25 TFT LCD 216W LG LC220WXE TBA1 RoHS MD.ASY.17LD104-19-22890 (MB25)BLUE CHS.ASSY.17MB37-52K12315372211115B6 MD.ASY.17IPS15-4-22"(MB25)(AVUSTRALYA) HCN DL08DIVX G1WO\USBMMCSAFE-ROHS (N.Hw) 5P/200 FLT W/C UL2468AWG26 ROHS CNAS 12P/350 SHL W/DC DVD UL2464#26 ROHS SPK.AS.19820/2/850(16/9(DVD(R/L)(MB37)BL CNAS 20P/100 SIS W/DC UL1007AWG24RoHS REMOTE CONTROL PART LIST EXPLANATION 1. VE20432333 BACK COVER 2. VE20444080 BUTTON FUNCTION Button Function 3. VE20500505 FRONT 22890 (B.C.BL/P-V(S)L-SANYO 4. VE20439864 LENS LED 19890 (PEARL SILVER/P) 5. VE20449329 LENS LED 19890 MILKY%30(I) 6. VE20454403 CABLE FFC 30P/300 P=1MM LVDS(22"MB25 7. VE30064829 TFT LCD VE20454403 CABLE 8. VE20447336 MD.ASY.17LD104-19-22890 (MB25)BLUE 9. VE20484013 CHASSIS 10. VE20492338 POWER SUPPLY IPS BOARD 11. VE30066607 DVD LOADER LVDS 12. VE30064217 CNAS 5P/200 FLT W/C UL2468AWG26 ROHS. The cable from led board to chassis (fix C119 position in chassis) 13. VE30064503 CNAS 12P/350 SHL W/DC DVD UL2464#26 ROHS. The cable from DVD to chassis (fix C143 position in chassis) 14. VE20463632 Double Speaker.This code also includes the Speaker cable from speaker to Chassis and this cable should be fixed CN115 position on chassis side. 15. VE30064154 CNAS 20P/100 SIS W/DC UL1007AWG24RoHS. The cable from Power board to chassis (fix C137 position in chassis) June/2008