Download ADMC401 Single-Chip, DSP-Based High

ADMC401
PWMCHA (R/W)
PWMCHB (R/W)
PWMCHC (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DM (0x200C)
DM (0x200D)
DM (0x200E)
PWMTM (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DM (0x2008)
PWMDT (R/W)
DM (0x2009)
PWMPD (R/W)
DM (0x200A)
PWMGATE (R/W)
1 = ENABLE
0 = DISABLE
DM (0x200B)
LOW-SIDE CHOPPING
GDCLK
HIGH-SIDE CHOPPING
PWMSEG (R/W)
1 = ENABLE
0 = DISABLE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DM (0x200F)
AH/AL CROSSOVER
CH ENABLE
BH/BL CROSSOVER
CL ENABLE
CH/CL CROSSOVER
BH ENABLE
BL ENABLE
1 = DISABLE
0 = ENABLE
AH ENABLE
AL ENABLE
PWMSYNCWT (R/W)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DM (0x2060)
PWMSWT (R/W)
DM (0x2061)
Figure 36. Structure of Registers of ADMC401
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
–48–
REV. B