Download MPC7400 Part Number Specification

™
Freescale Semiconductor, Inc.
MPC7400_K PNS 000626
Motorola Part Numbers Affected:
XPC7400RX400PK
XPC7400RX450PK
XPC7400RX500PK
Application-Specific Information
C.
N
This document describes part number specific changes to recommended operating conditions and revised
, I electrical specifications,
R
as applicable, from those described in the general MPC7400 Hardware Specifications.
O
THardware
C
Specifications provided in this Part Number Specification supersede those in the MPC7400
Specifications dated 9/99
Uherein are unchanged.
(order #: MPC7400EC/D) for these part numbers only; specifications not addressed
This document is
D
N
frequently updated, refer to the website at http://www.mot.com/SPS/PowerPC/ for
the latest version.
O
ICnumbered. They are intended to correspond to the
Note that headings and table numbers in this data sheet are not consecutively
M
heading or table affected in the general hardware specification.
SE
E
Part numbers addressed in this document are listed in Table A. For
AL more detailed ordering information see Table B.
C
Table A. Part Numbers
S Addressed by this Data Sheet
E
Operating Conditions
RE
Motorola Part Number
Significant Differences from Hardware Specification
F
CPU Frequency Y
Vdd
T (°C)
XPC7400RX400PK
400 MHz B
2.15V±50mV
0 to 65 Modified Voltage & Temperature Specification to achieve 400Mhz
D
frequency
E
V MHz
XPC7400RX450PK
450
2.15V±50mV
0 to 65 Modified Voltage & Temperature Specification to achieve 450Mhz
I
frequency
H
XPC7400RX500PKRC
500 MHz
2.15V±50mV
0 to 65 Modified Voltage & Temperature Specification to achieve 500Mhz
frequency
A
J
Note: The X prefix in a Motorola PowerPC part number designates a “Pilot Production Prototype” as defined by Motorola SOP 3-13.
These are from a limited production volume of prototypes manufactured, tested and Q.A. inspected on a qualified technology to
simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production
prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the
qualification status and the fact that product changes may still occur while shipping pilot production prototypes
Errata
This section summarizes design defects or errors (errata) that are known to exist for these parts. There may be additional errata that
are not known or are not yet documented here which may cause the part to deviate from the functional description provided in the
MPC7400 RISC Microprocessor User’s Manual (order # MPC7400UM/AD Rev 0). Refer to the website at http://www.mot.com/
SPS/PowerPC/ for the latest version of this Part Number Specification or to your local Motorola sales office for later and/or more
detailed description of the errata.
The known errata as of the date of this document are summarized below.
#
Problem
Description
1
Incorrect value was
written to the MSR after
running POR ABIST
When running ABIST after POR,
the renames remained valid causing MSR to be updated with the
incorrect value.
Impact
Running ABIST after
POR
Work-Around
Insert an ISYNC
instruction at the
interrupt vector
0xFFF0_0100
The PowerPC name and the PowerPC logotyp are trademarks of International Business Machines Corporation used by Motorola under license from
International Business Machines Corporation.
This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice.
© Motorola Inc. 1999. All rights reserved.
For More Information On This Product,
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PID7v-603e Apple-Only Data Sheet
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MPC7400 Part Number Specification
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
#
Problem
Description
Impact
2
Not all GPRs and FPRs
are initialized after
ABIST
Not all GPRs and FPRs are initialized after ABIST due to
invalid instructions in the instruction buffers.
GPRs and FPRs may
not be initialized during
ABIST if the contents of
the instruction buffers
can be decoded to nonzero GPR or FPR destination addresses.
None
3
Asserting TEA and
ARTRY together may
cause loss of data
Asserting TEA and ARTRY
together in the first cycle of the
snoop response window may
cause loss of iside data.
Any system that permits
the aggressive timing of
TEA in the first cycle of
the snoop response window.
Delay assertion of TEA
until the second cycle of
the snoop response window or later.
Any system which
allows 6 outstanding
transactions from a single processor and which
has a secondary bus
with characteristics as
detailed in full description.
1. Limit the number of
outstanding transactions from a secondary
bus to 5 in system logic,
or
2. Mark the memory
space on the secondary
bus as guarded and
avoid DST(ST)(T) and
LMW instructions.
4
Incorrect condition code
on mismatched
LWARX/STWCX pair
5
TLBSYNC may hang in
the presence of a DST
Work-Around
C
IN
.
R,
O
T
A STWCX instruction may be
Any code which usesC 1. Avoid mismatched
U
performed without setting the
mismatched LWARX/
LWARX/STWCX
D
N
condition code if the store hits in STWCX address
pairs
address pairs, or
the L2 and the LWARX instruc2. Turn off the L2
CO
I
tion that set the reservation is to
M
another coherency granule.
SE
E
The MPC7400 may not make
Any system which has
Insert a DSSALL
AL
forward progress if aC
DST has
an active DST engine
instruction before a
S
caused an
while executing a TLB- TLBSYNC instruction
E
E that MMU
MMU tablewalk,
SYNC instruction in a
FR
tablewalk
was marked by a
privileged context
Y instruction, and a TLBTLBIE
B
SYNC instruction is pipelined
ED the cycle after the MMU tableV
I
walk
6
CH
R
A
Queueing six transac-
accesses the dL1 cache.
tions to secondary bus
may hang the system
Queueing six transactions from a
single MAX processor could use
all Data Transaction Queue
resources and hang the system if
forward progress cannot be made
by allowing MAX to complete at
least one outstanding transaction.
1.2 General
This section summarizes changes to the features of the MPC7400 described in the MPC7400 Hardware Specifications.
•
None.
1.4.1 DC Electrical Characteristics
Table 3 provides the recommended operating conditions for the MPC7400 part numbers described herein.
Table 3. Recommended Operating Conditions
Characteristic
2
Symbol
Recommended Value
Core supply voltage
Vdd
2.15V±50mV
PLL supply voltage
AVdd
2.15V±50mV
L2 DLL supply voltage
L2AVdd
2.15V±50mV
Unit
MPC7400 Part Number Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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Table 3. Recommended Operating Conditions (Continued)
Characteristic
Processor bus supply voltage
L2 bus supply voltage
Freescale Semiconductor, Inc...
Input voltage
Symbol
Recommended Value
Unit
BVSEL = 0
OVdd
1.8V±100mV
V
BVSEL = HRESET
OVdd
2.5V±100mV
V
BVSEL = 1
OVdd
3.3V±165mV
V
L2VSEL = 0
L2OVdd
1.8V±100mV
V
L2VSEL = HRESET
L2OVdd
2.5V±100mV
L2VSEL = 1
L2OVdd
Processor bus
Vin
L2 Bus
Vin
JTAG Signals
Vin
Die-junction temperature
Tj
LE
A
SC
R,
GND toO
OVdd
CT
U
GND to L2OVdd
ND
3.3V±165mV
S
O
IC
EM
C
IN
.
V
V
V
V
GND to OVdd
V
0-65
°C
Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
E
Table 7 provides the power consumption for the MPC7400
RE part at the frequencies described herein.
F
Table 7. Power Consumption for MPC7400
BY
ED Processor
V
(CPU)
I
Frequency
Processor
(CPU)
Frequency
Processor
(CPU)
Frequency
400Mhz
450Mhz
500Mhz
Typical
7.56
8.51
9.45
W
1, 3
Maximum
15.1
17.0
18.9
W
1, 2, 4
6.7
7.5
8.3
W
1, 2
2.7
3.0
3.3
W
1, 2
2.7
3.0
3.3
W
1, 2
Typical
600
600
600
mW
1, 3
Maximum
1.0
1.0
1.0
W
1, 2
CH
R
A
Unit
Notes
Full-On Mode
Doze Mode
Maximum
Nap Mode
Maximum
Sleep Mode
Maximum
Sleep Mode—PLL and DLL Disabled
Notes:
See General hardware specification
4. These values are with Altivec. Without Altivec, estimate a 25% decrease.
1.4.2.1 Clock AC Specifications
Table 8 provides the additional clock AC timing specifications described in this Part Number Specification. Refer to the MPC7400
MPC7400 Part Number Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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3
Freescale Semiconductor, Inc.
Hardware Specification for the remaining frequencies.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 3)
400 MHz
Characteristic
500MHz
Unit
Min
Freescale Semiconductor, Inc...
450 MHz
Symbol
Max
Min
Max
Min
Processor frequency
fcore
350
400
350
450
350
500
MHz
VCO frequency
fVCO
700
800
700
900
700
1000
MHz
SYSCLK frequency
fSYSCLK
33
100
33
100
33
100
SYSCLK cycle time
tSYSCLK
10
30
SYSCLK rise and fall time
tKR & tKF
1.0
—
0.5
40
60
SYSCLK jitter
—
±150
Internal PLL relock time
—
100
SYSCLK duty cycle measured
at OVdd/2
tKHKL/tSYSCLK
—
Notes:
See General hardware specification.
EE
1.4.2.2 Processor Bus AC Specifications
R
F
LE
A
SC
30
10
C.
1
ns
2
ns
3
%
4
ps
5
µs
6
MHz
IN
,
—
1.0
—
1.0
OR0.5
—
0.5
—T
C
U
40
60
40
60
D
N
O
—
±150
IC±150 —
M
—E
100
—
100
S
10
Notes
Max
30
ns
Table 9 provides the processor bus AC timingYspecifications for the MPC7400 part described in this Part Number Specification.
B
TableD9. Processor Bus AC Timing Specifications1
VE
I
CH
R
A
At Vdd=AVdd=2.15V±50mV; 0 ≤ Tj ≤ 65°C, OVdd = 3.3V±165mV or OVdd = 2.5V±100mV or OVdd=1.8V±100mV
Parameter
400, 450, 500
Mhz
Symbol
Unit
Min
Max
Mode select input setup to HRESET
tMVRH
8
—
tsysclk
HRESET to mode select input hold
tMXRH
0
—
ns
2,3,5
ns
1.4
1.4
1.4
1.4
1.4
—
—
—
—
—
10
6
—
7
—
8
ns
0
0
0
0
0
—
—
—
—
—
11
6
—
7
—
8
—
—
—
—
—
—
3.0
3.0
3.5
3.5
2.3
3.0
0.75
0.75
0.6
0.75
0.75
—
—
—
—
—
Setup Times:
Address/Transfer Attribute
Transfer Start (TS)
Data/Data Parity
ARTRY/SHD0/SHD1
All Other Inputs
tAVKH
tTSVKH
tDVKH
tARVKH
tIVKH
Input Hold Times:
Address/Transfer Attribute
Transfer Start (TS)
Data/Data Parity
ARTRY/SHD0/SHD1
All Other Inputs
tAXKH
tTSXKH
tDXKH
tARXKH
tIXKH
Valid Times:
Address/Transfer Attribute
TS, ABB, DBB
Data
Data Parity
ARTRY/SHD0/SHD1
All Other Outputs
tKHAV
tKHTSV
tKHDV
tKHDPV
tKHARV
tKHOV
Output Hold Times:
Address/Transfer Attribute
TS, ABB, DBB
Data/Data Parity
ARTRY/SHD0/SHD1
All Other Outputs
4
Notes
tKHAX
tKHTSX
tKHDX
tKHARX
tKHOX
2,3,4,5
ns
12
6
—
7
7
—
9
ns
13
6
—
7
—
9
MPC7400 Part Number Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 9. Processor Bus AC Timing Specifications1 (Continued)
At Vdd=AVdd=2.15V±50mV; 0 ≤ Tj ≤ 65°C, OVdd = 3.3V±165mV or OVdd = 2.5V±100mV or OVdd=1.8V±100mV
400, 450, 500
Mhz
Freescale Semiconductor, Inc...
Parameter
Symbol
Unit
Min
Max
0.5
—
SYSCLK to Output Enable
tKHOE
SYSCLK to Output High Impedance (all except
TS, ABB/AMON(0), ARTRY/SHD, DBB/
DMON(0)
tKHOZ
SYSCLK to TS, ABB/AMON(0), DBB/DMON(0)
High Impedance after precharge
tKHABPZ
—
Maximum Delay to ARTRY/SHD0/SHD1
Precharge
tKHARP
—
SYSCLK to ARTRY/SHD0/SHD1 High
Impedance After Precharge
tKHARPZ
—
S
Notes
ns
3.5
14
ns
15
NC
I4,15,
.
R, 16,17
O
1
4,17
CtT
U
ND
1.0
tsysclk
sysclk
— O
IC
EM
2
tsysclk
4,17
Notes:
1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O
Supply Power (OVdd and L2OVdd) or PLL/DLL supply power (AVdd and L2AVdd). OVdd and
L2OVdd power is system dependent, but is typically <10% of Vdd power. Worst case power
consumption for AVdd = 15 mw and L2AVdd = 15 mW.
2. Maximum power is measured at Vdd = 2.2V while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, including AltiVec, maximally busy.
3. Typical power is an average value measured at Vdd = AVdd = L2AVdd = 2.15V, OVdd = L2OVdd =
3.3V in a system while running a codec application that is AltiVec intensive.
EE
R
F
LE
A
SC
BY
D
1.4.2.3 L2 Clock AC Specifications
VE
I
Table 10 provides the L2CLK H
COutput AC Timing Specifications for the MPC7400 part described in this Part Number Specification.
R
A
Table 10. L2CLK Output AC Timing Specifications
At recommended operating conditions (See Table 3)
400 MHz
Parameter
450 MHz
500 MHz
Symbol
Unit
Min
Max
Min
Max
Min
L2CLK frequency
fL2CLK
150
400
150
450
150
500
MHz
L2CLK cycle time
tL2CLK
2.5
6.67
2.22
6.67
2.0
6.67
ns
L2CLK duty cycle
tCHCL/tL2CLK
Internal DLL-relock time
DLL capture window
50
640
50
—
±200
640
50
—
Notes
Max
640
±200
1
%
2
—
L2CLK
4
±200
ns
5
Notes:
See General hardware specification.
MPC7400 Part Number Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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5
Freescale Semiconductor, Inc.
1.4.2.4 L2 Bus AC Specifications
Table 11 provides the L2 Bus Interface AC Timing Specifications for the frequencies described in this Part Number Specification.
Table 11. L2 Bus Interface AC Timing Specifications
At Vdd=AVdd=L2AVdd= 2.15V±50mV; 0 ≤ Tj ≤ 65°C, L2OVdd = 3.3V±165mV or L2OVdd = 2.5V±100mV or L2OVdd=1.8V±100mV
400 MHz
Parameter
450 MHz
500 MHz
Symbol
Min
Max
Min
Max
Min
Max
tL2CR & tL2CF
—
1.0
—
1.0
—
1.0
Data and parity
tDVL2CH
1.5
—
1.3
—
1.0
C
IN—
Data and parity
tDXL2CH
—
Valid Times:
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOV
L2SYNC_IN rise and fall time
Setup Times:
Freescale Semiconductor, Inc...
Input Hold Times:
-E
Output Hold Times
tL2CHOX
All outputs when L2CR[14-15] = 00
EE
All outputs when L2CR[14-15] = 01
R
F
All outputs when L2CR[14-15] = 10 Y
B
All outputs when L2CR[14-15] = 11
D
E
V
L2SYNC_IN to high impedance:
HI = 00
All outputs when L2CR[14-15]
C
All outputs when L2CR[14-15]
= 01
AR
All outputs when L2CR[14-15] = 10
AL
C
S
R,
O
0.0
—
0.0
CT —
U
ND
O
2.5
2.4
C
3.0 I M E
3.5
-
S 4.0
.
Notes
ns
1
ns
2
ns
2
ns
3,4
ns
3
0.0
-
-
-
2.3
-
0.4
1.0
1.4
1.8
-
0.3
-
-
0.2
-
-
-
2.0
2.5
3.0
3.5
-
2.0
2.5
3.0
3.5
-
2.0
2.5
3.0
3.5
ns
tL2CHOZ
All outputs when L2CR[14-15] = 11
Unit
Notes: See General Hardware Specification
1.10 Ordering Information
Table B provides the ordering information for the MPC7400 part described in this Part Number Specification..
Table B. Ordering Information for the MPC7400 Microprocessor
Package Type
360
CBGA
Device
Rev
Process
Mask Code
CPU
Frequency
(MHz)
Motorola
Part Number
2.9
HIP5P
89J87W
or
89K62D
400MHz
450MHz
500MHz
XPC7400RX400PK
XPC7400RX450PK
XPC7400RX500PK
1.10.1 Part Marking
Parts are marked as the example shown in Figure A.
6
MPC7400 Part Number Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
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XPC7400
RX500PK
MMMMMM
ATWLYYWWA
7400
BGA
Freescale Semiconductor, Inc...
Notes:
R,
O
CT
U
ND
C
IN
.
MMMMMM is the 6-digit mask number
ATWLYYWWA is the traceability code
CCCCC is the country of assembly (this space is left blank if parts are assembled in the United States)
O
IC
M
Figure A. Motorola Part Marking
for BGA Device
SE
LE
A
SC
E
E
FR
BY
D
VE
I
CH
R
A
MPC7400 Part Number Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
For More Information On This Product,
Go to: www.freescale.com
7
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
CH
R
A
ED
V
I
BY
EE
R
F
LE
A
SC
S
O
IC
EM
R,
O
CT
U
ND
C
IN
.
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted
hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated
for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application
in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages,
and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
IBM is a registered trademark of International Business Machines Corporation.
The PowerPC name and the PowerPC logotype are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines
Corporation. International Business Machines Corporation is an Equal Opportunity/Affirmative Action Employer.
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