Download C505 C505 C

On-Chip Peripheral Components
C505C Only
The bit time is determined by the C505C clock period CLP (see AC characteristics), the Baud Rate
Prescaler, and the number of time quanta per bit:
bit time
= tSync-Seg + tTSeg1 + tTSeg2
tSync-Seg
= 1 × tq
tTSeg1
= ( TSEG1 + 1 ) × tq
(= min. 4 × tq)
tTSeg2
= ( TSEG2 + 1 ) × tq
(= min. 3 × tq)
tq
= (BRP + 1) × 2(1 - CMOD) × CLP
TSEG1, TSEG2, and BRP are the programmed numerical values from the respective fields of the
Bit Timing Register and the bit CMOD in the SYSCON register (bit 3).
Semiconductor Group
6-91
1997-08-01