Download Packet Telephony Development Kit PSTN Card User`s Guide

Freescale Semiconductor
User’s Guide
PTKITPSTNUG
Rev. 1, 9/2005
Packet Telephony Development Kit
PSTN Card
The public switched telephone network (PSTN) card in the
Packet Telephony Development Kit (PDK) connects directly to
the PDK baseboard and provides four narrow-band T1/E1 timedivision multiplexing (TDM) ports that interface to the PSTN
network. The PSTN subsystem also supports four analog
telephony ports for direct interface to standard analog voice
terminals. It provides a TDM stream for the DSP array (that is,
MSC810xPFC card). Figure 1 shows a snapshot of the PSTN
card hardware.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
CONTENTS
1
2
3
3.1
3.2
3.3
3.4
4
5
6
7
Packet Telephony Development Kit .......................3
Getting Started With the PSTN Card ......................4
PSTN Card Components .........................................4
Time Slot Switch .....................................................5
Digital E1/T1 Interface ...........................................9
PLL Synchronization Module ...............................12
Complex Programmable Logic Device (CLPD) ...14
PSTN Card LEDs and Jumpers .............................16
Power Connector ...................................................17
PSTN Card Interface .............................................17
Default TDM Interface Timing .............................21
CLPD JTAG Power Connector
POTS
1
2
3
4
T1/E1
1
2
3
4
Figure 1. PSTN Hardware Overview
The PSTN card architecture consists of five main functional blocks, as shown in Figure 2:
•
Time slot switch. 3.3 V time slot interchange (TSI) digital switch (IDT72V70800).
•
Digital E1/T1 interface. Quad E1/T1/J1 framer and line interface component for long haul and short
haul applications (PEB22554 V1.3).
•
PLL synchronization module. WAN PLL with single-reference input (IDT82V30001A).
•
Complex programmable logic device (CPLD). A low power 3.3V 32 macro-cell device (XCR3032XL)
used for PLL control, reset, and chip-select management.
•
Plain Old Telephone Service (POTS). Two dual-channel subscriber line interfaces (PEB3264/-2) for
analog telephone access.
Packet Telephony Development Kit PSTN Card, Rev. 1
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Freescale Semiconductor
Packet Telephony Development Kit
Serial Peripheral
Interface (SPI)
Analog
POTS
Lines
Analog
POTS
Reset
Time
Slot
Switch
(IDF70800)
Microprocessor
Bus
CPLD
ChipSelect
Digital
E1/T1
Interface
T1/E1 Lines
Pulse Code
Modulation (PCM) Bus
PCM System
Configuration
PLL Synchronization Module
IDT-82V3001A
Figure 2. PSTN Card Architecture
1
Packet Telephony Development Kit
The Packet Telephony Development kit (PDK) is a platform for evaluating and developing voiceover packet
applications. The PDK has an MPC8260 host network processor that runs Linus, StarCore™ DSP resource cards
that run DSP code, and a Public Switched Telephone Network (PSTN) card with interfaces such as E1/T1 and
analog telephone lines (see Figure 3).
Telephone
Network
Managed
Packet
Network
MPC8260
Control
Processor
Ethernet
PSTN
StarCore DSP
Resource
Daughtercard
Baseboard
Figure 3. Components of the Packet Telephony Development Kit (PTK)
The documentation for the kit components is as listed in Table 1.
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
3
Getting Started With the PSTN Card
Table 1. PTK Components and Their Associated Documents
Component
Document
Document ID
Baseboard
Packet Development Kit Baseboard Hardware User’s Guide
PTKITBASEUG
MPC8260 Control
Processor
MPC8260 PowerQUICC II™ Family Reference Manual
(Available at the website listed on the back page of this document.)
MPC8260UM
PSTN Card
Packet Development Kit PSTN Card User’s Guide
PTKITPSTNUG
StarCore DSP
Resource Daughtercard
• MSC8102 Packet Telephony Farm Card (MSC8102PFC) User’s Guide
• MSC8101 Packet Telephony Farm Card (MSC8101PFC) User’s Guide
PTKIT8101UG
PTKIT8102UG
StarCore DSP
Resource
Reference manuals and other documentation for the MSC81xx products are
located at the website listed on the back page of this user’s guide.
Software
Packet Telephony Development Kit Software User’s Guide
CAUTION:
2
PTKITSOFTUG
The Packet Telephony Development Kit includes open-construction printed circuit boards that
contain static-sensitive components. These boards are subject to damage from electrostatic
discharge (ESD). To prevent such damage, you must use static-safe work surfaces and grounding
straps, as defined in ANSI/EOS/ESD S6.1 and ANSI/EOS/ESD S4.1. All handling of these boards
must be in accordance with ANSI/EAI 625.
Getting Started With the PSTN Card
This section presents unpacking instructions, hardware preparation, and installation instructions for bringing-up the
PSTN card.
First, unpack the equipment from the shipping carton. Refer to the packing list and verify that all items are present.
Save the packing material for storing and reshipping the equipment. If the shipping carton is damaged upon receipt,
request the carrier’s agent to be present during unpacking and inspection of equipment.
Most systems have a PSTN card already attached to the baseboard. If you have purchased a PSTN card separately,
you must plug it in. The PSTN card cannot operate as a stand-alone unit. The procedure for bringing up the PSTN
is as follows:
3
1.
Ensure that the PDK baseboard power supply is turned OFF.
2.
Ensure that the stands off are connected to the PSTN card.
3.
Gently connect the PSTN card PTMC connectors to the PDK baseboard.
4.
Twist and tighten the PSTN card stands off to baseboard.
5.
Ensure that the PSTN card is properly placed on top of the PDK baseboard.
6.
If you plan to use the analog telephones, connect the J17 power connector (see Section 5, Power Connector, on page 17).
7.
Turn on the power supply.
PSTN Card Components
This section discusses the main components of the PSTN card, which are the time slot switch, the digital E1/T1
interface, the PLL synchronization module, and the complex programmable logic device.
Packet Telephony Development Kit PSTN Card, Rev. 1
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Freescale Semiconductor
PSTN Card Components
3.1 Time Slot Switch
The TSI performs time slot switching to set up and tear down voice connections between communicating entities.
IDT-72V70800 is a 4-port switch that is dedicated to switch pulse code modulation (PCM) data between any two
ports during call control. It is a non-blocking digital switch that has a capacity of 512 × 512 channels at a serial bit
rate of 8.192 Mb/s. Figure 4 shows an overview of the TSI module. Key features of the IDT-72V70800 TSI switch
include:
•
64-kbit/s PCM channel switching.
•
Freely programmable streams and time slot control.
•
Data rate of 8.192 Mb/s equivalents to 128 PCM channels per port.
•
Transmit to receive channel loop-back for diagnostics.
•
Microprocessor control mode.
•
High impedance output control.
VCC GND RESET
Loopback
TX0
RX0
Receive
Serial
Data
Streams
RX1
RX2
Output
Multiplex
Data Memory
RX3
Internal
Registers
Connection
Memory
TX1
TX2
TX3
Microprocessor Interface
Timing Unit
CLK FOi
Transmit
Serial
Data
Streams
FE/ WFPS
HCLK
AS/ IM DS/ CS R/W/ A[0–7]DTA D[8–15]/
RD
ALE
WR
AD[0–7]
Figure 4. TSI Module
In the PSTN card, the TSI connects to the codec, Duslic (analog part of the PSTN card), QUADFALC (digital part
of the PSTN card), and CPLD. Figure 5 shows an overview of all PSTN modules that connect to the TSI. Table 2
shows how the TSI connects the TDM streams.
Table 2. TSI Connections
TSI Stream
Connects to
0
Baseboard connector
1
E1/T1 PSTN card interface
3
Plain Old Telephone Service (POTS) Analog Telephony PSTN card interface
4
Baseboard connector
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
5
PSTN Card Components
Duslic
RJ11
Serial Bus
SLIC
Infineon
Codec
PCM2
PCM2
(Infineon)
RJ11
PCM3
SLIC
Infineon
Switch
512 × 512
Duslic
RJ11
SLIC
Infineon
(IDT)
Codec
(Infineon)
RJ11
Microprocessor Bus
SLIC
Infineon
RJ45
T1/E1
RJ45
T1/E1
PCM0
QUADFALC
PCM1
PCM0
(Infineon)
RJ45
T1/E1
RCLK1
T1/E1
IDT_CSA
Microprocessor Bus
RJ45
CPLD
8 KHz
(Xilinx)
WAN
PLL
16.384 MHz
(IDT)
4.096 MHz
Microprocessor Bus
8.192 MHz
Figure 5. TSI Connections with Other PSTN Card Modules
The TSI is part of the PDK memory map. The MPC8260 device, which resides in the PDK baseboard, can access
the TSI via chip select 9. Refer to Table 3 andTable 4 for TSI Base and Option Register settings, as well as UPM
programming (MPC8260 memory controller programming to access the TSI).
Table 3. TSI Option and Base registers
Registers
Values
BR9 (TSI Base Register)
0xF8010C1
OR9 (TSI Option Register)
0xFFFF8106
Packet Telephony Development Kit PSTN Card, Rev. 1
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Freescale Semiconductor
PSTN Card Components
Table 4. Initializing the TSI
Operations
Instructions
Single Read
MCMR = 0x10008800
MDR = 0x8FFFF000
MDR = 0x0FFCF380
MDR = 0x0FFCF300
MDR = 0x0FFCF300
MDR = 0x0FFCF300
MDR = 0x0FFCF380
MDR = 0x0FFCF004
MDR = 0x1FFFF001
Single Write
MCMR = 0x10008818
MDR = 0x0FF3F300
MDR = 0x0FF0F380
MDR =0x0FF0F300
MDR = 0x0FF0F300
MDR = 0x0FF0F380
MDR = 0x0FF0F004
MDR = 0x0FF0F300
MDR = 0x3FF3F001
Exception
MCMR=0x1000883C
MDR = 0xFFFFCC05,
MDR = 0xFFFFFFFF
MDR = 0xFFFFFFFF
MDR = 0xFFFFFFFF
Run
MCMR = 0x00008800
3.1.1 Duslic Module
The analog PSTN interface supports four loop start telephone subscriber ports. The Infineon Dual-Channel
Subscriber Line Interface Concept (Duslic) PEB-3265 and PEB-4265 devices on the card form the interface
between the TDM interface to the TSI and the physical twisted copper pair. There are four RJ-11 physical
connectors on the PSTN card, as shown in Figure 6.
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
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PSTN Card Components
Duslic
RJ11
Serial Bus
SLIC
Infineon
Codec
(Infineon)
RJ11
PCM2
PCM2
PCM3
SLIC
Infineon
Switch
512 × 512
Duslic
RJ11
SLIC
Infineon
Codec
(IDT)
(Infineon)
RJ11
SLIC
Microprocessor Bus
Infineon
Figure 6. Duslic Connections to other Sub-modules of the PSTN Card
The Duslic requires that reset be applied when all the external clocks are stable. The CPLD ensures that the Duslic
reset signal is asserted only after the clocks generated by the PLL device are stable, approximately 300 ns or longer
after the PLL device undergoes reset.
The Duslic performs all the line interface functions generally known in the industry as the BORSCHT functions, as
follows:
1.
Battery feed [B]. Represents the voltage and current required to power the telephone equipment connected to the line. Battery voltage of –48 to –24 volts is fed directly into the Duslic devices from the
PDK power supply
2.
Over voltage protection [O]. Protects the PDK from damage to accidental exposure to high voltage,
such as those resulting from lightning
3.
Ringing [R]. The high voltage low frequency signal activated to ring the telephone equipment. Two
programmable ringing modes are supported: balanced ringing where ringing voltage is applied differentially between tip and ring and unbalance ringing in which the ringing voltage is applied singleended to either tip or ring. The ringing voltage of +30 to +60 volts is fed directly into the Duslic
devices from the PDK power supply.
4.
Signaling or Supervision [S]. Detects ON-hook and OFF-hook states for the telephone equipment connected to the line. ON/OFF hook can be detected while a station is ringing, which is referred to as Ring
Trip Detection, or it may can detected while the station is not ringing, which is referred to as Switch
Hook Detection.
5.
Coding [C]. Converts the analog signals into PCM and vice versa. Two software configurable standard
conversion algorithms are supported: A-law and µ-law. The default coding for the PDK is µ-law. The
reset value for Duslic is A-law can be programmed to µ-law by changing bit 7 of register BCR3.
6.
Hybrid 2-to-4-wire conversions [H]. A special network balancing circuit performs this function to
match the line impedance so echo generation can be avoided. Hybrid balancing is a Duslic programmable option.
7.
Testing [T]. Allows access to the loop so that regular diagnostic tests can be performed, including: loop
resistance measurement, line capacitance, leakage current, ringing voltage, line feed current, and transversal and longitudinal current.
Packet Telephony Development Kit PSTN Card, Rev. 1
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PSTN Card Components
3.1.2 Duslic Configuration and Operation
The Duslic devices are configured directly by the baseboard host processor through the SPI interface. Specific
values are written to Duslic registers to configure, for example, a given line into a specific mode of operation.
Refer to the Duslic user’s manual for detains on the functions of all registers supported.
During normal operation, specific Duslic registers must be read to determine the signaling exchanged between the
subscriber telephone set and the PDK. Dynamic conditions that are constantly monitored by the host processor and
appropriate action taken include ON-hook/OFF-hook signaling and DTMF signaling. The host processor can also
command the Duslic through the SPI interface to generate ringing voltage or tones such as dial tone, busy tone, and
reorder or fast busy tone.
3.2 Digital E1/T1 Interface
The digital E1/T1 interface supports four E1/T1 ports that can connect to central office (CO) lines such as ISDN
PRI or PBX trunks. The Infineon QUADFALC FEB-22554 device forms the interface between the TDM interface
to the TSI and the physical twisted copper pair. The QUADFALC recovers the PCM signal on the copper pairs and
multiplexes them on the TDM bus to the TSI switch. There are four RJ-45 physical connectors on the PSTN card
(see Figure 7). Each of the four digital interfaces of the QUADFALC includes a framer and a Line Interface Unit
(LIU), a PLL circuit for clock recovery, an HDLC controller for signaling, and an 8-bit microprocessor interface
for configuration.
PCM2
PCM2
PCM3
Switch
512 × 512
RJ45
T1/E1
RJ45
T1/E1
Microprocessor Bus
(IDT)
PCM0
QUADFALC
PCM1
PCM0
(Infineon)
T1/E1
RJ45
T1/E1
RCLK1
RJ45
IDT_CSA
Microprocessor Bus
8 KHz
CPLD
(Xilinx)
WAN
PLL
16.384 MHz
(IDT)
4.096 MHz
Microprocessor Bus
8.192 MHz
Figure 7. QUADFALC Connecting to Other Sub-modules of the PSTN Card
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
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PSTN Card Components
3.2.1 QUADFALC Clocking Options
The QUADFALC clocking configuration and the WAN-PLL device-clocking configuration jointly determine the
timing mode. Two timing modes are supported: master and slave clocking. The combination of master or slave
options provides maximum flexibility for telecommunications equipment developers using the PSTN card. In
master clocking mode, the QUADFALC derives its timing from its local free running 16.384 MHz free running
clock, as shown in Figure 8. The derived clock is either 1.544 MHz for T1 operation in North America or 2.048
MHz for E1 operation in Europe. This derived clock becomes the timing reference for the WAN-PLL device,
which generates all the system clocks, including the PCM clocks for the PDK.
T1/E1
T1/E1
PEB-22554
QUADFALC
T1/E1
F-ref (To WAN-PLL Device)
RCLK1
T1/E1
1.544/2.048 MHz
MCLK
16.384 MHz
XTAL Osc 20 ppm
(Sync Source)
Figure 8. QUADFALC Master Clocking Mode Configuration
In slave clocking mode, the QUADFALC derives its timing reference from one of the four T1/E1 line terminated
directly on the QUADFALC device as illustrated inFigure 9. The 1.544 MHz or 2.048 MHz derived clock is fed
into the WAN-PLL device, which generates the system PCM clocks. Clocking for the QUADFALC is supplied
through the MCLK pin; for the PDK this clock has a frequency of 16.384 MHz.
Packet Telephony Development Kit PSTN Card, Rev. 1
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Freescale Semiconductor
PSTN Card Components
T1/E1
PEB-22554
QUADFALC
T1/E1
T1/E1
F-ref (To WAN-PLL Device)
RCLK1
T1/E1
1.544/2.048 MHz
MCLK
16.384 MHz
XTAL Osc
(20 ppm)
Figure 9. QUADFALC Slave Clocking Mode Configuration
3.2.2 QUADFALC Default Operating Mode
The QUADFALC is part of the PDK memory map, and the MPC8260 device, which resides in the PDK baseboard,
can access the QUADFALC via chip select 8. Refer to Table 5 and Table 6 for QUADFALC Base and Option
Register values, as well as UPM programming
Table 5. QUADFALC Option and Base Registers
Registers
Values
BR8 (QUADFALC Base Register)
0xF70008A1
OR8 (QUADFALC Option Register)
0xFFFF8106
Table 6. QUADFALC UPM Programming
Operations
Instructions
Single Read
MBMR = 0x10015400
MDR = 0x8FFFF000
MDR = 0x0FFCF300
MDR = 0x0FFCF300
MDR = 0x0FFCF004
MDR = 0x0FFFF300
MDR = 0x0FFFF300
MDR = 0x3FFFF001
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
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PSTN Card Components
Table 6. QUADFALC UPM Programming (Continued)
Operations
Instructions
Single Write
MBMR = 0x10015418
MDR = 0x0FF3F000
MDR = 0x0FF0F300
MDR = 0x0FF0F300
MDR = 0x0FF0F004
MDR = 0x0FF3F300
MDR = 0x0FF3F300
MDR = 0x3FF3F001
Exception
MBMR=0x1001543C
MDR= 0xFFFFCC05,
Run
MBMR=0x00015400
3.3 PLL Synchronization Module
The IDT-82V3001 PLL device generates timing (clock) and synchronization (framing) signals for the PCM bus.
The IDT82V3001A is a WAN PLL with single reference input. It contains a Digital Phase-Lock Loop (DPLL),
which generates clock and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz, or 8 kHz input
reference. The PLL circuitry generates all TDM synchronization clocks used in the PDK, including the PCM
interface clocks. These clocks can either be generated locally (via the QUADFALC device) if the PDK is operating
in Master mode or be derived from any one of the T1/E1 lines by the QUADFALC if the PDK is operating in Slave
mode. The two relevant modes of operation for the IDT82V3001 are Free Run mode and Normal mode.
3.3.1 Free Run Mode
In Free Run mode, the PLL device uses its local clock (as opposed to the reference frequency) to synthesize the
system clock. The Free Run clocking mode for IDT-82V3001 is not used; only the Normal clocking mode is used,
as described in the following section.
3.3.2 Normal Mode
When the PLL device is configured in Normal mode, the frequency reference is received from the QUADFALC, as
illustrated in Figure 10. The timing reference fed into the PLL device is derived from one of the T1/E1 lines. In
this case, the second line is used as the timing reference source. However, any of the four digital lines terminated
on the PSTN card can be used as the timing reference source. This is a QUADFALC software configuration
feature.
Packet Telephony Development Kit PSTN Card, Rev. 1
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Freescale Semiconductor
PSTN Card Components
SCLKR1
T1/E1
SCLKX
XPA1
T1/E1
PEB-22554
QUADFALC
T1/E1
RCLK1
T1/E1
F-ref
1.544/2.048 MHz
C8
8.192M
F8
8K
PCM
System
Bus
MCLK
IDT82V3001
Sync
16.384 MHz
XTAL Osc
(20 ppm)
C4
4.096M
C16
16.384M
IDT
TSI
Switch
Figure 10. WAN-PLL Device in Support of Slave Clocking Mode
To operate the PLL device in Normal mode, the Mode_sel_0 signal must be set to 0, and the Mode_sel_1 signal must
be set to 0 through the CPLD, as shown in Table 7. To complete the PLL configuration, the input reference
frequency into the PLL must also be selected. In this case, the PRI frequency is 1.544 MHz in North America or
2.048 MHz in Europe. Frequency selection of 1.544 MHz (North America) is achieved by setting Freq_sel_0 = 0
and Freq_sel_1 = 1 via the CPLD. For Europe, the values are Freq_sel_0 = 1 and Freq_sel_1 = 1 via the CPLD.
Table 7. ID72V3001 Normal Mode Configuration
Mode Select
Frequency Select
Comment
mode_sel_1
mode_sel_0
Freq_sel_1
Freq_sel_0
0
0
1
0
North America
0
0
1
1
Europe
If the PDK is operating in Master clocking mode, the frequency reference is generated locally by the QUADFALC
and fed directly into the PLL device. Software can configure the QUADFALC to source a free running clock from
it local 16.384 MHz oscillator fed through the MCLK pin. This clock has a stability of 20 ppm, as illustrated in
Figure 11.
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
13
PSTN Card Components
SCLKR1
T1/E1
SCLKX
XPA1
T1/E1
PEB-22554
QUADFALC
T1/E1
RCLK1
T1/E1
F-ref
C8
1.544/2.048 MHz
8.192 MHz PCM
8 KHz
F8
System
Bus
MCLK
IDT82V3001
Sync
16.384 MHz
C4
XTAL Osc
(20 ppm)
C16
4.096 MHz IDT
16.384 MHz
TSI
Switch
Figure 11. WAN-PLL in support of Master Clocking Mode
The default clocking option for the PDK is Master synchronization as illustrated in Figure 11. The default
reference clock fed into the PLL device from the QUADFALC is 1.544 MHz, representing the North American
digital transmission line standard.
3.4 Complex Programmable Logic Device (CLPD)
The glue logic to help control access and configuration of all devices on the PSTN card is implemented on a CPLD.
The CPLD decodes the addresses to generate the chip select for the TSI device and the control signals for the PLL
device. The CPLD also monitors the PLL device and generates the Loss of Synchronization signal for the operation
status indicator or LED.
3.4.1 Chip-Select Logic
The CPLD uses address line 22 to select between assertion of the IDT time-slot switch and accesses to its own
internal registers, as shown in Table 8.
Table 8. Chip-Select Truth Table
PQ2_CS_TDM2
Chip Select Input
From the Baseboard
CONN_AD22
Address Line Input
From the Baseboard
IDT Time Slot Switch
Chip Select
Internal CPLD Chip
Select
1
X
1
1
0
0
0
1
0
1
1
0
Packet Telephony Development Kit PSTN Card, Rev. 1
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Freescale Semiconductor
PSTN Card Components
3.4.2 Output Signals
Writes to the memory-mapped registers control the output signals on the CPLD. Table 9 lists and describes the
registers. The address column refers to the address from which to write over the bus A[22–31]. The physical address
pins to the CPLD are only A[22–30]. The data bus bit is latched on to the output signal. Thus, to turn off the LED,
for example, one would write a value of 0x01 to address 0x20E. The physical address lines CONN_AD[22–30] would
be 100000111 and the 1 from D[15] would be latched causing the PLD_LOS_FALC signal to go high.
Table 9. CPLD Memory Map
Data Bus
Bit
Read/
Write
Default
Value
PLD_MODE_SEL0
D[14]
R/W
0
PLD_MODE_SEL1
D[15]
R/W
0
PLD_F_SEL0
D[14]
R/W
1
PLD_F_SEL1
D[15]
R/W
1
0x204
NORMAL_PLD
D[15]
R
—
Goes high when the WAN PLL goes into
Normal mode.
0x206
LOCK_PLD
D[15]
R
—
Goes high when the WAN PLL is locked to the
input reference frequency.
0x208
PLD_TCLRn
D[15]
R/W
1
Logic low at this signal resets the TIE control
block of the WAN PLL, resulting in a
realignment of the output phase with the input
phase.
0x20A
PLD_TIE_en
D[15]
R/W
1
Logic high at this signal enables the TIE block
of the WAN PLL.
0x20C
PLD_DUSLIC_TSI_RST
n
D[15]
R/W
1
Logic low at this signal resets the DuSLIC (U1
& U2) and TSI switch.
0x20E
PLD_LOS_FALC
D[15]
R/W
1
Logic low at this signal lights an LED.
0x210
HOLDOVER_PLD
D[15]
R
—
Goes to a logic high when the WAN PLL goes
to Holdover mode.
0x212
PLD_WAN_PLL_RSTn
D[15]
R/W
1
Logic low at this signal resets the WAN PLL.
Address
0x200
0x202
Output Signal Name
Description
Determine the state (Normal, Holdover, or
Free Run) of the WAN PLL.
Determine the input reference frequency of the
WAN PLL.
3.4.3 JTAG
The J16 header is used for programming the CPLD. The PSTN card comes programmed and use of this header
should not be needed.
1RWH 'RQRWUHFRQILJXUHWKH;LOLQ[FKLSLQWKH3671FDUG$WWHPSWVWRGRVRPD\OHDGWRLQVWDELOLW\LQ
WKHV\VWHP
Table 10. Xilinx JTAG Signals
Pin
JTAG Signal
1
+5V
2
GND
3
NC
4
TCK
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
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PSTN Card LEDs and Jumpers
Table 10. Xilinx JTAG Signals (Continued)
Pin
JTAG Signal
5
NC
6
TDO
7
TDI
8
NC
9
TMS
The only module that connects to the baseboard JTAG chain is the QUADFALC. PTMC connector J15 enables the
JTAG chain between the baseboard and the PSTN card.
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PSTN Card LEDs and Jumpers
This section describes the LEDs and jumpers of the PSTN card.
Table 11. PSTN Card LEDs
LED
Description
1
Indicates the Hook Status of the analog subscriber line 1 (P1.B1). LED1 is controlled by the port IO1B of the
PEB3265 It can be programmed to show the ON/OFF hook status for the corresponding subscriber line.
2
Indicates the Hook Status of the analog subscriber line 2 (P1.B1). LED2 is controlled by the port IO1A of the
PEB3265 It can be programmed to show the ON/OFF hook status for the corresponding subscriber line.
3
Indicates the Hook Status of the analog subscriber line 3 (P1.D1). LED3 is controlled by the port IO1B of the
PEB3265 It can be programmed to show the ON/OFF hook status for the corresponding subscriber line.
4
Indicates the Hook Status of the analog subscriber line 4 (P1.C1). LED4 is controlled by the port IO1A of the
PEB3265 It can be programmed to show the ON/OFF hook status for the corresponding subscriber line.
5
Shows the Loss Of Signal/Synchronization status of the QUADFALC device. It connects to a GPIO (pin no. 23) of the
CPLD. It is illuminated when the processor determines the Loss of Signal status after reading the Frame Receive
Status Register 0 (FRS0) of the QUADFALC.
6
3.3V power indication on PSTN. It is illuminated when 3.3V power rail is active.
7
5V power indication on PSTN card. It is illuminated to indicate that the 3.3V voltage is available on the board.
8
VHR (Ringing Voltage) power indication on PSTN card. It is illuminated to indicate ringing voltage is available.
9
VBATHX (Battery Voltage) power indication on PSTN. It is illuminated to indicate that the battery or line voltage is
available on the board.
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Packet Telephony Development Kit PSTN Card, Rev. 1
16
Freescale Semiconductor
Power Connector
Table 12 summarizes all jumper settings in the PSTN card. Jumper settings are verified before they are shipped to
customers.
Table 12. Jumper Settings
Jumper
Default Setting
Switches between T1 and E1 termination.
Shunt pins 1–2: E1.
Shunt pins 2–3: T1.
T1 (Pins 2–3 connected)
Selects source of +3.3V power supply.
Shunt pins 1–2: Power comes from power connector J17.
Shunt pins 2–3: Power comes from the baseboard
Baseboard power (Pins 2–3 connected)
J18
Selects source of +5V power supply.
Shunt pins 1–2: Power comes from power connector J17.
Shunt pins 2–3: Power comes from the baseboard.
Baseboard power (Pins 2–3 connected)
J19
Selects source of VHR (Ringing) power supply.
Shunt pins 1-2: Power comes from power connector J17.
Shunt pins 2-3: Power comes from the baseboard.
Baseboard power (Pins 2–3 connected)
J20
J1–J11
5
Meaning
Power Connector
Table 13 lists all power supplies used in the PSTN card from J17. The 48 V battery supply must be sourced
through this connector. All other supplies can come either from the baseboard or through J17 by using jumpers
J18–J20.
Table 13. PSTN Card Power Supply Distribution
Pin
Description
3.3 V
I/O power. By default, the 3.3 V power comes from the
baseboard. See Table 12.
+5 V
5 V power. By default, the 5 V power comes from the
baseboard. See Table 12.
3
+48 V
Ringing voltage for telephones.
4
–48 V
Battery supply for telephones.
5
GND
6
GND
1
2
6
Value
PSTN Card Interface
The baseboard and the PSTN card share common signals, such as address, data, and control lines. The signals
travel through PTMC connectors that connect the PDK baseboard to the PSTN card, as shown in Figure 12.
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
17
PSTN Card Interface
P13
P15
P14
Figure 12. Baseboard PTMC Connected
Table 14. PTMC 15 Header
Pin
Signal
Pin
Signal
1
TDM_SPI_CS1
2
JTAG_TRST
3
JTAG_TMS
4
TDM_TDO
5
TDM_TDI
6
GND
7
GND
8
JTAG_TCK
9
CONN_D0
10
CONN_AD23
11
CONN_D1
12
Vcc (5.0 v)
13
TDM_RESET
14
CONN_AD24
15
Vcc (5.0 v)
16
CONN_AD25
17
CONN_D2
18
GND
19
CONN_D3
20
CONN_AD26
21
GND
22
CONN_AD27
23
CONN_D4
24
Vcc (3.3 v)
25
CONN_D5
26
CONN_AD28
27
Vcc (3.3 v)
28
CONN_AD29
29
CONN_D6
30
GND
31
CONN_D7
32
CONN_AD30
33
GND
34
CONN_AD31
35
CONN_D8
36
Vcc (3.3 v)
37
GND
38
TDM_TO_PQ2_INT1
39
CONN_D9
40
GND
41
Vcc (3.3 v)
42
PQ2_CS_TDM1
43
CONN_D10
44
GND
45
CONN_D11
46
TDM_GPL2
Packet Telephony Development Kit PSTN Card, Rev. 1
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Freescale Semiconductor
PSTN Card Interface
Table 14. PTMC 15 Header (Continued)
Pin
Signal
Pin
Signal
47
GND
48
TDM_GPL1
49
CONN_D12
50
Vcc (3.3 v)
51
CONN_D13
52
PQ2_CS_TDM2
53
Vcc (3.3 v)
54
TDM_SPI_CS0
55
CONN_D14
56
GND
57
CONN_D15
58
TDM_SPIMOSO
59
GND
60
TDM_SPIMOSI
61
CONN_AD22
62
Vcc (3.3 v)
63
GND
64
TDM_SPICLK
Table 15. PTMC 14 Header
Pin
Signal
Pin
Signal
1
NC
2
GND
3
GND
4
VCC (5.0 V)
5
NC
6
NC
7
VCC (5.0 V)
8
GND
9
NC
10
VCC (5.0 V)
11
VCC (5.0 V)
12
NC
13
NC
14
GND
15
GND
16
NC
17
CT_FRAME_A
18
VCC (5.0 V)
19
NC
20
GND
21
NC
22
NC
23
NC
24
VCC (5.0 V)
25
CT_C8_A
26
GND
27
GND
28
NC
29
NC
30
NC
31
NC
32
GND
33
GND
34
NC
35
NC
36
VCC (5.0 V)
37
NC
38
GND
39
NC
40
NC
41
NC
42
VCC (5.0 V)
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
19
PSTN Card Interface
Table 15. PTMC 14 Header (Continued)
Pin
Signal
Pin
Signal
43
NC
44
GND
45
GND
46
NC
47
NC
48
NC
49
NC
50
NC
51
GND
52
NC
53
NC
54
NC
55
CT_D4
56
GND
57
VCC (5.0 V)
58
CT_D5
59
NC
60
NC
61
CT_D0
62
GND
63
GND
64
CT_D1
Table 16. PTMC 13 Header
Pin
Signal
Pin
Signal
1
NC
2
NC
3
GND
4
NC
5
NC
6
NC
7
NC
8
VCC (5.0 V)
9
NC
10
NC
11
GND
12
NC
13
NC
14
GND
15
GND
16
NC
17
NC
18
VCC (5.0 V)
19
VCC (3.3 V)
20
NC
21
NC
22
NC
23
NC
24
GND
25
GND
26
NC
27
NC
28
NC
29
NC
30
VCC (5.0 V)
31
NC
32
NC
33
NC
34
GND
35
GND
36
NC
37
NC
38
VCC (5.0 V)
Packet Telephony Development Kit PSTN Card, Rev. 1
20
Freescale Semiconductor
Default TDM Interface Timing
Table 16. PTMC 13 Header (Continued)
7
Pin
Signal
Pin
Signal
39
GND
40
NC
41
NC
42
NC
43
NC
44
GND
45
VCC (3.3 V)
46
NC
47
NC
48
NC
49
NC
50
VCC (5.0 V)
51
GND
52
NC
53
NC
54
NC
55
TDM_GPIO2
56
GND
57
VCC (3.3 V)
58
TDM_TO_PQ2_INT2
59
TDM_GPIO1
60
TDM_TO_PQ2_INT3
61
TDM_GPIO0
62
VCC (5.0 V)
63
GND
64
NC
Default TDM Interface Timing
Figure 13 diagrams the PSTN default TDM interface to the DSP daughter card. The default is 128 channels per
frame, 8 bits per channel. This yields 8.192 Mbps with an 8 K Hz frame synchronization signal.
122.0 ns
(8.192
MHz)
CT_C8_A (Clock)
FRAME_A (Frame)
125 µ s
(8 KHz)
122 ns
10.8 ns
CT_D0 (Rx Data)
Bit 1
Bit 2
Bit 3
Bit 4
22.8 ns
CT_D1 (Tx Data)
Bit 1
Bit 2
Bit 3
Bit 4
Figure 13. PSTN Card Default TDM Interface
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
21
Default TDM Interface Timing
Appendix A CPLD Source
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--declaration of INPUT and OUTPUT ports
entity pdk_cpld is
Port (
PQ2_CS_TDM2
CONN_AD22
CONN_AD
: in std_logic;
: in std_logic;
: in std_logic_vector(27
to 30);
CONN_D13
: out std_logic;
CONN_D14
: in std_logic;
CONN_D15
: in std_logic;
TDM_GPL1
: in std_logic;
TDM_GPL2
: in std_logic;
HOLDOVER_PLD
: in std_logic;
LOCK_PLD
: in std_logic;
NORMAL_PLD
: in std_logic;
CT_C8_A
: in std_logic;
TDM_RESET
: in std_logic;
CT_FRAME
: in std_logic;
CT_STFRAMEn
: in std_logic;
CT_WFRAMEn
: in std_logic;
PLD_MODE_SEL0
: out std_logic;
PLD_MODE_SEL1
: out std_logic;
PLD_F_SEL0
: out std_logic;
PLD_F_SEL1
: out std_logic;
PLD_TCLRn
: out std_logic;
PLD_TIE_en
: out std_logic;
PLD_DuSLIC_TSI_RSTn : out std_logic;
PLD_WAN_PLL_RSTn : out std_logic;
PLD_LOS_FALC
: out std_logic;
PLD_IDT_CSn
: out std_logic;
CT_FRAME_A
: out std_logic;
PLD_QFALC_FRAME : out std_logic);
end pdk_cpld;
architecture pdk_cpld of pdk_cpld is
signal signal_main_dec: std_logic;-- internal signal whic enables address decoder
signal signal_cpld_dec: std_logic_vector( 11 downto 0 ); -- internal signals which are out from address
decoder
signal signal_r_w_bar : std_logic;
signal signal_w_bar
:std_logic;
signal signal_r :std_logic;
signal sel_mux1: std_logic_vector(1 downto 0); -- select signals to select frame sync for Base card
connectors
signal sel_mux2: std_logic_vector(1 downto 0); -- select signals to select frame sync for QuadFALC
(optional)
begin
-- two bit decoder which selects IDT switch or address decoder of CPLD.
process(PQ2_CS_TDM2,CONN_AD22)
begin
-- the selection between IDT switch and cpld address decoder is done depending
-- upon status of PQ2_CS_TDM2 and CONN_AD22 .If PQ2_CS_TDM2 is 0 the selection
-- between IDT switch and CPLD address decoder is done based on CONN_AD22,
-- if CONN_AD22 is 0 then IDT switch is selected or if CONN_AD22 is 1 then
-- CPLD address decoder is selected, else if PQ2_CS_TDM2 = 1 then both
-- IDT switch and CPLD address decoder will be disabled.
if ( PQ2_CS_TDM2 = ’0’ and CONN_AD22 =’0’)then
PLD_IDT_CSn <= ’0’;
signal_main_dec <= ’1’;
elsif ( PQ2_CS_TDM2 = ’0’ and CONN_AD22 = ’1’)then
PLD_IDT_CSn <= ’1’;
signal_main_dec <= ’0’;
else
Packet Telephony Development Kit PSTN Card, Rev. 1
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Freescale Semiconductor
Default TDM Interface Timing
PLD_IDT_CSn <= ’1’;
signal_main_dec <= ’1’;
end if;
end process;
--end of two bit decoder
--Following process is to implement the CPLD address decoder,which will be
--enabled by output signal "signal_main_dec" of two bit decoder.
--Inputs for this decoder are AD[27:30] ,out put will be nine enable signals
--for internal latchs.
process(signal_main_dec,CONN_AD)
begin
if ( signal_main_dec = ’0’) then
case CONN_AD is
when "0000" => signal_cpld_dec <= "111111111110";
when "0001" => signal_cpld_dec <= "111111111101";
when "0010" => signal_cpld_dec <= "111111111011";
when "0011" => signal_cpld_dec <= "111111110111";
when "0100" => signal_cpld_dec <= "111111101111";
when "0101" => signal_cpld_dec <= "111111011111";
when "0110" => signal_cpld_dec <= "111110111111";
when "0111" => signal_cpld_dec <= "111101111111";
when "1000" => signal_cpld_dec <= "111011111111";
when "1001" => signal_cpld_dec <= "110111111111";
when "1010" => signal_cpld_dec <= "101111111111";
when "1011" => signal_cpld_dec <= "011111111111";
when others => signal_cpld_dec <= "111111111111";
end case;
else
signal_cpld_dec <= "111111111111";
end if;
end process;
--end of CPLD address decoder
------
Following process is to implement the two bit latch for mode select signals
for WAN PLL.
Default mode is NORMAL MODE i.e both signals are 0.
WAN PLL mode can be changed by writing into latch at address
CONN_AD[22:30] = 1XXXX0000 using CONN_D[14:15]
process (signal_cpld_dec(0),TDM_RESET,CONN_D15,CONN_D14,signal_w_bar)
begin
if TDM_RESET =’0’ then
PLD_MODE_SEL0 <= ’0’;
PLD_MODE_SEL1 <= ’0’;
elsif signal_cpld_dec(0) = ’0’
and signal_w_bar = ’0’ then
PLD_MODE_SEL0 <= CONN_D15;
PLD_MODE_SEL1 <= CONN_D14;
end if ;
end process;
------
implementation of two bit latch for Input reference frequency select signals
for WAN PLL.
Default Input reference frequency is 1.544 MHz(T1 mode).
WAN PLL Input reference frequency can be changed by writing into latch
at address CONN_AD[22:30] = 1XXXX0001 using CONN_D[14:15]
process (signal_cpld_dec(1),CONN_D15,CONN_D14,signal_w_bar,TDM_RESET)
begin
if TDM_RESET =’0’ then
PLD_F_SEL0 <= ’0’;
PLD_F_SEL1 <= ’1’;
elsif signal_cpld_dec(1) = ’0’and signal_w_bar = ’0’ then
PLD_F_SEL0 <= CONN_D15;
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
23
Default TDM Interface Timing
PLD_F_SEL1 <= CONN_D14;
end if ;
end process;
-- implementation of status read signal (NORMAL_PLD) of WAN PLL at ADDRESS
-- CONN_AD[22:30] = 1XXXX0010 using CONN_D[15]
process (
signal_r,NORMAL_PLD,HOLDOVER_PLD,LOCK_PLD,signal_cpld_dec(2),signal_cpld_dec(8),signal_cpld_dec(3))
begin
if signal_cpld_dec(2) = ’0’ and
signal_r = ’1’ then
CONN_D13 <= NORMAL_PLD;
-- implementation of status read signal(HOLDOVER_PLD) of WAN PLL at ADDRESS
-- CONN_AD[22:30] = 1XXXX1000 using CONN_D[15]
elsif signal_cpld_dec(8) = ’0’ and
signal_r = ’1’ then
CONN_D13 <= HOLDOVER_PLD;
-- implementation of status read signal(LOCK_PLD) of WAN PLL at ADDRESS
--CONN_AD[22:30] = 1XXXX0011 using CONN_D[15]
elsif signal_cpld_dec(3) = ’0’ and
CONN_D13 <= LOCK_PLD;
else
CONN_D13 <= ’Z’;
end if;
signal_r = ’1’ then
end process;
-- implementation of one bit latch for signal(PLD_TCLRn)of WAN PLL at ADDRESS
-- CONN_AD[22:30] = 1XXXX0100 using CONN_D[15]
-- default PLD_TCLRn <= 1
process (signal_cpld_dec(4),TDM_RESET,CONN_D15,signal_w_bar)
begin
if TDM_RESET =’0’ then
PLD_TCLRn <= ’1’;
elsif signal_cpld_dec(4) = ’0’ and signal_w_bar = ’0’ then
PLD_TCLRn <= CONN_D15 ;
end if ;
end process;
-- implementation of one bit latch for signal(PLD_TIE_en)of WAN PLL at ADDRESS
-- CONN_AD[22:30] = 1XXXX0101 using CONN_D[15]
-- default PLD_TIE_en <= 1
process (signal_cpld_dec(5),TDM_RESET,CONN_D15,signal_w_bar)
begin
if TDM_RESET =’0’ then
PLD_TIE_en <= ’1’;
elsif signal_cpld_dec(5) = ’0’and signal_w_bar = ’0’ then
PLD_TIE_en <= CONN_D15;
end if ;
end process;
-- implementation of one bit latch for signal(PLD_DuSLIC_TSI_RSTn) for DuSLIC and TSI reset
-- ADDRESS CONN_AD[22:30] = 1XXXX0110 using CONN_D[15]
-- default PLD_DuSLIC_TSI_RSTn <= 1
at
process (signal_cpld_dec(6),TDM_RESET, CONN_D15,signal_w_bar)
begin
if TDM_RESET =’0’ then
PLD_DuSLIC_TSI_RSTn <= ’1’;
Packet Telephony Development Kit PSTN Card, Rev. 1
24
Freescale Semiconductor
Default TDM Interface Timing
elsif signal_cpld_dec(6) = ’0’ and signal_w_bar = ’0’then
PLD_DuSLIC_TSI_RSTn <= CONN_D15;
end if ;
end process;
-- implementation of one bit latch for signal(PLD_LOS_FALC) for FALC at
-- ADDRESS CONN_AD[22:30] = 1XXXX0111 using CONN_D[15]
-- default PLD_LOS_FALC <= 1
process (signal_cpld_dec(7),TDM_RESET,CONN_D15,signal_w_bar)
begin
if TDM_RESET =’0’ then
PLD_LOS_FALC <= ’1’;
elsif signal_cpld_dec(7) = ’0’and signal_w_bar = ’0’ then
PLD_LOS_FALC <= CONN_D15;
end if ;
end process;
-- implementation of one bit latch for signal(PLD_WAN_PLL_RSTn) for WAN PLL reset
-- ADDRESS CONN_AD[22:30] = 1XXXX1001 using CONN_D[15]
-- default PLD_WAN_PLL_RSTn <= 1
at
process (signal_cpld_dec(9),TDM_RESET, CONN_D15,signal_w_bar)
begin
if TDM_RESET =’0’ then
PLD_WAN_PLL_RSTn <= ’1’;
elsif signal_cpld_dec(9) = ’0’ and signal_w_bar = ’0’then
PLD_WAN_PLL_RSTn <= CONN_D15;
end if ;
end process;
-- Following process is to implement the two bit internal latch for select signals
-- of MUX1 used to to select frame sync for base card connectors.
-- Default mode is sel_mux1(0) <= ’0’; and sel_mux1(1) <= ’1’; i.e
-- CT_FRAME = CT_FRAME_A (F8o from WAN PLL)
-- MUX1 enable signals can be changed by writing into latch at address
-- CONN_AD[22:30] = 1XXXX1010 using CONN_D[14:15]
process (signal_cpld_dec(10),CONN_D15,CONN_D14,signal_w_bar,TDM_RESET)
begin
if TDM_RESET =’0’ then
sel_mux1(0) <= ’0’;
sel_mux1(1) <= ’1’;
elsif signal_cpld_dec(10) = ’0’and signal_w_bar = ’0’ then
sel_mux1(0) <= CONN_D15;
sel_mux1(1) <= CONN_D14;
end if ;
end process;
-- 4 to 1 multiplexer design with case construct to select frame sync to base card connectors
process (sel_mux1, CT_FRAME, CT_STFRAMEn, CT_WFRAMEn)
begin
case sel_mux1 is
when "00" => CT_FRAME_A <= CT_WFRAMEn;
when "01" => CT_FRAME_A <= CT_STFRAMEn;
when "10" => CT_FRAME_A <= CT_FRAME;
when others => NULL;
end case;
end process;
-- Following process is to implement the two bit internal latch for select signals
-- of MUX2 used to to select frame sync for the QuadFALC (optional).
-- Default mode is sel_mux2(0) <= ’0’; and sel_mux2(1) <= ’1’; i.e
-- PLD_QFALC_FRAME = CT_FRAME_A (F8o from WAN PLL)
-- MUX2 enable signals can be changed by writing into latch at address
-- CONN_AD[22:30] = 1XXXX1011 using CONN_D[14:15]
process (signal_cpld_dec(11),CONN_D15,CONN_D14,signal_w_bar,TDM_RESET)
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
25
Default TDM Interface Timing
begin
if TDM_RESET =’0’ then
sel_mux2(0) <= ’0’;
sel_mux2(1) <= ’1’;
elsif signal_cpld_dec(11) = ’0’and signal_w_bar = ’0’ then
sel_mux2(0) <= CONN_D15;
sel_mux2(1) <= CONN_D14;
end if ;
end process;
-- 4 to 1 multiplexer design with case construct to select frame sync to QuadFALC (optional)
process (sel_mux2, CT_FRAME, CT_STFRAMEn, CT_WFRAMEn)
begin
case sel_mux2 is
when "00" => PLD_QFALC_FRAME <= CT_WFRAMEn;
when "01" => PLD_QFALC_FRAME <= CT_STFRAMEn;
when "10" => PLD_QFALC_FRAME <= CT_FRAME;
when others => NULL;
end case;
end process;
-- internal read write signal generation from TDM_GPL1 and TDM_GPL2
process(TDM_GPL2,TDM_GPL1)
begin
if TDM_GPL2 = ’0’ and TDM_GPL1 = ’0’ then
--signal_r_w_bar <= ’0’;
signal_w_bar
<= ’0’;
signal_r
<= ’0’;
elsif TDM_GPL2 = ’0’ and TDM_GPL1 = ’1’ then
-- signal_r_w_bar <= ’1’;
signal_w_bar
<= ’1’;
signal_r
<= ’1’;
else
signal_w_bar
signal_r
<= ’0’;
<= ’1’;
end if;
end process;
end pdk_cpld;--end of code
Packet Telephony Development Kit PSTN Card, Rev. 1
26
Freescale Semiconductor
Default TDM Interface Timing
Appendix B
Schematics
The following pages present the schematics for the PSTN card, as well as the board that provides power to the
PSTN card.
Packet Telephony Development Kit PSTN Card, Rev. 1
Freescale Semiconductor
27
A
B
C
+5VIN
+5VIN
+3.3V
+3.3V
J1
11
12
13
14
15
16
17
18
19
20
+5VIN
+5VIN
5
+5VIN
PWR_ON
+3.3V
ATX INPUT Tyco 2-794664-0
1
2
3
4
5
6
7
8
9
10
1
2
RESETTABLE FUSE
RGE400
1
U6
2
NMT0572S
V03
8
V02
7
V01
6
0V
5
GND
2
VIN
1
4
NMT0572S
V03
8
V02
7
V01
6
0V
5
GND
2
VIN
1
3
NMT0572S
V02
7
V01
6
0V
5
GND
2
VIN
1
NMT0572S
U5
+48V
+24V
-48V
+5VIN
+3.3V
PWR_ON
2
Packet telelphony
Motorola
Copyright 2001
PDK_POTS_PWR
Rich Cutler
Tuesday, February 10, 2004
Title
Name
Date:
1
1
2
3
4
5
6
7
8
9
10
1
Sheet
Block Schematic
EDGE PADS
J2
of
Rev
1
0.1
Pins 1-5: To PSTN Card
Pins 6-8: To Baseboard
Pins 9-10: To On/OFF Switch
The purpose of this
board is to provide
power to the PSTN
card of the Smart
Packet Telephony
Development Kit.
V03
8
U2
VIN
1
U3
GND
2
U4
2
0V
5
3
V01
6
4
V02
7
D
5
V03
8
A
B
C
D
3
2
1
4
3
2
Title
AURAL NETWORKS
Date:
Size
B
Thursday, June 12, 2003
Document Number
<Doc>
REVISION HISTORY
of
15
Rev
2.0
1
Sheet
1
A
C
A
Frame Sync for BASE BOARD Connectors is provided from CPLD
Brought F8o, F0o/, F16o/ (from WAN PLL) to CPLD.
Provided narrower frame pulse (F16o/ from WAN PLL)
for the TSI to operate in ST-BUS mode.
-->QuadFALC, CPLD
-->WAN PLL
-->TSI, DuSLIC
06/06/2003
18/11/2002
DATE
B
5
Swapping of the SPIMOSI and SPIMOSO signals.
2.0
Three level reset configuration.
Initial Revision.
Change from previous version
1.0
Revision
D
B
C
D
4
Packet Telephony Development Kit
POTS card Rev 2.0
5
A
B
C
5
RJ45
RJ45
RJ45
RJ45
RJ11
RJ11
RJ11
RJ11
SLIC
SLIC
SLIC
T1/E1
T1/E1
T1/E1
T1/E1
(Infineon)
SLIC
(Infineon)
(IDT)
WAN PLL
4.096MHz
8.192MHz
16.384MHz
8KHz
(Infineon)
FALC
Quad
(Infineon)
CODEC
DuSLIC
(Infineon)
(Infineon)
CODEC
DuSLIC
(Infineon)
4
3
PCM3
CPLD
PCM0
3
(Xilinx)
PCM1
(IDT)
SWITCH
512 x 512
PCM2
POTS BLOCK SCHEMATIC
RCLK1
4
IDT_CS#
D
5
uP BUS
uP BUS
PCM0
uP BUS
PCM3
SERIAL BUS
2
2
TO BASEBOARD CONNECTORS
Date:
Size
B
Title
Thursday, June 12, 2003
Document Number
<Doc>
Pots Card Block Schematic
1
Sheet
AURAL NETWORKS
1
2
of
15
Rev
2.0
A
B
C
D
A
B
C
D
DGND
DVDD3V3
L1
5
100mH
5
5
IL_1B
IT_1B
5
5
ACP_1B
ACN_1B
DCP_1B
DCN_1B
C1_1B
C2_1B
5
5
5
5
5
5
VCMS_1
IL_1A
IT_1A
5
5
ACP_1A
ACN_1A
DCP_1A
DCN_1A
C1_1A
C2_1A
47uF
C2
+
5
5
5
5
5
5
0_1uF
C1
AVDD3V3
R6
VCM1
R13
4
C10
C9
680nF_10P_16V
C12
68nF_10P_50V
680nF_10P_16V
680nF_10P_16V
1K6_1P_0W125
C14
C13
DGND
63
60
61
3
62
6
7
2
5
64
1
4
57
56
58
50
52
53
46
51
43
42
47
44
49
48
45
ILB
3
DGND
DGND
TEST
IO4B
IO3B
IO2B
IO1B
IO4A
IO3A
IO2A
IO1A
RSYNC
RESET
DXB
DD/DRB
TCB
DXA
SEL24/DRA
TCA
FSC
DCL/PCLK
MCLK
TS0/DIN
DU/DOUT
TS1/DCLK
TS2/CS
INT
PCM/IOM-2
SELCLK
U1
PEB3265
AVDD3V3 DVDD3V3
3
DGND
VCMITB
ITB
CDCPB
ITACB
ACPB
ACNB
DCPB
DCNB
C1B
C2B
CDCNB
VCM
VCMS
CREF
ILA
ITA
VCMITA
CDCPA
ITACA
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
100nF_10P_50V
C5
680nF_10P_16V
120nF_10P_25V
C11
DGND
C8
120nF_10P_25V
100nF_10P_50V
C4
1K6_1P_0W125
R11
R12
680E_1P_0W125 470E_1P_0W125
VCM1
R2
R3
680E_1P_0W125 470E_1P_0W125
100nF_10P_50V
C3
4
CHANNEL A
CHANNEL B
GNDR
GNDA
35
13
12
11
10
36
37
38
39
33
34
28
20
29
27
21
26
23
19
22
14
18
15
16
17
32
59
R122
10K
R1
1
1
1
1
R8
R7
R5
R4
0E
0E
TP4
TP5
TP1
TP2
0E
0E
0E
DGND
2
2
2
DGND
4,7
4,7
4,14,15
4,9,13,14,15
LED10
LED11
1
1
330E
R139
Date:
Size
B
Title
330E
R140
DVDD3V3
PLD_DuSLIC_TSI_RSTn 4,7,15
RX2
TX2
CT_FRAME
CT_C8_A
LED1
LED2
1
1
DVDD3V3
330E
R10
1
Thursday, June 12, 2003
Document Number
<Doc>
Analog Subscriber Line Interface
1
Sheet
AURAL NETWORKS
Hook status Indicators
2
2
330E
R9
From CPLD
To WAN PLL
From WAN PLL
From WAN PLL
From WAN PLL
TO BASEBOARD
100nF_10P_50V
C7
TDM_SPIMOSI 4,13
TDM_SPIMOSO 4,13
TDM_SPICLK 4,13
TDM_SPI_CS0 13
TDM_TO_PQ2_INT2 13
100nF_10P_50V
C6
2
1
2
54
41
8
VDDR
VDDA
VDDB
55
40
1
2
25
31
GNDD
GNDPLL
24
30
1
2
VDDD
VDDPLL
PCM
GNDB
9
1
2
3
of
15
Rev
2.0
A
B
C
D
A
B
C
D
5
5
ACP_2B
ACN_2B
DCP_2B
DCN_2B
C1_2B
C2_2B
IT_2B
6
6
6
6
6
6
6
IL_2B
VCMS_2
6
IL_2A
6
IT_2A
6
6
ACP_2A
ACN_2A
DCP_2A
DCN_2A
C1_2A
C2_2A
6
6
6
6
6
6
R19
VCM2
R26
680nF_10P_16V
C22
680nF_10P_16V
C26
4
1K6_1P_0W125
680nF_10P_16V
120nF_10P_25V
C24
68nF_10P_50V
C25
DGND
C23
1K6_1P_0W125
R24
R25
680E_1P_0W125 470E_1P_0W125
VCM2
680nF_10P_16V
C21
63
60
61
3
62
6
7
2
5
64
1
4
57
56
58
50
52
53
46
51
43
42
47
44
49
48
45
ILB
VCMITB
ITB
CDCPB
ITACB
ACPB
ACNB
DCPB
DCNB
C1B
C2B
CDCNB
VCM
VCMS
CREF
ILA
ITA
VCMITA
CDCPA
ITACA
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
100nF_10P_50V
C19
DGND
C20
120nF_10P_25V
100nF_10P_50V
100nF_10P_50V
R15
R16
680E_1P_0W125 470E_1P_0W125
C18
C17
4
CHANNEL A
CHANNEL B
AVDD3V3
DGND
DGND
3
DGND
TEST
IO4B
IO3B
IO2B
IO1B
IO4A
IO3A
IO2A
IO1A
RSYNC
RESET
DXB
DD/DRB
TCB
DXA
SEL24/DRA
TCA
FSC
DCL/PCLK
MCLK
TS0/DIN
DU/DOUT
TS1/DCLK
TS2/CS
INT
PCM/IOM-2
SELCLK
U2
PEB3265
DVDD3V3
3
55
40
35
13
12
11
10
36
37
38
39
33
34
28
20
29
27
21
26
23
19
22
14
18
15
16
17
32
59
R123
10K
R14
1
1
1
1
R21
R20
R18
R17
0E
DGND
TP10
TP11
TP7
TP8
0E
0E
0E
0E
DGND
2
2
2
LED12
LED13
1
1
330E
R141
Date:
Size
B
Title
330E
R142
DVDD3V3
1
1
330E
R23
Hook status Indicators
LED3
330E
R22
DVDD3V3
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
AURAL NETWORKS
2
2
LED4
1
100nF_10P_50V
C15
DVDD3V3
Analog Subscriber Line Interface
From CPLD
3,7 To WAN PLL
3,7 From WAN PLL
3,14,15
3,9,13,14,15
From WAN PLL
From WAN PLL
TO BASEBOARD
PLD_DuSLIC_TSI_RSTn 3,7,15
RX2
TX2
CT_FRAME
CT_C8_A
TDM_SPIMOSI 3,13
TDM_SPIMOSO 3,13
TDM_SPICLK 3,13
TDM_SPI_CS1 13
TDM_TO_PQ2_INT3 13
2
1
2
54
41
8
VDDR
VDDA
VDDB
GNDR
GNDA
1
2
25
31
GNDD
GNDPLL
24
30
1
2
VDDD
VDDPLL
PCM
GNDB
9
1
2
4
DGND
of
15
100nF_10P_50V
C16
Rev
2.0
A
B
C
D
C1_1A
C2_1A
IT_1A
IL_1A
3
3
3
3
C1_1B
C2_1B
IT_1B
IL_1B
3
3
3
3
A
VCMS_1
ACN_1B
ACP_1B
DCN_1B
DCP_1B
3
3B
3
3
3
C
VCMS_1
ACN_1A
ACP_1A
DCN_1A
DCP_1A
3
3
3
3
3
D
20
19
18
17
11
12
13
14
15
DGND
5
20
19
18
17
11
12
13
14
15
100nF_10P_50V
C38
DGND
100nF_10P_50V
C27
IT
IL
C1
C2
DGND
AVDD5V
VCMS
ACN
ACP
DCN
DCP
IT
IL
C1
C2
VCMS
ACN
ACP
DCN
DCP
AVDD5V
BGND
3
DGND
VBATL
DGND
TIP
RING
NC
NC
CEXT
DGND
R32
R33
2
1
VHR
4
30E_0P5_0W5
30E_0P5_0W5
470nF_10P_16V
C43
VBATH
16
8
10
DGND
C33
15nF_10P_100V
C46
DGND
15nF_10P_100V
C42
C44
220nF_20P_200V
3
5
8
2
NC
NC
GN
DGND
3
5
8
2
NC
NC
GN
100nF_10P_200V
C41
VBATH
100nF_10P_200V
100nF_10P_200V
DGND
C40
DGND
VBATH
C39
15nF_10P_100V
C35
DGND
15nF_10P_100V
100nF_10P_200V
C30
220nF_20P_200V
100nF_10P_200V
100nF_10P_200V
DGND
C31
C29
C28
4
30E_0P5_0W5
30E_0P5_0W5
R28
R29
2
1
VHR
470nF_10P_16V
C32
VBATH
16
8
U5
PEB4265
DGND
TIP
RING
NC
NC
CEXT
10
U3
PEB4265
VBATL
BGND
5
5
6
7
4
VDD
VBATL
VBATH
VHR
3
1
TIP
6
7
3
GP
6
7
3
U6
LCP02_150B1
SO8_300
GND
GND
GP
20E_1P_0W5
R31
R34
2
20E_1P_0W5
20E_1P_0W5
20E_1P_0W5
2
R30
220nF_20P_200V
C45
DGND
VHR
R27
220nF_20P_200V
C34
DGND
U4
LCP02_150B1
SO8_300
VHR
GND
GND
RING
4
AGND
9
5
6
7
4
VDD
VBATL
VBATH
VHR
AGND
9
1
TIP
RING
4
RING2
TIP2
RING1
TIP1
Date:
Size
B
Title
L3
100mH
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
5
0_1uF
C37
AURAL NETWORKS
CONN_RJ11_4STACK
P1B
DGND
DVDD5V
CONN_RJ11_4STACK
P1A
Analog Subscriber Line Interface
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1
1
of
15
47UF_16V
+ C36
AVDD5V
Rev
2.0
A
B
C
D
C1_2A
C2_2A
IT_2A
IL_2A
4
4
4
4
C1_2B
C2_2B
IT_2B
IL_2B
4
4
4
4
A
VCMS_2
ACN_2B
ACP_2B
DCN_2B
DCP_2B
4B
4
4
4
4
C
VCMS_2
ACN_2A
ACP_2A
DCN_2A
DCP_2A
4
4
4
4
4
D
20
19
18
17
11
12
13
14
15
DGND
5
20
19
18
17
11
12
13
14
15
100nF_10P_50V
C56
DGND
100nF_10P_50V
C47
IT
IL
C1
C2
DGND
AVDD5V
VCMS
ACN
ACP
DCN
DCP
IT
IL
C1
C2
VCMS
ACN
ACP
DCN
DCP
AVDD5V
BGND
3
DGND
TIP
RING
NC
NC
CEXT
DGND
TIP
RING
NC
NC
CEXT
R40
R41
2
1
DGND
DGND
VHR
4
C53
15nF_10P_100V
C64
DGND
15nF_10P_100V
C60
220nF_20P_200V
C62
5
8
2
NC
NC
GN
DGND
3
5
8
2
NC
NC
GN
100nF_10P_200V
C59
VBATH
100nF_10P_200V
DGND
C58
100nF_10P_200V
DGND
VBATH
C57
15nF_10P_100V
C55
DGND
3
100nF_10P_200V
C50
220nF_20P_200V
100nF_10P_200V
C49
15nF_10P_100V
C51
100nF_10P_200V
C48
30E_0P5_0W5
30E_0P5_0W5
470nF_10P_16V
C61
VBATH
16
8
10
U9
PEB4265
VBATL
DGND
2
1
4
30E_0P5_0W5
30E_0P5_0W5
R36
R37
VHR
470nF_10P_16V
C52
VBATH
16
8
10
U7
PEB4265
VBATL
DGND
BGND
5
5
6
7
4
VDD
VBATL
VBATH
VHR
3
1
TIP
6
7
3
GP
6
7
3
U10
LCP02_150B1
GND
GND
GP
U8
LCP02_150B1
GND
GND
RING
4
AGND
9
5
6
7
4
VDD
VBATL
VBATH
VHR
AGND
9
1
TIP
RING
4
R42
2
20E_1P_0W5
20E_1P_0W5
R39
220nF_20P_200V
C63
DGND
VHR
20E_1P_0W5
20E_1P_0W5
R38
220nF_20P_200V
C54
DGND
VHR
R35
2
RING4
TIP4
RING3
TIP3
Date:
Size
B
Title
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
AURAL NETWORKS
CONN_RJ11_4STACK
P1D
CONN_RJ11_4STACK
P1C
Analog Subscriber Line Interface
D6
D5
D4
D3
D2
D1
C6
C5
C4
C3
C2
C1
1
6
of
15
2.0
Rev
A
B
C
D
A
B
C
8,13,15 TDM_GPL1
8,13,15 TDM_GPL2
15 PLD_IDT_CSn
0
1
2
3
PCM
5
DSP
FALC
DuSLIC
BASE CARD
Description
DNP : Do Not Place
NOTE 4 :
WF Mode
-ST_BUS Mode --
Place R127
Place R128
NOTE 1&2 :
Motorola demultiplexed mode
considered
NOTE 3 :
WFPS=1, WFPS Mode
WFPS=0, ST_BUS Mode
TO BASEBOARD CONNECTOR 8,13,15 CONN_D[0:15]
TO BASEBOARD CONNECTOR 8,13,15 CONN_AD[22:31]
TO BASEBOARD CONNECTOR
TO BASEBOARD CONNECTOR
From CPLD
NOTE2
NOTE1
4
33
34
35
36
37
38
39
40
43
44
45
46
47
48
49
50
CONN_D7
CONN_D6
CONN_D5
CONN_D4
CONN_D3
CONN_D2
CONN_D1
CONN_D0
19
20
21
22
23
24
25
26
CONN_D15
CONN_D14
CONN_D13
CONN_D12
CONN_D11
CONN_D10
CONN_D9
CONN_D8
CONN_AD30
CONN_AD29
CONN_AD28
CONN_AD27
CONN_AD26
CONN_AD25
CONN_AD24
CONN_AD23
DGND
28
27
29
31
30
D8
D9
D10
D11
D12
D13
D14
D15
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A0
A1
A2
A3
A4
A5
A6
A7
R/W/WR
DS/RD
CS
IM
AS/ALE
POWER
INT CONN
I
N
T
E
R
F
A
C
E
M
I
C
R
O
P
R
O
C
E
S
S
O
R
DVDD3V3
14
VCC
D
4
64
VCC
RX0
RX1
RX2
RX3
TX0
TX1
TX2
TX3
GROUND
WFPS
FE/HCLK
FOi
CLK
DNC
DNC
DNC
RESET
R
X
T
X
DTA
3
DGND
18
11
10
13
52
16
15
17
2
3
4
5
55
56
57
58
51
54
U11
IDT72V70800
3
ODE
IC
IC
IC
IC
IC
IC
IC
IC
6
7
8
9
59
60
61
62
5
41
VCC
GND
GND
GND
GND
GND
GND
1
12
32
42
53
63
0E
0E
0E
0E
R52
R53
R54
R55
NOTE 4
R127
R128
DNP
NOTE 3
0E
0E
0E
0E
10K
10K
R48
R49
R50
R51
R44
R43
DNP
DVDD3V3
DNP
0E
0E
10K
R45
22K
DGND
13
9
3,4
13
13
9
3,4
13
1
TP13
TO BASEBOARD CONNECTOR
TO BASEBOARD CONNECTOR
TO BASEBOARD CONNECTOR
0_1uF
C66
TO BASEBOARD CONNECTOR
PLD_DuSLIC_TSI_RSTn 3,4,15 From CPLD
CT_D0
RX1
RX2
CT_D4
CT_D1
TX1
TX2
CT_D5
DGND
0_1uF
C65
DVDD3V3
DGND
0_1uF
C67
2
Date:
Size
B
Title
CT_WFRAMEn 14,15 From WAN PLL --
Frame Sync In WF-Bus mode
Thursday, June 12, 2003
Document Number
<Doc>
Digital Switch
AURAL NETWORKS
8KHz
HCLK
14
From WAN PLL --4.096MHz
CT_STFRAMEn 14,15 From WAN PLL -8KHz Frame Sync In ST-Bus mode
CLK
14
From WAN PLL -- 16.384MHz
0E
R47
R56
10K
DNP
R46
2
1
Sheet
1
7
of
15
Rev
2.0
A
B
C
D
A
B
C
D
DVDD3V3
DGND
10
28
55
91
101
124
132
42
67
114
139
38
71
110
143
DS#
5
R/W#
TDM_GPL2
7,13,15 CONN_AD[22:31]
TP26
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDR1
VDDR2
VDDR3
VDDR4
VDDX1
VDDX2
VDDX3
VDDX4
1
0
IM
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSR1
VSSR2
VSSR3
VSSR4
VSSX1
VSSX2
VSSX3
VSSX4
Motorola mode
DGND
JTAG_TRST
JTAG_TCK
JTAG_TMS
TDM_TDO
TDM_TDI
Intel mode
Description
11
29
56
92
102
125
135
45
64
117
136
1
36
73
108
U12B
Quad_falc
BASEBOARD CONNECTOR
13
13
13
13
13
FROM BASEBOARD CONNECTOR 7,13,15 TDM_GPL2
FROM BASEBOARD CONNECTOR 7,13,15 TDM_GPL1
Description
TDM_GPL1
Signal
DNP : Do Not Place
AVDD3V3
13 TDM_TO_PQ2_INT1
10K
10K
FROM BASEBOARD CONNECTOR 13,15 TDM_RESET
FROM BASEBOARD CONNECTOR 13 PQ2_CS_TDM1
R58
R57
DVDD3V3
TO BASEBOARD CONNECTOR
5
0
1
DBW
1
4
DGND
4
0E
0E
DGND
8 bit
16 bit
Description
R121
R70
CONN_AD31
CONN_AD30
CONN_AD29
CONN_AD28
CONN_AD27
CONN_AD26
CONN_AD25
CONN_AD24
CONN_AD23
CONN_AD22
10K
R59
DVDD3V3
131
140
141
113
112
46
86
62
41
40
68
85
84
87
74
75
76
77
78
79
80
81
82
83
TRS
TCK
TMS
TDO
TDI
0_1uF
C76
AVDD3V3
0_1uF
C69
NC
NC
XTAL/NC
MCLK
SYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DVDD3V3
RES
CS
ALE
INT
DBW
IM
RD/DS
WR/R/W
BHE/BLE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
0_1uF
C77
0_1uF
C70
118
63
134
133
48
88
89
90
93
94
95
96
97
98
99
100
103
104
105
106
107
U12A
Quad_falc
3
3
0_1uF
C78
0_1uF
C71
0_1uF
C79
0_1uF
C80
0_1uF
C73
MCLK
0_1uF
C72
27E
0E
DNP
R68
R69
CONN_D7
CONN_D6
CONN_D5
CONN_D4
CONN_D3
CONN_D2
CONN_D1
CONN_D0
0_1uF
C81
0_1uF
C82
DGND
0_1uF
C75
DGND
0_1uF
C83
2
R71
DNP
10K
Date:
Size
B
Title
CLOCK
TRI-STATE
output
U13
DVDD3V3
DGND
8
C68
MCLK
0_1uF
DGND
1
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
AURAL NETWORKS
QUAD FALC
1
OSCILLATOR
VITE_VCB2_B0F_16M384
9,10,11,12,14
DVDD3V3
CT_FRAMEn
10K 10K 10K 10K 10K 10K 10K 10K
R60 R61 R62 R63 R64 R65 R66 R67
0_1uF
C74
7,13,15
DVDD3V3
CONN_D[0:15]
2
14
VDD
GND
7
8
of
15
Rev
2.0
A
B
C
D
A
B
TX1
RX1
TP17
TP18
TP19
14 FSC_QFALC
3,4,13,14,15 CT_C8_A
7
1
1
1
1
1
1
R75 DNP
TP14
TP15
TP16
3,4,13,14,15 CT_C8_A
14
RCLK1
0,11,12,14 CT_FRAMEn
7
C
5
0E
TP20
1
69
8
7
6
5
4
9
3
119
123
122
121
120
2
SEC/FSC
SCLKR1
RPD1
RPC1
RPB1
RPA1
RDO1
SCLKX1
RCLK1
XPD1
XPC1
XPB1
XPA1
XDI1
RL2/RDIN/RCLKI
RL1/RDIP/ROID
XL2/XDON/XFM
XL1/XDOP/XOID
116
115
111
109
10E_5P_0W125
3
AVDD3V3
10E_5P_0W125
2E_5P_0W125
R76
AVDD3V3
4
DNP: Do Not Place
NOTE: Connect 1 & 2 for E1
Connect 2 & 3 for T1
R80
R77
NOTE
CON3
1
2
3
J2
7R5_5P_0W125
R74
2E_5P_0W125
CON3 R73
NOTE
3
BAV70
D4
2
1
1
2
3
2
1
BAV70
D1
3
1
3
3
D2
BAW56
DGND
D3
BAW56
2
7R5_5P_0W125
R72
3
120E_5P_0W125
J1
1
2
U12C
Quad_falc
4
J3
R79
CON3
R78
DGND
NOTE
1
2
3
4
3
2
1
5
37
38
2
U15B
TGSP-SO24NX
39
40
U15A
TGSP-SO24NX
2
Date:
Size
B
Title
1
2
TR600-150
2
TR600-150
2
TR600-150
2
TR600-150
1
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
AURAL NETWORKS
1
U20
1
U18
1
U17
1
U14
SiBAR
U19
SiBAR
U16
QUAD FALC
2
D
5
1
2
36
100E_5P_0W125
9
P2A
of
15
Rev
2.0
CONN_RJ45_4STACK
A8
A7
A6
A5
A4
A3
A2
A1
A
B
C
D
A
B
,11,12,14 CT_FRAMEn
C
R84
DNP
5
0E
13
17
16
15
14
12
19
130
129
128
127
126
18
SCLKR2
RPD2
RPC2
RPB2
RPA2
RDO2
SCLKX2
RCLK2
XPD2
XPC2
XPB2
XPA2
XDI2
137
138
142
144
R89
R86
DNP: Do Not Place
4
2E_5P_0W125
R82
10E_5P_0W125
3
AVDD3V3
10E_5P_0W125
2E_5P_0W125
R85
7R5_5P_0W125
R83
NOTE
CON3
1
2
3
J5
NOTE: Connect 1 & 2 for E1
Connect 2 & 3 for T1
RL2/RDIN/RCLKI
RL1/RDIP/ROID
XL2/XDON/XFM
XL1/XDOP/XOID
U12D
Quad_falc
NOTE
CON3
1
2
3
BAV70
D8
3
AVDD3V3
2
1
7R5_5P_0W125
R81
BAV70
D6
1
3
3
D7
BAW56
2
J4
2
1
3
DGND
3
D5
BAW56
120E_5P_0W125
D
1
2
4
J6
R88
CON3
R87
DGND
NOTE
1
2
3
7
6
9
8
10
34
35
2
U15D
TGSP-SO24NX
32
33
U15C
TGSP-SO24NX
2
Date:
Size
B
Title
1
2
5
1
2
31
100E_5P_0W125
2
TR600-150
2
TR600-150
2
TR600-150
2
TR600-150
Thursday, June 12, 2003
Document Number
<Doc>
QUAD FALC
1
Sheet
AURAL NETWORKS
1
U26
1
U24
1
U23
SiBAR
U25
SiBAR
U22
1
U21
1
P2B
10
of
15
Rev
2.0
CONN_RJ45_4STACK
B8
B7
B6
B5
B4
B3
B2
B1
A
B
C
D
A
B
C
9,10,12,14 CT_FRAMEn
R93
DNP
5
0E
26
25
24
23
22
27
21
47
54
53
52
51
20
SCLKR3
RPD3
RPC3
RPB3
RPA3
RDO3
SCLK3
RCLK3
XPD3
XPC3
XPB3
XPA3
XDI3
RL2/XDIN/RCLKI
RL1/RDIP/ROID
XL2/XDON/XFM
XL1/XDOP/XOID
R98
R95
NOTE
CON3
1
2
3
J8
4
DNP: Do Not Place
BAV70
D11
3
AVDD3V3
10E_5P_0W125
3
AVDD3V3
10E_5P_0W125
2E_5P_0W125
R94
7R5_5P_0W125
R92
2E_5P_0W125
R91
NOTE: Connect 1 & 2 for E1
Connect 2 & 3 for T1
44
43
39
37
NOTE
CON3
2
1
1
2
3
2
1
BAW56
3
D12
BAV70
D10
3
DGND
1
2
7R5_5P_0W125
R90
3
3
J9
R97
DGND
CON3
R96
D9
BAW56
120E_5P_0W125
J7
1
2
U12E
Quad_falc
4
NOTE
14
13
12
11
26
D
5
1
2
3
15
27
28
2
U15F
TGSP-SO24NX
29
30
U15E
TGSP-SO24NX
2
Date:
Size
B
Title
1
2
1
2
100E_5P_0W125
2
TR600-150
2
TR600-150
2
TR600-150
2
TR600-150
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
C8
C7
C6
C5
C4
C3
C2
C1
P2C
11
of
15
Rev
2.0
CONN_RJ45_4STACK
AURAL NETWORKS
1
U32
1
U30
1
U29
QUAD FALC
SiBAR
U31
SiBAR
U28
1
U27
1
A
B
C
D
A
B
C
9,10,11,14 CT_FRAMEn
R102
DNP
5
0E
31
35
34
33
32
30
50
61
60
59
58
57
49
SCLKR4
RPD4
RPC4
RPB4
RPA4
RDO4
SCLKX4
RCLK4
XPD4
XPC4
XPB4
XPA4
XDI4
RL2/RDIN/RCLKI
RL1/RDIP/ROID
XL2/XDON/XFM
XL1/XDOP/XOID
65
66
70
72
U12F
Quad_falc
BAV70
D16
4
DNP: Do Not Place
3
AVDD3V3
NOTE: Connect 1 & 2 for E1
Connect 2 & 3 for T1
3
AVDD3V3
10E_5P_0W125
2E_5P_0W125
R103
7R5_5P_0W125
R101
2E_5P_0W125
R100
10E_5P_0W125
R107
R104
NOTE
CON3
1
2
3
J11
NOTE
CON3
1
2
3
2
1
7R5_5P_0W125
R99
2
1
3
D15
BAW56
BAV70
D14
3
DGND
3
1
2
J10
1
2
4
DGND
CON3
J12
R105 R106
3
D13
BAW56
NOTE
1
2
3
17
16
19
18
20
21
24
25
2
U15H
TGSP-SO24NX
22
23
U15G
TGSP-SO24NX
2
Date:
Size
B
Title
1
1
U38
TR600-150
2
TR600-150
2
TR600-150
2
2
TR600-150
1
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
D8
D7
D6
D5
D4
D3
D2
D1
P2D
of
15
Rev
2.0
CONN_RJ45_4STACK
12
AURAL NETWORKS
SiBAR
U37
1
U36
1
U33
1
U35
SiBAR
U34
QUAD FALC
2
D
5
1
2
100E_5P_0W125
120E_5P_0W125
A
B
C
D
A
B
C
D
5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
JTAG_TCK
8
8
7,8,15
7,8,15
3,4
TDM_SPICLK
CONN_AD22
CONN_AD23
CONN_AD24
CONN_AD25
CONN_AD26
CONN_AD27
CONN_AD28
CONN_AD29
CONN_AD30
CONN_AD31
0E
0E
R133
R134
PQ2_CS_TDM2 15
TDM_SPI_CS0 3
TDM_GPL2
TDM_GPL1
PQ2_CS_TDM1 8
TDM_TO_PQ2_INT1 8
CONN_AD30
CONN_AD31
CONN_AD28
CONN_AD29
CONN_AD26
CONN_AD27
CONN_AD24
CONN_AD25
CONN_AD23
JTAG_TRST
TDM_TDO
+3.3V
+5V
7
4
CT_D0
CT_D4
3,4,9,14,15 CT_C8_A
15 CT_FRAME_A
+5V
TDM_SPIMOSO 3,4
7
TDM_SPIMOSI
3,4
DGND
8
REMEMBER: A0 is LSB on QuadFALC
A31 is LSB on Motorola!!
4
J13 will connect to J9 connector of base card
J14 will connect to J7 connector of base card
J15 will connect to J8 connector of base card
7,8,15 CONN_AD[22:31]
CONN_D0
CONN_D1
CONN_D2
CONN_D3
CONN_D4
CONN_D5
CONN_D6
CONN_D7
CONN_D8
CONN_D9
CONN_D10
CONN_D11
CONN_D12
CONN_D13
CONN_D14
CONN_D15
DGND
J15
HEADER32x2
1
3
5
7
CONN_D0
9
CONN_D1 11
13
15
CONN_D2 17
CONN_D3 19
21
CONN_D4 23
CONN_D5 25
27
CONN_D6 29
CONN_D7 31
33
CONN_D8 35
37
CONN_D9 39
41
CONN_D10 43
CONN_D11 45
47
CONN_D12 49
CONN_D13 51
53
CONN_D14 55
CONN_D15 57
59
CONN_AD2261
63
TDM_SPI_CS1
JTAG_TMS
TDM_TDI
8,15 TDM_RESET
4
8
8
REMEMBER: D0 is LSB on QuadFALC
D0 is MSB on Motorola!!
7,8,15 CONN_D[0:15]
+3.3V
+5V
5
DGND
CT_D0
3
CT_D4
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
CT_D1
CT_D5
CT_D0- Transmit to DSP (TDM0)
CT_D1- RX from DSP (TDM0)
CT_D4 Transmit to MPC8260
CT_D5 Recieve from MPC8260
HEADER32x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
J14
DGND
CT_D1
CT_D5
+5V
7
7
2
TP36
TP37
TP35
2
1
1
1
+3.3V
Date:
Size
B
Title
DGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Thursday, June 12, 2003
1
Sheet
Base Board Connectors
13
of
TDM_TO_PQ2_INT2 3
TDM_TO_PQ2_INT3 4
AURAL NETWORKS
HEADER32x2
Document Number
<Doc>
TDM_GPIO1
TDM_GPIO0
TDM_GPIO2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
J13
1
15
Rev
2.0
DGND
+5V
A
B
C
D
A
B
C
0_1uF
0_1uF
0_1uF
C87
5
DNP : Do Not Place
C86
C85
0_1uF
C88
DGND
0_1uF
C89
PLD_F_sel1
PLD_F_sel0
RCLK1
4
DVDD3V3
15
15
PLD_TCLRn
PLD_TIE_en
15 PLD_WAN_PLL_RSTn
15 PLD-MODE_sel1
15 PLD_MODE_sel0
15
15
9
R113
R137
R136
TP21
DNP
10K
0E
0E
DGND
0E
R114
10K
R138
DVDD3V3
3
6
7
8
11
21
22
34
35
43
29
32
30
28
31
45
3
56
4
2
1
10
9
5
IC
IC
IC
IC
IC
IC
IC
IC
IC
41
42
40
39
36
33
25
20
24
23
17
16
15
14
52
46
51
44
49
50
1
1
1
1
R110
R111
R112
TP25
0E
0E
0E
TP22TP23TP24
2CLK_OSC
33E
15 PLD_QFALC_FRAME
TP30
TP33
TP34
TP32
R109
1
Title
LOCK_PLD
DGND
2
IN
DGND
8
CLK_OSC
R130
DNP
0E
R129
0E
Thursday, June 12, 2003
1
Sheet
14
of
15
Rev
2.0
8,9,10,11,12
To QuadFALC
CT_FRAMEn
AURAL NETWORKS
4
NC7S04
U41
TP38
TO BASE BOARD CONNECTOR -- 8.192MHz
DuSLIC/FALC
Document Number
<Doc>
3
GND
DGND
O/P
0_1uF
DGND
C84
SWITCH---4.096MHz
SWITCH --- 16.384MHz
E/D
DVDD3V3
1
CLOCK SYNCHRONIZATION CIRCUIT
DVDD3V3
OUT*
1
FOX_F7C-2E3
U39
7 TO IDT
7 TO IDT
3,4,9,13,15
CT_STFRAMEn 7,15
CT_FRAME
3,4,15
CT_WFRAMEn 7,15
HCLK
CLK
CT_C8_A
2
Date:
Size
B
15
10K
HOLDOVER_PLD 15
NORMAL_PLD 15
VCC
RSP
TSP
F32o
F16o
F8o
F0o
C32o
C4o
C16o
C8o
C2o
C3o
C1.5o
C6o
HOLDOVER
NORMAL
FREERUN
LOCK
OSCo
OSCi
U40
IDT82V3001
5
TDO
TDI
TRST
TCK
TMS
FLOCK
TCLR
TIE_en
RST
MODE_sel1
MODE_sel0
F_sel1
F_sel0
Fref
DVDD3V3
R108
DVDD3V3
VSS
VSS
VSS
VSS
VSS
12
18
27
38
47
8 KHz FSC signal from QuadFALC
9
FSC_QFALC
1
13
19
26
37
48
VDD
VDD
VDD
VDD
VDD
IC2
IC1
IC0
55
54
53
D
2
1
DVDD3V3
3
1
4
1
5
1
14
VDD
GND
7
TO BASE BOARD CONNECTOR -- 8KHz
1
A
B
C
D
A
B
C
TMS_PLD
TDO_PLD
TDI_PLD
TCK_PLD
CONN_JTAG_PLD
1
2
3
4
5
6
7
8
9
J16
DVDD5V
5
330E
R115
DVDD3V3
0_1uF
DGND
C94
13 PQ2_CS_TDM2
LED5
2
2
3
5
6
CONN_AD30
CONN_AD29
CONN_AD28
CONN_AD27
TP31
+5V
+5V
VHR
VHRX
JUMPER3
1
1
DGND
DVDD5
J20 JUMPER3
J19
DVDD5V
J18 JUMPER3
FROM BASE BOARD CONNECTOR
FROM BASE BOARD CONNECTOR
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U42
DVDD3V3
+3.3V DVDD3V3 3V3
8
10
11
12
13
14
15
18
19
20
21
22
PLD_LOS_FALC
23
CONN_D15
CONN_D14
CONN_D13
CONN_D12
42
43
44
CONN_AD22
FROM BASE BOARD CONNECTOR
1
3,4,14 CT_FRAME
From WAN PLL
From WAN PLL
7,14 CT_STFRAMEn
From WAN PLL
7,14 CT_WFRAMEn
To Base board connectors 13 CT_FRAME_A
14 PLD_WAN_PLL_RSTn
8,13 TDM_RESET
7 PLD_IDT_CSn
3,4,9,13,14 CT_C8_A
7,8,13 CONN_D[0:15]
7,8,13 CONN_AD[22:31]
FROM BASEBOARD CONNECTOR
14 PLD_QFALC_FRAME
7,8,13 CONN_AD[22:31]
3
2
1
3
2
1
3
2
1
1
9
17
29
41
Vcc
Vcc
Vcc
Vcc
GND
GND
GND
16
24
36
D
26
1
32
7
4
40
39
38
37
25
27
28
30
31
33
34
35
VBATHX
VBATH
3
VBATL
IN4004
D20
DGND
C95
100nF_10P_200V
D19
IN4004
DGND
TP29
IN4004
D17
D18
DGND
10K
1
10K
1
10K
1
2
2
R125 R126
2
R124
DVDD3V3
IN4004
TP40
1
2
3
4
5
6
2
2
DGND
22K
R116
0_1uF
C90
DVDD3V3
TDM_GPL1
7,8,13 FROM BASEBOARD CONNECTOR
TDM_GPL2
7,8,13 FROM BASEBOARD CONNECTOR
LOCK_PLD
14
NORMAL_PLD 14
PLD_MODE_sel0 14
PLD-MODE_sel1 14
PLD_F_sel0
14
PLD_F_sel1
14
PLD_TCLRn
14
PLD_TIE_en 14
HOLDOVER_PLD 14
PLD_DuSLIC_TSI_RSTn 3,4,7
CON6_PowerSupply
J17
TCK_PLD
TDI_PLD
TDO_PLD
TMS_PLD
TP39 VBATHX VHRX DVDD5 3V3
TCK
TDI
TDO
TMS
PORT_EN
IN0/CLK0
IN1/CLK1
IN2/CLK2
IN3/CLK3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XCR3032XL_5VQ44I
2
0_1uF
0_1uF
DGND
C93
C92
1
Date:
Size
B
Title
1
2
1
2
DGND
LED7
330E
R118
DVDD5V
1
2
LED8
330E
R119
DGND
VHR
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
1
2
15
of
DGND
LED9
10K
R120
VBATHX
AURAL NETWORKS
CPLD and Power
DGND
LED6
330E
R117
DVDD3V3
SYNC :Synchronous clock from Central Office
DNP: Do Not Place
0_1uF
C91
1
2
3
2
1
1
2
4
1
1
1
2
5
2
12
1
2
1
15
Rev
2.0
A
B
C
D
A
B
C
+5VIN
+5VIN
+3.3V
+3.3V
J1
11
12
13
14
15
16
17
18
19
20
+5VIN
+5VIN
5
+5VIN
PWR_ON
+3.3V
ATX INPUT Tyco 2-794664-0
1
2
3
4
5
6
7
8
9
10
1
2
RESETTABLE FUSE
RGE400
1
U6
2
NMT0572S
V03
8
V02
7
V01
6
0V
5
GND
2
VIN
1
4
NMT0572S
V03
8
V02
7
V01
6
0V
5
GND
2
VIN
1
3
NMT0572S
V02
7
V01
6
0V
5
GND
2
VIN
1
NMT0572S
U5
+48V
+24V
-48V
+5VIN
+3.3V
PWR_ON
2
Packet telelphony
Motorola
Copyright 2001
PDK_POTS_PWR
Rich Cutler
Tuesday, February 10, 2004
Title
Name
Date:
1
1
2
3
4
5
6
7
8
9
10
1
Sheet
Block Schematic
EDGE PADS
J2
of
Rev
1
0.1
Pins 1-5: To PSTN Card
Pins 6-8: To Baseboard
Pins 9-10: To On/OFF Switch
The purpose of this
board is to provide
power to the PSTN
card of the Smart
Packet Telephony
Development Kit.
V03
8
U2
VIN
1
U3
GND
2
U4
2
0V
5
3
V01
6
4
V02
7
D
5
V03
8
A
B
C
D
3
2
1
4
3
2
Title
AURAL NETWORKS
Date:
Size
B
Thursday, June 12, 2003
Document Number
<Doc>
REVISION HISTORY
of
15
Rev
2.0
1
Sheet
1
A
C
A
Frame Sync for BASE BOARD Connectors is provided from CPLD
Brought F8o, F0o/, F16o/ (from WAN PLL) to CPLD.
Provided narrower frame pulse (F16o/ from WAN PLL)
for the TSI to operate in ST-BUS mode.
-->QuadFALC, CPLD
-->WAN PLL
-->TSI, DuSLIC
06/06/2003
18/11/2002
DATE
B
5
Swapping of the SPIMOSI and SPIMOSO signals.
2.0
Three level reset configuration.
Initial Revision.
Change from previous version
1.0
Revision
D
B
C
D
4
Packet Telephony Development Kit
POTS card Rev 2.0
5
A
B
C
5
RJ45
RJ45
RJ45
RJ45
RJ11
RJ11
RJ11
RJ11
SLIC
SLIC
SLIC
T1/E1
T1/E1
T1/E1
T1/E1
(Infineon)
SLIC
(Infineon)
(IDT)
WAN PLL
4.096MHz
8.192MHz
16.384MHz
8KHz
(Infineon)
FALC
Quad
(Infineon)
CODEC
DuSLIC
(Infineon)
(Infineon)
CODEC
DuSLIC
(Infineon)
4
3
PCM3
CPLD
PCM0
3
(Xilinx)
PCM1
(IDT)
SWITCH
512 x 512
PCM2
POTS BLOCK SCHEMATIC
RCLK1
4
IDT_CS#
D
5
uP BUS
uP BUS
PCM0
uP BUS
PCM3
SERIAL BUS
2
2
TO BASEBOARD CONNECTORS
Date:
Size
B
Title
Thursday, June 12, 2003
Document Number
<Doc>
Pots Card Block Schematic
1
Sheet
AURAL NETWORKS
1
2
of
15
Rev
2.0
A
B
C
D
A
B
C
D
DGND
DVDD3V3
L1
5
100mH
5
5
IL_1B
IT_1B
5
5
ACP_1B
ACN_1B
DCP_1B
DCN_1B
C1_1B
C2_1B
5
5
5
5
5
5
VCMS_1
IL_1A
IT_1A
5
5
ACP_1A
ACN_1A
DCP_1A
DCN_1A
C1_1A
C2_1A
47uF
C2
+
5
5
5
5
5
5
0_1uF
C1
AVDD3V3
R6
VCM1
R13
4
C10
C9
680nF_10P_16V
C12
68nF_10P_50V
680nF_10P_16V
680nF_10P_16V
1K6_1P_0W125
C14
C13
DGND
63
60
61
3
62
6
7
2
5
64
1
4
57
56
58
50
52
53
46
51
43
42
47
44
49
48
45
ILB
3
DGND
DGND
TEST
IO4B
IO3B
IO2B
IO1B
IO4A
IO3A
IO2A
IO1A
RSYNC
RESET
DXB
DD/DRB
TCB
DXA
SEL24/DRA
TCA
FSC
DCL/PCLK
MCLK
TS0/DIN
DU/DOUT
TS1/DCLK
TS2/CS
INT
PCM/IOM-2
SELCLK
U1
PEB3265
AVDD3V3 DVDD3V3
3
DGND
VCMITB
ITB
CDCPB
ITACB
ACPB
ACNB
DCPB
DCNB
C1B
C2B
CDCNB
VCM
VCMS
CREF
ILA
ITA
VCMITA
CDCPA
ITACA
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
100nF_10P_50V
C5
680nF_10P_16V
120nF_10P_25V
C11
DGND
C8
120nF_10P_25V
100nF_10P_50V
C4
1K6_1P_0W125
R11
R12
680E_1P_0W125 470E_1P_0W125
VCM1
R2
R3
680E_1P_0W125 470E_1P_0W125
100nF_10P_50V
C3
4
CHANNEL A
CHANNEL B
GNDR
GNDA
35
13
12
11
10
36
37
38
39
33
34
28
20
29
27
21
26
23
19
22
14
18
15
16
17
32
59
R122
10K
R1
1
1
1
1
R8
R7
R5
R4
0E
0E
TP4
TP5
TP1
TP2
0E
0E
0E
DGND
2
2
2
DGND
4,7
4,7
4,14,15
4,9,13,14,15
LED10
LED11
1
1
330E
R139
Date:
Size
B
Title
330E
R140
DVDD3V3
PLD_DuSLIC_TSI_RSTn 4,7,15
RX2
TX2
CT_FRAME
CT_C8_A
LED1
LED2
1
1
DVDD3V3
330E
R10
1
Thursday, June 12, 2003
Document Number
<Doc>
Analog Subscriber Line Interface
1
Sheet
AURAL NETWORKS
Hook status Indicators
2
2
330E
R9
From CPLD
To WAN PLL
From WAN PLL
From WAN PLL
From WAN PLL
TO BASEBOARD
100nF_10P_50V
C7
TDM_SPIMOSI 4,13
TDM_SPIMOSO 4,13
TDM_SPICLK 4,13
TDM_SPI_CS0 13
TDM_TO_PQ2_INT2 13
100nF_10P_50V
C6
2
1
2
54
41
8
VDDR
VDDA
VDDB
55
40
1
2
25
31
GNDD
GNDPLL
24
30
1
2
VDDD
VDDPLL
PCM
GNDB
9
1
2
3
of
15
Rev
2.0
A
B
C
D
A
B
C
D
5
5
ACP_2B
ACN_2B
DCP_2B
DCN_2B
C1_2B
C2_2B
IT_2B
6
6
6
6
6
6
6
IL_2B
VCMS_2
6
IL_2A
6
IT_2A
6
6
ACP_2A
ACN_2A
DCP_2A
DCN_2A
C1_2A
C2_2A
6
6
6
6
6
6
R19
VCM2
R26
680nF_10P_16V
C22
680nF_10P_16V
C26
4
1K6_1P_0W125
680nF_10P_16V
120nF_10P_25V
C24
68nF_10P_50V
C25
DGND
C23
1K6_1P_0W125
R24
R25
680E_1P_0W125 470E_1P_0W125
VCM2
680nF_10P_16V
C21
63
60
61
3
62
6
7
2
5
64
1
4
57
56
58
50
52
53
46
51
43
42
47
44
49
48
45
ILB
VCMITB
ITB
CDCPB
ITACB
ACPB
ACNB
DCPB
DCNB
C1B
C2B
CDCNB
VCM
VCMS
CREF
ILA
ITA
VCMITA
CDCPA
ITACA
ACPA
ACNA
DCPA
DCNA
C1A
C2A
CDCNA
100nF_10P_50V
C19
DGND
C20
120nF_10P_25V
100nF_10P_50V
100nF_10P_50V
R15
R16
680E_1P_0W125 470E_1P_0W125
C18
C17
4
CHANNEL A
CHANNEL B
AVDD3V3
DGND
DGND
3
DGND
TEST
IO4B
IO3B
IO2B
IO1B
IO4A
IO3A
IO2A
IO1A
RSYNC
RESET
DXB
DD/DRB
TCB
DXA
SEL24/DRA
TCA
FSC
DCL/PCLK
MCLK
TS0/DIN
DU/DOUT
TS1/DCLK
TS2/CS
INT
PCM/IOM-2
SELCLK
U2
PEB3265
DVDD3V3
3
55
40
35
13
12
11
10
36
37
38
39
33
34
28
20
29
27
21
26
23
19
22
14
18
15
16
17
32
59
R123
10K
R14
1
1
1
1
R21
R20
R18
R17
0E
DGND
TP10
TP11
TP7
TP8
0E
0E
0E
0E
DGND
2
2
2
LED12
LED13
1
1
330E
R141
Date:
Size
B
Title
330E
R142
DVDD3V3
1
1
330E
R23
Hook status Indicators
LED3
330E
R22
DVDD3V3
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
AURAL NETWORKS
2
2
LED4
1
100nF_10P_50V
C15
DVDD3V3
Analog Subscriber Line Interface
From CPLD
3,7 To WAN PLL
3,7 From WAN PLL
3,14,15
3,9,13,14,15
From WAN PLL
From WAN PLL
TO BASEBOARD
PLD_DuSLIC_TSI_RSTn 3,7,15
RX2
TX2
CT_FRAME
CT_C8_A
TDM_SPIMOSI 3,13
TDM_SPIMOSO 3,13
TDM_SPICLK 3,13
TDM_SPI_CS1 13
TDM_TO_PQ2_INT3 13
2
1
2
54
41
8
VDDR
VDDA
VDDB
GNDR
GNDA
1
2
25
31
GNDD
GNDPLL
24
30
1
2
VDDD
VDDPLL
PCM
GNDB
9
1
2
4
DGND
of
15
100nF_10P_50V
C16
Rev
2.0
A
B
C
D
C1_1A
C2_1A
IT_1A
IL_1A
3
3
3
3
C1_1B
C2_1B
IT_1B
IL_1B
3
3
3
3
A
VCMS_1
ACN_1B
ACP_1B
DCN_1B
DCP_1B
3
3B
3
3
3
C
VCMS_1
ACN_1A
ACP_1A
DCN_1A
DCP_1A
3
3
3
3
3
D
20
19
18
17
11
12
13
14
15
DGND
5
20
19
18
17
11
12
13
14
15
100nF_10P_50V
C38
DGND
100nF_10P_50V
C27
IT
IL
C1
C2
DGND
AVDD5V
VCMS
ACN
ACP
DCN
DCP
IT
IL
C1
C2
VCMS
ACN
ACP
DCN
DCP
AVDD5V
BGND
3
DGND
VBATL
DGND
TIP
RING
NC
NC
CEXT
DGND
R32
R33
2
1
VHR
4
30E_0P5_0W5
30E_0P5_0W5
470nF_10P_16V
C43
VBATH
16
8
10
DGND
C33
15nF_10P_100V
C46
DGND
15nF_10P_100V
C42
C44
220nF_20P_200V
3
5
8
2
NC
NC
GN
DGND
3
5
8
2
NC
NC
GN
100nF_10P_200V
C41
VBATH
100nF_10P_200V
100nF_10P_200V
DGND
C40
DGND
VBATH
C39
15nF_10P_100V
C35
DGND
15nF_10P_100V
100nF_10P_200V
C30
220nF_20P_200V
100nF_10P_200V
100nF_10P_200V
DGND
C31
C29
C28
4
30E_0P5_0W5
30E_0P5_0W5
R28
R29
2
1
VHR
470nF_10P_16V
C32
VBATH
16
8
U5
PEB4265
DGND
TIP
RING
NC
NC
CEXT
10
U3
PEB4265
VBATL
BGND
5
5
6
7
4
VDD
VBATL
VBATH
VHR
3
1
TIP
6
7
3
GP
6
7
3
U6
LCP02_150B1
SO8_300
GND
GND
GP
20E_1P_0W5
R31
R34
2
20E_1P_0W5
20E_1P_0W5
20E_1P_0W5
2
R30
220nF_20P_200V
C45
DGND
VHR
R27
220nF_20P_200V
C34
DGND
U4
LCP02_150B1
SO8_300
VHR
GND
GND
RING
4
AGND
9
5
6
7
4
VDD
VBATL
VBATH
VHR
AGND
9
1
TIP
RING
4
RING2
TIP2
RING1
TIP1
Date:
Size
B
Title
L3
100mH
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
5
0_1uF
C37
AURAL NETWORKS
CONN_RJ11_4STACK
P1B
DGND
DVDD5V
CONN_RJ11_4STACK
P1A
Analog Subscriber Line Interface
B6
B5
B4
B3
B2
B1
A6
A5
A4
A3
A2
A1
1
of
15
47UF_16V
+ C36
AVDD5V
Rev
2.0
A
B
C
D
C1_2A
C2_2A
IT_2A
IL_2A
4
4
4
4
C1_2B
C2_2B
IT_2B
IL_2B
4
4
4
4
A
VCMS_2
ACN_2B
ACP_2B
DCN_2B
DCP_2B
4B
4
4
4
4
C
VCMS_2
ACN_2A
ACP_2A
DCN_2A
DCP_2A
4
4
4
4
4
D
20
19
18
17
11
12
13
14
15
DGND
5
20
19
18
17
11
12
13
14
15
100nF_10P_50V
C56
DGND
100nF_10P_50V
C47
IT
IL
C1
C2
DGND
AVDD5V
VCMS
ACN
ACP
DCN
DCP
IT
IL
C1
C2
VCMS
ACN
ACP
DCN
DCP
AVDD5V
BGND
3
DGND
TIP
RING
NC
NC
CEXT
DGND
TIP
RING
NC
NC
CEXT
R40
R41
2
1
DGND
DGND
VHR
4
C53
15nF_10P_100V
C64
DGND
15nF_10P_100V
C60
220nF_20P_200V
C62
5
8
2
NC
NC
GN
DGND
3
5
8
2
NC
NC
GN
100nF_10P_200V
C59
VBATH
100nF_10P_200V
DGND
C58
100nF_10P_200V
DGND
VBATH
C57
15nF_10P_100V
C55
DGND
3
100nF_10P_200V
C50
220nF_20P_200V
100nF_10P_200V
C49
15nF_10P_100V
C51
100nF_10P_200V
C48
30E_0P5_0W5
30E_0P5_0W5
470nF_10P_16V
C61
VBATH
16
8
10
U9
PEB4265
VBATL
DGND
2
1
4
30E_0P5_0W5
30E_0P5_0W5
R36
R37
VHR
470nF_10P_16V
C52
VBATH
16
8
10
U7
PEB4265
VBATL
DGND
BGND
5
5
6
7
4
VDD
VBATL
VBATH
VHR
3
1
TIP
6
7
3
GP
6
7
3
U10
LCP02_150B1
GND
GND
GP
U8
LCP02_150B1
GND
GND
RING
4
AGND
9
5
6
7
4
VDD
VBATL
VBATH
VHR
AGND
9
1
TIP
RING
4
R42
2
20E_1P_0W5
20E_1P_0W5
R39
220nF_20P_200V
C63
DGND
VHR
20E_1P_0W5
20E_1P_0W5
R38
220nF_20P_200V
C54
DGND
VHR
R35
2
RING4
TIP4
RING3
TIP3
Date:
Size
B
Title
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
AURAL NETWORKS
CONN_RJ11_4STACK
P1D
CONN_RJ11_4STACK
P1C
Analog Subscriber Line Interface
D6
D5
D4
D3
D2
D1
C6
C5
C4
C3
C2
C1
1
6
of
15
2.0
Rev
A
B
C
D
A
B
C
8,13,15 TDM_GPL1
8,13,15 TDM_GPL2
15 PLD_IDT_CSn
0
1
2
3
PCM
5
DSP
FALC
DuSLIC
BASE CARD
Description
DNP : Do Not Place
NOTE 4 :
WF Mode
-ST_BUS Mode --
Place R127
Place R128
NOTE 1&2 :
Motorola demultiplexed mode
considered
NOTE 3 :
WFPS=1, WFPS Mode
WFPS=0, ST_BUS Mode
TO BASEBOARD CONNECTOR 8,13,15 CONN_D[0:15]
TO BASEBOARD CONNECTOR 8,13,15 CONN_AD[22:31]
TO BASEBOARD CONNECTOR
TO BASEBOARD CONNECTOR
From CPLD
NOTE2
NOTE1
4
33
34
35
36
37
38
39
40
43
44
45
46
47
48
49
50
CONN_D7
CONN_D6
CONN_D5
CONN_D4
CONN_D3
CONN_D2
CONN_D1
CONN_D0
19
20
21
22
23
24
25
26
CONN_D15
CONN_D14
CONN_D13
CONN_D12
CONN_D11
CONN_D10
CONN_D9
CONN_D8
CONN_AD30
CONN_AD29
CONN_AD28
CONN_AD27
CONN_AD26
CONN_AD25
CONN_AD24
CONN_AD23
DGND
28
27
29
31
30
D8
D9
D10
D11
D12
D13
D14
D15
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A0
A1
A2
A3
A4
A5
A6
A7
R/W/WR
DS/RD
CS
IM
AS/ALE
POWER
INT CONN
I
N
T
E
R
F
A
C
E
M
I
C
R
O
P
R
O
C
E
S
S
O
R
DVDD3V3
14
VCC
D
4
64
VCC
RX0
RX1
RX2
RX3
TX0
TX1
TX2
TX3
GROUND
WFPS
FE/HCLK
FOi
CLK
DNC
DNC
DNC
RESET
R
X
T
X
DTA
3
DGND
18
11
10
13
52
16
15
17
2
3
4
5
55
56
57
58
51
54
U11
IDT72V70800
3
ODE
IC
IC
IC
IC
IC
IC
IC
IC
6
7
8
9
59
60
61
62
5
41
VCC
GND
GND
GND
GND
GND
GND
1
12
32
42
53
63
0E
0E
0E
0E
R52
R53
R54
R55
NOTE 4
R127
R128
DNP
NOTE 3
0E
0E
0E
0E
10K
10K
R48
R49
R50
R51
R44
R43
DNP
DVDD3V3
DNP
0E
0E
10K
R45
22K
DGND
13
9
3,4
13
13
9
3,4
13
1
TP13
TO BASEBOARD CONNECTOR
TO BASEBOARD CONNECTOR
TO BASEBOARD CONNECTOR
0_1uF
C66
TO BASEBOARD CONNECTOR
PLD_DuSLIC_TSI_RSTn 3,4,15 From CPLD
CT_D0
RX1
RX2
CT_D4
CT_D1
TX1
TX2
CT_D5
DGND
0_1uF
C65
DVDD3V3
DGND
0_1uF
C67
2
Date:
Size
B
Title
CT_WFRAMEn 14,15 From WAN PLL --
Frame Sync In WF-Bus mode
Thursday, June 12, 2003
Document Number
<Doc>
Digital Switch
AURAL NETWORKS
8KHz
HCLK
14
From WAN PLL --4.096MHz
CT_STFRAMEn 14,15 From WAN PLL -8KHz Frame Sync In ST-Bus mode
CLK
14
From WAN PLL -- 16.384MHz
0E
R47
R56
10K
DNP
R46
2
1
Sheet
1
7
of
15
Rev
2.0
A
B
C
D
A
B
C
D
DVDD3V3
DGND
10
28
55
91
101
124
132
42
67
114
139
38
71
110
143
DS#
5
R/W#
TDM_GPL2
7,13,15 CONN_AD[22:31]
TP26
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDR1
VDDR2
VDDR3
VDDR4
VDDX1
VDDX2
VDDX3
VDDX4
1
0
IM
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSR1
VSSR2
VSSR3
VSSR4
VSSX1
VSSX2
VSSX3
VSSX4
Motorola mode
DGND
JTAG_TRST
JTAG_TCK
JTAG_TMS
TDM_TDO
TDM_TDI
Intel mode
Description
11
29
56
92
102
125
135
45
64
117
136
1
36
73
108
U12B
Quad_falc
BASEBOARD CONNECTOR
13
13
13
13
13
FROM BASEBOARD CONNECTOR 7,13,15 TDM_GPL2
FROM BASEBOARD CONNECTOR 7,13,15 TDM_GPL1
Description
TDM_GPL1
Signal
DNP : Do Not Place
AVDD3V3
13 TDM_TO_PQ2_INT1
10K
10K
FROM BASEBOARD CONNECTOR 13,15 TDM_RESET
FROM BASEBOARD CONNECTOR 13 PQ2_CS_TDM1
R58
R57
DVDD3V3
TO BASEBOARD CONNECTOR
5
0
1
DBW
1
4
DGND
4
0E
0E
DGND
8 bit
16 bit
Description
R121
R70
CONN_AD31
CONN_AD30
CONN_AD29
CONN_AD28
CONN_AD27
CONN_AD26
CONN_AD25
CONN_AD24
CONN_AD23
CONN_AD22
10K
R59
DVDD3V3
131
140
141
113
112
46
86
62
41
40
68
85
84
87
74
75
76
77
78
79
80
81
82
83
TRS
TCK
TMS
TDO
TDI
0_1uF
C76
AVDD3V3
0_1uF
C69
NC
NC
XTAL/NC
MCLK
SYNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DVDD3V3
RES
CS
ALE
INT
DBW
IM
RD/DS
WR/R/W
BHE/BLE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
0_1uF
C77
0_1uF
C70
118
63
134
133
48
88
89
90
93
94
95
96
97
98
99
100
103
104
105
106
107
U12A
Quad_falc
3
3
0_1uF
C78
0_1uF
C71
0_1uF
C79
0_1uF
C80
0_1uF
C73
MCLK
0_1uF
C72
27E
0E
DNP
R68
R69
CONN_D7
CONN_D6
CONN_D5
CONN_D4
CONN_D3
CONN_D2
CONN_D1
CONN_D0
0_1uF
C81
0_1uF
C82
DGND
0_1uF
C75
DGND
0_1uF
C83
2
R71
DNP
10K
Date:
Size
B
Title
CLOCK
TRI-STATE
output
U13
DVDD3V3
DGND
8
C68
MCLK
0_1uF
DGND
1
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
AURAL NETWORKS
QUAD FALC
1
OSCILLATOR
VITE_VCB2_B0F_16M384
9,10,11,12,14
DVDD3V3
CT_FRAMEn
10K 10K 10K 10K 10K 10K 10K 10K
R60 R61 R62 R63 R64 R65 R66 R67
0_1uF
C74
7,13,15
DVDD3V3
CONN_D[0:15]
2
14
VDD
GND
7
8
of
15
Rev
2.0
A
B
C
D
A
B
TX1
RX1
TP17
TP18
TP19
14 FSC_QFALC
3,4,13,14,15 CT_C8_A
7
1
1
1
1
1
1
R75 DNP
TP14
TP15
TP16
3,4,13,14,15 CT_C8_A
14
RCLK1
0,11,12,14 CT_FRAMEn
7
C
5
0E
TP20
1
69
8
7
6
5
4
9
3
119
123
122
121
120
2
SEC/FSC
SCLKR1
RPD1
RPC1
RPB1
RPA1
RDO1
SCLKX1
RCLK1
XPD1
XPC1
XPB1
XPA1
XDI1
RL2/RDIN/RCLKI
RL1/RDIP/ROID
XL2/XDON/XFM
XL1/XDOP/XOID
116
115
111
109
10E_5P_0W125
3
AVDD3V3
10E_5P_0W125
2E_5P_0W125
R76
AVDD3V3
4
DNP: Do Not Place
NOTE: Connect 1 & 2 for E1
Connect 2 & 3 for T1
R80
R77
NOTE
CON3
1
2
3
J2
7R5_5P_0W125
R74
2E_5P_0W125
CON3 R73
NOTE
3
BAV70
D4
2
1
1
2
3
2
1
BAV70
D1
3
1
3
3
D2
BAW56
DGND
D3
BAW56
2
7R5_5P_0W125
R72
3
120E_5P_0W125
J1
1
2
U12C
Quad_falc
4
J3
R79
CON3
R78
DGND
NOTE
1
2
3
4
3
2
1
5
37
38
2
U15B
TGSP-SO24NX
39
40
U15A
TGSP-SO24NX
2
Date:
Size
B
Title
1
2
TR600-150
2
TR600-150
2
TR600-150
2
TR600-150
1
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
AURAL NETWORKS
1
U20
1
U18
1
U17
1
U14
SiBAR
U19
SiBAR
U16
QUAD FALC
2
D
5
1
2
36
100E_5P_0W125
9
P2A
of
15
Rev
2.0
CONN_RJ45_4STACK
A8
A7
A6
A5
A4
A3
A2
A1
A
B
C
D
A
B
,11,12,14 CT_FRAMEn
C
R84
DNP
5
0E
13
17
16
15
14
12
19
130
129
128
127
126
18
SCLKR2
RPD2
RPC2
RPB2
RPA2
RDO2
SCLKX2
RCLK2
XPD2
XPC2
XPB2
XPA2
XDI2
137
138
142
144
R89
R86
DNP: Do Not Place
4
2E_5P_0W125
R82
10E_5P_0W125
3
AVDD3V3
10E_5P_0W125
2E_5P_0W125
R85
7R5_5P_0W125
R83
NOTE
CON3
1
2
3
J5
NOTE: Connect 1 & 2 for E1
Connect 2 & 3 for T1
RL2/RDIN/RCLKI
RL1/RDIP/ROID
XL2/XDON/XFM
XL1/XDOP/XOID
U12D
Quad_falc
NOTE
CON3
1
2
3
BAV70
D8
3
AVDD3V3
2
1
7R5_5P_0W125
R81
BAV70
D6
1
3
3
D7
BAW56
2
J4
2
1
3
DGND
3
D5
BAW56
120E_5P_0W125
D
1
2
4
J6
R88
CON3
R87
DGND
NOTE
1
2
3
7
6
9
8
10
34
35
2
U15D
TGSP-SO24NX
32
33
U15C
TGSP-SO24NX
2
Date:
Size
B
Title
1
2
5
1
2
31
100E_5P_0W125
2
TR600-150
2
TR600-150
2
TR600-150
2
TR600-150
Thursday, June 12, 2003
Document Number
<Doc>
QUAD FALC
1
Sheet
AURAL NETWORKS
1
U26
1
U24
1
U23
SiBAR
U25
SiBAR
U22
1
U21
1
P2B
10
of
15
Rev
2.0
CONN_RJ45_4STACK
B8
B7
B6
B5
B4
B3
B2
B1
A
B
C
D
A
B
C
9,10,12,14 CT_FRAMEn
R93
DNP
5
0E
26
25
24
23
22
27
21
47
54
53
52
51
20
SCLKR3
RPD3
RPC3
RPB3
RPA3
RDO3
SCLK3
RCLK3
XPD3
XPC3
XPB3
XPA3
XDI3
RL2/XDIN/RCLKI
RL1/RDIP/ROID
XL2/XDON/XFM
XL1/XDOP/XOID
R98
R95
NOTE
CON3
1
2
3
J8
4
DNP: Do Not Place
BAV70
D11
3
AVDD3V3
10E_5P_0W125
3
AVDD3V3
10E_5P_0W125
2E_5P_0W125
R94
7R5_5P_0W125
R92
2E_5P_0W125
R91
NOTE: Connect 1 & 2 for E1
Connect 2 & 3 for T1
44
43
39
37
NOTE
CON3
2
1
1
2
3
2
1
BAW56
3
D12
BAV70
D10
3
DGND
1
2
7R5_5P_0W125
R90
3
3
J9
R97
DGND
CON3
R96
D9
BAW56
120E_5P_0W125
J7
1
2
U12E
Quad_falc
4
NOTE
14
13
12
11
26
D
5
1
2
3
15
27
28
2
U15F
TGSP-SO24NX
29
30
U15E
TGSP-SO24NX
2
Date:
Size
B
Title
1
2
1
2
100E_5P_0W125
2
TR600-150
2
TR600-150
2
TR600-150
2
TR600-150
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
C8
C7
C6
C5
C4
C3
C2
C1
P2C
11
of
15
Rev
2.0
CONN_RJ45_4STACK
AURAL NETWORKS
1
U32
1
U30
1
U29
QUAD FALC
SiBAR
U31
SiBAR
U28
1
U27
1
A
B
C
D
A
B
C
9,10,11,14 CT_FRAMEn
R102
DNP
5
0E
31
35
34
33
32
30
50
61
60
59
58
57
49
SCLKR4
RPD4
RPC4
RPB4
RPA4
RDO4
SCLKX4
RCLK4
XPD4
XPC4
XPB4
XPA4
XDI4
RL2/RDIN/RCLKI
RL1/RDIP/ROID
XL2/XDON/XFM
XL1/XDOP/XOID
65
66
70
72
U12F
Quad_falc
BAV70
D16
4
DNP: Do Not Place
3
AVDD3V3
NOTE: Connect 1 & 2 for E1
Connect 2 & 3 for T1
3
AVDD3V3
10E_5P_0W125
2E_5P_0W125
R103
7R5_5P_0W125
R101
2E_5P_0W125
R100
10E_5P_0W125
R107
R104
NOTE
CON3
1
2
3
J11
NOTE
CON3
1
2
3
2
1
7R5_5P_0W125
R99
2
1
3
D15
BAW56
BAV70
D14
3
DGND
3
1
2
J10
1
2
4
DGND
CON3
J12
R105 R106
3
D13
BAW56
NOTE
1
2
3
17
16
19
18
20
21
24
25
2
U15H
TGSP-SO24NX
22
23
U15G
TGSP-SO24NX
2
Date:
Size
B
Title
1
1
U38
TR600-150
2
TR600-150
2
TR600-150
2
2
TR600-150
1
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
D8
D7
D6
D5
D4
D3
D2
D1
P2D
of
15
Rev
2.0
CONN_RJ45_4STACK
12
AURAL NETWORKS
SiBAR
U37
1
U36
1
U33
1
U35
SiBAR
U34
QUAD FALC
2
D
5
1
2
100E_5P_0W125
120E_5P_0W125
A
B
C
D
A
B
C
D
5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
JTAG_TCK
8
8
7,8,15
7,8,15
3,4
TDM_SPICLK
CONN_AD22
CONN_AD23
CONN_AD24
CONN_AD25
CONN_AD26
CONN_AD27
CONN_AD28
CONN_AD29
CONN_AD30
CONN_AD31
0E
0E
R133
R134
PQ2_CS_TDM2 15
TDM_SPI_CS0 3
TDM_GPL2
TDM_GPL1
PQ2_CS_TDM1 8
TDM_TO_PQ2_INT1 8
CONN_AD30
CONN_AD31
CONN_AD28
CONN_AD29
CONN_AD26
CONN_AD27
CONN_AD24
CONN_AD25
CONN_AD23
JTAG_TRST
TDM_TDO
+3.3V
+5V
7
4
CT_D0
CT_D4
3,4,9,14,15 CT_C8_A
15 CT_FRAME_A
+5V
TDM_SPIMOSO 3,4
7
TDM_SPIMOSI
3,4
DGND
8
REMEMBER: A0 is LSB on QuadFALC
A31 is LSB on Motorola!!
4
J13 will connect to J9 connector of base card
J14 will connect to J7 connector of base card
J15 will connect to J8 connector of base card
7,8,15 CONN_AD[22:31]
CONN_D0
CONN_D1
CONN_D2
CONN_D3
CONN_D4
CONN_D5
CONN_D6
CONN_D7
CONN_D8
CONN_D9
CONN_D10
CONN_D11
CONN_D12
CONN_D13
CONN_D14
CONN_D15
DGND
J15
HEADER32x2
1
3
5
7
CONN_D0
9
CONN_D1 11
13
15
CONN_D2 17
CONN_D3 19
21
CONN_D4 23
CONN_D5 25
27
CONN_D6 29
CONN_D7 31
33
CONN_D8 35
37
CONN_D9 39
41
CONN_D10 43
CONN_D11 45
47
CONN_D12 49
CONN_D13 51
53
CONN_D14 55
CONN_D15 57
59
CONN_AD2261
63
TDM_SPI_CS1
JTAG_TMS
TDM_TDI
8,15 TDM_RESET
4
8
8
REMEMBER: D0 is LSB on QuadFALC
D0 is MSB on Motorola!!
7,8,15 CONN_D[0:15]
+3.3V
+5V
5
DGND
CT_D0
3
CT_D4
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
CT_D1
CT_D5
CT_D0- Transmit to DSP (TDM0)
CT_D1- RX from DSP (TDM0)
CT_D4 Transmit to MPC8260
CT_D5 Recieve from MPC8260
HEADER32x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
J14
DGND
CT_D1
CT_D5
+5V
7
7
2
TP36
TP37
TP35
2
1
1
1
+3.3V
Date:
Size
B
Title
DGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Thursday, June 12, 2003
1
Sheet
Base Board Connectors
13
of
TDM_TO_PQ2_INT2 3
TDM_TO_PQ2_INT3 4
AURAL NETWORKS
HEADER32x2
Document Number
<Doc>
TDM_GPIO1
TDM_GPIO0
TDM_GPIO2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
J13
1
15
Rev
2.0
DGND
+5V
A
B
C
D
A
B
C
0_1uF
0_1uF
0_1uF
C87
5
DNP : Do Not Place
C86
C85
0_1uF
C88
DGND
0_1uF
C89
PLD_F_sel1
PLD_F_sel0
RCLK1
4
DVDD3V3
15
15
PLD_TCLRn
PLD_TIE_en
15 PLD_WAN_PLL_RSTn
15 PLD-MODE_sel1
15 PLD_MODE_sel0
15
15
9
R113
R137
R136
TP21
DNP
10K
0E
0E
DGND
0E
R114
10K
R138
DVDD3V3
3
6
7
8
11
21
22
34
35
43
29
32
30
28
31
45
3
56
4
2
1
10
9
5
IC
IC
IC
IC
IC
IC
IC
IC
IC
41
42
40
39
36
33
25
20
24
23
17
16
15
14
52
46
51
44
49
50
1
1
1
1
R110
R111
R112
TP25
0E
0E
0E
TP22TP23TP24
2CLK_OSC
33E
15 PLD_QFALC_FRAME
TP30
TP33
TP34
TP32
R109
1
Title
LOCK_PLD
DGND
2
IN
DGND
8
CLK_OSC
R130
DNP
0E
R129
0E
Thursday, June 12, 2003
1
Sheet
14
of
15
Rev
2.0
8,9,10,11,12
To QuadFALC
CT_FRAMEn
AURAL NETWORKS
4
NC7S04
U41
TP38
TO BASE BOARD CONNECTOR -- 8.192MHz
DuSLIC/FALC
Document Number
<Doc>
3
GND
DGND
O/P
0_1uF
DGND
C84
SWITCH---4.096MHz
SWITCH --- 16.384MHz
E/D
DVDD3V3
1
CLOCK SYNCHRONIZATION CIRCUIT
DVDD3V3
OUT*
1
FOX_F7C-2E3
U39
7 TO IDT
7 TO IDT
3,4,9,13,15
CT_STFRAMEn 7,15
CT_FRAME
3,4,15
CT_WFRAMEn 7,15
HCLK
CLK
CT_C8_A
2
Date:
Size
B
15
10K
HOLDOVER_PLD 15
NORMAL_PLD 15
VCC
RSP
TSP
F32o
F16o
F8o
F0o
C32o
C4o
C16o
C8o
C2o
C3o
C1.5o
C6o
HOLDOVER
NORMAL
FREERUN
LOCK
OSCo
OSCi
U40
IDT82V3001
5
TDO
TDI
TRST
TCK
TMS
FLOCK
TCLR
TIE_en
RST
MODE_sel1
MODE_sel0
F_sel1
F_sel0
Fref
DVDD3V3
R108
DVDD3V3
VSS
VSS
VSS
VSS
VSS
12
18
27
38
47
8 KHz FSC signal from QuadFALC
9
FSC_QFALC
1
13
19
26
37
48
VDD
VDD
VDD
VDD
VDD
IC2
IC1
IC0
55
54
53
D
2
1
DVDD3V3
3
1
4
1
5
1
14
VDD
GND
7
TO BASE BOARD CONNECTOR -- 8KHz
1
A
B
C
D
A
B
C
TMS_PLD
TDO_PLD
TDI_PLD
TCK_PLD
CONN_JTAG_PLD
1
2
3
4
5
6
7
8
9
J16
DVDD5V
5
330E
R115
DVDD3V3
0_1uF
DGND
C94
13 PQ2_CS_TDM2
LED5
2
2
3
5
6
CONN_AD30
CONN_AD29
CONN_AD28
CONN_AD27
TP31
+5V
+5V
VHR
VHRX
JUMPER3
1
1
DGND
DVDD5
J20 JUMPER3
J19
DVDD5V
J18 JUMPER3
FROM BASE BOARD CONNECTOR
FROM BASE BOARD CONNECTOR
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U42
DVDD3V3
+3.3V DVDD3V3 3V3
8
10
11
12
13
14
15
18
19
20
21
22
PLD_LOS_FALC
23
CONN_D15
CONN_D14
CONN_D13
CONN_D12
42
43
44
CONN_AD22
FROM BASE BOARD CONNECTOR
1
3,4,14 CT_FRAME
From WAN PLL
From WAN PLL
7,14 CT_STFRAMEn
From WAN PLL
7,14 CT_WFRAMEn
To Base board connectors 13 CT_FRAME_A
14 PLD_WAN_PLL_RSTn
8,13 TDM_RESET
7 PLD_IDT_CSn
3,4,9,13,14 CT_C8_A
7,8,13 CONN_D[0:15]
7,8,13 CONN_AD[22:31]
FROM BASEBOARD CONNECTOR
14 PLD_QFALC_FRAME
7,8,13 CONN_AD[22:31]
3
2
1
3
2
1
3
2
1
1
9
17
29
41
Vcc
Vcc
Vcc
Vcc
GND
GND
GND
16
24
36
D
26
1
32
7
4
40
39
38
37
25
27
28
30
31
33
34
35
VBATHX
VBATH
3
VBATL
IN4004
D20
DGND
C95
100nF_10P_200V
D19
IN4004
DGND
TP29
IN4004
D17
D18
DGND
10K
1
10K
1
10K
1
2
2
R125 R126
2
R124
DVDD3V3
IN4004
TP40
1
2
3
4
5
6
2
2
DGND
22K
R116
0_1uF
C90
DVDD3V3
TDM_GPL1
7,8,13 FROM BASEBOARD CONNECTOR
TDM_GPL2
7,8,13 FROM BASEBOARD CONNECTOR
LOCK_PLD
14
NORMAL_PLD 14
PLD_MODE_sel0 14
PLD-MODE_sel1 14
PLD_F_sel0
14
PLD_F_sel1
14
PLD_TCLRn
14
PLD_TIE_en 14
HOLDOVER_PLD 14
PLD_DuSLIC_TSI_RSTn 3,4,7
CON6_PowerSupply
J17
TCK_PLD
TDI_PLD
TDO_PLD
TMS_PLD
TP39 VBATHX VHRX DVDD5 3V3
TCK
TDI
TDO
TMS
PORT_EN
IN0/CLK0
IN1/CLK1
IN2/CLK2
IN3/CLK3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XCR3032XL_5VQ44I
2
0_1uF
0_1uF
DGND
C93
C92
1
Date:
Size
B
Title
1
2
1
2
DGND
LED7
330E
R118
DVDD5V
1
2
LED8
330E
R119
DGND
VHR
Thursday, June 12, 2003
Document Number
<Doc>
1
Sheet
1
2
15
of
DGND
LED9
10K
R120
VBATHX
AURAL NETWORKS
CPLD and Power
DGND
LED6
330E
R117
DVDD3V3
SYNC :Synchronous clock from Central Office
DNP: Do Not Place
0_1uF
C91
1
2
3
2
1
1
2
4
1
1
1
2
5
2
12
1
2
1
15
Rev
2.0
A
B
C
D
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