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Peripherals
When the receiver enable bit S0REN or S1REN of a serial channel in asynchronous operation
is reset to '0' while a reception is in progress, the current reception will be completed, including
generation of the receive interrupt request and, in case of errors, generation of the error
interrupt request and setting of the error status flags which are described in the following.
Reception then stops for the affected channel, and further start bits at the receive data input
pin will be ignored.
In order to use pin RXD0/P3.11 or RXD1/P3.9 as receive data input, the corresponding
direction control bit DP3.11 or DP3.9 must be set to '0'.
Hardware Error Detection Capabilities
To improve the safety of asynchronous data exchange, the serial channels of the SAB 80C166
provide selectable hardware error detection capabilities. For each channel, three error status
flags in the channel's control register S0CON or S1CON indicate whether an error has been
detected during reception. Upon completion of a reception, the error interrupt request flag
S0EIR or S1EIR will be set simultaneously with the receive interrupt request flag S0RIR or
S1RIR if one or more of the following conditions are met:
– If the framing error detection enable bit S0FEN or S1FEN is set and any of the expected
stop bits is not high, the framing error flag S0FE or S1FE is set indicating that the error
interrupt request is due to a framing error.
– If the parity error detection enable bit S0PEN or S1PEN is set in the modes where a parity
bit is received, and the parity check on the received data bits proves false, the parity error
flag S0PE or S1PE is set indicating that the error interrupt request is due to a parity error.
– If the overrun error detection enable bit S0OEN or S1OEN is set and the last character
received was not read out of the receive buffer by software or PEC transfer at the time
reception of a new frame is complete, the overrun error flag S0OE or S1OE is set indicating
that the error interrupt request is due to an overrun error.
In the following subsections, specific characteristics of the individual operating modes for the
asynchronous communication are described in more detail.
Semiconductor Group
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